Voltage-controlled frequency source with embedded current vector synthesis frequency doubling function

Abstract

The invention discloses a voltage-controlled frequency source for embedded current vector synthesis frequency multiplication. An intermediate frequency differential clock signal output end of a multi-frequency output dual-core inverse F voltage-controlled oscillator is connected with a differential clock input end of a differential-single-ended output buffer and a differential clock input end of an orthogonal / 2 frequency divider; the output end of the differential-single-ended output buffer is connected with the intermediate-frequency clock signal output end, and the four-phase output end of the orthogonal / 2 frequency divider is connected with the corresponding phase in the orthogonal four-phase low-frequency clock signal output end. A first high-frequency differential clock signal output end and a second high-frequency differential clock signal output end of the multi-frequency output dual-core inverse F voltage-controlled oscillator are respectively connected with a first differential clock signal input end and a second differential clock signal input end of the current vector synthesis frequency multiplier; the voltage-controlled frequency source has the characteristics of low phase noise, low hardware overhead and low extra power consumption, and the frequency multiplier has low influence on the spurious characteristic of an output frequency signal.

Description

Technical Field

[0001] This invention belongs to the field of electronic technology and relates to a voltage-controlled frequency source with embedded current vector synthesis frequency multiplication. Background Technology

[0002] Frequency sources, as modules for generating clock and carrier signals, have wide applications in communications. Their phase noise characteristics and output frequency range directly determine the performance and even the functionality of transceiver systems. With the continuous development of communication technology, low phase noise and wide output frequency range frequency sources have become a basic requirement for integrated communication systems.

[0003] Although complementary cross-coupled LC oscillators have lower phase noise than ring oscillators, their structure has limitations in suppressing flicker noise injected into the resonant cavity by the tail current source, restricting their application in future communication systems. While using a second harmonic resonant cavity connected in parallel with the tail current source can reduce flicker noise injection when the cross-coupled negative resistance transistor operates in the linear region, the second harmonic resonant cavity requires an additional capacitor array to adjust its oscillation frequency to match the oscillation frequency of the oscillator's main resonant cavity. This not only increases hardware overhead but also increases the complexity of oscillator frequency modulation control. Furthermore, based on implicit common-mode LC oscillators, two mutually coupled transformer resonant cavities oscillating at the fundamental frequency and second harmonic respectively are used, and the coupling coefficient between the two transformer coils is appropriately set. k The inductance and capacitance values ​​are adjusted to ensure that the resonant cavity exhibits high impedance at both the differential-mode fundamental frequency and the common-mode second harmonic, effectively reducing the common-mode flicker noise injected into the resonant cavity. However, its quality factor is relatively low at the second harmonic, and its phase noise suppression effect is limited.

[0004] To overcome the shortcomings of implicit common-mode LC oscillators, researchers proposed an inverse Class-F oscillator without common-mode resonance. Its quality factor at the second harmonic is further reduced by 1 / f ² to 1 / fThe phase noise in the ³ region is effectively suppressed, and the voltage gain provided by the transformer effectively suppresses the thermal noise of the negative resistance unit, enabling high impedance and high Q value at both the differential fundamental frequency and the second harmonic. However, the difference in parasitic capacitance between the PMOS and NMOS transistors providing the negative resistance leads to aggravated phase and amplitude mismatch at high frequencies in the pseudo-differential output node, limiting further improvement in phase noise characteristics. Furthermore, when a voltage-controlled oscillator (VCO) is applied to a phase-locked loop (PLL), a large difference between its output frequency and the PLL reference clock frequency necessitates a larger division ratio. This results in a decrease in the PLL's ability to suppress phase noise within the loop bandwidth, hindering the achievement of lower jitter. Although using a frequency multiplier can increase the PLL's output frequency and alleviate the conflict between the division ratio and jitter, the additional multiplier not only increases hardware overhead and power consumption, but its harmonic suppression effect directly impacts the spurious characteristics of the output frequency signal. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a voltage-controlled frequency source with embedded current vector synthesis frequency multiplication. This voltage-controlled frequency source has the characteristics of low phase noise, low hardware overhead and low additional power consumption, while the frequency multiplier has a low impact on the spurious characteristics of the output frequency signal.

[0006] To achieve the above objectives, this invention discloses a voltage-controlled frequency source with embedded current vector synthesis frequency multiplier, including a high-frequency clock signal output terminal, an intermediate-frequency clock signal output terminal, an orthogonal four-phase low-frequency clock signal output terminal, a multi-frequency output dual-core inverse F voltage-controlled oscillator, a current vector synthesis frequency multiplier, a differential-single-ended output buffer, and an orthogonal ÷ 2 frequency divider. The intermediate frequency differential clock signal output terminal of the multi-frequency output dual-core inverse F voltage-controlled oscillator is connected to the differential clock input terminal of the differential-single-ended output buffer and the differential clock input terminal of the quadrature ÷ 2 divider. The output terminal of the differential-single-ended output buffer is connected to the intermediate frequency clock signal output terminal. The four-phase output terminals of the quadrature ÷ 2 divider are respectively connected to the corresponding phases of the quadrature four-phase low-frequency clock signal output terminals. The first high-frequency differential clock signal output terminal and the second high-frequency differential clock signal output terminal of the multi-frequency output dual-core inverse F voltage-controlled oscillator are respectively connected to the first differential clock signal input terminal and the second differential clock signal input terminal of the current vector synthesizer frequency multiplier. The output terminal of the current vector synthesizer frequency multiplier is connected to the high-frequency clock signal output terminal.

[0007] Furthermore, it also includes a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor; The first and second high-frequency differential clock signal output terminals of the multi-frequency output dual-core inverse F voltage-controlled oscillator are respectively connected to one end of the first capacitor, one end of the second capacitor, one end of the third capacitor, and one end of the fourth capacitor. The other ends of the first and second capacitors are respectively connected to the first differential clock signal input terminal of the current vector synthesizer frequency multiplier. The other ends of the third and fourth capacitors are respectively connected to the second differential clock signal input terminal of the current vector synthesizer frequency multiplier.

[0008] Furthermore, it also includes a primary control voltage input terminal, a secondary control voltage input terminal, a four-bit wide primary frequency modulation control signal input terminal, and a six-bit wide secondary frequency modulation control signal input terminal; The first voltage input terminal and the second voltage input terminal of the multi-frequency output dual-core inverse F voltage-controlled oscillator are connected to the primary control voltage input terminal and the secondary control voltage input terminal, respectively. The first frequency modulation signal control input terminal and the second frequency modulation signal control input terminal of the multi-frequency output dual-core inverse F voltage-controlled oscillator are connected to the four-bit wide primary frequency modulation control signal input terminal and the six-bit wide secondary frequency modulation control signal input terminal, respectively.

[0009] Furthermore, it also includes a first bias voltage input terminal and a second bias voltage input terminal; The first bias voltage input terminal and the second bias voltage input terminal of the current vector synthesis frequency multiplier are respectively connected to the first bias voltage input terminal and the second bias voltage input terminal.

[0010] Furthermore, the multi-frequency output dual-core inverse F voltage-controlled oscillator includes a primary control voltage input terminal, a secondary control voltage input terminal, a four-bit wide primary frequency modulation control signal input terminal, a six-bit wide secondary frequency modulation control signal input terminal, an intermediate frequency differential clock signal output terminal, a first high-frequency differential clock signal output terminal, a second high-frequency differential clock signal output terminal, a first oscillation core, and a second oscillation core. The core of the first oscillator includes a first primary varactor, a second primary varactor, a first secondary varactor, a second secondary varactor, a first PMOS transistor, a first NMOS transistor, a first transformer, a 4-unit switched capacitor array, and a 6-unit switched capacitor array. In the first oscillator core, each unit of the 4-unit switched capacitor array includes a first primary switch, a first primary capacitor, and a second primary capacitor; each unit of the 6-unit switched capacitor array includes a first primary switch, a first primary capacitor, and a second primary capacitor; and the first transformer includes a coupling coefficient of... k 1. The first primary inductance and the first secondary inductance; The core of the second oscillator includes a third primary varactor, a fourth primary varactor, a third secondary varactor, a fourth secondary varactor, a second PMOS transistor, a second NMOS transistor, a second transformer, a 4-unit switched capacitor array, and a 6-unit switched capacitor array. The second oscillator core comprises a 4-unit switched capacitor array, each unit including a second primary switch, a third primary capacitor, and a fourth primary capacitor. The second oscillator core also comprises a 6-unit switched capacitor array, each unit including a second-stage switch, a third-stage capacitor, and a fourth primary capacitor. The second transformer includes a coupling coefficient of... k 2. The second primary inductor and the second secondary inductor; The primary control voltage input terminals are connected to one end of the first, second, third, and fourth primary varactor diodes, respectively. The secondary control voltage input terminals are connected to one end of the first, second, third, and fourth secondary varactor diodes, respectively. The four-bit wide primary frequency modulation control signal input terminals are connected to the control terminals of the first and second primary switches, respectively. The input and output terminals of the first primary switch are connected to one end of the first and second primary capacitors, respectively. The input and output terminals of the second primary switch are connected to one end of the third and fourth primary capacitors, respectively. The six-bit wide secondary frequency modulation control signal input terminals are connected to the control terminals of the first and second primary switches, respectively. The input and output terminals of the first primary switch are connected to one end of the first and second primary capacitors, respectively. The second primary switch... The input and output terminals of the transistor are connected to one end of the third-stage capacitor and one end of the fourth-stage capacitor, respectively. The source of the first NMOS transistor is connected to the power supply ground. The drain of the first NMOS transistor is connected to the positive terminal of the first primary inductor in the first transformer, the other end of the second primary varactor, the other end of the second primary capacitor, and the negative terminal of the first high-frequency differential clock signal output terminal. The gate of the first NMOS transistor is connected to the negative terminal of the first primary inductor in the first transformer, the other end of the second primary varactor, the other end of the second-stage capacitor, the other end of the third-stage capacitor, the other end of the third-stage varactor, the positive terminal of the second primary inductor in the second transformer, the gate of the second PMOS transistor, and the positive terminal of the intermediate-frequency differential clock signal output terminal. The source of the second PMOS transistor is connected to the power supply. The drain of the second PMOS transistor is connected to the negative terminal of the second primary inductor in the second transformer, the other end of the third primary varactor, the other end of the third primary capacitor, and the negative terminal of the second high-frequency differential clock signal output terminal. The source of the second NMOS transistor is connected to the power supply ground. The drain of the second NMOS transistor is connected to the positive terminal of the second primary inductor in the second transformer, the other end of the fourth primary varactor, the other end of the fourth primary capacitor, and the positive terminal of the second high-frequency differential clock signal output terminal. The gate of the second NMOS transistor is connected to the negative terminal of the second secondary inductor in the second transformer, the other end of the fourth secondary varactor, the other end of the fourth secondary capacitor, the other end of the first primary capacitor, the other end of the first secondary varactor, the positive terminal of the first primary inductor in the first transformer, the gate of the first PMOS transistor, and the negative terminal of the intermediate frequency differential clock signal output terminal. The source of the first PMOS transistor is connected to the power supply. The drain of the first PMOS transistor is connected to the negative terminal of the first primary inductor in the first transformer, the other end of the first primary varactor, the other end of the first primary capacitor, and the positive terminal of the first high-frequency differential clock signal output terminal.

[0011] Furthermore, when the multi-frequency output dual-core inverse F voltage-controlled oscillator is working, the first oscillation core and the second oscillation core are synchronously frequency-modulated; the secondary resonant cavities of the first oscillation core and the second oscillation core are connected by DC coupling.

[0012] Furthermore, the primary coils of the first and second oscillation cores output independently, controlling the current vector synthesis of the current vector synthesizer frequency multiplier to extract the second harmonic.

[0013] The current vector synthesis frequency multiplier includes a first differential clock signal input terminal, a second differential clock signal input terminal, a first bias voltage signal input terminal, a second bias voltage signal input terminal, a high-frequency clock signal output terminal, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a thirteenth capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a third transformer, and a fourth transformer; Furthermore, the third transformer includes a coupling coefficient of k The first and second coupling coils of the 3, and the fourth transformer including the coupling coefficient of 3 k The third and fourth coupling coils of 3; The first bias voltage signal input terminal is connected to one end of the first resistor, one end of the second resistor, one end of the third resistor, and one end of the fourth resistor, respectively. The positive terminal of the first differential clock signal input terminal is connected to one end of the fifth capacitor, the gate of the third NMOS transistor, and the other end of the first resistor. The negative terminal of the first differential clock signal input terminal is connected to one end of the sixth capacitor, the gate of the fourth NMOS transistor, and the other end of the second resistor. The positive terminal of the second differential clock signal input terminal is connected to one end of the eighth capacitor, the gate of the fifth NMOS transistor, and the other end of the third resistor. The second differential clock signal... The negative terminal of the input is connected to one end of the ninth capacitor, the gate of the sixth NMOS transistor, and the other end of the fourth resistor. The sources of the third, fourth, fifth, and sixth NMOS transistors are all connected to the power supply ground. The drain of the third NMOS transistor is connected to the other end of the sixth capacitor, one end of the seventh capacitor, one end of the tenth capacitor, the other end of the ninth capacitor, the positive terminal of the first coupling coil in the third transformer, and the drain of the fifth NMOS transistor. The drain of the fourth NMOS transistor is connected to the other end of the fifth capacitor, the other end of the seventh capacitor, and the fourth... The other end of the eighth capacitor, the other end of the tenth capacitor, the negative terminal of the first coupling coil in the third transformer, and the drain of the sixth NMOS transistor are connected. The center tap of the second coupling coil in the third transformer is connected to the second bias voltage signal input terminal. The center tap of the first coupling coil in the third transformer is connected to the power supply. The positive terminal of the second coupling coil in the third transformer is connected to the gate of the seventh NMOS transistor and one end of the eleventh capacitor. The negative terminal of the second coupling coil in the third transformer is connected to the gate of the eighth NMOS transistor and one end of the twelfth capacitor. The source of the seventh NMOS transistor... The source of the seventh NMOS transistor and the eighth NMOS transistor are both connected to the power supply ground. The drain of the seventh NMOS transistor is connected to the other end of the twelfth capacitor, one end of the thirteenth capacitor, and the positive terminal of the third coupling coil in the fourth transformer. The drain of the eighth NMOS transistor is connected to the other end of the eleventh capacitor, the other end of the thirteenth capacitor, and the negative terminal of the third coupling coil in the fourth transformer. The center tap of the third coupling coil in the fourth transformer is connected to the power supply. The positive terminal of the fourth coupling coil in the fourth transformer is connected to the high-frequency clock signal output terminal. The negative terminal of the fourth coupling coil in the fourth transformer is connected to the power supply ground.

[0014] Furthermore, the current vector synthesizer frequency multiplier converts the voltage values ​​of the two sets of differential clock signals into vector currents, which are then synthesized and amplified before being output.

[0015] The input signal of the quadrature ÷ 2 divider circuit is the intermediate frequency differential clock signal of the multi-frequency output dual-core inverse F voltage-controlled oscillator, and the output signal of the quadrature ÷ 2 divider circuit is four clock signals with a period twice that of the input signal.

[0016] The present invention has the following beneficial effects: The voltage-controlled frequency source with embedded current vector synthesis frequency multiplication described in this invention employs a multi-frequency output dual-core inverse Class-F voltage-controlled oscillator (VCO) during operation. This VCO can simultaneously generate one set of intermediate-frequency differential clock signals and two sets of high-frequency differential clock signals. The two sets of high-frequency outputs include both a common-mode fundamental signal and a differential-mode second harmonic signal. The multi-frequency output dual-core inverse Class-F VCO organically combines frequency multiplication with the oscillator, achieving low phase noise, low hardware overhead, and low power consumption while outputting the fundamental and second harmonic signals, as well as quadrature clock signals. The fundamental signal is used for frequency synthesis in a phase-locked loop (PLL), while the second harmonic is extracted through current vector synthesis to achieve the output of a second harmonic signal. Since the fundamental signal is a common-mode signal and the second harmonic is a differential-mode signal, a purer second harmonic is effectively separated and extracted, thereby suppressing spurious components during frequency multiplication and improving the output spectrum quality. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a structural diagram of the present invention; Figure 2 This is a schematic diagram of the multi-frequency output dual-core inverse F voltage-controlled oscillator in this invention; Figure 3 This is a schematic diagram of the current vector synthesis frequency multiplier in this invention; Figure 4 The diagram shows the circuit structure and time-domain waveform of the quadrature ÷ 2 frequency divider in this invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] In the description of this invention, it should be understood that the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0021] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0022] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Additionally, the character " / " in this invention generally indicates that the preceding and following objects have an "or" relationship.

[0023] It should be understood that although terms such as first, second, third, etc., may be used in the embodiments of the present invention to describe the preset range, these preset ranges should not be limited to these terms. These terms are only used to distinguish the preset ranges from one another. For example, without departing from the scope of the embodiments of the present invention, the first preset range may also be referred to as the second preset range, and similarly, the second preset range may also be referred to as the first preset range.

[0024] Depending on the context, the word "if" as used here can be interpreted as "when," "when," "in response to determination," or "in response to detection." Similarly, depending on the context, the phrase "if determination" or "if detection (of the stated condition or event)" can be interpreted as "when determination," "in response to determination," "when detection (of the stated condition or event)," or "in response to detection (of the stated condition or event)."

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0026] The accompanying drawings illustrate various structural schematic diagrams according to embodiments disclosed in this invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0027] refer to Figure 1 The voltage-controlled frequency source with embedded current vector synthesis frequency multiplication described in this invention includes a primary control voltage input terminal. V C,P Secondary control voltage input terminal V C,S 4-bit wide primary frequency modulation control signal input terminal BS P [3:0], Six-bit wide secondary frequency modulation control signal input terminal BS S [5:0] First bias voltage input terminal V B1 Second bias voltage input terminal V B2 Φ high-frequency clock signal output terminal HF 1. Intermediate frequency clock signal output terminal Φ IF Orthogonal four-phase low-frequency clock signal output terminal Φ LF,I Φ LF,Q Φ LF,IB and Φ LF,QB Multi-frequency output dual-core inverse F voltage-controlled oscillator, first capacitor C 1. Second capacitor C 2. Third capacitor C 3. Fourth capacitor C 4. Current vector synthesizer frequency multiplier, differential-single-ended output buffer and quadrature ÷ 2 frequency divider; The first and second voltage input terminals of the multi-frequency output dual-core inverse F voltage-controlled oscillator are respectively connected to the primary control voltage input terminal. V C,P and secondary control voltage input terminal V C,S Connected to each other, the first frequency modulation signal control input terminal and the second frequency modulation signal control input terminal are respectively connected to the four-bit wide primary frequency modulation control signal input terminal BS. P [3:0] and six-bit wide secondary frequency modulation control signal input terminal BS S [5:0] Connected to the intermediate frequency differential clock signal output terminal Φ of the multi-frequency output dual-core inverse F voltage-controlled oscillator. + VCO,IF and Φ － VCO,IFThe differential clock input of the differential-single-ended output buffer and the differential clock input of the quadrature ÷ 2 divider are connected. The output of the differential-single-ended output buffer is connected to the intermediate frequency clock signal output terminal Φ. IF The four-phase outputs of the quadrature ÷ 2 frequency divider are connected to the quadrature four-phase low-frequency clock signal outputs Φ respectively. LF,I Φ LF,Q Φ LF,IB and Φ LF,QB The corresponding phase connection in the multi-frequency output dual-core inverse F voltage-controlled oscillator, the first high-frequency differential clock signal output terminal Φ + VCO,HF1 and Φ － VCO,HF1 and the second high-frequency differential clock signal output terminal Φ + VCO,HF2 and Φ － VCO,HF2 respectively with the first capacitor C One end of 1, the second capacitor C One end of 2, the third capacitor C One end of 3 and the fourth capacitor C Connect one end of 4 to the first capacitor. C The other end of 1 and the second capacitor C The other end of 2 is connected to the first differential clock signal input terminal Φ of the current vector synthesizer frequency multiplier. + FM,in1 and Φ － FM,in1 Connected, third capacitor C The other end of 3 and the fourth capacitor C 4. The other end is connected to the second differential clock signal input terminal Φ of the current vector synthesizer frequency multiplier. + FM,in2 and Φ － FM,in2 Connected to each other, the first bias voltage input terminal and the first bias voltage input terminal of the current vector synthesis frequency multiplier are respectively connected to the first bias voltage input terminal. V B1 and the second bias voltage input terminal V B2 Connected to the output terminal of the current vector synthesizer frequency multiplier and the high-frequency clock signal output terminal Φ HF Connected.

[0028] refer to Figure 2 The multi-frequency output dual-core inverse F voltage-controlled oscillator includes a primary control voltage input terminal. V C,P Secondary control voltage input terminal V C,S Four-bit wide primary frequency modulation control signal input terminal BS P[3:0], Six-bit wide secondary frequency modulation control signal input terminal BS S [5:0], Intermediate frequency differential clock signal output terminal Φ + VCO,IF and Φ － VCO,IF First high-frequency differential clock signal output terminal Φ + VCO,HF1 and Φ － VCO,HF1 Φ, the second high-frequency differential clock signal output terminal + VCO,HF2 and Φ － VCO,HF2 The first oscillation core and the second oscillation core.

[0029] The core of the first oscillator includes a first primary variable capacitance tube. C VAR,P1 Second primary variable capacitance tube C VAR,P2 First stage variable capacity tube C VAR,S1 Secondary variable capacity tube C VAR,S2 First PMOS transistor MP1, first NMOS transistor MN1, first transformer T 1. A 4-unit switched capacitor array and a 6-unit switched capacitor array; Each unit in the four-unit switched capacitor array in the core of the first oscillator includes a first primary switch. SW P1 First primary capacitor C P1 Second primary capacitor C P2 Each cell in the 6-cell switched capacitor array includes a first-stage switch. SW S1 Primary capacitor C S1 Secondary capacitor C S2 First transformer T 1 includes coupling coefficients of k 1's first primary inductance L P1 and primary inductor L S1 .

[0030] The core of the second oscillator includes a third primary variable capacitance tube. C VAR,P3 Fourth primary variable capacitance tube C VAR,P4 Third-stage variable capacitance tube C VAR,S3Fourth secondary variable capacitance tube C VAR,S4 Second PMOS transistor MP2, second NMOS transistor MN2, second transformer T 2. A 4-unit switched capacitor array and a 6-unit switched capacitor array.

[0031] In particular, each unit in the four-unit switched capacitor array within the core of the second oscillator includes a second primary switch. SW P2 Third primary capacitor C P3 and the fourth primary capacitor C P4 Each unit in the 6-unit switched capacitor array within the core of the second oscillator includes a second-stage switch. SW S2 Third stage capacitor C S3 and the fourth primary capacitor C S4 Second transformer T 2 includes coupling coefficients of k 2 Second primary inductor L P2 and the second stage inductor L S2 .

[0032] Primary control voltage input terminal V C,P Respectively with the first primary variable capacitance tube C VAR,P1 One end, the second primary variable capacitance tube C VAR,P2 One end, the third primary variable capacitance tube C VAR,P3 One end and the fourth primary variable capacitance tube C VAR,P4 One end is connected to the secondary control voltage input terminal. V C,S With the first stage variable capacitance tube respectively C VAR,S1 One end, the second stage variable capacitance tube C VAR,S2 One end, the third stage variable capacitance tube C VAR,S3 One end and the fourth secondary variable capacitor tube C VAR,S4 One end is connected to the four-bit wide primary frequency modulation control signal input terminal BS. P [3:0] respectively with the first primary switch SW P1 Control terminal and second primary switch SW P2Connected to the control terminal, the first primary switch SW P1 The input and output terminals are respectively connected to the first primary capacitor. C P1 one end and the second primary capacitor C P2 One end is connected to the second primary switch. SW P2 The input and output terminals are respectively connected to the third primary capacitor. C P3 One end and the fourth primary capacitor C P4 One end is connected to the six-bit wide secondary frequency modulation control signal input terminal BS. S [5:0] respectively with the first-stage switch SW S1 Control terminal and secondary switch SW S2 Connected to the control terminal, primary switch SW S1 The input and output terminals are respectively connected to the first stage capacitor. C S1 One end and the secondary capacitor C S2 One end is connected to the second-stage switch. SW S2 The input and output terminals are respectively connected to the third stage capacitor. C S3 One end and the fourth secondary capacitor C S4 One end of the first NMOS transistor MN1 is connected to the power supply ground, and the drain of the first NMOS transistor MN1 is connected to the first transformer. T 1. First primary inductor L P1 positive end, second primary variable capacitance tube C VAR,P2 The other end, the second primary capacitor C P2 The other end and the negative terminal Φ of the first high-frequency differential clock signal output terminal － VCO,HF1 The gate of the first NMOS transistor MN1 is connected to the first transformer. T 1. First-stage inductor L S1 The negative terminal, the secondary variable capacitor tube C VAR,S2 The other end, the secondary capacitor C S2 The other end, the third stage capacitor C S3 The other end, the third stage variable capacitance tubeC VAR,S3 The other end, the second transformer T 2 Secondary inductor L S2 The positive terminal of the first PMOS transistor, the gate of the second PMOS transistor MP2, and the positive terminal Φ of the intermediate frequency differential clock signal output. + VCO,IF The source of the second PMOS transistor MP2 is connected to the power supply, and the drain of the second PMOS transistor MP2 is connected to the second transformer. T 2 Second primary inductor L P2 The negative terminal, the third primary variable capacitance tube C VAR,P3 The other end, the third primary capacitor C P3 The other end and the negative terminal of the second high-frequency differential clock signal output Φ － VCO,HF2 Connected.

[0033] The source of the second NMOS transistor MN2 is connected to the power supply ground, and the drain of the second NMOS transistor MN2 is connected to the second transformer. T 2 Second primary inductor L P2 positive end, fourth primary variable capacitance tube C VAR,P4 The other end, the fourth primary capacitor C P4 The other end and the positive terminal Φ of the second high-frequency differential clock signal output terminal + VCO,HF2 The gate of the second NMOS transistor MN2 is connected to the second transformer. T 2 Secondary inductor L S2 The negative terminal, the fourth secondary variable capacitor C VAR,S4 The other end, the fourth secondary capacitor C S4 The other end, the primary capacitor C S1 The other end, the first stage variable capacitance tube C VAR,S1 The other end, the first transformer T 1. First-stage inductor L S1 The positive terminal, the gate of the first PMOS transistor MP1, and the negative terminal Φ of the intermediate frequency differential clock signal output terminal. － VCO,IF The first PMOS transistor MP2 is connected to the power supply, and the drain of the first PMOS transistor MP1 is connected to the first transformer. T 1. First primary inductor LP1 The negative terminal, the first primary variable capacitor tube C VAR,P1 The other end, the first primary capacitor C P1 The other end and the positive terminal Φ of the first high-frequency differential clock signal output terminal + VCO,HF1 Connected.

[0034] In the operation of the multi-frequency output dual-core inverse F voltage-controlled oscillator, the first and second oscillating cores are synchronously frequency-modulated, but the primary and secondary resonant cavities can be controlled through the primary control voltage input terminal. V C,P With secondary control voltage input terminal V C,S and the primary frequency modulation control signal input terminal BS P [3:0] and secondary frequency modulation control signal input terminal BS S [5:0] Frequency modulation is performed under independent control. The secondary resonant cavities of the first and second oscillation cores are connected via DC coupling to ensure oscillation synchronization. The secondary resonant cavity can serve as a feedback signal for the phase-locked loop (PLL) for frequency synthesis. Simultaneously, the primary coils of the first and second oscillation cores output independently, controlling the current vector synthesis of the current vector synthesizer frequency multiplier to extract the second harmonic.

[0035] refer to Figure 3 The current vector synthesizer frequency multiplier includes a first differential clock signal input terminal Φ + FM,in1 and Φ － FM,in1 Second differential clock signal input terminal Φ + FM,in2 and Φ － FM,in2 First bias voltage signal input terminal V B1 Second bias voltage signal input terminal V B2 Φ high-frequency clock signal output terminal HF Fifth capacitor C 5. Sixth capacitor C 6. Seventh capacitor C 7. Eighth capacitor C 8. Ninth capacitor C 9. Tenth capacitor C 10 Eleventh capacitor C 11 12th capacitor C 12 13th capacitor C 13First resistor R 1. Second resistor R 2. Third resistor R 3. Fourth resistor R 4. Third NMOS transistor MN3, fourth NMOS transistor MN4, fifth NMOS transistor MN5, sixth NMOS transistor MN6, seventh NMOS transistor MN7, eighth NMOS transistor MN8, third transformer T Transformer 3 and 4 T 4; The third transformer T 3 includes coupling coefficients of k 3 First coupling coil L TX1 and the second coupling coil L TX2 Fourth transformer T 4. Including coupling coefficients of k 3's third coupling coil L TX3 and the fourth coupling coil L TX4 ; First bias voltage signal input terminal V B1 respectively with the first resistor R One end of 1, the second resistor R 2, one end, third resistor R One end of 3 and the fourth resistor R Connect one end of 4 to the positive terminal Φ of the first differential clock signal input. + VCO,HF1 With the fifth capacitor C One end of 5, the gate of the third NMOS transistor MN3, and the first resistor R The other end of 1 is connected to the negative terminal Φ of the first differential clock signal input. － VCO,HF1 With the sixth capacitor C One end of 6, the gate of the fourth NMOS transistor MN4, and the second resistor R The other end of 2 is connected to the positive terminal Φ of the second differential clock signal input. + VCO,HF2 With the eighth capacitor C One end of 8, the gate of the fifth NMOS transistor MN5, and the third resistor R The other end of 3 is connected to the negative terminal Φ of the second differential clock signal input. － VCO,HF2 With the ninth capacitor C One end of 9, the gate of the sixth NMOS transistor MN6, and the fourth resistor RThe other end of 4 is connected, and the sources of the third NMOS transistor MN3, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5, and the sixth NMOS transistor MN6 are all connected to the power supply ground. The drain of the third NMOS transistor MN3 is connected to the sixth capacitor. C The other end of 6, the seventh capacitor C One end of 7, the tenth capacitor C 10 One end, the ninth capacitor C The other end of 9, the third transformer T The first coupling coil in 3 L TX1 The positive terminal of the capacitor is connected to the drain of the fifth NMOS transistor MN5, and the drain of the fourth NMOS transistor MN4 is connected to the fifth capacitor. C The other end of 5, the seventh capacitor C The other end of 7, the eighth capacitor C The other end of 8, the tenth capacitor C 10 The other end, the third transformer T The first coupling coil in 3 L TX1 The negative terminal of the third transformer is connected to the drain of the sixth NMOS transistor MN6. T The second coupling coil in 3 L TX2 The center tap terminal and the second bias voltage signal input terminal V B2 Connected, third transformer T The first coupling coil in 3 L TX1 The center tap is connected to the power supply, and the third transformer... T The second coupling coil in 3 L TX2 The positive terminal is connected to the gate of the seventh NMOS transistor MN7 and the eleventh capacitor. C 11 One end is connected to the third transformer. T 3 Second coupling coil L TX2 The negative terminal is connected to the gate of the eighth NMOS transistor MN8 and the twelfth capacitor. C 12 One end is connected to the ground, and the source of the seventh NMOS transistor MN7 and the source of the eighth NMOS transistor MN8 are both connected to the power supply ground. The drain of the seventh NMOS transistor MN7 is connected to the twelfth capacitor. C 12 The other end, thirteen capacitors C 13 One end and the fourth transformer T The third coupling coil in 3 LTX3 The positive terminal is connected to the eleventh capacitor, and the drain of the eighth NMOS transistor MN8 is connected to the eleventh capacitor. C 11 The other end, thirteen capacitors C 13 The other end and the fourth transformer T The third coupling coil in 3 L TX3 The negative terminal is connected to the fourth transformer. T The third coupling coil in 4 L TX3 The center tap is connected to the power supply; the fourth transformer... T The fourth coupling coil in 4 L TX4 The positive terminal and the high-frequency clock signal output terminal Φ HF Connected, fourth transformer T 4. Fourth coupling coil L TX4 The negative terminal is connected to the power ground.

[0036] The current vector synthesizer frequency multiplier converts the voltage values ​​of two sets of differential clock signals into vector currents, then synthesizes them, and finally amplifies them for output. Because Φ + FM,in1 With Φ + FM,in2 , and Φ － FM,in1 With Φ － FM,in2 The second harmonic in the signal is in phase, and the two signals superimpose during current synthesis. However, the fundamental frequency is 180° out of phase, so they cancel each other out during current synthesis. Therefore, the current vector synthesizer frequency multiplier achieves frequency doubling while suppressing the fundamental signal.

[0037] refer to Figure 4 The time-domain waveform diagram shows that the input signal of the quadrature ÷ 2 frequency divider circuit is the intermediate frequency differential clock signal Φ of the multi-frequency output dual-core inverse F voltage-controlled oscillator. + VCO,IF and Φ － VCO,IF The output signal of the quadrature ÷ 2 frequency divider circuit is four clock signals with a period twice that of the input signal, and the output signal Φ LF,I With Φ LF,Q Φ LF,Q With Φ LF,IB Φ LF,IB With Φ LF,QB Φ LF,QB With Φ LF,I The phase difference between them is π / 2, that is, the four output signals are orthogonal four-phase low-frequency clock signals.

[0038] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and disclosure of the invention. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the following claims.

[0039] It should be understood that the present invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

[0040] The above description is merely a preferred embodiment of the present invention and does not constitute any limitation on the present invention. Any simple modifications, alterations, or equivalent structural changes made to the above embodiments based on the technical essence of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A voltage-controlled frequency source with embedded current vector synthesis frequency multiplication, characterized in that, Including the high-frequency clock signal output terminal (Φ) HF ), intermediate frequency clock signal output terminal (Φ IF Orthogonal four-phase low-frequency clock signal output terminal (Φ LF,I Φ LF,Q Φ LF,IB and Φ LF,QB Multi-frequency output dual-core inverse F voltage-controlled oscillator, current vector synthesis frequency multiplier, differential-single-ended output buffer and quadrature ÷ 2 frequency divider; The intermediate frequency differential clock signal output terminal (Φ) of the multi-frequency output dual-core inverse F voltage-controlled oscillator + VCO,IF and Φ － VCO,IF The differential clock input of the differential-single-ended output buffer and the differential clock input of the quadrature ÷ 2 divider are connected. The output of the differential-single-ended output buffer is connected to the intermediate frequency clock signal output (Φ). IF The four-phase outputs of the quadrature ÷ 2 divider are connected to the quadrature four-phase low-frequency clock signal outputs (Φ). LF,I Φ LF,Q Φ LF,IB and Φ LF,QB The corresponding phase connections in the multi-frequency output dual-core inverse F voltage-controlled oscillator (Φ) are connected to the first high-frequency differential clock signal output terminal. + VCO,HF1 and Φ － VCO,HF1 ) and the second high-frequency differential clock signal output terminal (Φ + VCO,HF2 and Φ － VCO,HF2 ) respectively connected to the first differential clock signal input terminal (Φ) of the current vector synthesizer frequency multiplier + FM,in1 and Φ － FM,in1 ) and the second differential clock signal input terminal (Φ + FM,in2 and Φ － FM,in2 The current vector synthesizer frequency multiplier is connected to the high-frequency clock signal output terminal (Φ). HF ) are connected.

2. The voltage-controlled frequency source with embedded current vector synthesis frequency multiplication according to claim 1, characterized in that, It also includes the first capacitor ( C 1) Second capacitor ( C 2) Third capacitor ( C 3) and the fourth capacitor ( C 4); The first high-frequency differential clock signal output terminal (Φ) of the multi-frequency output dual-core inverse F voltage-controlled oscillator + VCO,HF1 and Φ － VCO,HF1 ) and the second high-frequency differential clock signal output terminal (Φ + VCO,HF2 and Φ － VCO,HF2 ) respectively with the first capacitor ( C 1) One end, the second capacitor ( C 2) One end, the third capacitor ( C 3) one end and the fourth capacitor ( C 4) is connected to one end, the first capacitor ( C 1) at the other end and the second capacitor ( C 2) The other end is connected to the first differential clock signal input terminal (Φ) of the current vector synthesizer frequency multiplier. + FM,in1 and Φ － FM,in1 ) connected together, the third capacitor ( C 3) at the other end and the fourth capacitor ( C 4) The other end is connected to the second differential clock signal input terminal (Φ) of the current vector synthesizer frequency multiplier. + FM,in2 and Φ － FM,in2 ) are connected.

3. The voltage-controlled frequency source with embedded current vector synthesis frequency multiplication according to claim 2, characterized in that, It also includes the primary control voltage input terminal ( V C,P Secondary control voltage input terminal ( V C,S ), Four-bit wide primary frequency modulation control signal input terminal (BS) P [3:0]) and six-bit wide secondary frequency modulation control signal input terminal (BS) S [5:0]); The first and second voltage input terminals of the multi-frequency output dual-core inverse F voltage-controlled oscillator are respectively connected to the primary control voltage input terminal ( V C,P and secondary control voltage input terminal ( V C,S The first and second frequency modulation signal control input terminals of the multi-frequency output dual-core inverse F voltage-controlled oscillator are connected to the four-bit wide primary frequency modulation control signal input terminal (BS). P [3:0]) and six-bit wide secondary frequency modulation control signal input terminal (BS) S [5:0]) are connected.

4. The voltage-controlled frequency source with embedded current vector synthesis frequency multiplication according to claim 3, characterized in that, It also includes the first bias voltage input terminal ( V B1 and the second bias voltage input terminal ( V B2 ); The first bias voltage input terminal and the second bias voltage input terminal of the current vector synthesizer frequency multiplier are respectively connected to the first bias voltage input terminal ( V B1 and the second bias voltage input terminal ( V B2 ) are connected.

5. The voltage-controlled frequency source with embedded current vector synthesis frequency multiplication according to claim 4, characterized in that, The multi-frequency output dual-core inverse F voltage-controlled oscillator includes a primary control voltage input terminal ( V C,P Secondary control voltage input terminal ( V C,S ), four-bit wide primary frequency modulation control signal input terminal (BS) P [3:0]), six-bit wide secondary frequency modulation control signal input terminal (BS) S [5:0]), intermediate frequency differential clock signal output terminal (Φ + VCO,IF and Φ － VCO,IF ), First high-frequency differential clock signal output terminal (Φ + VCO,HF1 and Φ － VCO,HF1 ), second high-frequency differential clock signal output terminal (Φ + VCO,HF2 and Φ － VCO,HF2 ), first oscillation core, second oscillation core; The core of the first oscillator includes a first primary variable capacitance tube ( C VAR,P1 ), second primary variable capacitance tube ( C VAR,P2 ), primary variable capacitance tube ( C VAR,S1 ), Secondary variable capacitance tube ( C VAR,S2 ), First PMOS transistor (MP1), First NMOS transistor (MN1), First transformer ( T 1) A 4-unit switched capacitor array and a 6-unit switched capacitor array; Among them, each unit in the 4-unit switched capacitor array in the core of the first oscillator includes a first primary switch ( SW P1 ), first primary capacitor ( C P1 ), second primary capacitor ( C P2 Each cell in the 6-cell switched capacitor array includes a first-stage switch ( SW S1 ), primary capacitor ( C S1 ), secondary capacitor ( C S2 ), First Transformer ( T 1) Including coupling coefficients of k 1's first primary inductance ( L P1 ) and primary inductor ( L S1 ); The core of the second oscillator includes a third primary variable capacitance tube ( C VAR,P3 ), fourth primary variable capacitance tube ( C VAR,P4 ), third-stage variable capacitance tube ( C VAR,S3 ), fourth secondary variable capacitance tube ( C VAR,S4 ), second PMOS transistor (MP2), second NMOS transistor (MN2), second transformer ( T 2) A 4-unit switched capacitor array and a 6-unit switched capacitor array; Among them, each unit in the four-unit switched capacitor array within the core of the second oscillator includes a second primary switch ( SW P2 ), third primary capacitor ( C P3 ) and the fourth primary capacitor ( C P4 The core of the second oscillator contains a 6-unit switched capacitor array, each unit of which includes a second-stage switch. SW S2 ), third-stage capacitor ( C S3 ) and the fourth primary capacitor ( C S4 ), second transformer ( T 2) Including coupling coefficients of k 2. The second primary inductor ( L P2 ) and secondary inductor ( L S2 ); Primary control voltage input terminal ( V C,P ) respectively with the first primary variable capacitance tube ( C VAR,P1 One end of the second primary variable capacitance tube () C VAR,P2 One end of the third primary variable capacitance tube () C VAR,P3 One end of the fourth primary variable capacitance tube and the fourth primary variable capacitance tube C VAR,P4 One end is connected to the secondary control voltage input terminal ( V C,S ) respectively with the first stage variable capacitance tube ( C VAR,S1 One end of the second-stage variable capacitance tube () C VAR,S2 One end of the third-stage variable capacitance tube () C VAR,S3 One end of the fourth secondary variable capacitance tube () C VAR,S4 Connect one end to the primary frequency modulation control signal input terminal (BS) P [3:0]) respectively with the first primary switch ( SW P1 The control terminal and the second primary switch () SW P2 Connected to the control terminal of ), the first primary switch ( SW P1 The input and output terminals of ) are respectively connected to the first primary capacitor ( C P1 One end of the capacitor and the second primary capacitor ( C P2 One end of the primary switch is connected to the second primary switch. SW P2 The input and output terminals of ) are respectively connected to the third primary capacitor ( C P3 One end of the capacitor and the fourth primary capacitor ( C P4 Connect one end to the ) and the six-bit wide secondary frequency modulation control signal input terminal (BS) S [5:0]) respectively with the first-stage switch ( SW S1 The control terminal and secondary switch () SW S2 Connected to the control terminal of the primary switch ( SW S1 The input and output terminals of ) are respectively connected to the first stage capacitor ( C S1 One end of the capacitor and the second stage capacitor ( C S2 Connect one end of the secondary switch to the first-stage switch. SW S2 The input and output terminals of ) are respectively connected to the third stage capacitor ( C S3 One end of the capacitor and the fourth secondary capacitor ( C S4 One end of the first NMOS transistor (MN1) is connected to the power supply ground, and the drain of the first NMOS transistor (MN1) is connected to the first transformer (MN1). T 1) The first primary inductor ( L P1 The positive end of the second primary variable capacitance tube () C VAR,P2 The other end of the second primary capacitor () C P2 The other end of the first high-frequency differential clock signal output terminal (Φ) and the negative terminal of the first high-frequency differential clock signal output terminal. － VCO,HF1 The gate of the first NMOS transistor (MN1) is connected to the gate of the first transformer (MN1). T 1) The first intermediate inductor ( L S1 The negative terminal of the second-stage variable capacitance tube () C VAR,S2 The other end of the capacitor ( ) and the second stage capacitor ( ) C S2 The other end of the third stage capacitor () C S3 The other end of the third-stage variable capacitance tube ( C VAR,S3 The other end of the second transformer () T 2) Secondary inductor ( L S2 The positive terminal of the first PMOS transistor (MP2), the gate of the second PMOS transistor (MP2), and the positive terminal of the intermediate frequency differential clock signal output (Φ) + VCO,IF The second PMOS transistor (MP2) is connected to the power supply, and the drain of the second PMOS transistor (MP2) is connected to the second transformer. T 2) The second primary inductor ( L P2 The negative end of the third primary variable capacitance tube () C VAR,P3 The other end of the third primary capacitor () C P3 The other end of the second high-frequency differential clock signal output terminal (Φ) and the negative terminal of the second high-frequency differential clock signal output terminal. － VCO,HF2 Connected to each other; The source of the second NMOS transistor (MN2) is connected to the power supply ground, and the drain of the second NMOS transistor (MN2) is connected to the second transformer (…). T 2) The second primary inductor ( L P2 The positive end of the fourth primary variable capacitance tube () C VAR,P4 The other end of the fourth primary capacitor () C P4 The other end of the second high-frequency differential clock signal output terminal (Φ) and the positive terminal of the second high-frequency differential clock signal output terminal. + VCO,HF2 The gate of the second NMOS transistor (MN2) is connected to the gate of the second transformer (MN2). T 2) Secondary inductor ( L S2 The negative terminal of the fourth secondary variable capacitor () C VAR,S4 The other end of the capacitor is the fourth secondary capacitor. C S4 The other end of the capacitor is the primary capacitor. C S1 The other end of the first stage variable capacitance tube ( C VAR,S1 The other end of the first transformer () T 1) The first intermediate inductor ( L S1 The positive terminal of the first PMOS transistor (MP1), the gate of the first PMOS transistor (MP1), and the negative terminal of the intermediate frequency differential clock signal output (Φ) － VCO,IF The first PMOS transistor (MP2) is connected to the power supply, and the drain of the first PMOS transistor (MP1) is connected to the first transformer. T 1) The first primary inductor ( L P1 The negative terminal of the first primary variable capacitance tube () C VAR,P1 The other end of the first primary capacitor () C P1 The other end of the first high-frequency differential clock signal output terminal (Φ) and the positive terminal of the first high-frequency differential clock signal output terminal. + VCO,HF1 ) are connected.

6. The voltage-controlled frequency source with embedded current vector synthesis frequency multiplication according to claim 5, characterized in that, When the multi-frequency output dual-core inverse F voltage-controlled oscillator is working, the first oscillation core and the second oscillation core are synchronously frequency-modulated; the secondary resonant cavities of the first oscillation core and the second oscillation core are connected by DC coupling.

7. The voltage-controlled frequency source with embedded current vector synthesis frequency multiplication according to claim 5, characterized in that, The primary coils of the first and second oscillation cores output independently, controlling the current vector synthesis of the current vector synthesizer frequency multiplier to extract the second harmonic.

8. The voltage-controlled frequency source with embedded current vector synthesis frequency multiplication according to claim 4, characterized in that, The current vector synthesizer frequency multiplier includes a first differential clock signal input terminal (Φ). + FM,in1 and Φ － FM,in1 ), second differential clock signal input terminal (Φ + FM,in2 and Φ － FM,in2 ), first bias voltage signal input terminal ( V B1 ), second bias voltage signal input terminal ( V B2 ), high-frequency clock signal output terminal (Φ HF ), fifth capacitor ( C 5) The sixth capacitor ( C 6) Seventh capacitor ( C 7) Eighth capacitor ( C 8) Ninth capacitor ( C 9) Tenth capacitor ( C 10 ), Eleventh capacitor ( C 11 ), the twelfth capacitor ( C 12 ), the thirteenth capacitor ( C 13 ), first resistor ( R 1) Second resistor ( R 2) Third resistor ( R 3) Fourth resistor ( R 4) Third NMOS transistor (MN3), fourth NMOS transistor (MN4), fifth NMOS transistor (MN5), sixth NMOS transistor (MN6), seventh NMOS transistor (MN7), eighth NMOS transistor (MN8), third transformer ( T 3) and the fourth transformer ( T 4); The third transformer ( T 3) Including coupling coefficients of k 3's first coupling coil ( L TX1 ) and the second coupling coil ( L TX2 ), Fourth Transformer ( T 4) Including coupling coefficients of k The third coupling coil of 3 ( L TX3 ) and the fourth coupling coil ( L TX4 ); First bias voltage signal input terminal ( V B1 ) respectively with the first resistor ( R 1) One end, the second resistor ( R 2) One end, the third resistor ( R 3) one end and the fourth resistor ( R 4) is connected to one end, and the positive terminal (Φ) of the first differential clock signal input is connected to the other end. + VCO,HF1 ) and the fifth capacitor ( C 5) one end, the gate of the third NMOS transistor (MN3) and the first resistor ( R 1) is connected to the other end, the negative terminal (Φ) of the first differential clock signal input terminal. － VCO,HF1 ) and the sixth capacitor ( C 6) one end, the gate of the fourth NMOS transistor (MN4) and the second resistor ( R 2) is connected to the other end, and the positive terminal (Φ) of the second differential clock signal input is connected to it. + VCO,HF2 ) and the eighth capacitor ( C 8) one end, the gate of the fifth NMOS transistor (MN5) and the third resistor ( R 3) is connected to the other end, and the negative terminal (Φ) of the second differential clock signal input is connected to it. － VCO,HF2 ) and the ninth capacitor ( C 9) one end, the gate of the sixth NMOS transistor (MN6) and the fourth resistor ( R 4) The other end is connected, and the source of the third NMOS transistor (MN3), the source of the fourth NMOS transistor (MN4), the source of the fifth NMOS transistor (MN5), and the source of the sixth NMOS transistor (MN6) are all connected to the power supply ground. The drain of the third NMOS transistor (MN3) is connected to the sixth capacitor ( C The other end of 6), the seventh capacitor ( C 7) one end, tenth capacitor ( C 10 One end of the capacitor, the ninth capacitor ( C 9) at the other end, the third transformer ( T 3) The first coupling coil ( L TX1 The positive terminal of the fourth NMOS transistor (MN4) is connected to the drain of the fifth NMOS transistor (MN5), and the drain of the fifth NMOS transistor (MN4) is connected to the positive terminal of the fifth capacitor (MN5). C 5) at the other end, the seventh capacitor ( C 7) at the other end, the eighth capacitor ( C The other end of 8), the tenth capacitor ( C 10 The other end of the third transformer () T 3) The first coupling coil ( L TX1 The negative terminal of the third transformer (MN6) is connected to the drain of the sixth NMOS transistor (MN6). T 3) The second coupling coil ( L TX2 The center tap of the second bias voltage signal input terminal is connected to the center tap of the second bias voltage signal input terminal. V B2 Connected to the third transformer () T 3) The first coupling coil ( L TX1 The center tap of the third transformer is connected to the power supply. T 3) The second coupling coil in ( L TX2 The positive terminal of ) is connected to the gate of the seventh NMOS transistor (MN7) and the eleventh capacitor ( C 11 Connect one end of the transformer to the third transformer. T 3) The second coupling coil ( L TX2 The negative terminal of ) is connected to the gate of the eighth NMOS transistor (MN8) and the twelfth capacitor ( C 12 One end of the transistor is connected to the ground, the source of the seventh NMOS transistor (MN7) and the source of the eighth NMOS transistor (MN8) are both connected to the power supply ground, and the drain of the seventh NMOS transistor (MN7) is connected to the twelfth capacitor (MN8). C 12 The other end of the capacitor (13 capacitors) C 13 One end of the fourth transformer and the fourth transformer T 4) The third coupling coil ( L TX3 The positive terminal of the eighth NMOS transistor (MN8) is connected to the positive terminal of the eleventh capacitor. C 11 The other end of the capacitor (13 capacitors) C 13 The other end of the fourth transformer and the fourth transformer T 4) The third coupling coil ( L TX3 Connect the negative terminal of the fourth transformer to the negative terminal. T 4) The third coupling coil ( L TX3 The center tap of the fourth transformer is connected to the power supply. T 4) The fourth coupling coil ( L TX4 The positive terminal of ) and the high-frequency clock signal output terminal (Φ) HF Connected to the fourth transformer () T 4) The fourth coupling coil ( L TX4 The negative terminal of the circuit is connected to the power ground.

9. The voltage-controlled frequency source with embedded current vector synthesis frequency multiplication according to claim 8, characterized in that, The current vector synthesizer frequency multiplier converts the voltage values ​​of two sets of differential clock signals into vector currents, which are then synthesized and amplified before being output.

10. The voltage-controlled frequency source with embedded current vector synthesis frequency multiplication according to claim 4, characterized in that, The input signal of the quadrature ÷ 2 frequency divider circuit is the intermediate frequency differential clock signal (Φ) of the multi-frequency output dual-core inverse F voltage-controlled oscillator. + VCO,IF and Φ － VCO,IF The output signal of the quadrature ÷ 2 divider circuit is a clock signal with a period twice that of the input signal.

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