Hybrid decoder architecture design method and system based on special nodes

Abstract

The invention discloses a polarization code hybrid decoding system based on special nodes. The polarization code hybrid decoding system is composed of a storage module, a calculation module, a controller and a decoding unit for executing Fast-SCL and Fast-DSCF algorithms. The system synchronously executes two types of algorithms: at a high signal-to-noise ratio, a Fast-DSCF and an early stop mechanism are utilized to reduce time delay; and the Fast-SCL is utilized to guarantee the performance under a low signal-to-noise ratio. According to the hardware architecture, the second unit adopts block storage and a two-stage assembly line for shallow nodes, operation resources of the first unit are multiplexed with low bandwidth, assembly line pause of Fast-SCL is effectively relieved, and area efficiency is improved. In addition, the second unit optimizes the pass rate by generating a dynamic flipping set in parallel with a high-order flipping mechanism. According to the scheme, high performance, low time delay and high area efficiency are considered.

Description

Technical Field

[0001] This invention belongs to the field of wireless communication technology, specifically the field of channel coding, and particularly relates to a hybrid decoder architecture design method and system based on special nodes. Background Technology

[0002] Polar coding is a channel coding technique and the first coding scheme rigorously mathematically proven to achieve the required channel capacity. Due to its high performance and low complexity, polar coding was selected in 2016 as the coding scheme for control channels in 5G Enhanced Mobile Broadband scenarios. In communication systems, channel coding techniques can effectively combat channel interference and ensure reliable transmission of information data to the receiving end.

[0003] Research on polar code decoding algorithms mainly focuses on two objectives: improving decoding performance and reducing decoding complexity and latency while maintaining performance. Arikan's Successive-Cancellation (SC) algorithm is low in complexity and easy to implement, but its serial decoding mechanism is prone to error propagation; that is, an error in one decoding step will affect all subsequent decoding processes. To overcome this shortcoming, researchers have successively proposed several improved algorithms, such as the Successive-Cancellation List (SCL) algorithm and the Cyclic Redundancy Check-Aided SCL (CA-SCL) algorithm, which significantly improve the decoding performance of polar codes with short to medium code lengths.

[0004] However, the aforementioned algorithms still have shortcomings in terms of decoding latency, throughput, and hardware implementation complexity. To further improve decoding performance under finite code lengths, the Successive Cancellation Flip (SC-Flip) algorithm was proposed. Its core idea is to flip key bits after detecting a decoding error to block error propagation. The subsequently proposed Dynamic Flip (D-SCF) algorithm introduces a higher-order bit flipping strategy, further optimizing error correction performance.

[0005] To reduce computational complexity, the mainstream approach is to deploy parallel decoding units at the intermediate nodes of the SC decoding tree to estimate multiple bits simultaneously. Based on this idea, the Fast Serial Cancellation Dynamic Flip (Fast-DSCF) and Fast Serial Cancellation List (Fast-SCL) algorithms, based on special node structures, have been proposed in recent years, significantly reducing decoding computational complexity.

[0006] Different decoding algorithms have inherent differences in hardware resource consumption and processing latency. Therefore, a hybrid decoder architecture that can combine the advantages of different decoding algorithms is a powerful way to improve decoder performance. Summary of the Invention

[0007] Given the shortcomings of existing technologies in terms of decoding latency, throughput, and hardware implementation complexity, this invention aims to provide a polar code decoding scheme that achieves high-performance decoding while maintaining low latency and high area efficiency. Specifically, it improves decoding efficiency by synergistically utilizing the advantages of different decoding algorithms and enhances area efficiency by employing a hardware architecture with shared computing units, thereby increasing the decoding throughput per unit area.

[0008] To achieve the above objectives, this invention provides a polar code hybrid decoding method based on special nodes, the method comprising the following steps: S1 initialization steps: Input the channel log-likelihood ratio and special node identification command, calculate the log-likelihood ratio of the nodes in the decoding tree up to the position of the first special node, and copy the calculated log-likelihood ratio to the log-likelihood ratio storage module of the first decoding unit and the second decoding unit; S2 Parallel Decoding Steps: The first decoding unit and the second decoding unit are started simultaneously; wherein, the first decoding unit is configured to execute the Fast Serial Cancellation List (Fast-SCL) decoding algorithm to ensure decoding performance under low signal-to-noise ratio, and the second decoding unit is configured to execute the Fast Dynamic Serial Cancellation Flip (Fast-DSCF) decoding algorithm to reduce decoding latency under high signal-to-noise ratio with an early stopping mechanism, and the initial decoding cycle flip set of the second decoding unit is empty; wherein, the log-likelihood ratio of the nodes with the smallest depth in the decoding tree of the second decoding unit adopts a block storage structure and a two-stage pipeline calculation method, so that the large-scale computing units in the computing unit module corresponding to the first decoding unit can be reused with lower input data bandwidth; S3 Result Monitoring and Output: Monitor the decoding completion status of the first decoding unit and the second decoding unit; if the first decoding unit completes the decoding cycle, output its decoding result and end decoding; if the second decoding unit completes the current decoding cycle first, perform cyclic redundancy check (CRC) on its decoding result; if the check passes, output the decoding result of the second decoding unit and end decoding; if the check fails, determine whether its flip count has reached the preset maximum flip count; if it has not reached the maximum, generate a new flip set, restart the second decoding unit, and return to the step of monitoring the decoding completion status of the first decoding unit and the second decoding unit; if it has reached the maximum, wait for the first decoding unit to complete and output its decoding result to end decoding.

[0009] Preferably, the block storage structure and the two-stage pipelined computing method specifically include: For the Nth layer decoding process, the log-likelihood ratio sequence, which has a quantity of 2^N, is divided into four parts and stored in four memory units. The log-likelihood ratio sequence calculation adopts a two-stage pipelined operation structure. The log-likelihood ratios from the four memory units of the Nth layer are continuously input into the two-stage pipelined operation unit array, and the resulting log-likelihood ratios are written into the memory units of the N-1 and N-2 layers respectively. With the same input data bandwidth, a 1.5 times computational throughput can be achieved.

[0010] Preferably, the process of the first decoding unit executing the Fast-SCL algorithm specifically includes: s3.1 The received channel log-likelihood ratio is stored in the channel log-likelihood ratio storage module, and the log-likelihood ratio sequence is calculated by the upper-layer node and passed to the lower-layer node until the special node level; s3.2 passes the node log-likelihood ratio sequence to the SCL node processor for decoding decision and path expansion based on the specific node type; s3.3 uses the path metric module to sort the expanded paths according to the path metric values ​​and retains the L paths with the lowest path metric values ​​in real time; s3.4 calculates the partial sum of the determined bit sequence and passes it to the upper-level node. It continues to calculate the log-likelihood ratio sequence from the upper-level node and pass it to the lower-level node, repeating the above process until all special nodes have completed the calculation.

[0011] Preferably, the process of the second decoding unit executing the Fast-DSCF algorithm specifically includes: The s4.1 received channel log-likelihood ratio is stored in the channel log-likelihood ratio storage module, and the log-likelihood ratio sequence is calculated by the upper-layer node and passed to the lower-layer node until the special node level; s4.2 passes the node log-likelihood ratio sequence to the SCF node processor, and performs decoding decisions based on the special node type and the flip flag; at the same time, it passes the node log-likelihood ratio sequence to the dynamic flip set generation module, calculates the flip metric value based on the special node type, and updates the flip set queue. s4.3 calculates the determined bit sequence to the child node and outputs it to the decoding result storage module. At the same time, it uses the partial sum calculation module to calculate the partial sum bit sequence passed from the lower node to the upper node and passes it to the upper node. It continues to calculate the log likelihood ratio sequence from the upper node and pass it to the lower node until all special nodes have completed the calculation, and then ends the current decoding cycle. s4.4 Determine whether the CRC check result of the decoding result passes. If it passes, output the decoding result and terminate the decoding process. If it fails, select the set with the smallest metric value from the dynamically generated flip set as the new current flip set, start the next round of decoding, until the CRC check passes or the preset maximum number of flip rounds has been reached.

[0012] Preferably, the generation of the new flip set includes performing dynamic flip set generation in parallel during the decoding process of the second decoding unit; The dynamic flip set generation specifically includes: s5.1 Input the node position ID, node type, and node log-likelihood ratio sequence of the special node being decoded, add the node position ID to the current flip set to generate a new set, and calculate the metric of the new set according to the node type; s5.2 Based on the comparison between the measure of the new set and the maximum measure in the flipped set queue, determine whether to overwrite the set with the maximum measure in the queue with the new set; s5.3 sorts the updated queues according to the metric values ​​to obtain the queue position information and metric values ​​corresponding to the set of maximum and minimum metric values. The above process is repeated until all special nodes in the current decoding cycle are decoded. s5.4 When a decoding cycle is completed, the set with the smallest metric value is selected as the new current flip set. All bits of the metric value corresponding to the set with the smallest metric value in the queue are set to a specific value, and the next round of decoding is started.

[0013] The present invention also provides a polar code hybrid decoding system based on special nodes, characterized in that it includes: The log-likelihood ratio storage module is configured to store the channel log-likelihood ratio and the log-likelihood ratio of nodes during the decoding process; The computation unit module is configured to compute the log-likelihood ratio sequence passed from the upper-level node to the lower-level node; The instruction storage module is configured to pre-store special node type identification instructions, which are provided to the first decoding unit and the second decoding unit for the node type of the special node being decoded. The controller is configured to control the access to and decoding process of the first decoding unit and the second decoding unit to the shared resources, monitor the decoding status of the first decoding unit and the second decoding unit, and select the output decoded codeword according to the decoding status. The first decoding unit is configured to execute the Fast-SCL decoding algorithm; The second decoding unit is configured to execute the Fast-DSCF decoding algorithm; The shared resources accessed by the first decoding unit and the second decoding unit include: a log-likelihood ratio storage module, a computation unit module, and an instruction storage module.

[0014] Preferably, the first decoding unit and the second decoding unit specifically include the following functional modules: The SCL node processor, belonging to the first decoding unit, is configured to complete the special node decoding process in the Fast-SCL decoding algorithm, and to perform decoding decisions and path expansion based on the special node type. The PM module, or path metric module, belongs to the first decoding unit and is configured to sort the expanded paths according to the path metric value and retain the L paths with the lowest path metric value in real time. The SCF node processor, belonging to the second decoding unit, is configured to complete the special node decoding process in the Fast-DSCF decoding algorithm and make decoding decisions based on the special node type and whether the flip flag is toggled. The dynamic flip set generation module, belonging to the second decoding unit, is configured to generate a new flip set and calculate a metric value after decoding a special node, determine whether to add it to the flip set queue, and select the flip set for the next round of decoding after the decoding cycle ends. The PSUM module, or Partial Sum Calculation Module, is configured to compute the codeword sequence passed from the lower-level node to the upper-level node. The decoding result storage module is configured to temporarily store candidate decoded codewords generated by the first decoding unit and the second decoding unit, which are to be selected and output by the controller. The CRC check module is configured to perform CRC checks on the decoded codewords.

[0015] Preferably, the system is capable of identifying and processing special nodes, which are nodes with special information bit and frozen bit distribution patterns, and can perform parallel decoding directly at intermediate nodes. The types of special nodes include: Rate-0 node: All bits are frozen bits; Rate-1 node: All bits are information bits; REP node: Only the last bit is an information bit, the rest are frozen bits; SPC node: Only the first bit is a frozen bit, the rest are information bits; ML nodes: Nodes in the remaining distribution pattern; The SCL node processor, SCF node processor, and dynamic flip set generation module all perform corresponding calculations and decisions based on the aforementioned special node types.

[0016] The present invention also provides a decoding apparatus, comprising: a memory; and a processor coupled to the memory, the processor being configured to execute, based on instructions stored in the memory, the polar code hybrid decoding method based on special nodes as described above.

[0017] The present invention also provides a computer-readable storage medium storing computer instructions that, when executed by a processor, implement the polar code hybrid decoding method based on special nodes as described above.

[0018] Compared with the prior art, the present invention has the following advantages: 1. The hybrid decoder architecture design method and system based on special nodes proposed in this invention can fully integrate the advantages of Fast-SCL and Fast-DSCF decoding algorithms to achieve high-performance decoding of polar codes, balancing low latency and high decoding performance. Under high signal-to-noise ratio conditions, the Fast-DSCF decoding algorithm obtains the correct decoding result with no or few flips, and achieves lower decoding latency through an early stopping mechanism; under low signal-to-noise ratio conditions, the Fast-SCL algorithm ensures the decoding performance of the decoder.

[0019] 2. In this invention, the log-likelihood ratio of several layers of nodes with the lowest depth in the decoding tree is calculated using a block storage structure and a two-stage pipeline method. As a result, the second decoding unit can share the large-area operation unit in the corresponding calculation unit module of the first decoding unit with a lower input data bandwidth, thereby reducing the decoding latency of the second decoding unit. At the same time, it realizes the interleaving and multiplexing of operation units, solves the pipeline stall problem in the Fast-SCL decoder, and improves area efficiency.

[0020] 3. This invention utilizes a special node decoding principle, using a node processor to directly perform parallel decoding at the intermediate nodes of the decoding tree, which significantly improves the decoder throughput.

[0021] 4. In the Fast-DSCF decoding process, the present invention performs dynamic flip set generation in parallel, and uses a higher-order flip mechanism to improve the decoding pass rate of the second decoding unit. Attached Figure Description

[0022] Figure 1 This is a structural diagram of a polar code hybrid decoder based on special nodes provided by the present invention; Figure 2 This invention provides a decoding flowchart for a polar code hybrid decoder based on special nodes. Figure 3 This is a block diagram of the PE unit module in a polar code hybrid decoder based on special nodes provided by the present invention; Figure 4 This is a block diagram of the SCF node processor module in a polar code hybrid decoder based on special nodes provided by the present invention; Figure 5 This is a block diagram of the dynamic flip set generation module in a polar code hybrid decoder based on special nodes provided by the present invention; Figure 6This is a flowchart of the dynamic flip set generation process in a polar code hybrid decoder based on special nodes provided by the present invention; Figure 7 This is a schematic diagram of the block storage and two-stage pipelined computation process in a polar code hybrid decoder based on special nodes provided by the present invention; Detailed Implementation The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0023] Example 1 This embodiment aims to provide a specific, parameterized application scenario to verify the feasibility and technical effectiveness of the "polar code hybrid decoding method and system based on special nodes" proposed in this invention.

[0024] Parameter settings The polar code length N is 1024, the code rate is 0.5, the CRC concatenation length is 24, and the special node length DN=4. The log-likelihood ratio quantization of the input decoder is a 6-bit signed number, and the number of paths in the Fast-SCL decoding algorithm is L=4.

[0025] like Figure 2 As shown, a method for designing a polar code hybrid decoder architecture based on special nodes includes the following steps: S1 initialization steps: Input the channel log-likelihood ratio and special node identification command, calculate the log-likelihood ratio of the nodes in the decoding tree up to the position of the first special node, and copy the log-likelihood ratio obtained in the calculation process to the log-likelihood ratio storage module of the first decoding unit and the second decoding unit; S2 Parallel Decoding Steps: Simultaneously start the first decoding unit and the second decoding unit. Configure the first decoding unit to execute the Fast-SCL algorithm and configure the second decoding unit to execute the Fast-DSCF algorithm. The initial decoding cycle flip set is empty, i.e., no flipping is performed. The log-likelihood ratio of the three-layer nodes with the smallest depth in the decoding tree of the second decoding unit adopts a block storage structure and a two-stage pipeline calculation method, so that the large-scale computing units in the computing unit module corresponding to the first decoding unit can be reused with lower input data bandwidth. S3 Result Monitoring and Output Steps: Monitor the decoding completion status of the first decoding unit and the second decoding unit; if the first decoding unit completes its decoding cycle, output its decoding result and end decoding; if the second decoding unit completes its current decoding cycle first, perform cyclic redundancy check (CRC) on its decoding result; if the check passes, output the decoding result of the second decoding unit and end decoding; if the check fails, determine whether its flip count has reached the preset maximum flip count; if it has not reached the maximum, generate a new flip set, restart the second decoding unit, and return to the step of monitoring the decoding completion status of the first decoding unit and the second decoding unit; if it has reached the maximum, wait for the first decoding unit to complete, output its decoding result, and end decoding.

[0026] like Figure 1 As shown, a method and system for designing a polar code hybrid decoder architecture based on special nodes is characterized by the following functional modules: The log-likelihood ratio storage module is used to store the channel log-likelihood ratio and the decoding process log-likelihood ratio; The computation unit module, composed of multiple PE computation units, is used to calculate the log-likelihood ratio sequence passed from the upper-level node to the lower-level node. For example... Figure 3 As shown, the PE unit is used to perform... function or Function, calculation formula: in the formula and They are respectively functions and The function's output value, which is the log-likelihood ratio passed from the upper-level node to the lower-level node; For the input log-likelihood ratio, the subscript is... and subscript The log-likelihood ratio input is used to distinguish between two different computation paths. Specifically refers to the computation path The log-likelihood of the input is greater than that of the input. Specifically refers to the computation path The log-likelihood ratio is greater than the input; This represents a symbolic function configured to extract the algebraic symbol from the input parameter. If the input parameter is greater than 0, it outputs 1; if the input parameter is less than 0, it outputs -1. This represents the minimum value function, which is configured to select the smallest value from a plurality of input values ​​as the output. The determined bit sequence; The instruction storage module is configured to pre-store special node type identification instructions, which are provided to the first decoding unit and the second decoding unit for the node type of the special node being decoded. The controller is configured to control the access to and decoding process of the first and second decoding units to the shared resources, monitor the decoding status of the first and second decoding units, and select the output decoded codewords according to the decoding status. The first decoding unit is configured to execute the Fast-SCL decoding algorithm; The second decoding unit is configured to execute the Fast-DSCF decoding algorithm; The shared resources accessed by the first decoding unit and the second decoding unit include: a log-likelihood ratio storage module, a computation unit module, and an instruction storage module.

[0027] The first decoding unit and the second decoding unit specifically include the following functional modules: The SCF node processor completes the special node decoding process in the Fast-DSCF decoding algorithm executed by the second decoding unit, and makes decoding decisions based on the special node type and whether the flip flag is toggled. The SCL node processor completes the special node decoding process in the Fast-SCL decoding algorithm executed by the first decoding unit, and performs decoding decisions and path expansion according to the special node type. The dynamic flip set generation module generates a new flip set and calculates the metric value after decoding a special node, determines whether to add it to the flip set queue, and selects the flip set for the next round of decoding after the decoding cycle ends. The PSUM module, a partial sum calculation module, is used to calculate the bit sequence passed from the lower-level node to the upper-level node; The PM module, or path metric module, is used to sort the expanded paths based on their path metric values ​​and retain the L paths with the lowest path metric values ​​in real time. The decoding result storage module is configured to temporarily store candidate decoded codewords generated by the first decoding unit and the second decoding unit, which are to be selected and output by the controller. The CRC check module is used to perform CRC checks on the decoded codewords.

[0028] The decoding process of the Fast-SCL decoding algorithm executed by the first decoding unit includes: The received channel log-likelihood ratio is stored in the channel log-likelihood ratio storage module, and the log-likelihood ratio sequence is calculated by the upper-layer node. And pass it to the lower-level node; When decoding reaches a specific node level, the node log-likelihood ratio sequence will be used. The path is passed to the first decoding unit, where a decoding decision is made based on the special node type. The path extension and path metric module sorts the path metric values ​​and selects the L paths with the lowest path metric values ​​in real time to retain them. For ease of expression, For the first The path processing number is the first The metric value at a specific node, with the subscript. This represents the sequence number corresponding to a special node in the decoding tree. This indicates the path's index in the list during list decoding; The function represents a hard-decision function, which determines the input parameter's sign based on the input parameter's sign. If the input parameter is greater than or equal to 0, the output is 0; if the input parameter is less than 0, the output is 1. For the serial number The log-likelihood ratio of special nodes in the path to the in-sequence index is The log-likelihood ratio; for Sort by size from smallest to largest The index of each element. For the serial number The log-likelihood of a special node in the path is greater than that of the first node in the sequence. Small log-likelihood ratio; and For the first The path metrics for the two new paths generated after path expansion are as follows, with the path metric formula for special nodes being: 1) For the Rate-0 node, Updated formula: 2) For a Rate-1 node, to ensure decoding performance, a minimum of (L-1) decoding iterations are required. and Iterative calculation formula: During the iteration process, one bit is processed per iteration, with the index k starting from 1. After each iteration, the index k is incremented by 1. The decoded bit sequence corresponding to the path is before iteration. The decoded bit sequence corresponding to the path, The decoded bit sequence corresponding to the path is the sequence before iteration. The index in the decoded bit sequence corresponding to the path The result after bit flipping; 3) For the REP node, for the first node in the list... The path is calculated to correspond to the decoded bit sequence as follows: Path metrics And corresponding to the decoded bit sequence are Path metrics Path metrics By using the hard decision function Compared with the log-likelihood, the absolute value The product from the subscript Start, to subscript The path metric is obtained by accumulating the results at the end. By analyzing the function Compared with the log-likelihood, the absolute value The product from the subscript Start, to subscript The result is obtained by accumulating the sums at the end. and Updated formula: 4) For SPC nodes, parity check flag The XOR operation is performed on the bits after hard decision of the input log-likelihood ratio sequence. The formula is as follows: Initialization process path metric The calculation formula is: To ensure decoding performance, the parity flag needs to be iteratively expanded and updated. The formulas for calculating the expanded path and updating the parity flag are as follows: During the iteration, one bit is processed per iteration; the index k starts from 2, and after one iteration, the index is... Add 1, after one iteration The decoded bit sequence corresponding to the path is before iteration. The decoded bit sequence corresponding to the path, The decoded bit sequence corresponding to the path is the sequence before iteration. The index in the decoded bit sequence corresponding to the path and index The result after flipping the bits simultaneously; The partial sum of the determined bit sequence is calculated and passed to the upper-level node, and the log-likelihood ratio sequence is calculated from the upper-level node and passed down to the lower-level node. This process is repeated until all special nodes have been decoded. Fast-SCL decoding is complete. The decoding result is output, and the decoder terminates the decoding process.

[0029] The decoding process of the Fast-DSCF decoding algorithm executed by the second decoding unit includes: The received channel log-likelihood ratio is stored in the channel log-likelihood ratio storage module, and the upper-layer node calculates the log-likelihood ratio sequence and passes it to the lower-layer node. like Figure 4 As shown, when decoding reaches the special node level, the node log-likelihood ratio sequence is passed to the second decoding unit. The bit sequence is obtained by making a decoding decision based on the special node type and whether the node is flipped. ; The function represents a hard decision function, defined as above; This is the parity check flag, defined as above; For special nodes, the log-likelihood ratio is the in-sequence index. The log-likelihood ratio; The decoding decision calculation formula is as follows: 1) For the Rate-0 node, 2) For the Rate-1 node, 3) For REP nodes, 4) For SPC nodes, in, This represents a function that searches for an index, configured to search from all candidate indices. In the middle, find the one that makes The specific index that yields the minimum value ; This is the bit decision value corresponding to index i in the bit sequence; 5) For ML nodes, in, These are the decision values ​​for the bits corresponding to indices 1 and 3 in the bit sequence. These are the bit decision values ​​corresponding to indices 2 and 4 in the bit sequence; Simultaneously, the node log-likelihood ratio sequence is passed to the dynamic flip set generation module, such as... Figure 5 As shown, the flip metric is calculated based on the special node type, and the decision on whether to add it to the flip set queue is based on the comparison between the flip metric and the largest flip metric in the current queue. For ease of expression, For the serial number The flip metric value corresponding to the special node, that is, the flip metric value calculated, compared and stored by the dynamic flip set generation module; This represents the metric value corresponding to a specific node, indicating the estimated change in path metric that would occur if the current node were flipped. This indicates that the serial number is The metric value corresponding to the special node; This refers to the bit position index or set of indices where the flipped bit is located when a special node bit is flipped. This is the parity check flag, defined as above; Same definition as above; For different special nodes, the metric values and the bit position index or index set of special node flip bits. The calculation formula is as follows: 1) Rate-0 nodes do not contain information bits and do not need to calculate the flip metric to participate in the flip.

[0030] 2) For Rate-1 nodes in, This represents a function that searches for the minimum value of the absolute value of the log-likelihood ratio among all candidate log-likelihood ratios. This represents a function that looks up an index, defined as above; 3) For REP nodes 4) For SPC nodes in, This represents the index corresponding to the absolute value of the smallest log-likelihood ratio. This represents the index corresponding to the absolute value of the second smallest log-likelihood ratio. This represents the absolute value of the smallest log-likelihood ratio. This represents the absolute value of the second smallest log-likelihood ratio; 5) For ML nodes Flip the metric The calculation formula is as follows: in, For the serial number The cumulative metric value of a special node is calculated by summing the metric values ​​of all flipped special nodes before the currently translated special node. For the serial number The cumulative approximate metric value of the special node is calculated by approximately accumulating the metric values ​​of the unflipped special nodes with smaller metric values ​​before the position of the currently translated special node. The process of approximately accumulating the metric values ​​of the unflipped special nodes with smaller metric values ​​is as follows: if the metric value is less than 5, then 3 / 2 is accumulated; if it is greater than or equal to 5, then no accumulation is performed. The determined bit sequence is calculated to the child node and output to the decoding result storage module. At the same time, the calculated part of the determined bit sequence is passed to the upper node, and the log-likelihood ratio sequence is calculated from the upper node and passed to the lower node. Repeat the above process until all special nodes are decoded; Determine if the CRC check result passes. If yes, output the decoding result of the second decoding unit and the decoder stops. If no, select the set with the smallest metric value as the new current flip set, start the next round of decoding, and repeat the above process until the decoder terminates or the specified maximum number of flips is reached.

[0031] The special node is a node with a special information bit and frozen bit distribution pattern, which can perform parallel decoding directly at intermediate nodes.

[0032] The special node types include: Rate-0: All bits are frozen bits; Rate-1: All bits are information bits; REP: Only the last bit is an information bit, the rest are frozen bits; SPC: Only the first bit is a frozen bit, and the rest are information bits; ML: Nodes in the remaining distribution pattern.

[0033] like Figure 6 As shown, the dynamic flip set generation method includes: Input the node position ID, node type, and node log-likelihood ratio sequence for the current decoding. Add the ID to the current flip set to generate a new set. Calculate the metric of the new set based on the node type. Based on the comparison between the new set's metric value and the maximum metric value in the flipped set queue, determine whether to overwrite the set with the maximum metric value in the queue with the new set. The updated queue is sorted according to the metric value to obtain the queue position information and metric value corresponding to the set of maximum and minimum metric values. The current decoding node position ID, node type and node LLR are input to wait for the next special node to complete the decoding. The above process is repeated until all special nodes in the current decoding cycle are decoded. When a decoding cycle is completed, the set with the smallest metric value is selected as the new current flip set, and all bits of the metric value corresponding to the set with the smallest metric value in the queue are set to 1, and the next round of decoding begins.

[0034] like Figure 7 As shown, the block storage structure and two-stage pipelined computation method divide the 2^N log-likelihood ratio sequence corresponding to the Nth layer decoding process into four parts and store them in four storage units. The log-likelihood ratio sequence calculation adopts a two-stage pipelined operation structure, continuously inputting the log-likelihood ratios from the four storage units of the Nth layer into the two-stage pipelined computation unit array. The resulting log-likelihood ratios are then written into the storage units of the N-1 and N-2 layers, respectively. With the same input data bandwidth, a 1.5 times computational throughput can be achieved.

[0035] Based on the same inventive concept, this disclosure also provides a polar code hybrid decoding system based on special nodes. The system includes: a log-likelihood ratio storage module, a computation unit module, a first decoding unit core module (including an SCL node processor and a PM module), a second decoding unit core module (including an SCF node processor and a dynamic flip set generation module), and a common processing module (PSUM module, decoding result storage module, and CRC check module).

[0036] The specific functions and connections of the above modules have been described in Example 1 and Figure 1 The architecture diagram provides a detailed description. For example, the specific method by which the second decoding unit and the first decoding unit multiplex the computing unit is the same as step S2 in Embodiment 1. Figure 7 The described "block storage structure and two-stage pipelined computation method" are consistent; the logic executed by the dynamic flip set generation module is consistent with the formulas described in Example 1. Figure 5 , Figure 6 The process is the same, so it will not be repeated here.

[0037] Furthermore, this embodiment also provides a polar code decoding device (e.g., an FPGA or ASIC chip), which includes a memory and a processor. The memory stores computer instructions and decoding process data (such as LLRs, flip sets, etc.), and the processor executes the instructions to implement any of the decoding method steps described in Embodiment 1 above.

[0038] This embodiment also provides a computer-readable storage medium storing computer instructions that, when executed by a processor, implement the decoding method described in Embodiment 1 above.

[0039] In this specification, the term "embodiment" refers to a specific feature, structure, material, or characteristic described in connection with that embodiment, which is included in at least one embodiment of the invention. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments. Moreover, those skilled in the art can combine and integrate the different embodiments described in this specification and the features of those different embodiments without contradiction.

[0040] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, unless otherwise explicitly specified.

[0041] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A special node-based polar code hybrid decoding method, characterized in that, include: S1 initialization steps: Input the channel log-likelihood ratio and special node identification command, calculate the log-likelihood ratio of the nodes in the decoding tree up to the position of the first special node, and copy the calculated log-likelihood ratio to the log-likelihood ratio storage module of the first decoding unit and the second decoding unit; S2 Parallel Decoding Steps: The first decoding unit and the second decoding unit are started simultaneously; wherein, the first decoding unit is configured to execute the Fast Serial Cancellation List (Fast-SCL) decoding algorithm to ensure decoding performance under low signal-to-noise ratio, and the second decoding unit is configured to execute the Fast Dynamic Serial Cancellation Flip (Fast-DSCF) decoding algorithm to reduce decoding latency under high signal-to-noise ratio with an early stopping mechanism, and the initial decoding cycle flip set of the second decoding unit is empty; wherein, the second decoding unit uses a block storage structure and a two-stage pipeline calculation method for the log likelihood ratio of several layers of nodes with the lowest depth in the decoding tree, so that the large-scale computing units in the computing unit module corresponding to the first decoding unit can be reused with lower input data bandwidth; S3 Result Monitoring and Output: Monitor the decoding completion status of the first decoding unit and the second decoding unit; if the first decoding unit completes decoding, output its decoding result and end decoding; if the second decoding unit completes the current decoding cycle first, perform cyclic redundancy check (CRC) on its decoding result; if the check passes, output the decoding result of the second decoding unit and end decoding; if the check fails, determine whether its flip count has reached the preset maximum flip count; if it has not reached the maximum, generate a new flip set, restart the second decoding unit, and return to the step of monitoring the decoding completion status of the first decoding unit and the second decoding unit; if it has reached the maximum, wait for the first decoding unit to complete, output its decoding result, and end decoding.

2. The method according to claim 1, characterized in that, The block storage structure and two-stage pipelined computing method specifically include: For the Nth layer decoding process, the log-likelihood ratio sequence, which has a quantity of 2^N, is divided into four parts and stored in four memory units. The log-likelihood ratio sequence calculation adopts a two-stage pipelined operation structure. The log-likelihood ratios from the four memory units of the Nth layer are continuously input into the two-stage pipelined operation unit array, and the resulting log-likelihood ratios are written into the memory units of the N-1 and N-2 layers respectively. With the same input data bandwidth, a 1.5 times computational throughput can be achieved.

3. The method according to claim 1 or 2, characterized in that, The process of the first decoding unit executing the Fast-SCL decoding algorithm specifically includes: s3.1 The received channel log-likelihood ratio is stored in the channel log-likelihood ratio storage module. The log-likelihood ratio sequence is calculated by the upper-layer node and passed to the lower-layer node until the level of the special node. s3.2 passes the node log-likelihood ratio sequence to the SCL node processor for decoding decision and path expansion based on the specific node type; s3.3 uses the path metric module to sort the expanded paths according to the path metric values ​​and retains the L paths with the lowest path metric values ​​in real time; s3.4 passes the determined bit sequence to the upper-level node, continues to calculate the log-likelihood ratio sequence from the upper-level node and pass it to the lower-level node, and repeats the above process until all special nodes have completed decoding.

4. The method according to claim 1 or 3, characterized in that, The process of the second decoding unit executing the Fast-DSCF decoding algorithm specifically includes: s4.1 The received channel log-likelihood ratio is stored in the channel log-likelihood ratio storage module. The log-likelihood ratio sequence is calculated by the upper-layer node and passed to the lower-layer node until the level of the special node. s4.2 passes the node log-likelihood ratio sequence to the SCF node processor, and performs decoding decisions based on the special node type and the flip flag; at the same time, it passes the node log-likelihood ratio sequence to the dynamic flip set generation module, calculates the flip metric value based on the special node type, and updates the flip set queue. s4.3 calculates the determined bit sequence to the child node and outputs it to the decoding result storage module. At the same time, it uses the partial sum calculation module to calculate the partial sum bit sequence passed from the lower node to the upper node and passes it to the upper node. It continues to calculate the log-likelihood ratio sequence from the upper node and pass it to the lower node until all special nodes are decoded and the current decoding cycle ends. s4.4 Determine whether the CRC check result of the decoding result passes. If it passes, output the decoding result and terminate the decoding process. If it fails, select the set with the smallest metric value from the dynamically generated flip set as the new current flip set, start the next round of decoding, until the CRC check passes or the preset maximum number of flip rounds has been reached.

5. The method according to claim 1, characterized in that, The generation of the new flip set includes performing dynamic flip set generation in parallel during the decoding process of the second decoding unit; The dynamic flip set generation specifically includes: s5.1 Input the node position ID, node type, and node log-likelihood ratio sequence of the special node being decoded, add the node position ID to the current flip set to generate a new set, and calculate the metric of the new set according to the node type; s5.2 Based on the comparison between the measure of the new set and the maximum measure in the flipped set queue, determine whether to overwrite the set with the maximum measure in the queue with the new set; s5.3 sorts the updated queues according to the metric values ​​to obtain the queue position information and metric values ​​corresponding to the set of maximum and minimum metric values. The above process is repeated until all special nodes in the current decoding cycle are decoded. s5.4 When a decoding cycle is completed, the set with the smallest metric value is selected as the new current flip set, and all bits of the metric value corresponding to the set with the smallest metric value in the queue are set to a specific value, and the next round of decoding is started.

6. A polar code hybrid decoding system based on special nodes, characterized in that, include: The log-likelihood ratio storage module is configured to store the channel log-likelihood ratio and the log-likelihood ratio of nodes during the decoding process; The computation unit module is configured to compute the log-likelihood ratio sequence passed from the upper-level node to the lower-level node; The instruction storage module is configured to pre-store special node type identification instructions, which are provided to the first decoding unit and the second decoding unit for the node type of the special node being decoded. The controller is configured to control the access to and decoding process of the first decoding unit and the second decoding unit to the shared resources, monitor the decoding status of the first decoding unit and the second decoding unit, and select the output decoded codeword according to the decoding status. The first decoding unit is configured to execute the Fast-SCL decoding algorithm; The second decoding unit is configured to execute the Fast-DSCF decoding algorithm; The shared resources accessed by the first decoding unit and the second decoding unit include: a log-likelihood ratio storage module, a computation unit module, and an instruction storage module.

7. The system according to claim 6, characterized in that, The first decoding unit and the second decoding unit specifically include the following functional modules: The SCL node processor, belonging to the first decoding unit, is configured to complete the special node decoding process in the Fast-SCL decoding algorithm, and to perform decoding decisions and path expansion based on the special node type. The PM module, or path metric module, belongs to the first decoding unit and is configured to sort the expanded paths according to the path metric value and retain the L paths with the lowest path metric value in real time. The SCF node processor, belonging to the second decoding unit, is configured to complete the special node decoding process in the Fast-DSCF decoding algorithm and make decoding decisions based on the special node type and whether the flip flag is toggled. The dynamic flip set generation module, belonging to the second decoding unit, is configured to generate a new flip set and calculate a metric value after decoding a special node, determine whether to add it to the flip set queue, and select the flip set for the next round of decoding after the decoding cycle ends. The PSUM module, or Partial Sum Calculation Module, is configured to compute the bit sequence passed from the lower-level node to the upper-level node. The decoding result storage module is configured to temporarily store candidate decoded codewords generated by the first decoding unit and the second decoding unit, which are to be selected and output by the controller. The CRC check module is configured to perform CRC checks on the decoded codewords.

8. The system according to claim 7, characterized in that, The system is capable of identifying and processing special nodes, including the following types of special nodes: Rate-0 node: All bits are frozen bits; Rate-1 node: All bits are information bits; REP node: Only the last bit is an information bit, the rest are frozen bits; SPC node: Only the first bit is a frozen bit, the rest are information bits; ML nodes: Nodes in the remaining distribution pattern; The SCL node processor, SCF node processor, and dynamic flip set generation module all perform corresponding calculations and decisions based on the aforementioned special node types.

9. A decoding device, characterized in that, include: Memory; And a processor coupled to the memory, the processor being configured to execute, based on instructions stored in the memory, the polar code hybrid decoding method based on any one of claims 1 to 5.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed by a processor, implement the polar code hybrid decoding method based on special nodes as described in any one of claims 1 to 5.

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