Production control signal transmission system under industrial internet architecture

Abstract

The invention relates to the technical field of transmission systems of measured values and control signals, and discloses a production control signal transmission system under an industrial internet architecture, which comprises a signal cut-off unit for acquiring a continuous physical control variable, cutting off a most significant bit sequence and a least significant bit sequence according to a binary mask, and transmitting the cut-off sequence to a control unit; respectively packaging into a first signal frame and a second signal frame; the topology reconstruction unit discretely maps the first signal frame data to the second signal frame data sequence according to the discrete mapping step length to generate a mixed data stream; and the signal recovery unit receives the mixed data stream, extracts the first signal frame, performs zero padding on the tail part of the most significant bit sequence of the first signal frame when detecting that the second signal frame has an error code, and outputs the most significant bit sequence. And the target execution equipment is ensured to maintain a coherent physical moving trajectory.

Description

Technical Field

[0001] This invention belongs to the technical field of transmission systems for measured values ​​and control signals, and particularly relates to a production control signal transmission system under an industrial internet architecture. Background Technology

[0002] In current industrial production control architectures, the control end typically relies on deterministic transmission protocols to send multi-dimensional numerical control variables to the target execution equipment. These protocols encapsulate continuous physical control signals into standard rigid data frames and attach a uniform check sequence for the entire frame to screen for communication errors. However, industrial sites are often accompanied by the start-up and shutdown of high-power equipment or transient electromagnetic pulses, which can easily cause random bit flips on the physical transmission medium. Since the existing transmission system treats a single control variable as an indivisible atomic information unit, this bundled transmission of integer variables and the overall check logic hide a serious risk of control state misalignment.

[0003] In terms of physical representation, the high-signal bit data sequence of a continuous numerical control signal carries the physical potential energy to maintain the basic safety envelope of the device, while the low-signal bit data sequence only represents a small size adjustment margin. When a sudden interference hits a minor auxiliary bit, the link layer network protocol directly discards the entire data frame, causing the target execution device to be in a stalled or blindly interpolated state during the microsecond-level period of waiting for retransmission. Conventional countermeasures attempt to increase high-order forward error correction redundancy or increase physical layer transmit power. This strategy inevitably increases the computational overhead of edge nodes and the channel bandwidth load, and the time delay caused by high-frequency retransmission directly offsets the control value of the signal itself, revealing the atomic verification logic of the communication protocol and the physical potential energy of industrial commands. There are fundamental contradictions that cannot be reconciled between gradients. For example, Chinese invention patent CN120017079B discloses an error correction method and system for FPGAs. It improves the real-time performance of RS code error correction by optimizing the computation of the adjoint polynomial and the Qian search process in the Galois domain through parallel pipeline design. However, the underlying logic is based on the atomicity of mathematical correction for whole-frame verification. Under extreme conditions of industrial Ethernet, if transient electromagnetic interference causes bit flips that exceed the algorithm's preset error correction boundary, the existing error correction system will fail and trigger the whole-frame discard mechanism. The defect is that it equates control commands with physical potential gradients with undifferentiated mathematical code streams and fails to establish a degraded transmission path that matches the physical tolerance of the controlled object.

[0004] Therefore, how to reconstruct the bit-order encoding of control variables and the channel transmission mapping mechanism, and break the limitation of atomic encapsulation to achieve adaptive guaranteed transmission based on physical potential gradient, has become the technical problem to be solved by this invention. Summary of the Invention

[0005] This invention provides a production control signal transmission system under an industrial internet architecture, the system comprising: The signal truncation unit is used to obtain continuous physical control variables that characterize the state of the controlled node. It performs a bitwise AND operation on each continuous physical control variable according to a preset binary mask, truncates the most significant bit sequence of the continuous physical control variable and encapsulates it into a first signal frame, and truncates the least significant bit sequence of the continuous physical control variable and encapsulates it into a second signal frame. The topology reconstruction unit, connected to the signal truncation unit, is used to acquire the first signal frame and the second signal frame, and to discretly map the data bytes in the first signal frame to the data byte sequence of the second signal frame according to the preset discrete mapping step size to generate a mixed data stream, so that the data bytes of the second signal frame are arranged on both sides of the data bytes of the first signal frame in the transmission timing. The signal recovery unit, connected to the topology reconstruction unit, is used to receive the mixed data stream transmitted through the physical channel, extract the data bytes of the first signal frame in the mixed data stream according to the discrete mapping step size, and when a bit error is detected in the second signal frame, perform zero padding on the end of the most significant bit sequence of the extracted first signal frame and output it.

[0006] Preferably, the topology reconstruction unit is also used to monitor the bit error rate of the data bytes in the second signal frame, and when the bit error rate is greater than a preset first bit error threshold, it sends a congestion flag back to the signal truncation unit; when the signal truncation unit receives the congestion flag, it strips the preset lowest priority data parameter from the first signal frame according to the congestion flag, so as to reduce the byte length of the first signal frame.

[0007] Preferably, the system further includes a state monitoring unit connected to the signal truncation unit, which is used to calculate the time change rate of the value corresponding to the least significant bit sequence in the second signal frame, and generate a state change indicator when the time change rate is greater than a preset safety threshold, and write the state change indicator into a preset verification area of ​​the first signal frame.

[0008] Preferably, the topology reconstruction unit is also used to calculate and update the discrete mapping step size at the end of each monitoring cycle using the following formula: Where S is the updated discrete mapping step size, The preset initial reference step size, This represents the number of error bytes in the second signal frame received during the previous monitoring period. K represents the total number of bytes of the mixed data stream received in the previous monitoring period, and K is a preset step size adjustment constant.

[0009] Preferably, the signal recovery unit is further configured to extract the state change indicator written in the preset verification area of ​​the first signal frame when a bit error is detected in the second signal frame and a discard operation is performed, and to intercept the preceding periodic data call instruction for the second signal frame in response to the state change indicator, and output a degradation control instruction.

[0010] Preferably, the signal truncation unit includes a mask register and a shift logic gate array. The shift logic gate array is used to directly perform bitwise AND operations on the binary bit plane of the continuous physical control variable to generate physically isolated most significant bit sequences and least significant bit sequences.

[0011] Preferably, the continuous physical control variables include low-frequency macroscopic state indication data, spatial physical coordinate data, and high-frequency transient disturbance feedback data; the most significant bit sequence includes macroscopic control reference data of the continuous physical control variables, and the least significant bit sequence includes surface regulation tolerance data of the continuous physical control variables.

[0012] Preferably, when generating the hybrid data stream, the topology reconstruction unit is used to fill the beginning and end of the second signal frame with static redundancy check codes of a preset fixed length, forming a data structure that wraps the second signal frame.

[0013] Preferably, after stripping the preset lowest priority data parameters, the signal truncation unit generates a mapping defect mark that records the stripping position information, and sends the mapping defect mark to the signal recovery unit via an independent channel; the signal recovery unit is used to parse the mapping defect mark and adjust the byte read pointer for extracting the first signal frame according to the mapping defect mark.

[0014] Preferably, the system further includes a timing alignment buffer, which is set at the input of the signal recovery unit to buffer the received mixed data stream and synchronously trigger the output action of the mixed data stream according to a preset reference clock signal, so that the data bytes of the first signal frame entering the signal recovery unit and the data bytes of the second signal frame are in the same time coordinate system.

[0015] Compared with existing technologies, the production control signal transmission system under the industrial internet architecture of this invention has the following advantages: 1. In the transmission of production control signals under the industrial internet architecture, a cross-frame decoupling and reconstruction mechanism for control signals based on numerical effective bit order is constructed. By forcibly truncating the bit plane dimension of continuous control variables, the high effective bit sequence representing the basic displacement potential energy and the low effective bit sequence representing the adjustment size are separated, and an asymmetric channel transmission mapping is established accordingly. When an asymmetric communication interruption occurs in the heterogeneous channel, the receiving end extracts the independently arriving high effective bit sequence, performs zero-padding at the end, and reconstructs the control command with a basic safety envelope. This mechanism breaks the encapsulation limitation that a single control variable cannot be divided, so that when the control system encounters channel extreme compression or severe interference, the sudden loss of integer variable data is transformed into a smooth bit order accuracy degradation. The control system relies on this mechanism to ensure that the target execution equipment maintains a continuous physical operating trajectory while retaining the basic state response capability.

[0016] 2. A passive sensing of channel state and an adaptive contraction path for the load boundary are established. The system transforms the verification failure events of the auxiliary dataset into discrete physical channel noise sampling probes. Based on the failure frequency, a congestion backpressure flag is sent back to the transmitter. After the transmitter responds to this flag, it dynamically strips the parameters with terminal priority in the core control set and reduces the physical byte distribution length of the core control set on the transmission medium. This cooperative logic uses the statistical characteristics of the data failure events themselves to replace the channel state detection message, and compresses the time exposure window of the core data to enable the key control flow to penetrate the continuous environmental degradation interval in a simplified form, and establishes an adaptive anti-interference closed loop based on the basic network interaction frames.

[0017] 3. A burst interference energy absorption architecture based on physical spatial topology rearrangement is proposed. By changing the continuous splicing encapsulation mode, the encapsulation unit discretizes the data bytes in the core control set to the data byte sequence of the auxiliary control set according to a fixed step size. This topology structure makes the auxiliary data form an isolation absorption segment that wraps the core bytes in terms of physical transmission timing. When encountering continuous electromagnetic pulse waves and transmission media, the destructive energy is concentrated and lost in the auxiliary data area. The receiving end extracts the core bytes by relying on the preset offset step size of the memory pointer, avoiding the need to call the deinterleaving matrix operation unit. By redistributing the spatial position, the physical damage of specific frequency bands is offset, and continuous physical damage is resisted while maintaining strict time rigidity constraints. Attached Figure Description

[0018] Figure 1 This is a flowchart of the bit-level decoupling and accuracy degradation recovery of the production control signal in this invention; Figure 2 This is a diagram of the hardware deployment and channel interference-resistant transmission architecture under the industrial internet architecture of this invention. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0020] It should be noted that all directional and positional terms used in this invention, such as: up, down, left, right, front, back, vertical, horizontal, inner, outer, top, low, lateral, longitudinal, center, etc., are only used to explain the relative positional relationship and connection between components in a specific state (as shown in the accompanying drawings). They are only for the convenience of describing this invention and do not require that this invention be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention. In addition, the descriptions of "first," "second," etc., in this invention are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly indicating the number of technical features indicated.

[0021] In the description of this invention, unless otherwise explicitly specified and limited, the terms installation, connection, and linking should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to the internal connection of two components. For those skilled in the art, the specific meaning of the above terms in this invention can be understood according to the specific circumstances.

[0022] In the description of this specification, references to the terms "an embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example, and the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0023] A production control signal transmission system under an industrial internet architecture, the system comprising: The signal truncation unit is used to obtain continuous physical control variables that characterize the state of the controlled node. It performs a bitwise AND operation on each continuous physical control variable according to a preset binary mask, truncates the most significant bit sequence of the continuous physical control variable and encapsulates it into a first signal frame, and truncates the least significant bit sequence of the continuous physical control variable and encapsulates it into a second signal frame. The topology reconstruction unit, connected to the signal truncation unit, is used to acquire the first signal frame and the second signal frame, and to discretly map the data bytes in the first signal frame to the data byte sequence of the second signal frame according to the preset discrete mapping step size to generate a mixed data stream, so that the data bytes of the second signal frame are arranged on both sides of the data bytes of the first signal frame in the transmission timing. The signal recovery unit, connected to the topology reconstruction unit, is used to receive the mixed data stream transmitted through the physical channel, extract the data bytes of the first signal frame in the mixed data stream according to the discrete mapping step size, and when a bit error is detected in the second signal frame, perform zero padding on the end of the most significant bit sequence of the extracted first signal frame and output it.

[0024] Preferably, the topology reconstruction unit is also used to monitor the bit error rate of the data bytes in the second signal frame, and when the bit error rate is greater than a preset first bit error threshold, it sends a congestion flag back to the signal truncation unit; when the signal truncation unit receives the congestion flag, it strips the preset lowest priority data parameter from the first signal frame according to the congestion flag, so as to reduce the byte length of the first signal frame.

[0025] Preferably, the system further includes a state monitoring unit connected to the signal truncation unit, which is used to calculate the time change rate of the value corresponding to the least significant bit sequence in the second signal frame, and generate a state change indicator when the time change rate is greater than a preset safety threshold, and write the state change indicator into a preset verification area of ​​the first signal frame.

[0026] Preferably, the topology reconstruction unit is also used to calculate and update the discrete mapping step size at the end of each monitoring cycle using the following formula: Where S is the updated discrete mapping step size, The preset initial reference step size, This represents the number of error bytes in the second signal frame received during the previous monitoring period. K represents the total number of bytes of the mixed data stream received in the previous monitoring period, and K is a preset step size adjustment constant.

[0027] Preferably, the signal recovery unit is further configured to extract the state change indicator written in the preset verification area of ​​the first signal frame when a bit error is detected in the second signal frame and a discard operation is performed, and to intercept the preceding periodic data call instruction for the second signal frame in response to the state change indicator, and output a degradation control instruction.

[0028] Preferably, the signal truncation unit includes a mask register and a shift logic gate array. The shift logic gate array is used to directly perform bitwise AND operations on the binary bit plane of the continuous physical control variable to generate physically isolated most significant bit sequences and least significant bit sequences.

[0029] Preferably, the continuous physical control variables include low-frequency macroscopic state indication data, spatial physical coordinate data, and high-frequency transient disturbance feedback data; the most significant bit sequence includes macroscopic control reference data of the continuous physical control variables, and the least significant bit sequence includes surface regulation tolerance data of the continuous physical control variables.

[0030] Preferably, when generating the hybrid data stream, the topology reconstruction unit is used to fill the beginning and end of the second signal frame with static redundancy check codes of a preset fixed length, forming a data structure that wraps the second signal frame.

[0031] Preferably, after stripping the preset lowest priority data parameters, the signal truncation unit generates a mapping defect mark that records the stripping position information, and sends the mapping defect mark to the signal recovery unit via an independent channel; the signal recovery unit is used to parse the mapping defect mark and adjust the byte read pointer for extracting the first signal frame according to the mapping defect mark.

[0032] Preferably, the system further includes a timing alignment buffer, which is set at the input of the signal recovery unit to buffer the received mixed data stream and synchronously trigger the output action of the mixed data stream according to a preset reference clock signal, so that the data bytes of the first signal frame entering the signal recovery unit and the data bytes of the second signal frame are in the same time coordinate system.

[0033] Example 1: In the physical control network of a continuous stamping production line with transient high-frequency electromagnetic pulse fluctuations exceeding 600V, the underlying fieldbus continuously transmits continuous physical control variables containing multi-axis absolute position parameters; the physical transmission medium frequently encounters periodic electromagnetic pulse sweeps, causing microsecond-level random bit flips within the transmission cable; when an Ethernet node using an atomized indivisible encapsulation protocol detects a bit error in the status indicator bit within a data frame, it triggers a full frame discard action, causing the target execution device to lose spatial physical coordinate data during the microsecond-level control cycle of waiting for protocol stack retransmission and fall into a blind interpolation state, resulting in a control conflict between the overall verification and discard logic of the data link layer and the potential gradient of the industrial control command.

[0034] The production control signal transmission system under the Industrial Internet architecture transforms the communication processing logic of continuous physical control variables into a binary bit plane. The signal truncation unit acquires the continuous physical control variables representing the state of the controlled node, performs a bitwise AND operation on each continuous physical control variable according to a preset binary mask, truncates the most significant bit sequence of the continuous physical control variable carrying global control reference data and encapsulates it independently into a first signal frame, and simultaneously truncates the least significant bit sequence of the continuous physical control variable representing local adjustment tolerance data and encapsulates it into a second signal frame. The topology reconstruction unit acquires the first signal frame and the second signal frame, and according to a preset discrete mapping step size, discretizes the data bytes in the first signal frame to the data byte sequence of the second signal frame to generate a mixed data stream, so that the data bytes of the second signal frame are arranged on both sides of the data bytes of the first signal frame in the transmission timing. This feature combination utilizes the data volume of the second signal frame to construct an absorption segment that wraps the core data in the temporal and spatial topology, eliminating the static binding association between the core displacement data and sudden continuous physical interference.

[0035] The signal recovery unit at the network end receives the mixed data stream transmitted through the physical channel and extracts the data bytes of the first signal frame from the mixed data stream by offsetting the memory pointer according to the discrete mapping step size. When the signal recovery unit detects that the second signal frame, which acts as the outer padding layer, has a bit error, it blocks the whole frame discarding action, performs zero padding on the end of the most significant bit sequence of the extracted first signal frame, and outputs it. The above steps exchange the data state change of the second signal frame for the complete preservation of the control command backbone parameters, transforming the sudden communication interruption into a precision degradation state that keeps the target execution device within the set envelope, so that the target execution device maintains a coherent physical running trajectory based on the reconstructed physical control variables.

[0036] Example 2: To verify the impact of transient electromagnetic pulses on the transmission stability of multi-axis absolute position parameters in the physical control network of a continuous stamping production line, a hardware-in-the-loop physical test platform was constructed, comprising a motion controller providing reference coordinates, a servo driver driving the mechanical axes, and a 100Mbps industrial Ethernet physical transmission medium connecting the motion controller and the servo driver. A signal generator actively injected Gaussian white noise with a signal-to-noise ratio of 20dB into the physical transmission medium, simultaneously superimposing a 50Hz power frequency interference harmonic. Multiple interference sources induced transient high-frequency electromagnetic pulse fluctuations with amplitudes exceeding 600V, causing microsecond-level random bit flips within the transmission cable. This approach reproduces the physical disturbance state in the underlying fieldbus communication environment. The initial reference step size of the topology reconstruction unit is set to be controlled by the ratio of the total length of the data frame to the expected maximum burst interference width. The technical consideration is to balance reducing the discrete mapping computation load of the embedded microprocessor and increasing the physical wrapping density of peripheral auxiliary data on the core data. The system follows the judgment rule that the initial reference step size tends to the lower limit of its computational domain when the expected maximum burst interference width expands. Under the setting conditions of 100 Mbps transmission bandwidth and a maximum expected physical bit error length of 16 bytes, the discrete value of the initial reference step size is determined to be 4, which constitutes the initial state reference for subsequent dynamic topology reconstruction.

[0037] The experiment established a control group using a standard indivisible encapsulation protocol and an experimental group using a hybrid data stream reconstruction mechanism. The initial input data consisted of 32-bit continuous physical control variables generated by the motion controller. Under both Gaussian white noise and electromagnetic pulse disturbances, the underlying physical channel exhibited fluctuating bit error rate. In the experimental group, the signal truncation unit acquired the continuous physical control variables and calculated bitwise AND logic based on a preset binary mask to separate and generate a first signal frame and a second signal frame. The topology reconstruction unit discretized and mapped the data bytes in the first signal frame to the data byte sequence of the second signal frame according to the initial reference step size, generating a hybrid data stream. At the end of each monitoring cycle, the topology reconstruction unit calculated and updated the discrete mapping step size according to a specific mathematical model. The specific evolution formula is as follows: , where S is the updated discrete mapping step size; The initial reference step size is preset; K is the step size adjustment coefficient. This refers to the number of bit errors counted in the previous monitoring period. This represents the total number of bits transmitted.

[0038] Extracting key intermediate feature data confirms the nonlinear absorption state of the dynamic mapping mechanism; when the actual bit error rate of the physical channel is between 5.2% and 14.8%, the number of bit error bytes in the second signal frame increases linearly with the interference intensity, but the extracted first signal frame maintains a 99.7% error-free extraction rate; this data phenomenon confirms that the second signal frame fulfills its function of absorbing external physical interference; when the physical channel bit error rate exceeds the boundary extreme of 15.3%, the data volume absorption capacity of the second signal frame reaches physical saturation, causing the error-free extraction rate of the first signal frame to drop to 81.6%; this performance inflection point data conversely confirms that the optimal working window constructed by the system for control signal transmission is below a bit error rate of 15.0%, and the network... The signal recovery unit at the end generates servo drive control commands based on the extracted state. In the control group, when a bit error is detected in the state indicator bit within the data frame, the entire frame is discarded, causing a 12.5ms control blind zone in the servo drive and triggering a stall protection mechanism. In the experimental group, when a bit error is detected in the second signal frame, the signal recovery unit blocks the entire frame discard logic and adds a fixed length of zero values ​​to the end of the most significant bit sequence of the extracted undamaged first signal frame to output the reconstructed control variables. The signal recovery unit performs zero-padding to suppress the oscillation of the actuator caused by the step change in numerical bit weights. The reconstructed control variables are input to a first-order slope limiter, which presets the maximum allowable displacement increment based on the physical motion limit of the controlled node. , This represents the upper limit of the allowable displacement change within a single sampling period of the actuator, where the absolute value of the difference between the reconstructed value and the output value of the previous period is greater than the maximum allowable displacement increment. At that time, the current cycle output value is corrected to the previous cycle value plus the maximum allowable displacement increment in the sign bit direction. Under the condition of reduced accuracy, the acceleration envelope of the target execution device is kept intact and the physical trajectory is smoothly connected. Based on the reconstructed physical control variables, the servo drive maintains the reduced accuracy operation. The measured deviation of the actual physical trajectory of the stamping shaft is within the tolerance envelope of 0.14mm. The physical measurement data confirms that by splitting the control signal into high and low bit frames in the binary bit plane and wrapping it with discrete mapping in spatial and temporal sequence, the system cuts off the binding association between the core displacement data and sudden continuous physical interference, and transforms the communication interruption caused by random bit flips into a reduced accuracy state within the allowable range of physical tolerance, thus maintaining the continuity of the target execution device's running trajectory.

[0039] Example 3: In the initial configuration and underlying memory mapping of multi-axis absolute position parameter bit-level decoupling transmission, the system faces the technical challenges of determining the high and low bit truncation boundaries and establishing the surface data cross-assembly path; the signal truncation unit applies the quantization calibration procedure of binary mask before starting network data transmission; this unit obtains the maximum physical tolerance margin of the target execution device under the current stamping process and extracts the minimum physical resolution of the underlying hardware corresponding to the continuous physical control variables; based on the aforementioned input parameters, the system calculates the bit width required to construct the second signal frame according to the logarithmic mapping model, and the specific calculation formula is as follows: Where W is the bit width of the least significant bit sequence; For the maximum physical tolerance margin, To achieve the minimum physical resolution, based on the calculated bit width, the signal truncation unit generates a bit sequence in the storage array with the low-order bits equal to the bit width and all numerical bits set to zero, while the remaining high-order bits are all set to one, as a preset binary mask. By applying this preset binary mask to the acquired continuous physical control variables and performing bitwise AND logic, the system separates the continuous signal representing the controlled node's state into a first signal frame carrying reference coordinate parameters and a second signal frame carrying local floating parameters. After generating the first and second signal frames, the topology reconstruction unit calls the pointer reconstruction logic for the mixed data stream. In the microprocessor's transmit buffer, a continuous linear address space with a total length equal to the sum of the number of bytes in two frames is allocated. Alternating incrementing first and second memory write pointers are established. The first memory write pointer traverses the continuous linear address space in a skipping manner according to a preset discrete mapping step size as a span constant, and stores the data bytes in the first signal frame in sequence. The second memory write pointer traverses the memory gap addresses left after the first memory write pointer jumps, and stores the data bytes of the second signal frame in sequence, so that the data bytes of the second signal frame are arranged on both sides of the data bytes of the first signal frame in the transmission timing, and are encapsulated and sent to the physical channel.

[0040] The signal recovery unit at the network end receives the mixed data stream transmitted through the physical channel, allocates a receive buffer of equal width, and establishes a reference read pointer. This reference read pointer offsets the memory read address according to the same discrete mapping step size, crosses the storage block belonging to the second signal frame, extracts the data bytes of the first signal frame in the mixed data stream, and stores them in a temporary register. The aforementioned steps transform the abstract communication protocol splitting and reassembly mechanism into the addressing operation of the embedded processor, confirming that the physical pointer interaction of the underlying memory array supports the closed-loop operation of the control signal transmission system. The topology reconstruction unit executes the memory pointer interaction process, configures the microprocessor direct memory access controller hardware-level address jump extraction, satisfies the microsecond-level time rigidity constraint of the control signal, and sets the direct memory access controller transmission step size register to the value corresponding to the discrete mapping step size S, where S is the physical distance between the data bytes in the first signal frame in the mixed data stream. The direct memory access controller automatically skips the second signal frame data block during the process of transporting the mixed data stream. The first signal frame byte sequence is continuously written into the target task buffer, avoiding the latency fluctuation of the central processing unit software addressing processing. The total physical delay from receiving the mixed data stream to output reconstruction control variables is constant within the preset communication period.

[0041] Example 4: In the pre-deployment debugging of a newly deployed industrial control network, the system initiates a baseline calibration procedure to quantify and establish the first bit error rate threshold and safety threshold required for signal transmission; the test terminal continuously injects simulated electromagnetic pulses with progressively increasing interference intensity into the physical channel; the topology reconstruction unit collects the actual bit error rate and the time change rate of the least significant bit sequence value of the second signal frame data byte within a specified time window under each interference step; the status monitoring unit synchronously extracts the physical trajectory deviation of the target execution device after receiving the reconstruction command; the system processor constructs a mathematical transfer function of the physical trajectory deviation relative to the bit error rate, and the specific determination formula is as follows: ,in, This is the first bit error threshold after calibration; The target is the physical limit of the mechanical tolerance of the equipment. It is the inverse mapping operator of the transfer function; at the same time, the state monitoring unit calculates the second derivative sequence of the physical trajectory deviation, extracts the time change rate corresponding to the critical point of the step change in the second derivative sequence, and saves it into the non-volatile memory of the hardware controller as a preset safety threshold.

[0042] After completing the basic threshold calibration, the system initiates an offline data filling procedure for the priority of control parameters; the test terminal extracts a continuous physical control variable sample set containing multi-axis absolute coordinates and auxiliary compensation parameters under the standard process cycle; the system main control chip calculates the variance contribution of each parameter in the sample set to maintaining the servo mechanism's running trajectory; the processor constructs a global feature vector mapping table based on the variance contribution values ​​arranged from largest to smallest; the physical addresses of parameters with cumulative variance contribution values ​​in the last 10% range are fixed in the dedicated register of the signal truncation unit, and the corresponding physical addressing markers are configured as the preset lowest priority data parameters; in the specific data structure mapping of this embodiment, the first signal frame consists of a 32-bit binary length, where bits 0 to 23 are defined as the kernel containing the three-axis spatial physical coordinates. The first signal frame is divided into four control segments, with bits 24 to 31 defined as auxiliary monitoring segments containing ambient humidity and motor housing temperature. The system defines these last 8 bits as preset lowest priority data parameters, and the corresponding physical addressing flag is set in the storage area 3 bytes after the buffer base address offset. When the topology reconstruction unit detects that the actual bit error rate of the channel is greater than the first bit error threshold and sends a congestion flag back to the signal truncation unit, the signal truncation unit directly calls the hardware address in the dedicated register to trigger a bypass drop operation on a specific parameter, stripping the preset lowest priority data parameter, thereby reducing the byte length of the first signal frame. The aforementioned engineering process converts the importance determination of the control signal into a fixed memory pointer operation at the lower level, quantifying the execution boundary of the first signal frame truncation under physical layer congestion.

[0043] Example 5: During the pre-deployment debugging phase of an industrial field control network that has undergone physical equipment replacement and communication cable aging, the system faces the engineering requirement of dynamically calibrating the step size adjustment coefficient based on the physical attenuation characteristics of the cables. The topology reconstruction unit deployed within the master control node triggers a basic impedance detection test of the communication link when the physical channel is connected. This topology reconstruction unit drives the underlying transceiver to inject a standard probe pulse sequence containing high and low level transitions into the transmission cable, simultaneously measuring the round-trip propagation delay and frequency domain attenuation amplitude of the transmission cable. The system processor extracts the product of the round-trip propagation delay and the frequency domain attenuation amplitude as the inherent degradation parameter of the channel, and calculates the preset step size adjustment coefficient based on a linear proportional model. The specific calibration formula is as follows: Where K is the step size adjustment coefficient; A frequency matching constant preset for the hardware interface; For round-trip propagation delay, To determine the frequency domain attenuation amplitude, the aforementioned calibration steps convert the step size adjustment parameter into a quantized value controlled by the electrical characteristics of the physical cable. In the specific engineering configuration of this embodiment, the hardware interface preset frequency matching constant is fixed at 0.85. This value is a baseline value predetermined by injecting a pseudo-random sequence with a frequency of 100MHz and a peak-to-peak value of 3.3V into the physical channel during the system initialization phase and using the error counter of the underlying receiver to count the physical layer verification pass rate within 1000ms. The step size adjustment coefficient K is quantized and calibrated by injecting a standard pulse sequence into the transmission cable using an underlying fieldbus analyzer during the startup phase, and collecting the frequency response curve of the transmission cable in the 50MHz to 200MHz frequency band to extract the frequency domain attenuation amplitude. The round-trip propagation delay is calculated based on the physical length of the transmission cable and the signal propagation speed. Substituting multiple sets of experimental data into the least squares fitting model, the proportional constant that minimizes the mechanical trajectory deviation was determined as the preset frequency matching constant for the hardware interface. Establish a quantitative update procedure for the step size adjustment coefficient K of cable electrical characteristics.

[0044] During the continuous operation phase of reconstructing the hybrid data stream based on the updated discrete mapping step size, the system introduces boundary state verification to address the risk of hardware addressing out-of-bounds errors caused by memory pointer offsets. The topology reconstruction unit obtains the updated discrete mapping step size and performs address boundary determination logic before discretely mapping the data bytes of the first signal frame to the transmit buffer. This topology reconstruction unit calculates the estimated jump physical address after adding the discrete mapping step size to the current first memory write pointer and compares the estimated jump physical address with the highest physical address boundary of the continuous linear address space allocated by the transmit buffer. When the estimated jump physical address is greater than the highest physical address boundary, the topology reconstruction unit extracts the difference between the estimated jump physical address and the highest physical address boundary, uses this difference as a new offset reference, and performs an accumulation operation from the starting physical address of the continuous linear address space to determine the target write. Location; The aforementioned memory fallback overlay procedure restricts the divergent address stream generated by discrete mapping within the hardware capacity boundary of the transmit buffer; The signal recovery unit located at the network end synchronously adjusts the reference read pointer of the receive buffer according to the same memory fallback operator when receiving the mixed data stream, so that the read action of extracting the data byte of the first signal frame is synchronized with the cyclic mapping instruction of the transmitting end at the physical timing level; The test terminal extracts the end control response state of the servo driver under the condition of injecting electromagnetic interference of twice the intensity of the specified physical tolerance into the physical transmission medium; The measured hardware detection data shows that the servo driver maintains continuous reference position parsing action and does not trigger the bus reset hardware interrupt; The aforementioned physical execution results prove that the system combines the step quantization of cable electrical characteristics and the construction of closed cyclic memory boundaries to avoid address overflow of control signals during the interaction of underlying registers.

[0045] The embodiments of this application have been described above with reference to the accompanying drawings. Unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other. This application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit of this application and the scope of protection of this invention, and all of these forms are within the protection scope of this application.

Claims

1. A production control signal transmission system under an industrial internet architecture, characterized in that, The system includes: The signal truncation unit is used to obtain continuous physical control variables that characterize the state of the controlled node. It performs a bitwise AND operation on each continuous physical control variable according to a preset binary mask, truncates the most significant bit sequence of the continuous physical control variable and encapsulates it into a first signal frame, and truncates the least significant bit sequence of the continuous physical control variable and encapsulates it into a second signal frame. The topology reconstruction unit, connected to the signal truncation unit, is used to acquire the first signal frame and the second signal frame, and to discretly map the data bytes in the first signal frame to the data byte sequence of the second signal frame according to a preset discrete mapping step size to generate a mixed data stream, so that the data bytes of the second signal frame are arranged on both sides of the data bytes of the first signal frame in the transmission timing. The signal recovery unit, connected to the topology reconstruction unit, is used to receive the mixed data stream transmitted through the physical channel, extract the data bytes of the first signal frame in the mixed data stream according to the discrete mapping step size, and when a bit error is detected in the second signal frame, perform zero padding on the end of the most significant bit sequence of the extracted first signal frame and output it.

2. The production control signal transmission system under the industrial internet architecture according to claim 1, characterized in that, The topology reconstruction unit is also used to monitor the bit error rate of the data bytes in the second signal frame, and when the bit error rate is greater than the preset first bit error threshold, it sends a congestion flag back to the signal truncation unit; when the signal truncation unit receives the congestion flag, it strips the preset lowest priority data parameter from the first signal frame according to the congestion flag, so as to reduce the byte length of the first signal frame.

3. The production control signal transmission system under the industrial internet architecture according to claim 1, characterized in that, The system also includes a status monitoring unit, which is connected to the signal truncation unit. The status monitoring unit is used to calculate the time change rate of the value corresponding to the least significant bit sequence in the second signal frame, and generate a status change indicator when the time change rate is greater than a preset safety threshold. The status change indicator is then written into the preset verification area of ​​the first signal frame.

4. The production control signal transmission system under the industrial internet architecture according to claim 1, characterized in that, The topology reconstruction unit is also used to calculate and update the discrete mapping step size at the end of each monitoring cycle using the following formula: Where S is the updated discrete mapping step size, The preset initial reference step size, This represents the number of error bytes in the second signal frame received during the previous monitoring period. K represents the total number of bytes of the mixed data stream received in the previous monitoring period, and K is a preset step size adjustment constant.

5. The production control signal transmission system under the industrial internet architecture according to claim 3, characterized in that, The signal recovery unit is also used to extract the state change indicator written in the preset check area of ​​the first signal frame when a bit error is detected in the second signal frame and a discard operation is performed, and to intercept the preceding periodic data call instruction for the second signal frame in response to the state change indicator, and output the degradation control instruction.

6. The production control signal transmission system under an industrial internet architecture according to claim 1, characterized in that, The signal truncation unit includes a mask register and a shift logic gate array. The shift logic gate array is used to directly perform bitwise AND operations on the binary bit plane of continuous physical control variables to generate physically isolated most significant bit sequences and least significant bit sequences.

7. The production control signal transmission system under the industrial internet architecture according to claim 1, characterized in that, Continuous physical control variables include low-frequency macroscopic state indication data, spatial physical coordinate data, and high-frequency transient disturbance feedback data; the most significant bit sequence includes macroscopic control baseline data of continuous physical control variables, and the least significant bit sequence includes surface regulation tolerance data of continuous physical control variables.

8. The production control signal transmission system under the industrial internet architecture according to claim 1, characterized in that, When generating a hybrid data stream, the topology reconstruction unit is used to fill the beginning and end of the second signal frame with static redundancy check codes of a preset fixed length, forming a data structure that wraps the second signal frame.

9. A production control signal transmission system under an industrial internet architecture according to claim 2, characterized in that, After stripping the preset lowest priority data parameters, the signal truncation unit generates a mapping defect mark that records the stripping position information and sends the mapping defect mark to the signal recovery unit via an independent channel. The signal recovery unit is used to parse the mapping defect mark and adjust the byte read pointer for extracting the first signal frame according to the mapping defect mark.

10. A production control signal transmission system under an industrial internet architecture according to claim 1, characterized in that, The system also includes a timing alignment buffer, which is set at the input of the signal recovery unit to buffer the received mixed data stream and synchronously trigger the output action of the mixed data stream according to a preset reference clock signal, so that the data bytes of the first signal frame entering the signal recovery unit and the data bytes of the second signal frame are in the same time coordinate system.

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