Novel shield gate trench MOS device and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, in particular to a novel shield gate trench MOS device and a preparation method thereof, and the device comprises a substrate, an epitaxial layer located on the substrate, a trench located in the epitaxial layer, and a control gate region, a shield gate region and a first interlayer dielectric layer which are located in the trench; the control gate region and the shielding gate region are distributed up and down, and the first interlayer dielectric layer is located between the control gate region and the shielding gate region; the control gate region comprises a control gate, a gate oxide layer and a specified dielectric layer; the lower surface of the control gate is in contact with the first interlayer dielectric layer; the gate oxide layer is filled between the control gate and the inner side wall of the groove; the top designated area and the bottom designated area are filled with the designated dielectric layer, the top designated area is located at the top of the control gate, and the bottom designated area is located at the bottom of the control gate. According to the device, the gate dielectric layer structure is optimized, so that the device has excellent gate voltage endurance capability, and the reliability of the device is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a novel shielded gate trench MOS device and its fabrication method. Background Technology

[0002] Currently, shielded gate trench MOSFETs (SGTMOS) are widely used in high-frequency switching power supplies. Due to their structural characteristics, SGTMOS devices have low parasitic capacitance, resulting in faster turn-on and turn-off speeds. In harsh operating conditions, the performance and reliability requirements for SGTMOS devices are gradually increasing, thus ensuring a longer service life for critical components.

[0003] However, shielded gate trench MOS devices are subjected to high-temperature gate bias stress for extended periods, making the gate oxide layer prone to breakdown. This leads to the formation of a permanent low-resistance path between the gate and the inversion channel formed by the P-body region and the gate oxide layer, causing a short circuit between the gate and source of the shielded gate trench MOS device and reducing its reliability. Therefore, existing shielded gate trench MOS devices suffer from reduced reliability in harsh operating conditions. Summary of the Invention

[0004] This application provides a novel shielded gate trench MOS device and its fabrication method, which solves the technical problem of reduced reliability of shielded gate trench MOS devices in harsh operating conditions in the prior art. It optimizes the gate dielectric layer structure of the shielded gate trench MOS device, giving the device better gate withstand voltage capability, improving the reliability of the shielded gate trench MOS device in harsh operating conditions, reducing gate-drain capacitance and gate-source capacitance, reducing the switching loss of the device, increasing the lifespan of the device in extreme environments, reducing the probability of device failure, and enhancing practical efficiency.

[0005] In a first aspect, embodiments of the present invention provide a novel shielded gate trench MOS device, comprising: a substrate, an epitaxial layer of a first conductivity type located on the substrate, a trench located in the epitaxial layer, a control gate region, a shielded gate region, and a first interlayer dielectric layer located in the trench; The control gate region and the shield gate region are arranged in an upper and lower structure, and the first interlayer dielectric layer is located between the control gate region and the shield gate region; The shielding gate region includes: a shielding gate and a field oxide layer; the upper surface of the shielding gate is in contact with the lower surface of the first interlayer dielectric layer, and the field oxide layer fills the space between the shielding gate and the sidewalls and bottom wall of the trench; The control gate region includes: a control gate, a gate oxide layer, and a specified dielectric layer; The control gate has a cross-shaped structure, and the lower surface of the control gate is in contact with the upper surface of the first interlayer dielectric layer; The gate oxide layer fills the space between the control gate and the sidewalls within the trench; The specified dielectric layer fills the top specified area and the bottom specified area, wherein the top specified area is the area formed by the top of the control gate, the gate oxide layer and the opening of the trench, and the bottom specified area is the area formed by the bottom of the control gate, the gate oxide layer and the first interlayer dielectric layer.

[0006] Optionally, on each sidewall within the trench, the sum of the lateral width of the gate oxide layer and the lateral width of the corresponding designated dielectric layer is consistent with the lateral width of the field oxide layer between the sidewall of the shielding gate and the corresponding sidewall within the trench.

[0007] Optionally, the minimum lateral width of the control gate is the same as the lateral width of the shielding gate.

[0008] Optionally, it further includes: a doped region located on the epitaxial layer and surrounding the trench; The doped region includes: a body region of the second conductivity type and a source region of the first conductivity type; The body region is located on the epitaxial layer and surrounds the trench; The source region is located on the body region and surrounds the trench; The upper surface of the source region, the upper surface of the body region, the opening of the trench, and the upper surface of the epitaxial layer are located on the same horizontal plane.

[0009] Optionally, the longitudinal depth of the control gate region is greater than the longitudinal depth of the body region.

[0010] Optionally, on each sidewall within the trench, the longitudinal depth of the designated dielectric layer in the bottom designated region is consistent with the difference between the longitudinal depth of the control gate region and the longitudinal depth of the body region.

[0011] Optionally, on each sidewall within the trench, the longitudinal depth of the designated medium layer in the top designated area is consistent with the longitudinal depth of the source area.

[0012] Optionally, it may also include: a second interlayer dielectric layer and a drain region; The second interlayer dielectric layer is located above the epitaxial layer and covers the trench and the doped region; The drain region is located beneath the substrate.

[0013] Optionally, it may also include: a metal layer and multiple electrode regions; The metal layer is located above the second interlayer dielectric layer; The plurality of electrode regions are in contact with the metal layer at one end and with the corresponding region at the other end to form the electrode of the corresponding region.

[0014] Based on the same inventive concept, in a second aspect, the present invention also provides a method for fabricating a novel shielded gate trench MOS device, used to fabricate the novel shielded gate trench MOS device described in the first aspect, the method comprising: An epitaxial layer of a first conductivity type is formed on the substrate; Trenches are formed in the epitaxial layer; A control gate region, a shield gate region, and a first interlayer dielectric layer are formed in the trench, wherein the control gate region and the shield gate region are distributed in an upper and lower structure, and the first interlayer dielectric layer is located between the control gate region and the shield gate region. The shielding gate region includes: a shielding gate and a field oxide layer; the upper surface of the shielding gate is in contact with the lower surface of the first interlayer dielectric layer, and the field oxide layer fills the space between the shielding gate and the sidewalls and bottom wall of the trench; The control gate region includes: a control gate, a gate oxide layer, and a specified dielectric layer; The control gate has a cross-shaped structure, and the lower surface of the control gate is in contact with the upper surface of the first interlayer dielectric layer; The gate oxide layer fills the space between the control gate and the sidewalls within the trench; The specified dielectric layer fills the top specified area and the bottom specified area, wherein the top specified area is the area formed by the top of the control gate, the gate oxide layer and the opening of the trench, and the bottom specified area is the area formed by the bottom of the control gate, the gate oxide layer and the first interlayer dielectric layer.

[0015] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages: This embodiment provides a novel shielded gate trench MOS device. The device has a shielded gate region, a first interlayer dielectric layer, and a control gate region sequentially arranged from bottom to top within a trench in an epitaxial layer above a substrate. The control gate region includes a control gate, a gate oxide layer, and a designated dielectric layer. The control gate has a cross-shaped structure, and the gate oxide layer fills the space between the control gate and the sidewalls within the trench. Designated dielectric layers are filled in the top and bottom designated regions of the control gate, forming composite gate dielectric layers on the left and right sides of the top and bottom of the control gate. Specifically, a composite gate dielectric layer is formed by combining the designated dielectric layer of the top designated region of the control gate with the gate oxide layer adjacent to the designated dielectric layer of the top designated region, and a composite gate dielectric layer is formed by combining the designated dielectric layer of the bottom designated region of the control gate with the gate oxide layer adjacent to the designated dielectric layer of the bottom designated region.

[0016] Increasing the gate dielectric layer thickness in the overlapping region between the control gate sidewall and the source region and epitaxial layer not only does not affect the formation of the inversion channel layer, but also weakens the effect of high temperature and high gate voltage stress accelerating the degradation of the gate dielectric layer. Furthermore, the designated dielectric layer in the composite gate dielectric layer uses a high-k dielectric material (i.e., silicon nitride). Silicon nitride has a higher dielectric constant and a higher critical electric field strength than silicon oxide, enhancing the device's gate breakdown voltage. The composite gate dielectric layer structure also increases the thickness of the dielectric layer between the control gate and the doped region, further improving the device's gate breakdown voltage.

[0017] Furthermore, the designated dielectric layer of the composite gate dielectric layer replaces a portion of the polysilicon in the control gate of a traditional shielded gate trench MOS device, increasing the dielectric layer thickness between the control gate and drain, and between the control gate and source. This significantly reduces the gate-drain capacitance and gate-source capacitance, lowering the device's switching losses. Simultaneously, the designated dielectric layer in the composite gate dielectric layer replaces a portion of the polysilicon in the control gate of a traditional shielded gate trench MOS device, reducing the thickness of part of the control gate, lowering the control gate resistance Rg, and improving the device's switching speed. Moreover, the designated dielectric layer in the bottom designated region also helps deplete carriers within the epitaxial layer, reducing the peak electric field intensity at the PN junction formed by the doped body and the epitaxial layer, improving the device's avalanche tolerance, and also reducing the probability of device failure in high-temperature applications. Thus, by optimizing the gate dielectric layer structure of the shielded gate trench MOS device, this embodiment enables the device to have a better gate withstand voltage capability, improves the reliability and performance of the shielded gate trench MOS device in harsh operating conditions, reduces gate-drain capacitance and gate-source capacitance, reduces the switching loss of the device, increases the service life of the device in extreme environments, reduces the probability of device failure, and enhances practical efficiency. Attached Figure Description

[0018] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference figures denote the same parts throughout the drawings. In the drawings: Figure 1 A schematic diagram of the structure of a novel shielded gate trench MOS device according to an embodiment of the present invention is shown; Figure 2 This diagram illustrates a structure in which an epitaxial layer and trenches are formed on a substrate according to an embodiment of the present invention. Figure 3 A schematic diagram of the structure of the etching field oxide layer in the trench is shown in an embodiment of the present invention; Figure 4 This diagram illustrates a structure in which a shielding grid is formed within a trench, according to an embodiment of the present invention. Figure 5 This invention illustrates another structural schematic diagram of forming a shielding grid and a field oxide layer within a trench, according to an embodiment of the invention. Figure 6 This diagram illustrates a structure in which a first interlayer dielectric layer and a gate oxide layer are formed within a trench, according to an embodiment of the present invention. Figure 7 This diagram illustrates a structure in which a designated medium layer is formed in a designated bottom region within a trench, according to an embodiment of the present invention. Figure 8 A schematic diagram of the structure of the control gate forming a portion within the trench is shown in an embodiment of the present invention; Figure 9 This invention illustrates a schematic diagram of a structure in which a designated medium layer with a designated top region is formed within a trench, according to an embodiment of the invention. Figure 10 This diagram illustrates a structure in which a complete control grid is formed within a trench, according to an embodiment of the present invention. Figure 11 This diagram illustrates a structure in which a body region is formed on an epitaxial layer according to an embodiment of the present invention. Figure 12 This diagram illustrates a structure in which a source region is formed on a body region according to an embodiment of the present invention. Figure 13 This diagram illustrates a structure in which a second interlayer dielectric layer is formed on top of an epitaxial layer in an embodiment of the present invention. Figure 14 A schematic diagram of the structure for forming the electrode region and the metal layer in an embodiment of the present invention is shown; Figure 15 A schematic flowchart of the fabrication method of the novel shielded gate trench MOS device in an embodiment of the present invention is shown.

[0019] In the attached figures, 110 is the substrate; 120 is the epitaxial layer; 130 is the trench; 140 is the control gate region; 150 is the shielding gate region; 160 is the first interlayer dielectric layer; 170 is the doped region; 180 is the second interlayer dielectric layer; 190 is the metal layer; 191 is the electrode region; and 192 is the drain region. 141. Control gate; 142. Gate oxide layer; 143. Specified dielectric layer; 151. Shielding grid; 152. Field oxide layer; 171. Body region; 172. Source region. Detailed Implementation

[0020] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0021] Example 1 The first embodiment of the present invention provides a novel shielded gate trench MOS device, such as... Figure 1 As shown, it includes: a substrate 110, an epitaxial layer 120 of a first conductivity type located on the substrate 110, a trench 130 located in the epitaxial layer 120, a control gate region 140, a shielding gate region 150 and a first interlayer dielectric layer 160 located in the trench 130.

[0022] The control gate region 140 and the shield gate region 150 are arranged in an upper and lower structure, and the first interlayer dielectric layer 160 is located between the control gate region 140 and the shield gate region 150. Figure 1 As shown, within the trench 130, the first interlayer dielectric layer 160 is located in the middle of the trench 130, the control gate region 140 is located above the first interlayer dielectric layer 160, and the shielding gate region 150 is located below the first interlayer dielectric layer 160. The structures of both the control gate region 140 and the shielding gate region 150 are symmetrical about the centerline of the trench 130.

[0023] The shielded gate region 150 includes a shielded gate 151 and a field oxide layer 152. The upper surface of the shielded gate 151 is in contact with the lower surface of the first interlayer dielectric layer 160. The field oxide layer 152 fills the space between the shielded gate 151 and the sidewalls and bottom wall of the trench 130, and the upper surface of the field oxide layer 152 is in contact with the lower surface of the first interlayer dielectric layer 160.

[0024] The control gate region 140 includes a control gate 141, a gate oxide layer 142, and a designated dielectric layer 143. The control gate 141 has a cross-shaped structure, and its lower surface contacts the upper surface of the first interlayer dielectric layer 160. The gate oxide layer 142 fills the space between the control gate 141 and the sidewalls within the trench 130. The designated dielectric layer 143 fills a top designated region and a bottom designated region. The top designated region is the area formed by the top of the control gate 141, the gate oxide layer 142, and the opening of the trench 130; the bottom designated region is the area formed by the bottom of the control gate 141, the gate oxide layer 142, and the first interlayer dielectric layer 160.

[0025] It should be noted that the substrate 110 is made of, but is not limited to, silicon substrates doped with impurities such as arsenic, red phosphorus, or antimony. The epitaxial layer 120 is a lightly doped epitaxial layer of a first conductivity type, and its material includes, but is not limited to, silicon. The shielding gate 151 is shielding gate conductive polysilicon, and its material is polysilicon doped with a first conductivity type. The control gate 141 is made of, but is not limited to, polysilicon doped with a first conductivity type. The field oxide layer 152 is made of, but is not limited to, silicon dioxide. The gate oxide layer 142 is an insulating gate oxide layer, and its material includes, but is not limited to, silicon dioxide. The first interlayer dielectric layer 160 is made of, but is not limited to, silicon dioxide. The first interlayer dielectric layer 160 is an insulating dielectric layer. The specified dielectric layer 143 is made of silicon nitride. In this embodiment, for an N-type MOS field-effect transistor, the first conductivity type refers to N-type, and the second conductivity type is P-type. For a P-type MOS field-effect transistor, the first and second conductivity types are exactly the opposite of those for an N-type MOS field-effect transistor, i.e., the first conductivity type is P-type, and the second conductivity type is N-type.

[0026] This embodiment provides a novel shielded gate trench MOS device. In the trench 130 of the epitaxial layer 120 located above the substrate 110, a shielded gate region 150, a first interlayer dielectric layer 160, and a control gate region 140 are sequentially provided from bottom to top. The control gate region 140 includes a control gate 141, a gate oxide layer 142, and a designated dielectric layer 143. The control gate 141 has a cross-shaped structure, and the gate oxide layer 142 fills the space between the control gate 141 and the sidewalls within the trench 130. A designated dielectric layer 143 is filled in the top and bottom designated areas of the control gate 141, such that a composite gate dielectric layer is formed on the top left and right sides and the bottom left and right sides of the control gate 141. That is, a composite gate dielectric layer is formed by the composite dielectric layer 143 of the top designated area of ​​the control gate 141 and the gate oxide layer 142 adjacent to the designated dielectric layer 143 of the top designated area, and a composite gate dielectric layer is formed by the composite dielectric layer 143 of the bottom designated area of ​​the control gate 141 and the gate oxide layer 142 adjacent to the designated dielectric layer 143 of the bottom designated area.

[0027] Increasing the thickness of the gate dielectric layer in the overlapping region between the control gate 141 and the source region 172 and the epitaxial layer 120 not only does not affect the formation of the inversion channel layer, but also weakens the effect of high temperature and high gate voltage stress accelerating the degradation of the gate dielectric layer. Furthermore, the designated dielectric layer 143 in the composite gate dielectric layer uses a high-k dielectric material (i.e., silicon nitride). Silicon nitride has a higher dielectric constant and a higher critical electric field strength than silicon oxide, enhancing the gate breakdown voltage of the device. The composite gate dielectric layer structure also increases the thickness of the dielectric layer between the control gate 141 and the doped region 170, thereby improving the gate breakdown voltage of the device.

[0028] Furthermore, the designated dielectric layer 143 of the composite gate dielectric layer replaces a portion of the polysilicon in the control gate 141 of a conventional shielded gate trench MOS device, increasing the dielectric layer thickness between the control gate 141 and the drain, and between the control gate 141 and the source. This significantly reduces the gate-drain capacitance and gate-source capacitance, lowering the device's switching losses. Simultaneously, the designated dielectric layer 143 of the composite gate dielectric layer replaces a portion of the polysilicon in the control gate 141 of a conventional shielded gate trench MOS device, reducing the thickness of part of the control gate 141, lowering the control gate resistance Rg, and improving the device's switching speed. Moreover, the designated dielectric layer 143 in the bottom designated region also helps deplete carriers within the epitaxial layer 120, reducing the peak electric field intensity at the PN junction formed by the body region 171 of the doped region 170 and the epitaxial layer 120, improving the device's avalanche tolerance, and also reducing the probability of device failure in high-temperature applications. Thus, by optimizing the gate dielectric layer structure of the shielded gate trench MOS device, this embodiment enables the device to have a better gate withstand voltage capability, improves the reliability and performance of the shielded gate trench MOS device in harsh operating conditions, reduces gate-drain capacitance and gate-source capacitance, reduces the switching loss of the device, increases the service life of the device in extreme environments, reduces the probability of device failure, and enhances practical efficiency.

[0029] Below, in conjunction with Figure 1 The specific structure of the novel shielded gate trench MOS device in this embodiment is described in detail: like Figure 1As shown, in the control gate region 140, the control gate 141 has a cross-shaped structure. The top of the control gate 141 has two inwardly recessed right-angled regions, namely the top right-angled regions, and the bottom of the control gate 141 has two inwardly recessed right-angled regions, namely the bottom right-angled regions. The longitudinal depth of the control gate region 140 is the maximum longitudinal depth of the control gate 141. The minimum longitudinal depth of the control gate 141 is the longitudinal depth of the control gate 141 between the top right-angled regions and the bottom right-angled regions on each of the left and right sides of the control gate region 140. The lateral width of the control gate region 140 is the maximum lateral width of the control gate 141. The minimum lateral width of the control gate 141 is the lateral width of the control gate 141 between the two top right-angled regions or between the two bottom right-angled regions. The lower surface of the control gate 141 is the bottom surface of the control gate 141, that is, the bottom surface of the control gate 141 between the two bottom right-angled regions.

[0030] The top designated region is the area formed by the top of the control gate 141, the gate oxide layer 142, and the opening of the trench 130. The top designated region is a top right-angled region. The bottom designated region is the area formed by the bottom of the control gate 141, the gate oxide layer 142, and the first interlayer dielectric layer 160. The bottom designated region is a bottom right-angled region. The top designated region and the bottom designated region are designated regions that differ only in location, and will be referred to as each designated region in the following text. A designated dielectric layer 143 is filled in each designated region, such that the designated dielectric layer 143 of each designated region and the gate oxide layer 142 adjacent to the designated dielectric layer 143 form a composite gate dielectric layer. Figure 1 There are four composite gate dielectric layers in the middle.

[0031] In the shielded gate region 150, the thickness of the field oxide layer 152 between the bottom of the shielded gate 151 and the bottom of the trench 130 is the same as the thickness of the field oxide layer 152 between the sidewall of the shielded gate 151 and the corresponding sidewall inside the trench 130. The corresponding sidewall inside the trench 130 is the sidewall inside the trench 130 adjacent to the sidewall of the shielded gate 151. The function of the field oxide layer 152 is: the field oxide layer 152 and the shielded gate 151 together play a charge coupling role, that is, to help deplete the charge carriers in the epitaxial layer 120, thereby realizing the source-drain breakdown voltage capability of the device.

[0032] The MOS device in this embodiment further includes a doped region 170. The doped region 170 is located on the epitaxial layer 120 and surrounds the trench 130. The doped region 170 includes a body region 171 of a second conductivity type and a source region 172 of a first conductivity type. The body region 171 is a heavily doped body region of the second conductivity type, and the source region 172 is a heavily doped source region of the first conductivity type. The body region 171 is located on the epitaxial layer 120 and surrounds the trench 130. The source region 172 is located on the body region 171 and surrounds the trench 130. The upper surface of the source region 172, the upper surface of the body region 171, the opening of the trench 130, and the upper surface of the epitaxial layer 120 are located on the same horizontal plane. The upper surface of the source region 172 and the upper surface of the body region 171 are the upper surfaces of the doped region 170, and the upper surface of the doped region 170 is located on the same horizontal plane as the upper surface of the epitaxial layer 120.

[0033] On each sidewall within the trench 130, the sum of the lateral width of the gate oxide layer 142 and the lateral width of the corresponding designated dielectric layer 143 is equal to the lateral width of the field oxide layer 152 between the sidewall of the shielding gate 151 and the corresponding sidewall within the trench 130. The corresponding designated dielectric layer 143 is the designated dielectric layer 143 adjacent to the gate oxide layer 142. Specifically, on the left sidewall within the trench 130, the sum of the lateral width of the left gate oxide layer 142 and the lateral width of the designated dielectric layer 143 in any designated area on the left side is equal to the lateral width of the field oxide layer 152 between the left sidewall of the shielding gate 151 and the corresponding sidewall within the trench 130. On the right sidewall within the trench 130, the sum of the lateral width of the right gate oxide layer 142 and the lateral width of the designated dielectric layer 143 in any designated area on the right side is equal to the lateral width of the field oxide layer 152 between the right sidewall of the shielding gate 151 and the corresponding sidewall within the trench 130.

[0034] For shielded gate trench MOS devices, the thickness of the field oxide layer 152 is not directly proportional to its drain and source breakdown voltage; that is, a thicker field oxide layer 152 does not necessarily result in better drain and source breakdown voltage. Therefore, this limitation aims to make the designated dielectric layer 143 in the trench 130 (especially the designated dielectric layer 143 in the bottom designated region) play a better role in assisting in the depletion of carriers in the epitaxial layer 120, reducing the peak electric field intensity at the PN junction formed by the body region 171 and the epitaxial layer 120, improving the avalanche withstand capability of the device, and also reducing the failure probability of the device in high-temperature applications.

[0035] The minimum lateral width of the control gate 141 is the same as the lateral width of the shielding gate 151. Specifically, the lateral width of the bottom surface of the control gate 141 is the same as the lateral width of the shielding gate 151. Maintaining a certain thickness of the control gate 141 structure between the designated dielectric layers 143 in two designated regions on the horizontal plane improves the fault tolerance of ion implantation in the body region 171 and the source region 172. In other words, if the body region 171 is made deeper or the source region 172 is made shallower, there will be an overlap region between the body region 171 and the source region 172 and the designated dielectric layer 143. In this overlap region, without the presence of the control gate 141, a complete inversion channel layer cannot be formed, and the device will lack the basic turn-on and turn-off performance. Therefore, this aims to improve the fault tolerance of the device fabrication and ensure no loss of yield. Furthermore, another effect is to increase the dielectric layer thickness between the control gate 141 and the drain to reduce the gate-drain capacitance and decrease the device switching losses.

[0036] The longitudinal depth of the control gate region 140 is greater than the longitudinal depth of the body region 171. This is to ensure that the control gate region 140 has absolute control over the formation of the inversion channel layer. On each sidewall within the trench 130, the longitudinal depth of the designated dielectric layer 143 in the bottom designated region is consistent with the difference between the longitudinal depth of the control gate region 140 and the longitudinal depth of the body region 171. On each sidewall within the trench 130, the longitudinal depth of the designated dielectric layer 143 in the top designated region is consistent with the longitudinal depth of the source region 172.

[0037] Specifically, on the left side wall of trench 130, the longitudinal depth of the designated dielectric layer 143 in the bottom designated region on the left side is consistent with the difference between the longitudinal depth of the control gate region 140 and the longitudinal depth of the body region 171, that is, consistent with the difference between the maximum longitudinal depth of the control gate 141 and the longitudinal depth of the body region 171. On the right side wall of trench 130, the longitudinal depth of the designated dielectric layer 143 in the bottom designated region on the right side is consistent with the difference between the longitudinal depth of the control gate region 140 and the longitudinal depth of the body region 171, that is, consistent with the difference between the maximum longitudinal depth of the control gate 141 and the longitudinal depth of the body region 171. On the left side wall of trench 130, the longitudinal depth of the designated dielectric layer 143 in the top designated region on the left side is consistent with the longitudinal depth of the source region 172 on the left side. On the right side wall of trench 130, the longitudinal depth of the designated dielectric layer 143 in the top designated region on the right side is consistent with the longitudinal depth of the source region 172 on the right side.

[0038] By setting the vertical depth of the specified dielectric layer 143 in the top specified region and the specified dielectric layer 143 in the bottom specified region, not only is the degradation effect of the gate oxide layer 142 maximized and the gate withstand voltage capability of the device enhanced, but the charge coupling effect at the main junction near the sidewall of the trench 130 is also optimized. Furthermore, the formation of the inversion channel layer is not affected, thus not affecting the threshold voltage of the device.

[0039] It should be noted that the longitudinal depth in this embodiment refers to the longitudinal depth from the upper surface of the epitaxial layer 120 to the substrate 110.

[0040] The shielded gate trench MOS device of this embodiment further includes: a second interlayer dielectric layer 180 and a drain region 192. The second interlayer dielectric layer 180 is located above the epitaxial layer 120 and covers the trench 130 and the doped region 170. The second interlayer dielectric layer 180 is an insulating dielectric layer. The material of the second interlayer dielectric layer 180 includes, but is not limited to, undoped silicate glass (USG) and borosilicate glass (BPSG). The function of the second interlayer dielectric layer 180 is to serve as an electrical isolation dielectric layer between the metal layers 190. The drain region 192 is located below the substrate 110. The material of the drain region 192 includes, but is not limited to, metals such as titanium nickel silver and titanium nickel silver tin.

[0041] The shielded gate trench MOS device of this embodiment further includes a metal layer 190 and a plurality of electrode regions 191. The metal layer 190 is located above the second interlayer dielectric layer 180. One end of the plurality of electrode regions 191 contacts the metal layer 190, and the other end contacts the corresponding region to form the electrode of the corresponding region.

[0042] Specifically, multiple electrode regions 191 represent electrodes in corresponding regions. For example... Figure 1 As shown, the top of the electrode region 191 corresponding to the source region 172 (i.e., the electrode corresponding to the source region 172) contacts the metal layer 190, passes through the second interlayer dielectric layer 180 and the source region 172, and the bottom contacts the body region 171. The device in this embodiment also includes an electrode region 191 corresponding to a control gate 141 and an electrode region 191 corresponding to a shielding gate 151. The top of the electrode region 191 corresponding to the control gate 141 contacts the metal layer 190, passes through the second interlayer dielectric layer 180 and the opening of the trench 130, and the bottom contacts the control gate 141. The top of the electrode region 191 corresponding to the shielding gate 151 contacts the metal layer 190, passes through the second interlayer dielectric layer 180 and the opening of the trench 130, and the bottom contacts the shielding gate 151.

[0043] Each electrode region 191 includes: a contact hole, a contact electrode, and a contact area. The contact area is located at the bottom of the contact hole. The contact electrode fills the contact hole and is located above the contact area. Each electrode region 191 is one electrode. The conductivity type of the contact area is the second conductivity type.

[0044] To facilitate understanding of the structural principle of the shielded gate trench MOS device in this embodiment, it is necessary to first explain the structure of the traditional shielded gate trench MOS device (hereinafter referred to as the traditional device): A traditional shielded-gate trench MOS device contains a control gate and a shielding gate within the trench, arranged vertically with the control gate at the top and the shielding gate at the bottom. A gate oxide layer fills the space between the control gate and the inner wall of the trench, while a field oxide layer fills the space between the shielding gate and the inner wall of the trench. The shielded-gate trench MOS device in this embodiment has the same doped region structure as a traditional shielded-gate trench MOS device.

[0045] Between the control gate and the doped region lies a dielectric layer, namely the gate oxide layer, which is approximately rectangular in shape. When a forward bias voltage is applied to the control gate, an inversion channel layer, or simply the channel, is formed in the overlapping region between the gate oxide layer and the body region on the side where the body region contacts the gate oxide layer. The length of the inversion channel layer is called the channel length. When a forward bias voltage is applied across the drain and source terminals, charge carriers move from the epitaxial layer through the inversion channel layer to the source region, forming a complete current path within the device, and the device is in a conducting state. Typically, to ensure that the control gate has absolute control over the formation of the inversion channel layer, the longitudinal length of the control gate must be longer than the channel length, which results in overlapping regions between the control gate and both the source region and the epitaxial layer. In traditional shielded-gate trench MOS devices subjected to prolonged high-temperature gate bias stress, charge carriers (holes) from the source, body, and epitaxial layers tunnel into the gate oxide layer via thermal emission. The injected charge is captured by defects within the gate oxide layer (such as oxygen vacancies and dangling bonds) or by interface states at the oxide-silicon interface, leading to increased leakage current in the control gate. Continuous charge injection and accumulation can cause local electric field distortion, resulting in gate oxide breakdown. Ultimately, this leads to the formation of a permanent low-resistance path between the control gate and the channel, causing a short circuit between the device's gate and source.

[0046] In the shielded gate trench MOS device of this embodiment, a top designated region is formed on the top of the control gate 141, and a top designated region is formed on the bottom of the control gate 141. A designated dielectric layer 143 is filled in each designated region, such that the designated dielectric layer 143 of each designated region and the gate oxide layer 142 adjacent to the designated dielectric layer 143 form a composite gate dielectric layer. This is equivalent to changing the gate oxide layer 142 between the control gate 141 and the source region 172, the body region 171, and the outer delay layer in a conventional shielded gate trench MOS device into a composite gate dielectric layer. This increases the gate dielectric layer thickness in the overlapping region between the control gate 141 and the source region 172 and the epitaxial layer 120, which not only ensures the formation of the inversion channel layer, but also weakens the effect of high temperature and high gate voltage stress accelerating the degradation of the gate dielectric layer of the device. The weakening principle is as follows: One of the key failure mechanisms of gate dielectric layer degradation is the TDDB (Time-Delayed Dielectric Breakdown) effect, where the accumulation of defects within the gate oxide layer 142 leads to an increase in leakage current in the control gate 141 and even gate oxide breakdown. Defects within the gate oxide layer 142 include electron traps, hole traps, and neutral traps. When current flows through the gate oxide layer 142, these traps capture charge carriers, accumulating positive or negative charges and enhancing the local electric field of the gate oxide layer 142. When the traps accumulate a large amount of charge and the local electric field is strong enough, it will cause the Si-O bond (silicon-oxygen bond) to break, leading to the breakdown of the gate oxide layer 142. As long as the charge carriers inside the device have enough energy to overcome the potential barrier, they can freely pass through the dielectric layer into the metal layer 190. Voltage stress and high-temperature stress can provide the charge carriers with additional energy.

[0047] By using the composite gate dielectric layer structure of this embodiment, the dielectric layer thickness in local regions between the source region 172 and the control gate 141, and between the epitaxial layer 120 and the control gate 141 is increased. The specified dielectric layer 143 is thicker than the gate oxide layer 142, that is, the lateral width of the specified dielectric layer 143 is larger than the lateral width of the gate oxide layer 142. This can share most of the voltage stress of the control gate 141, thereby reducing the energizing effect of the control gate 141 on the carriers of the doped region 170 when voltage stress is applied. This reduces the probability that the internal carriers of the source region 172 and the epitaxial layer 120 below the specified dielectric layer 143 will gain energy and enter the gate oxide layer 142, thereby reducing the probability that the carriers will be trapped by the internal traps of the gate oxide layer 142, resulting in an enhanced local electric field and weakening the degradation effect of the gate oxide layer 142.

[0048] Furthermore, the designated dielectric layer 143 in the composite gate dielectric layer uses a high-k dielectric material, namely silicon nitride. The dielectric constant of the silicon nitride layer is higher than that of the silicon dioxide layer, resulting in a higher critical electric field strength, which enhances the gate withstand voltage of the device. The composite gate dielectric layer structure also increases the thickness of the dielectric layer between the control gate 141 and the source region 172, further improving the gate withstand voltage of the device. Additionally, the designated dielectric layer 143 of the composite gate dielectric layer replaces part of the polysilicon of the control gate in conventional devices, increasing the thickness of the dielectric layer between the control gate 141 and the drain, and between the control gate 141 and the source. Since this dielectric layer is a high-k dielectric material, it significantly reduces the gate-drain capacitance and gate-source capacitance of the device, lowering the switching losses. Simultaneously, the designated dielectric layer 143 of the composite gate dielectric layer replaces part of the polysilicon of the control gate in conventional devices, reducing the thickness of part of the control gate 141, lowering the resistance Rg of the control gate 141, and improving the switching speed of the device.

[0049] Furthermore, the designated dielectric layer 143 in the top designated region within the trench 130 serves two purposes: First, the material selected for the designated dielectric layer 143 is a high-k dielectric material, which has a higher critical electric field strength than silicon nitride, thereby improving the gate breakdown voltage of the device. Second, the presence of the designated dielectric layer 143 in the top designated region increases the thickness of the dielectric layer between the control gate 141 and the source region 172. This reduces the electric field strength at the gate dielectric layer when the device is biased with the same gate voltage, thus improving the gate breakdown voltage of the device.

[0050] The designated dielectric layer 143 in the bottom designated region of trench 130 can also assist in depleting the charge carriers in the epitaxial layer 120, reducing the peak electric field strength at the PN junction formed by the body region 171 and the epitaxial layer 120, improving the avalanche resistance of the device, and reducing the failure probability of the device in high-temperature applications. The mechanism by which the designated dielectric layer 143 in the bottom designated region assists in depleting the charge carriers in the epitaxial layer 120 is as follows: In conventional devices, the PN junction formed by the body region 171 and the epitaxial layer 120 is called the main junction. The drain-source breakdown voltage of the device is mainly determined by the breakdown voltage of the main junction and the charge coupling effect of the shielding gate 151 and the field oxide layer 152. There is usually a peak electric field strength at the main junction, called the surface electric field peak. The higher the surface electric field peak, the easier it is for the main junction to break down, and the worse the avalanche resistance of the device.

[0051] In traditional devices, the gate oxide layer in the overlapping region between the epitaxial layer and the control gate also plays a certain role in charge coupling. However, due to the thinness of the gate oxide layer, the charge coupling effect is poor, and the main resistance of the main junction is mainly used to deplete the carriers of the epitaxial layer. Typically, the doping concentration of the epitaxial layer in the overlapping region between the epitaxial layer and the control gate is higher than that of the epitaxial layer closer to the substrate, resulting in a larger peak electric field intensity. Therefore, this area is not only a weak point for gate oxide breakdown but also a weak point for drain-source breakdown. Through the structural arrangement of the designated dielectric layer 143 in the designated region of this embodiment, a charge coupling effect consistent with that of the field oxide layer 152 can be achieved, reducing the peak electric field intensity near the main junction close to the sidewall of the trench 130 and improving the avalanche tolerance of the device.

[0052] Thus, this embodiment optimizes the gate dielectric layer structure of the shielded gate trench MOS device, enabling the device to have superior gate withstand voltage and improving its reliability and performance in harsh applications. Furthermore, it reduces gate-drain capacitance and gate-source capacitance, lowering switching losses, increasing device lifespan in extreme environments, reducing the probability of device failure, and enhancing practical efficiency.

[0053] The fabrication process of the novel shielded gate trench MOS device in this embodiment will be described below: like Figure 2 As shown, a lightly doped epitaxial layer 120 of a first conductivity type is formed on substrate 110 using an epitaxial process. A first dielectric layer (composed of silicon dioxide, silicon nitride, and silicon dioxide sequentially) is grown on the epitaxial layer 120. A masking and etching process is performed on the first dielectric layer to form a first hard mask layer for forming an etching trench 130. Using the first hard mask layer as an etch stop layer, the epitaxial layer 120 is etched to form the trench 130.

[0054] like Figure 3 As shown, a second dielectric layer (the material of the second dielectric layer is silicon dioxide) is formed by CVD deposition in the bottom and sidewalls of the trench 130, and a field oxide layer 152 of the shielding gate 151 is formed by etching.

[0055] like Figure 4 and Figure 5 As shown, a shielding gate conductive polysilicon is deposited on the field oxide layer 152 by CVD deposition, and the polysilicon and the field oxide layer 152 are etched to form a shielding gate 151 and the final field oxide layer 152 in the trench 130.

[0056] like Figure 6As shown, silicon dioxide is deposited in trench 130 by CVD, and an etching process is performed using a first hard mask layer as an etch barrier layer to form a first interlayer dielectric layer 160. The first hard mask layer is removed by etching, and a gate oxide layer 142 is formed on the sidewall of trench 130 by thermal diffusion.

[0057] like Figure 7 As shown, insulating silicon nitride is deposited on the first interlayer dielectric layer 160, and a designated dielectric layer 143 is formed in the bottom designated area by mask etching.

[0058] like Figure 8 As shown, gate conductive polysilicon is deposited in trench 130, and a control gate 141 is formed in part in trench 130 by etching back.

[0059] like Figure 9 As shown, insulating silicon nitride is deposited on the control gate 141, and a designated dielectric layer 143 is formed in the top designated area by mask etching.

[0060] like Figure 10 As shown, gate conductive polysilicon is deposited in trench 130, and a complete control gate 141 is formed in trench 130 by etching back.

[0061] like Figure 11 As shown, a body region 171 is defined by photoresist. Boron ions of a second conductivity type are implanted into the epitaxial layer 120, followed by high-temperature annealing to achieve junction pushing and impurity activation. The body region 171 is formed on the epitaxial layer 120. The vertical depth of the body region 171 is 0.5~0.8 μm.

[0062] like Figure 12 As shown, arsenic ions of the first conductivity type are implanted into the body region 171 and then subjected to high-temperature annealing to achieve the functions of impurity push-through and activation. A source region 172 is formed on the body region 171, and the longitudinal depth of the source region 172 is 0.25~0.3um.

[0063] like Figure 13 As shown, a dielectric layer formed by USG and BPSG is sequentially deposited on the epitaxial layer 120 to form a second interlayer dielectric layer 180. The second interlayer dielectric layer 180 covers the doped region 170 and the trench 130.

[0064] like Figure 14 As shown, the contact hole area is defined by photoresist, the contact hole is formed by etching in the second interlayer dielectric layer 180, and boron difluoride (BF2), a second conductivity type impurity, is implanted into the contact hole. A metal layer 190 is then deposited in the contact hole. Thus, the electrode region 191 and the metal layer 190 are formed.

[0065] like Figure 1As shown, a drain region 192 is deposited under the substrate 110.

[0066] In the device fabrication process of this embodiment, by fabricating an optimized gate dielectric layer structure for the shielded gate trench MOS device, the device exhibits superior gate withstand voltage, improving its reliability and performance in harsh operating conditions. Furthermore, it reduces gate-drain capacitance and gate-source capacitance, lowering switching losses, increasing device lifespan in extreme environments, reducing the probability of device failure, and enhancing practical efficiency. Simultaneously, this device possesses the advantages of simple fabrication process, low manufacturing cost, and high manufacturing efficiency.

[0067] Example 2 Based on the same inventive concept, the second embodiment of the present invention also provides a method for fabricating a novel shielded gate trench MOS device, used to fabricate the novel shielded gate trench MOS device as described in Embodiment 1, such as... Figure 15 As shown, the preparation method includes: S201, an epitaxial layer of a first conductivity type is formed on the substrate; S202, forming trenches in the epitaxial layer; S203, a control gate region, a shield gate region, and a first interlayer dielectric layer are formed in the trench, wherein the control gate region and the shield gate region are distributed in an upper and lower structure, and the first interlayer dielectric layer is located between the control gate region and the shield gate region. The shielded gate region includes: a shielded gate and a field oxide layer; the upper surface of the shielded gate is in contact with the lower surface of the first interlayer dielectric layer, and the field oxide layer fills the space between the shielded gate and the sidewalls and bottom wall of the trench; The control gate region includes: a control gate, a gate oxide layer, and a specified dielectric layer; The control gate has a cross-shaped structure, and the lower surface of the control gate is in contact with the upper surface of the first interlayer dielectric layer; The gate oxide layer fills the space between the control gate and the sidewalls within the trench; The specified dielectric layer is filled in the top specified area and the bottom specified area, wherein the top specified area is the area formed by the top of the control gate, the gate oxide layer and the opening of the trench, and the bottom specified area is the area formed by the bottom of the control gate, the gate oxide layer and the first interlayer dielectric layer.

[0068] Since the fabrication method of the novel shielded gate trench MOS device described in this embodiment is the same as the fabrication method used in Embodiment 1 of this application, those skilled in the art can understand the specific implementation method and various variations of the fabrication method of the novel shielded gate trench MOS device described in Embodiment 1 of this application based on the novel shielded gate trench MOS device described therein. Therefore, how the fabrication method of this novel shielded gate trench MOS device implements the novel shielded gate trench MOS device in Embodiment 1 of this application will not be described in detail here. As long as those skilled in the art implement the fabrication method used in Embodiment 1 of this application, it falls within the scope of protection of this application.

[0069] Those skilled in the art will understand that although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the invention.

[0070] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A novel shielded gate trench MOS device, characterized in that, include: A substrate, an epitaxial layer of a first conductivity type located on the substrate, a trench located in the epitaxial layer, a control gate region, a shielding gate region and a first interlayer dielectric layer located in the trench; The control gate region and the shield gate region are arranged in an upper and lower structure, and the first interlayer dielectric layer is located between the control gate region and the shield gate region; The shielding gate region includes: a shielding gate and a field oxide layer; the upper surface of the shielding gate is in contact with the lower surface of the first interlayer dielectric layer, and the field oxide layer fills the space between the shielding gate and the sidewalls and bottom wall of the trench; The control gate region includes: a control gate, a gate oxide layer, and a specified dielectric layer; The control gate has a cross-shaped structure, and the lower surface of the control gate is in contact with the upper surface of the first interlayer dielectric layer; The gate oxide layer fills the space between the control gate and the sidewalls within the trench; The specified dielectric layer fills the top specified area and the bottom specified area, wherein the top specified area is the area formed by the top of the control gate, the gate oxide layer and the opening of the trench, and the bottom specified area is the area formed by the bottom of the control gate, the gate oxide layer and the first interlayer dielectric layer.

2. The novel shielded gate trench MOS device as described in claim 1, characterized in that, On each sidewall of the trench, the sum of the lateral width of the gate oxide layer and the lateral width of the corresponding designated dielectric layer is consistent with the lateral width of the field oxide layer between the sidewall of the shielding gate and the corresponding sidewall in the trench.

3. The novel shielded gate trench MOS device as described in claim 2, characterized in that, The minimum lateral width of the control gate is the same as the lateral width of the shielding gate.

4. The novel shielded gate trench MOS device as described in claim 2, characterized in that, Also includes: A doped region located on the epitaxial layer and surrounding the trench; The doped region includes: a body region of the second conductivity type and a source region of the first conductivity type; The body region is located on the epitaxial layer and surrounds the trench; The source region is located on the body region and surrounds the trench; The upper surface of the source region, the upper surface of the body region, the opening of the trench, and the upper surface of the epitaxial layer are located on the same horizontal plane.

5. The novel shielded gate trench MOS device as described in claim 4, characterized in that, The longitudinal depth of the control gate region is greater than the longitudinal depth of the body region.

6. The novel shielded gate trench MOS device as described in claim 5, characterized in that, On each sidewall within the trench, the longitudinal depth of the designated dielectric layer in the bottom designated region is consistent with the difference between the longitudinal depth of the control gate region and the longitudinal depth of the body region.

7. The novel shielded gate trench MOS device as described in claim 5, characterized in that, On each sidewall within the trench, the longitudinal depth of the designated medium layer in the top designated area is consistent with the longitudinal depth of the source area.

8. The novel shielded gate trench MOS device according to any one of claims 4 to 7, characterized in that, It also includes: the second interlayer dielectric layer and the drain region; The second interlayer dielectric layer is located above the epitaxial layer and covers the trench and the doped region; The drain region is located beneath the substrate.

9. The novel shielded gate trench MOS device as described in claim 8, characterized in that, Also includes: Metal layer and multiple electrode regions; The metal layer is located above the second interlayer dielectric layer; The plurality of electrode regions are in contact with the metal layer at one end and with the corresponding region at the other end to form the electrode of the corresponding region.

10. A method for fabricating a novel shielded gate trench MOS device, characterized in that, The method for fabricating the novel shielded gate trench MOS device as described in any one of claims 1 to 9 comprises: An epitaxial layer of a first conductivity type is formed on the substrate; Trenches are formed in the epitaxial layer; A control gate region, a shield gate region, and a first interlayer dielectric layer are formed in the trench, wherein the control gate region and the shield gate region are distributed in an upper and lower structure, and the first interlayer dielectric layer is located between the control gate region and the shield gate region. The shielding gate region includes: a shielding gate and a field oxide layer; the upper surface of the shielding gate is in contact with the lower surface of the first interlayer dielectric layer, and the field oxide layer fills the space between the shielding gate and the sidewalls and bottom wall of the trench; The control gate region includes: a control gate, a gate oxide layer, and a specified dielectric layer; The control gate has a cross-shaped structure, and the lower surface of the control gate is in contact with the upper surface of the first interlayer dielectric layer; The gate oxide layer fills the space between the control gate and the sidewalls within the trench; The specified dielectric layer fills the top specified area and the bottom specified area, wherein the top specified area is the area formed by the top of the control gate, the gate oxide layer and the opening of the trench, and the bottom specified area is the area formed by the bottom of the control gate, the gate oxide layer and the first interlayer dielectric layer.

Images