Work function metal boundary offset test structure and test method
By designing a work function metal boundary offset test structure and a simplified data processing method, the problems of complex and costly detection in existing technologies have been solved, achieving efficient and accurate monitoring of metal boundary offset and improving the yield and reliability of semiconductor products.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-26
- Publication Date
- 2026-04-17
AI Technical Summary
Existing methods for detecting the metal boundary offset of the work function are complex and costly, making it difficult to accurately monitor the impact of metal element diffusion on the threshold voltage, which affects the yield and reliability of semiconductor products.
A work function metal boundary offset test structure is designed, including N sets of test units. Each set of units contains a first MOS structure and two second MOS structures. By measuring the threshold voltage of the second MOS structure in each set of test units, the overlay error value is calculated to monitor the metal boundary offset.
By simplifying data processing logic and using a symmetrical structural design, the work function metal boundary offset in the metal replacement gate process can be accurately monitored, improving testing efficiency and result accuracy while reducing costs.
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Figure CN121888925A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor design and manufacturing technology, and particularly relates to a work function metal boundary offset test structure and test method. Background Technology
[0002] In advanced FinFET processes, device voltage regulation is primarily achieved through metal-substituted gate (MBE) technology. In actual layouts, the work function metal boundaries of FinFETs with different threshold voltage (VT) types are adjacent. If the work function metal boundaries between MOSFETs with different threshold voltages are offset (OVL, Overlay) relative to the layout on the actual silicon wafer, the metal boundary effect (MBE) caused by metal diffusion will lead to changes in the threshold voltage of the transistors on both sides of the boundary, affecting product yield and long-term reliability. MBE management (such as suppressing metal diffusion, optimizing OVL alignment, and designing dedicated test structures) has become a core technological bottleneck determining chip performance, yield, and reliability, and a key target in semiconductor process competition.
[0003] Currently, the method for detecting the offset of the work function boundary is TEM (Transmission Electron Microscope) section monitoring. This method requires complex manual steps such as section splitting and point finding, which are time-consuming and costly due to unclear targets and the need for multiple sample cuttings. Summary of the Invention
[0004] To address all or part of the problems in the prior art, this invention provides a work function metal boundary offset test structure and test method to accurately monitor the work function metal boundary offset.
[0005] To achieve the above objectives, the present invention provides a work function metal boundary offset test structure, comprising: N groups of test units, each group of test units comprising: at least one MOS structure group, each MOS structure group comprising a first MOS structure and two second MOS structures different from the first MOS structure, the two second MOS structures being spaced apart on both sides of the first MOS structure; the first MOS structure and the second MOS structures form two work function metal boundaries; In the same group of test units, the work function metal boundary on the same side has the same preset offset relative to the active region of the first MOS structure; in different groups of test units, the work function metal boundary on the same side has different preset offsets relative to the active region of the first MOS structure. N is an integer and N≥3.
[0006] In some embodiments, the first MOS structure and the second MOS structure have different threshold voltage types.
[0007] In some embodiments, the threshold voltage type includes at least one of the following: Positive threshold voltage, negative threshold voltage, standard threshold voltage, low threshold voltage, high threshold voltage, ultra-low threshold voltage, ultra-high threshold voltage.
[0008] In some embodiments, the first MOS structure includes a first substrate, on which a first active region is disposed, and a first source region, a first drain region, and a first metal gate are formed on the first active region. The first source region, the first drain region, and the first metal gate are respectively connected to the test through a first metal layer. The second MOS structure includes a second substrate, on which a second active region is disposed, and a second source region, a second drain region, and a second metal gate are formed on the second active region. The second source region, the second drain region, and the second metal gate are respectively connected to the test through a second metal layer.
[0009] In some embodiments, the first metal gate includes a first test gate and a first dummy gate, the first test gate and the first dummy gate are arranged in parallel with a gap, and the first test gate is connected through the first metal layer; The second metal gate includes a second test gate and a second dummy gate, the second test gate and the second dummy gate are arranged in parallel with a gap between them, and the second test gate is connected through the second metal layer.
[0010] In some embodiments, the work function metal boundary of the first test gate is adjacent to the work function metal boundary of the second test gate; the work function metal boundary of the first dummy gate is adjacent to the work function metal boundary of the second dummy gate.
[0011] This application also provides a test method for the work function metal boundary offset test structure as described above, comprising the following steps: Obtain the threshold voltages of the two second MOS structures in each MOS structure group within each test unit group; Using the threshold voltages and corresponding preset offsets of the two second MOS structures in each MOS structure group in each test unit as reference data, data processing is performed to obtain the overlay error value of the work function metal boundary offset test structure.
[0012] In some embodiments, obtaining the threshold voltage of the two second MOS structures in each MOS structure group within each group of test units includes: Connect the substrate, second source region, second drain region and second metal gate of the second MOS structure of each MOS structure group in any group of test units, and measure the threshold voltage of the corresponding second MOS structure using the dichotomy method. Repeat the above steps to obtain the threshold voltages of the two second MOS structures in each MOS structure group in each group of test units.
[0013] In some embodiments, in a MOS structure group, a preset offset of the work function metal boundary of the second MOS structure relative to the active region of the first MOS structure and the corresponding threshold voltage are defined as a reference data point. Two second MOS structures spaced apart on either side of the first MOS structure are MOS1 and MOS2. Then, the data processing using the threshold voltages and corresponding preset offsets of the two second MOS structures in each MOS structure group as reference data to obtain the overlay error value of the work function metal boundary offset test structure includes: Obtain N reference data points of MOS1 and N reference data points of MOS2, measured by N sets of test units; Obtain at least one threshold voltage reference value; Based on the N reference data points of MOS1 and the N reference data points of MOS2, the first preset offset of MOS1 and the second preset offset of MOS2 are determined respectively under the threshold voltage reference value. The overlay error value of the work function metal boundary offset test structure is calculated based on the first preset offset and the second preset offset under the threshold voltage reference value.
[0014] In some embodiments, calculating the overlay error value of the work function metal boundary offset test structure based on the first preset offset and the second preset offset includes: The average of the first preset offset and the second preset offset under the threshold voltage reference value is taken to obtain the intermediate parameter of the threshold voltage reference value; Data processing is performed based on intermediate parameters of N threshold voltage reference values to obtain the overlay error value of the work function metal boundary offset test structure; N is an integer and N≥3.
[0015] The above-mentioned work function metal boundary offset test structure and test method have the following beneficial effects: (1) By setting up N groups of test units, in the same group of test units, the work function metal boundary on the same side has the same preset offset relative to the active region of the first MOS structure; in different groups of test units, the work function metal boundary on the same side has different preset offset relative to the active region of the first MOS structure, so that the work function metal offset of the metal replacement gate process can be monitored by measuring the threshold voltage electrical data of the two second MOS structures in each group of test units.
[0016] (2) Each test unit group includes: at least one MOS structure group, each MOS structure group including one first MOS structure and two second MOS structures different from the first MOS structure, the two second MOS structures being spaced apart on both sides of the first MOS structure; the first MOS structure and the second MOS structure form two work function metal boundaries, and the MOS structure group is a positionally symmetrical structure. Due to the symmetry of the structure, work function metal boundary offset analysis can be performed by collecting the electrical data of two symmetrical MOS in the same MOS structure group. Since the device environment of the two symmetrical MOS is consistent, the calculation is less affected by process fluctuations, and the calculation results are more accurate. At the same time, accurate overlay error measurement results can be obtained by comprehensively analyzing multiple sets of electrical data. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 This is a schematic diagram of a work function metal boundary offset test structure provided in an embodiment of this application; Figure 2 This is a schematic diagram of a work function metal boundary offset test structure provided in another embodiment of this application; Figure 3 This is a schematic diagram of a work function metal boundary offset test structure provided in another embodiment of this application; Figure 4 A schematic diagram showing the different preset offsets of a first MOS structure relative to two second MOS structures provided in an embodiment of this application; Figure 5 This is a schematic diagram of a test method for a work function metal boundary offset test structure provided in an embodiment of this application; Figure 6 The test result curve of the work function metal boundary offset test structure provided in an embodiment of this application is shown. Detailed Implementation
[0019] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front, or back, are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the present invention.
[0020] This application provides a work function metal boundary offset test structure that can be applied to advanced FinFET process monitoring, particularly for monitoring the offset of the work function metal boundary relative to the layout design in the metal-to-gate replacement process of FinFET. The test structure of this embodiment can measure the offset of the work function metal boundary along a specified direction of the wafer plane and analyze the effect of the resulting metal boundary effect (MBE) on the threshold voltage (VT).
[0021] The metal replacement gate process consists of two parts. The first part is similar to the traditional polysilicon gate process. After the polysilicon gate is completed, an inter-layer dielectric (ILD) is deposited. The second part involves using etching technology to remove the polysilicon gate and the inter-layer dielectric. Then, a high-k dielectric layer and a work function metal suitable for n-type or p-type devices are deposited to adjust the threshold voltage (Vt) of the MOSFET. Finally, the gate trench is filled with a low-resistivity metal.
[0022] In actual layouts, the work function metal boundaries of FinFETs with different threshold voltages (Vt) in metal-substituted gate processes are adjacent. If the work function metal boundaries between MOS transistors with different threshold voltages are offset relative to the layout on the actual silicon wafer (OVL, Overlay), the threshold voltages of the transistors on both sides of the work function metal boundary will change due to the MBE (metal boundary effect) caused by the diffusion of metal elements.
[0023] In this embodiment, as Figure 1 As shown, a work function metal boundary offset test structure is provided, including: N groups of test units, each group of test units including: at least one MOS structure group, each MOS structure group including a first MOS structure and two second MOS structures different from the first MOS structure, the two second MOS structures are spaced apart on both sides of the first MOS structure, that is, symmetrically arranged with respect to the position of the first MOS structure, so that the test unit has a position symmetrical structure, where N is an integer and N≥3.
[0024] Please refer to the following for details. Figure 2 The first MOS structure includes a first substrate SN, on which a first active region AA is disposed. A first source region, a first drain region, and a first metal gate GT1 are formed on the first active region AA. The first source region, the first drain region, and the first metal gate GT1 are respectively connected to a first metal layer for testing. In some embodiments, the first metal layer includes an M0 layer and an M1 layer. The first source region, the first drain region, and the first metal gate GT1 are respectively connected to the M0 layer. The M0 layer is connected to the M1 layer through a via V0 to connect the first source region, the first drain region, and the first metal gate GT1 to the test layer. By testing the threshold voltage of the first MOS structure, the influence of the work function metal layer boundary movement on the threshold voltage value of the first MOS structure can be analyzed.
[0025] The second MOS structure includes a second substrate SP, on which a second active region AA is formed. A second source region, a second drain region, and a second metal gate GT2 are formed on the second active region AA. The second source region, the second drain region, and the second metal gate GT2 are connected to a second metal layer for testing to obtain the threshold voltage value of the second MOS structure. In some embodiments, the second metal layer includes an M0 layer and an M1 layer. The second source region, the second drain region, and the second metal gate GT2 are connected to the M0 layer, and the M0 layer is connected to the M1 layer through a via V0 to connect the second source region, the second drain region, and the second metal gate GT2 for testing. By connecting the second source region, the second drain region, and the second metal gate GT2 to the second MOS structure in each test unit through the second metal layer for testing, two sets of threshold voltage data corresponding to the two second MOS structures can be obtained, thereby calculating the accurate overlay error value. The specific calculation method is described below.
[0026] Of course, in other embodiments, such as Figure 3 As shown, each group of test units may include two or more MOS structure groups. For example, each group of test units includes at least two first MOS structures and at least four second MOS structures, with the at least two second MOS structures arranged side by side and each second MOS structure spaced apart on both sides of each first MOS structure. When each test unit has multiple MOS structure groups, multiple sets of test data can be collected for data processing, reducing the impact of errors.
[0027] In some embodiments, such as Figure 2As shown, to simulate the process environment of densely packed actual devices, stabilize the impact of process deviations and parasitic interference on test results, and ensure that the test structure can accurately reflect the real performance of devices in mass-produced chips, a virtual gate can also be set in the work function metal boundary offset test structure. Exemplarily, the first metal gate GT1 includes a first test gate and a first virtual gate, which are arranged parallel to each other with a gap. Optionally, one or more first virtual gates can be set. When multiple first virtual gates are set, they are arranged parallel to each other with a gap along both sides of the first test gate, and the first test gate is connected through the first metal layer. In some embodiments, the first metal layer includes an M0 layer and an M1 layer. The first test gate is connected to the M0 layer, and the M0 layer is connected to the M1 layer through a via V0 to connect the first test gate for testing. Correspondingly, the second metal gate GT2 includes a second test gate and a second virtual gate, which are arranged parallel to each other with a gap. Optionally, one or more second virtual gates can be set. When multiple second virtual gates are set, they are arranged parallel to each other with a gap along both sides of the second test gate, and the second test gate is connected through the second metal layer. In some embodiments, the second metal layer includes an M0 layer and an M1 layer, and the second test gate is connected to the M0 layer. The M0 layer is connected to the M1 layer through a via V0 to connect the second test gate for testing.
[0028] In this embodiment, the first MOS structure and the second MOS structure have different threshold voltage types. The threshold voltage type can be any one of positive threshold voltage, negative threshold voltage, standard threshold voltage, low threshold voltage, high threshold voltage, ultra-low threshold voltage, and ultra-high threshold voltage. The positive threshold voltage is defined as NMOS (N-channel MOSFET), and the negative threshold voltage as PMOS (P-channel MOSFET). Standard threshold voltages can be, for example, NSVT MOSFET (N-channel Standard Threshold Voltage MOSFET) or PSVT MOSFET (P-channel Standard Threshold Voltage MOSFET). Low threshold voltages can be NLVT MOSFET (N-channel Low Threshold Voltage MOSFET) or PLVT MOSFET (P-channel Low Threshold Voltage MOSFET). Ultra-low threshold voltages can be NULVT MOSFET (N-channel Ultra-Low Threshold Voltage MOSFET) or PULVT MOSFET (P-channel Ultra-Low Threshold Voltage MOSFET). High threshold voltages can be NHVT MOSFET (N-channel High Threshold Voltage MOSFET) or PHVT MOSFET (P-channel High Threshold Voltage MOSFET). Voltage MOSFET, a P-channel MOSFET with high threshold voltage; ultra-high threshold voltage can be NUHVT MOSFET (N-channel Ultra-High Threshold Voltage MOSFET) or PUHVT MOSFET (P-channel Ultra-High Threshold Voltage MOSFET).
[0029] For example, when the first MOS structure can be an NMOS, the second MOS structure can be a PMOS; when the first MOS structure can be a PSVT MOS, the second MOS structure can be a PLVT MOS. This application does not limit the scope of the invention.
[0030] The work function metal is the core structure that determines the gate threshold voltage, forming a physical interface within the gate. In this embodiment, the two second MOS structures in each MOS structure group are spaced apart on both sides of the first MOS structure. The first metal gate GT1 of the first MOS structure and the second metal gates GT2 of the two second MOS structures respectively form two work function metal boundaries, as shown below. Figure 1 As shown in the blue dashed box. In some embodiments, when a dummy gate is provided in the test structure, the first metal gate GT1 includes a first test gate and a first dummy gate, and the second metal gate GT2 includes a second test gate and a second dummy gate. In this case, the two first test gates of the two second MOS structures and the first test gate of the first MOS structure form two work function metal boundaries, and the two first dummy gates of the two second MOS structures and the first dummy gate of the first MOS structure form two work function metal boundaries.
[0031] like Figure 4 As shown, in this embodiment, within the same group of test units, the work function metal boundary on the same side has the same preset offset relative to the active region of the first MOS structure. In different groups of test units, the work function metal boundary on the same side has different preset offsets relative to the active region of the first MOS structure. These different preset offsets include zero offset, several positive offsets relative to zero offset according to a preset offset step size, and several negative offsets.
[0032] In some embodiments, a preset offset of the work function metal boundary of the second MOS structure relative to the active region of the first MOS structure and the corresponding threshold voltage are defined as a reference data point in a MOS structure group. Two second MOS structures, MOS1 and MOS2, are spaced apart on either side of the first MOS structure. When the first MOS structure is offset relative to MOS1 in the direction towards MOS1, the work function metal boundary is offset relative to the active region of the first MOS structure; this offset is positive, and vice versa. For example, the first MOS structure is an NMOS, and MOS1 and MOS2 are PMOS1 and PMOS2, respectively. The zero offset is defined as the NMOS being located between the two PMOS structures. Based on this zero offset, the NMOS is offset along the work function metal boundary direction (i.e.,...). Figure 2The metal boundary of the n MOS / p MOS work function moves (moving towards MOS1 is positive, moving away from MOS1 is negative). The distance of movement can be set to + / -1nm, + / -2nm, + / -3nm, + / -4nm, + / -5nm, + / -6nm, + / -7nm, + / -8nm, + / -9nm, etc., and this application does not make specific limitations.
[0033] In this embodiment, (1) by setting N groups of test units, in the same group of test units, the work function metal boundary on the same side has the same preset offset relative to the active region of the first MOS structure; in different groups of test units, the work function metal boundary on the same side has different preset offset relative to the active region of the first MOS structure, so that the work function metal offset of the metal replacement gate process can be monitored by measuring the threshold voltage electrical data of the two second MOS structures in each group of test units. (2) Each group of test units includes: at least one MOS structure group, each MOS structure group includes a first MOS structure and two second MOS structures different from the first MOS structure, the two second MOS structures are spaced apart on both sides of the first MOS structure; the first MOS structure and the second MOS structure form two work function metal boundaries, and the MOS structure group is a positionally symmetrical structure. Due to the symmetry of the structure, the work function metal boundary offset analysis can be performed by collecting the electrical data of the two symmetrical MOS in the same MOS structure group. Since the device environment of the two symmetrical MOS is consistent, the calculation is less affected by process fluctuations, and the calculation results are more accurate. At the same time, the accurate overlay error measurement results can be obtained by comprehensively analyzing multiple groups of electrical data.
[0034] This application also provides a test method for the work function metal boundary offset test structure described in any of the above embodiments. In the following embodiments, where the work function metal boundary offset test structure is not mentioned, please refer to the corresponding description of the above embodiments. The method includes the following steps S101-S102.
[0035] Step S101: Obtain the threshold voltage of the two second MOS structures in each MOS structure group in each group of test units.
[0036] In this embodiment, a work function metal boundary offset test structure is provided. The test structure includes N test units, each test unit including at least one MOS structure group. Each MOS structure group includes one first MOS structure and two second MOS structures different from the first MOS structure. The two second MOS structures are spaced apart on both sides of the first MOS structure. The first MOS structure and the second MOS structures form two work function metal boundaries. In the two second MOS structures in each test unit's MOS structure group, the second source region, the second drain region, and the second metal gate GT2 are respectively connected and tested through a second metal layer to obtain two sets of threshold voltage data corresponding to the two second MOS structures, which are then used to calculate subsequent overlay errors.
[0037] In some embodiments, obtaining the threshold voltages of the two second MOS structures in each MOS structure group within each group of test units includes: connecting the substrate, second source region, second drain region, and second metal gate GT2 of the second MOS structure in each MOS structure group of any group of test units, and measuring the threshold voltage of the corresponding second MOS structure using a binary search method; repeating the above steps to obtain the threshold voltages of the two second MOS structures in each MOS structure group of each group of test units. Of course, in other embodiments, the method for obtaining the threshold voltages of the two second MOS structures is not limited to the binary search method, and this application does not limit it.
[0038] Step S102: Using the threshold voltages and corresponding preset offsets of the two second MOS structures in each MOS structure group in each group of test units as reference data, data processing is performed to obtain the overlay error value of the work function metal boundary offset test structure.
[0039] In this embodiment, in different groups of test units, the work function metal boundary on the same side has different preset offsets relative to the active region of the first MOS structure. These different preset offsets include zero offset, several positive offsets varying relative to zero offset according to preset offset steps, and several negative offsets. Furthermore, when the preset offset of one second MOS structure is positive, the preset offset of the other second MOS structure is negative, and the absolute value of the preset offsets of the two second MOS structures is zero. Using the threshold voltages of the two second MOS structures in each group of test units and their corresponding preset offsets as reference data, the variation of the threshold voltages of the two second MOS structures with their corresponding preset offsets can be obtained. It should be noted that in the same group of test units, the work function metal boundary on the same side has the same preset offset relative to the active region of the first MOS structure. When one second MOS structure is located on one side of the first MOS structure, the other second MOS structure is located on the other side of the first MOS structure. Moreover, when the preset offset of one second MOS structure is positive, the preset offset of the other second MOS structure is negative, and the absolute value of the preset offsets of the two second MOS structures is zero.
[0040] In this embodiment, the overlay error value of the work function metal boundary offset test structure is obtained by processing the above reference data.
[0041] Specifically, in some embodiments, an "offset-threshold voltage" variation model can be established using the preset offset of the work function metal boundary of the second MOS structure in each test unit relative to the active region of the first MOS structure and the corresponding threshold voltage. The actual measured threshold voltage data is then substituted into the model to infer the overlay error. In practice, sufficient test data can be obtained to ensure the coverage (positive and negative offsets) of the reference data and the model's fitting accuracy. Finally, a reliable overlay error value is obtained using data from two second MOS structures in symmetrically positioned test units. This method is used for the quantitative analysis of work function metal boundary offsets in advanced FinFET processes, supporting process optimization and yield improvement.
[0042] In other embodiments, since each test unit in the test structure has two second MOS structures symmetrically arranged on both sides of the first MOS, theoretically, the threshold voltages of the two second MOS structures should be equal when there is no overlay error (OVL). If an overlay error exists, the threshold voltages of the two second MOS structures will differ, and the magnitude of the difference is monotonically related to OVL. By obtaining the difference in threshold voltages of the two second MOS structures, the influence of global process fluctuations (such as gate dielectric thickness deviation and doping uniformity) can be offset, retaining only the differential signal of OVL, and thus calculating an accurate overlay error value.
[0043] Of course, the method for calculating overlay error is not limited to this. Those skilled in the art can perform corresponding analysis and data processing based on the collected reference data.
[0044] The test unit is a positionally symmetrical structure. Due to the symmetry of the structure, the work function metal boundary offset analysis is performed by collecting the electrical data of two symmetrical MOS in the MOS structure group in the same test unit. Since the device environment of the two symmetrical MOS is the same, the calculation is less affected by process fluctuations and the calculation results are more accurate. At the same time, the accurate overlay error measurement results can be obtained by comprehensively analyzing multiple sets of electrical data.
[0045] In some embodiments, step S102 includes steps S1021-S1024.
[0046] S1021, acquire N reference data points of MOS1 and N reference data points of MOS2 obtained by N sets of test units.
[0047] In this embodiment, among the N test units, corresponding to N MOS1s, N threshold voltage values can be obtained. Using the preset offset of the work function metal boundary of each MOS1 relative to the active region of the first MOS structure and the corresponding threshold voltage as a reference data point, N reference data points for the N MOS1s can be obtained. Similarly, corresponding to N MOS2s, N threshold voltage values can be obtained. Using the preset offset of the work function metal boundary of each MOS2 relative to the active region of the first MOS structure and the corresponding threshold voltage as a reference data point, N reference data points for the N MOS2s can be obtained.
[0048] Of course, in other embodiments, when each group of test units may include at least two MOS structure groups, the average or median of the threshold voltage values corresponding to the at least two MOS structure groups can be used as the threshold voltage of the group of test units, and then the threshold voltages corresponding to N groups of test units can be calculated. This application is not limited to this.
[0049] S1022, Obtain at least one threshold voltage reference value.
[0050] In this embodiment, the threshold voltage reference value refers to any threshold voltage between the maximum and minimum threshold voltage range among the threshold voltages corresponding to the N reference data points of MOS1 and the N reference data points of MOS2. For example, the threshold voltage reference value may be the median of the aforementioned threshold voltage range. This application is not limited thereto.
[0051] S1023, based on the N reference data points of MOS1 and the N reference data points of MOS2, determine the first preset offset corresponding to MOS1 and the second preset offset corresponding to MOS2 under the threshold voltage reference value.
[0052] In this embodiment, as Figure 6 As shown, based on N test units, using N reference data points of MOS1, with the preset offset (boundary shift) of MOS1 as the x-axis and the corresponding threshold voltage Vt at the preset offset as the y-axis, the test result curve of MOS1 can be obtained through data fitting; using N reference data points of MOS2, with the preset offset of MOS2 as the x-axis and the corresponding threshold voltage at the preset offset as the y-axis, the test result curve of MOS2 can be obtained through data fitting.
[0053] In the same coordinate system, on the two test result curves, the first preset offset corresponding to MOS1 and the second preset offset corresponding to MOS2 can be determined under at least one of the above-mentioned threshold voltage reference values.
[0054] S1024, the overlay error value of the work function metal boundary offset test structure is calculated based on the first preset offset and the second preset offset under the threshold voltage reference value.
[0055] Generally, when the work function metal boundary does not shift, the threshold voltage on the test result curve increases or decreases with the preset offset. In this embodiment, since MOS1 and MOS2 in each MOS structure group are symmetrical with respect to the first MOS structure in different test units, the trends of the threshold voltage changes with the offset distance on the two curves are symmetrical. That is, when the threshold voltage reference value Vt is the same, the offset of one MOS boundary is positive, and the offset of the other MOS boundary must be negative, and the absolute values of the two offsets are the same. On the contour line determined by the threshold voltage reference value Vt, at any threshold voltage reference value, the sum of the offset vectors of MOS1 and MOS2 is zero. However, when the work function metal boundary of either MOS1 or MOS2 shifts by 0VL relative to the active region of the first MOS structure, the symmetry of the test structure is broken. At this time, for the work function metal boundary offset test structure with an offset of 0, its actual work function boundary has shifted. Regardless of whether the work function metal layer boundary of the first MOS structure deviates towards MOS1 or MOS2, at any threshold voltage reference value Vt, the sum of the actual offset vectors of MOS1 and MOS2 will deviate from zero by an amount equal to the offset distance.
[0056] In some embodiments, calculating the overlay error value of the work function metal boundary offset test structure based on the first preset offset and the second preset offset under the threshold voltage reference value includes: taking the average of the first preset offset and the second preset offset under the threshold voltage reference value, and determining the average value as the overlay error of the work function metal boundary offset. The average value of the first preset offset and the second preset offset is the average value of the abscissa of the intersection point of the contour line where the threshold voltage reference value is located and the two curves.
[0057] In related technologies, each offset data point has an independent test structure. Data is collected from multiple test structures with different offsets to calculate the corresponding overlay error. However, the locations of the test structures with different offsets and the device environment vary, resulting in significant data errors and a reduced match between the calculated overlay error and the actual situation. Furthermore, comparing multiple test data points to obtain the relative offset is time-consuming.
[0058] The overlay error acquisition method in this embodiment employs simplified data processing logic and utilizes the complementary offset characteristics of symmetrical test units. It quantifies the overlay error of the work function metal boundary offset by measuring the threshold voltage, eliminating the need for complex model fitting and formula derivation, thus improving testing efficiency. Furthermore, in the work function metal boundary offset test structure, the threshold voltage of the second MOS structure is theoretically affected not only by the work function metal boundary offset but also by additional deviations caused by local process fluctuations (such as gate dielectric thickness deviations in small regions, uneven channel doping, and metal deposition thickness fluctuations), leading to distortion of the threshold voltage value corresponding to a single preset offset. The method of "taking the average of the preset offsets of two second MOS structures in the same test unit" in this application essentially utilizes the complementarity of the preset offsets of the second MOS structures (usually the two are "symmetrically offset," both distributed around the true OVL). Since the threshold voltage changes with the offset on the two curves are symmetrical, the curve's center of symmetry shifts after the actual work function boundary shifts. Therefore, the average of the x-coordinates of the intersection points of the contour line containing the threshold voltage reference value and the two curves is the offset value of the metal layer boundary.
[0059] In other embodiments, calculating the overlay error value of the work function metal boundary offset test structure based on the first preset offset and the second preset offset under the threshold voltage reference value includes the following steps: First, take the average of the first preset offset and the second preset offset under the threshold voltage reference value to obtain the intermediate parameter of the threshold voltage reference value. Then, perform data processing based on the intermediate parameters of N threshold voltage reference values to obtain the overlay error value of the work function metal boundary offset test structure; N is an integer and N≥3.
[0060] In this embodiment, the average of the first preset offset and the second preset offset under the threshold voltage reference value is used as an intermediate parameter. Based on this intermediate parameter, further data processing is performed to obtain the overlay error value of the work function metal boundary offset test structure. Specifically, on the test result curve, multiple threshold voltage reference values are determined, and multiple intermediate parameters are obtained based on the average of the first preset offset and the second preset offset under each threshold voltage reference value. The average or median of the multiple intermediate parameters is taken as the overlay error value of the work function metal boundary offset test structure. For example, n (n>=1) contour lines are drawn on the test result curve, where n takes the value from 0 to Vmax, and Vmax is the measured maximum threshold voltage. The abscissa values of the intersection points of each contour line and the two curves are summed to obtain the average x. The average or median of the n x values is taken as the overlay error value. Through the above steps, this embodiment first eliminates the noise interference of local process fluctuations on the threshold voltage measurement results by using intermediate parameters, so as to provide a more stable data basis and significantly reduce the interference on the final overlay error. Then, multiple sets of intermediate parameters are taken for calculation and processing. The median can reduce the interference of extreme data values, and the mean can reduce random errors and improve the accuracy of the calculation results, thereby ensuring that the overlay error reflects the true process level.
[0061] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0062] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.
Claims
1. A work function metal boundary offset test structure, comprising: include: N groups of test units, each group of test units includes: At least one MOS structure group, each MOS structure group including a first MOS structure and two second MOS structures different from the first MOS structure, the two second MOS structures being spaced apart on both sides of the first MOS structure; the first MOS structure and the second MOS structures form two work function metal boundaries; In the same group of test units, the work function metal boundary on the same side has the same preset offset relative to the active region of the first MOS structure; in different groups of test units, the work function metal boundary on the same side has different preset offsets relative to the active region of the first MOS structure. N is an integer and N≥3.
2. The work function metal boundary offset test structure of claim 1, wherein, The first MOS structure and the second MOS structure have different threshold voltage types.
3. The work function metal boundary offset test structure of claim 1, wherein, The threshold voltage type includes at least one of the following: Positive threshold voltage, negative threshold voltage, standard threshold voltage, low threshold voltage, high threshold voltage, ultra-low threshold voltage, ultra-high threshold voltage.
4. The work function metal boundary offset test structure according to claim 1, characterized in that, The first MOS structure includes a first substrate, on which a first active region is disposed, and a first source region, a first drain region, and a first metal gate are formed on the first active region. The first source region, the first drain region, and the first metal gate are respectively connected to the test through a first metal layer. The second MOS structure includes a second substrate, on which a second active region is disposed, and a second source region, a second drain region, and a second metal gate are formed on the second active region. The second source region, the second drain region, and the second metal gate are respectively connected to the test through a second metal layer.
5. The work function metal boundary offset test structure of claim 4, wherein, The first metal gate includes a first test gate and a first dummy gate, the first test gate and the first dummy gate are arranged in parallel with a gap, and the first test gate is connected through the first metal layer; The second metal gate includes a second test gate and a second dummy gate, the second test gate and the second dummy gate are arranged in parallel with a gap between them, and the second test gate is connected through the second metal layer.
6. The work function metal boundary offset test structure according to claim 5, characterized in that, The work function metal boundary of the first test gate is adjacent to the work function metal boundary of the second test gate; the work function metal boundary of the first virtual gate is adjacent to the work function metal boundary of the second virtual gate.
7. A test method applied to the work function metal border offset test structure according to any one of claims 1 to 6, characterized in that, Includes the following steps: Obtain the threshold voltages of the two second MOS structures in each MOS structure group within each test unit group; Using the threshold voltages and corresponding preset offsets of the two second MOS structures in each MOS structure group in each test unit as reference data, data processing is performed to obtain the overlay error value of the work function metal boundary offset test structure.
8. The test method of claim 7, wherein, The acquisition of the threshold voltage of the two second MOS structures in each MOS structure group within each test unit group includes: Connect the substrate, second source region, second drain region and second metal gate of the second MOS structure of each MOS structure group in any group of test units, and measure the threshold voltage of the corresponding second MOS structure using the dichotomy method. Repeat the above steps to obtain the threshold voltages of the two second MOS structures in each MOS structure group in each group of test units.
9. The test method of claim 7, wherein, In a defined MOS structure group, the preset offset of the work function metal boundary of the second MOS structure relative to the active region of the first MOS structure and the corresponding threshold voltage are used as a reference data point. Two second MOS structures spaced apart on either side of the first MOS structure are MOS1 and MOS2. Then, using the threshold voltages and corresponding preset offsets of the two second MOS structures in each MOS structure group as reference data for data processing, the overlay error value of the work function metal boundary offset test structure is obtained, including: Obtain N reference data points of MOS1 and N reference data points of MOS2, measured by N sets of test units; Obtain at least one threshold voltage reference value; Based on the N reference data points of MOS1 and the N reference data points of MOS2, the first preset offset of MOS1 and the second preset offset of MOS2 are determined respectively under the threshold voltage reference value. The overlay error value of the work function metal boundary offset test structure is calculated based on the first preset offset and the second preset offset under the threshold voltage reference value.
10. The test method according to claim 9, characterized in that, The calculation of the overlay error value of the work function metal boundary offset test structure based on the first preset offset and the second preset offset includes: The average of the first preset offset and the second preset offset under the threshold voltage reference value is taken to obtain the intermediate parameter of the threshold voltage reference value; Data processing is performed based on intermediate parameters of N threshold voltage reference values to obtain the overlay error value of the work function metal boundary offset test structure; N is an integer and N≥3.