Optical inspection method and defect detection method of semiconductor structure

Abstract

The embodiment of the invention discloses an optical inspection method and a defect detection method of a semiconductor structure. A method embodiment includes generating a first image of a previous layer in a semiconductor structure, generating a second image of an inspection layer in the semiconductor structure, transforming the first image using a deep learning model to generate a noise cancelled image, and removing image noise from the second image based on the noise cancelled image.

Description

Technical Field

[0001] The embodiments of this application relate to optical inspection methods and defect detection methods for semiconductor structures. Background Technology

[0002] As IC technology continues to evolve towards smaller feature sizes, such as 32nm, 28nm, 20nm and below, integrated circuit (IC) design becomes increasingly challenging. For example, when manufacturing IC devices, their performance is affected by photolithographic printability, which indicates the degree to which the final wafer pattern formed on the wafer corresponds to the target pattern defined by the IC design layout. As patterns become increasingly complex, the need for high-resolution inspection systems becomes more apparent to accurately detect and resolve defects. Summary of the Invention

[0003] According to one aspect of the embodiments of this application, an optical inspection method for a semiconductor structure is provided, comprising: generating a first image of a previous layer in the semiconductor structure; generating a second image of the inspection layer in the semiconductor structure; transforming the first image using a deep learning model to generate a noise-reduced image; and removing image noise from the second image based on the noise-reduced image.

[0004] According to another aspect of the embodiments of this application, an optical inspection method for a semiconductor structure is provided, comprising: training a deep learning model by performing operations including: collecting first image data of each of a plurality of previous layers of the semiconductor structure and second image data of an inspection layer of the semiconductor structure; identifying a first noise feature in the first image data and identifying a second noise feature in the second image data; and adjusting parameters of the deep learning model such that the deep learning model transforms the first noise feature to generate a noise-cancelled image approximating the second noise feature. The optical inspection method further comprises: reducing image noise in the second image by performing pixel-level subtraction on the noise-cancelled image in the second image data to generate a corrected image of the inspection layer.

[0005] According to another aspect of the embodiments of this application, a defect detection method for a semiconductor structure is provided, comprising: collecting first image data of each of a plurality of previous layers of the semiconductor structure; collecting second image data of an inspection layer of the semiconductor structure; generating a noise-reduced image using a deep learning model, wherein the deep learning model uses the design layout of the semiconductor structure and the first image data as input and provides the noise-reduced image as output; removing image noise in the second image data by subtracting the noise-reduced image from the second image data to generate a corrected image of the inspection layer; and performing a defect detection algorithm on the corrected image of the inspection layer to detect at least one defect in the inspection layer. Attached Figure Description

[0006] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various parts are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various parts may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 This is a block diagram of an image noise reduction method according to various embodiments.

[0008] Figure 2A This is a top view of a previous layer in a semiconductor device structure according to various embodiments.

[0009] Figure 2B This is a top view of a previous layer in a semiconductor device structure according to various embodiments.

[0010] Figure 2C This is a top view of the inspection layer of a semiconductor device structure according to various embodiments.

[0011] Figure 3 According to various embodiments Figures 2A to 2C A vertical cross-sectional view of the semiconductor device structure.

[0012] Figure 4A This is a block diagram detailing a method for generating a first image of a previous layer according to various embodiments.

[0013] Figure 4B This is a block diagram of a first deep learning model according to various embodiments.

[0014] Figure 4C This is a block diagram of a method for training a first deep learning model according to various embodiments.

[0015] Figure 5A This is a block diagram of a method for training a second deep learning model according to various embodiments.

[0016] Figure 5B This is a block diagram of a method for applying a second deep learning model to defect detection according to various embodiments.

[0017] Figure 5C It is a three-dimensional perspective view of an inspection tool that represents multiple custom chips representing various previous layers, according to various embodiments.

[0018] Figure 5D This is a block diagram detailing the methods for generating the first image of the previous layer and training the deep learning model according to various embodiments.

[0019] Figure 6 This is a flowchart of a method for removing image noise from an image of an inspection layer in a semiconductor structure according to various embodiments.

[0020] Figure 7 This is a flowchart of a method for removing image noise from an image of an inspection layer in a semiconductor structure according to various embodiments.

[0021] Figure 8 This is a flowchart of a method for detecting defects in a semiconductor structure according to various embodiments.

[0022] Figure 9 It is configured to execute according to various implementation examples. Figure 6 , Figure 7 and Figure 8 A schematic layout of a computer system using this method. Detailed Implementation

[0023] It should be understood that the following disclosure provides many different embodiments or instances for implementing the various features of this disclosure. Specific embodiments or instances of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, the dimensions of elements are not limited to the disclosed range or values, but may depend on process conditions and / or desired characteristics of the device. Furthermore, in the following description, forming a first component on or above a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. For simplicity and clarity, various features may be drawn at any scale.

[0024] Furthermore, for ease of description, spaced relation terms such as “below,” “under,” “lower,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or component and another element or component as shown in the figures. In addition to the orientations shown in the figures, spaced relation terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spaced relation descriptors used herein may be interpreted accordingly. Furthermore, the term “composed of” may mean “comprising” or “made of.” In this disclosure, the phrase “one of A, B, and C” means “A, B, and / or C” (A, B, C, A and B, A and C, B and C, or A, B, and C), and unless otherwise stated, does not refer to an element from A, an element from B, and an element from C.

[0025] One or more of the disclosed embodiments advantageously disclose a method for inspecting an inspection layer (IL) in a semiconductor device layer based on information collected from one or more previously formed layers (also referred to as prior layers (PL)). In this regard, the disclosed systems and methods transform images from one or more prior layers with layout and process critical dimensions (CD) to generate one or more noise-reduced images that are effective in suppressing noise in the inspection layer images. The generation of these noise-reduced images utilizes the deep learning capabilities of a vision transformer model that leverages layout information and is modulated with CD data from the wafer being inspected.

[0026] Optical inspection is a useful tool for detecting yield-affecting defects in semiconductor wafers and devices due to its speed and versatility. However, in advanced node structures, yield-affecting defects not only become smaller but are often embedded in nanoscale structures. For many types of embedded defects, light waves can penetrate nanostructures and capture signals from these defects. However, since these defects are mostly at the nanoscale, the defect signals are very weak. During inspection, these weak signals are often masked by noise caused by structural or material variations in previous layers, making the defect signals difficult to detect.

[0027] Figure 1 This is a block diagram of an image noise reduction method 100 according to various embodiments. According to method 100, a first operation includes generating a first image 102 of a previous layer in a semiconductor structure during or after the formation of the previous layer, and generating a second image 104 of an inspection layer during or after the formation of an inspection layer. The second image 104 shows the presence of a defect 106 in the inspection layer and a region of interest 108 is shown in the first image 102. The region of interest 108 is not related to the defect in the previous layer but is used to highlight the region generating a noise signal that tends to mask the defect signal generated by the defect 106 in the inspection layer.

[0028] Method 100 further includes using a deep learning model to transform the first image 102 to generate a noise-reduced image, as shown in box 110. The noise-reduced image is then subtracted from the second image 104 to generate a corrected image 112 for the inspection layer, as further indicated in box 110. Method 100 also includes performing a defect detection algorithm on the corrected image 112, as shown in box 114. According to some embodiments, method 100 selects at least one previous layer that contributes to image noise in the inspection layer. This determination utilizes process knowledge; for example, when inspecting polysilicon layers, global etch variations are often a significant source of noise.

[0029] Figure 2A and Figure 2B This is a top view of the previous layers (200a, 200b) according to various embodiments. Figure 2CThis is a top view of the inspection layer 200c of a semiconductor device. A first prior layer 200a has a first layout including a first geometric pattern 202a, a second prior layer 200b has a second layout including a second geometric pattern 202b, and the inspection layer 200c has a third layout including a third geometric pattern 202c. Therefore, the semiconductor device is a stacked structure, wherein the second prior layer 200b is formed over the first prior layer 200a, and the inspection layer 200c is formed over the second prior layer 200b. The inspection layer 200c also includes two nanoscale defects 206a and 206b. In other embodiments, the inspection layer 200c has more or fewer defects.

[0030] Inspection radiation (e.g., light or electron beam) for inspecting inspection layer 200c is introduced and propagates within the structure, scattering from various geometric patterns (202a, 202b, 202c). Therefore, first radiation 204a scattered from the first geometric pattern 202a propagates in various directions, including upwards through the top surface of the second preceding layer 200b and inspection layer 200c. Thus, the presence of first radiation 204a generates a noise signal 204a', which tends to mask the first defect signal 302a scattered from the first nanoscale defect 206a (e.g., see...). Figure 3 Similarly, the second radiation 204b scattered from the second geometric pattern 202b propagates in various directions, including upward through the top surface of the inspection layer 200c. Therefore, the presence of the second radiation 204b acts as a noise signal that masks the second defect signal 302b scattered from the second nanoscale defect 206b (see, for example, [link to relevant documentation]). Figure 3 ).

[0031] Figure 3 According to various embodiments Figures 2A to 2C A vertical cross-sectional view of a semiconductor device structure 300. (See diagram below.) Figure 3 As shown, the semiconductor device structure 300 includes a second prior layer 200b formed over the first prior layer 200a and an inspection layer 200c formed over the second prior layer 200b. As described above, the semiconductor device structure 300 includes a first geometric pattern 202a formed on the surface of the first prior layer 200a, a second geometric pattern 202b formed on the surface of the second prior layer 200b, and a third geometric pattern 202c formed on the surface of the inspection layer 200c.

[0032] The first radiation 204a originates from a first portion of the inspection radiation (e.g., light or electron beam) scattered from the first geometric pattern 202a, while the second radiation 204b originates from a second portion of the inspection radiation scattered from the second geometric pattern 202b. The first radiation 202a in the second prior layer 200b propagates to the inspection layer 200c, thereby generating the first radiation 202a' in the inspection layer 200c. The first radiation 204a' and the second radiation 204b tend to mask (i.e., obscure) the first defect signal 302a and the second defect signal 302b, respectively. Therefore, the first radiation 204a' and the second radiation 204b act as unwanted noise sources. Figures 2A to 3 As shown, due to reflection and refraction, the spatial distribution and intensity of the noise sources (204a', 204b) vary as radiation propagates within the structures (200a, 200b, 200c). Therefore, the first image 102 captured during or after the formation of the previous layers (200a, 200b) (see, for example, [reference needed]) Figure 1 The noise sources (204a', 204b) at the inspection layer 200c cannot be removed by subtracting such a first image 102 from the second image 104 of the inspection layer, because the second noise sources (204a', 204b) are not simple copies of their sources in the layers below.

[0033] Based on the above insights, one or more embodiments use a deep learning model to automatically transform image data from one or more previous layers to generate at least one noise-reduced image that approximates the noise sources (204a', 204b) found in the second image 104 of the inspection layer 200c. This noise-reduced image is then subtracted from the second image 104 to remove unwanted noise sources (204a', 204b), thereby improving the signal-to-noise ratio of the defect signals (302a, 302b). Therefore, the detection of nanoscale defects is significantly improved.

[0034] Compared to other methods, one or more embodiments utilize image data from multiple previous layers to completely cover the noise sources of the previous layers and leverage layout information to distinguish regions within each previous layer image 102 for more efficient noise cancellation. The disclosed deep learning model is trained to determine the optimal selection of previous layers based on layout and weights. Various embodiments further incorporate the CD and film stack data of the inspection layer to adjust the weights of the previous layer images during image noise cancellation operations. Both the inspection layer and previous layer images are aligned with the design layout as a common reference. This use of the common reference achieves optimal alignment, thereby reducing errors caused by misalignment between subsequently subtracted images. According to various embodiments, data for training the deep learning model is collected based on experimental measurements of the fabricated semiconductor structure. Alternatively, in other embodiments, data for training the deep learning model is generated based on numerical simulations based on physical optics theory.

[0035] Deep learning models are advanced machine learning algorithms designed to automatically learn patterns and features from large amounts of data. These models are based on artificial neural networks, which consist of multiple layers of interconnected nodes or “neurons” that process and transform input data in layers. Specific types of deep learning models that can be used in semiconductor applications include, but are not limited to, convolutional neural networks (CNNs), visual transformers, recurrent neural networks (RNNs), and fully connected deep neural networks (DNNs).

[0036] In box 404, and refer to Figure 4C In more detail, a first deep learning model (e.g., using a self-attention mechanism) is trained to identify various features of image noise sources included in each first image 102. For example, in a visual transformer, the self-attention mechanism helps distinguish noise from actual image content by computing attention scores that reflect the relationships between image patches. Noise characterized by random variations in pixel values ​​manifests as high-frequency patterns, local perturbations, and / or irrelevant correlations that do not follow the natural structure of the image. Because the noise is not aligned with the spatial structure of the image, the self-attention mechanism assigns less importance to the allocation of noisy patches. This mechanism identifies these patches as less relevant because they disrupt the meaningful correlation between adjacent image patches.

[0037] The self-attention mechanism in visual transformers works by focusing on blocks that exhibit coherent spatial relationships (such as edges or textures) while ignoring blocks containing random, irrelevant noise. Through this process, the model suppresses the effects of noise, allowing it to focus on the more structured content of the image. The attention mechanism highlights coherent patterns representing actual content, such as gradations of color and intensity, which represent realistic image features. In contrast, noise does not maintain any consistent relationship with its surroundings, and this lack of structure allows the model to reduce or ignore noisy blocks.

[0038] Similarly, in convolutional neural networks (CNNs), noise identification and reduction are primarily driven by the network's ability to learn spatial hierarchies through convolutional layers. CNNs process images by applying filters (cores) that slide across the image to detect local patterns and features such as edges, textures, and / or shapes. Noise manifests as random, high-frequency fluctuations that do not correspond to any meaningful image structure. Because CNNs focus on learning spatial relationships, convolutional filters are trained to recognize these inconsistencies, which appear as irregular patterns that disrupt the natural flow of image features.

[0039] During training, CNNs learn to distinguish between relevant content and noise in an image by adjusting their filters to capture and enhance important features while minimizing the impact of noise. The first layer of the network typically detects low-level features such as edges, corners, or simple textures, which are generally unaffected by noise. As the image progresses to deeper layers, the CNN combines these low-level features into more complex structures, such as objects or regions of interest. Noise is random and uncorrelated, and does not form coherent patterns at these higher levels. Therefore, CNNs tend to learn to focus on stable, structured patterns in the image while ignoring unstable disturbances caused by noise.

[0040] Convolutional filters in a network automatically learn to identify noise through their receptive fields (regions of the image they focus on). Filters sensitive to high-frequency components are more likely to detect noise because noise tends to introduce high-frequency variations that are not part of the image's true structure. CNNs suppress these noise components by applying more focused low-frequency filters in deeper layers, which naturally smooths the image and enhances its meaningful features. Furthermore, pooling layers reduce the spatial resolution of the image, smoothing out random disturbances by averaging variations in pixel values ​​over larger regions, further contributing to noise reduction. Thus, convolutional neural networks identify noise by learning to distinguish between high-frequency random fluctuations and more consistent, meaningful patterns in an image. Through its hierarchical structure, CNNs focus on relevant features while suppressing irrelevant noise components, effectively reducing noise and improving image quality.

[0041] Figure 5A This is a block diagram 500a detailing a method for training a second deep learning model according to various embodiments. In block 502, the input information of the second deep learning model includes information from a first deep learning model (i.e., see...). Figure 4CMultiple noise-reduced images 412 are generated (box 410), as shown in boxes 504a to 504n, where n is a positive non-zero integer representing the number of noise-reduced images 412. In box 506, the input information of the second deep learning model also includes checking the design layout of the layers. In box 508, the output of the second deep learning model is a single noise-reduced image generated as a weighted sum of all the input noise-reduced images 412.

[0042] In box 510, as shown in box 512, a device with known defects (206a, 206b) is used (see, for example, see...). Figure 2C The second image 104 of the inspection layer 200c is used to generate image differences. Then, the combined noise-reduced image of box 508 is subtracted from the second image 104 to reduce the noise signals (204a', 204b) in the second image 104, resulting in image differences, as shown in box 512. A defect detection algorithm is then applied to the corrected second image to determine defect signals (302a, 302b). The cost function 514 is then defined as 1 / SNR, where SNR is the signal-to-noise ratio calculated by comparing one or more defect signals (302a, 302b) to the average residual noise in the corrected second image 104. The model is then trained by adjusting various weights in the model. Figure 5A The second deep learning model minimizes the cost function. In this regard, the weights include weights associated with the node pairs in the neural network and weights associated with the weighted sum of the noise-reduced images indicated in box 502.

[0043] Figure 5B This is a block diagram detailing methods for applying a second deep learning model to defect detection according to various embodiments. After training the second deep learning model, for example, as referenced above... Figure 5A The second deep learning model is applicable to the practical situation of defect detection in semiconductor wafers and devices. In this regard, during the manufacturing process, a first image 102 is collected using a corresponding optimized optical pattern at each previous layer. The first image 102 is then provided to the first deep learning model 410 to generate a plurality of corresponding noise-reduced images 412. Figure 5B In this process, the multiple noise-cancelled images 412 are then provided as input to a second deep learning model, such as Figure 5B As shown in box 502.

[0044] Then, adjust the weights W1…Wn associated with the weighted sum of these noise-reduced images 412 as needed (e.g., see [link to relevant documentation]). Figure 5BThe weights W1…Wn are further adjusted to take into account the geometric differences (e.g., CD differences) between the previous layers (200a, 200b) in the semiconductor device under inspection and the corresponding previous layers used to train the first and second deep learning models. According to some embodiments, the weights W1…Wn are further adjusted to take into account the geometric differences between the inspection layer 200c of the semiconductor device under inspection and the corresponding inspection layers used to train the first and second deep learning models.

[0045] In box 508, the output of the second deep learning model is a combined noise-reduced image, which is subtracted from the second image 104 of the inspection layer (e.g., see box 510) to produce an image difference, as shown in box 512. The image difference in box 512 is the second image 104 with noise reduction correction that can be used for defect detection, as shown in box 514.

[0046] Figure 9 It is configured to execute according to various implementation examples. Figure 6 , Figure 7 , Figure 8 A schematic diagram of a computer system 100 for the method. In some embodiments, the device (also referred to herein as a computer system) 1100 includes an optical simulator and / or a defect detection device 1100. All or part of the processes, methods, and / or operations of the embodiments described above are implemented using computer hardware and computer programs executed thereon. In addition to an optical disc drive 1105 and a disk drive 1106, the computer 1101 is equipped with one or more processors 1111, such as a microprocessor (MPU), a read-only memory (ROM) 1112 (wherein programs, such as boot programs, are stored), random access memory (RAM) 1113 (connected to the MPU 1111 and temporarily storing application commands and providing temporary storage areas therein), a hard disk 1114 (wherein applications, system programs, and data are stored), and a bus 1115 (connected to the MPU 1112, ROM 1112, etc.). Note that the computer 1101 may include a network card (not shown) for providing connectivity to a LAN. In some embodiments, one or more of the ROM 1112, RAM 1113, and hard disk 1114 are not included in the computer 1101.

[0047] In the foregoing embodiments, computer program instructions configured to cause computer system 1100 to execute processes for defining a mask layout are stored in a non-transitory computer-readable storage medium, such as optical disc 1121 or disk 1122. Such a storage medium is configured to be inserted into optical disc drive 1105 or disk drive 1106 and transferred to hard disk 1114. Alternatively, the program can be transferred to computer 1101 via a network (not shown) and stored in hard disk 1114 (or other non-transitory computer-readable storage medium). During execution, the program is loaded into RAM 1113. The program can be loaded from optical disc 1121 or disk 1122, or directly from the network. In the above embodiments, the program does not necessarily need to include an operating system (OS) or third-party programs to cause computer 1101 to perform the process of manufacturing a photolithographic mask for semiconductor devices. The program may only include a command portion to call appropriate functions (modules) in controlled mode and obtain the desired results.

[0048] In some embodiments, recurrent neural networks (RNNs) capable of processing sequential data are applied to scenarios where there is temporal correlation, such as analyzing time-series data or data from wafer inspection systems that collect measurements that vary over time. In some embodiments, RNNs help identify data patterns that evolve over time, making such networks suitable for defect tracking or prediction of future wafer features based on historical data.

[0049] Fully connected deep neural networks (DNNs) are more general networks in which each neuron in one layer is connected to every neuron in subsequent layers. These models are effective for tasks that do not specifically involve spatial or temporal dependencies, such as predicting certain wafer characteristics from a variety of input features, such as process parameters or measurements. DNNs are particularly useful in situations where there is a complex nonlinear relationship between the input and output.

[0050] In some embodiments, these deep learning models are trained using labeled datasets, where input data is paired with known results to optimize the network's parameters. Training is typically performed using a process called backpropagation, which adjusts the weights of the connections between neurons to minimize the error between the predicted output and the true output.

[0051] Various implementations are based on CNNs, which are designed to analyze image data by leveraging the inherent spatial structure within images. These networks are well-suited for tasks requiring hierarchical pattern recognition, such as detecting anomalies or features in images with complex patterns, like those encountered in semiconductor device manufacturing. CNNs operate by learning patterns at multiple levels of abstraction, allowing for the detection of fine-grained features, such as edges and textures, as well as higher-order structures that are important for recognizing more complex patterns.

[0052] The architecture of a CNN comprises several key layers that process image data hierarchically. Convolutional layers apply a set of learnable filters to the input image. Each filter slides across the image, performing a convolution operation that determines local features such as edges, corners, and texture. Multiple filters are applied in parallel to capture different features at different levels. After the convolution operation, the output is typically passed through an activation function, such as a rectified linear unit (ReLU), which introduces non-linearity into the network and allows it to model complex patterns. Subsequent pooling layers (typically max pooling) reduce the spatial dimensionality of the data while preserving important features, allowing the network to focus on larger, more abstract patterns. Pooling also reduces the computational burden and the number of parameters in the model.

[0053] Following these layers, the network typically includes fully connected layers, where learned features from convolutional and pooling layers are combined and used for prediction or classification. The network's output layer provides the final result, which can be a classification decision, such as identifying the presence of a defect, or a regression value indicating the severity or type of an anomaly.

[0054] One advantage of CNNs is their ability to learn hierarchical representations of data. In the initial layers, the network captures low-level features, such as simple geometric patterns and textures. As data progresses to deeper layers, the network begins to combine these low-level features into more complex abstract patterns, which is crucial for understanding the context of an image. This hierarchical approach enables the network to identify specific features or anomalies, such as deviations from expected patterns or local defects, which are relevant to the inspection process.

[0055] Furthermore, CNNs utilize local connectivity and weight sharing, which are essential for their efficiency. In traditional fully connected neural networks, each neuron in a layer is connected to every neuron in the next layer, resulting in a large number of parameters. In contrast, the convolutional layers in CNNs have local connectivity, meaning that each neuron is connected to only a small region of the input image. This reduces the number of parameters and allows the network to focus on detecting local features. Moreover, weight sharing means that the same filter can be applied to different parts of the image, enabling the CNN model to capture features regardless of their location within the image.

[0056] In some embodiments related to semiconductor device manufacturing, CNNs are applied to analyze optical images generated during various stages of wafer inspection. The CNN processes the generated images to identify patterns and anomalies that may indicate defects or problems in the semiconductor manufacturing process. By learning to recognize specific patterns in the images, such as deviations from expected geometry or the presence of foreign objects, the CNN is trained to detect a variety of potential defects. The network's ability to learn from labeled data allows it to generalize the learned features to new, unseen images, providing automated and reliable defect detection.

[0057] The ability of CNNs to automatically detect and locate defects in complex, high-dimensional image data makes them suitable for inspecting semiconductor wafers. Furthermore, CNNs can be used to monitor the manufacturing process in real time, marking deviations from expected patterns or detecting early signs of potential problems. This capability makes CNNs a powerful tool for improving the accuracy and efficiency of semiconductor manufacturing, potentially leading to increased yields and reduced process variability. The hierarchical learning methods inherent in CNNs, combined with their efficiency in processing large-scale image data, enable the identification of subtle local anomalies that might be difficult to detect using traditional methods.

[0058] Figure 4A The generation of the previous layer PL according to various embodiments i The first image 102 is a detailed block diagram of method 400a. During the manufacturing process, when each previous layer PL is formed according to block 401a... i At that time, select multiple optical modes OM j And as shown in box 401c, by scanning each previous layer PL i To generate a plurality of corresponding first images 102, so as to generate a first image 102 for each of a plurality of optical models OMj. Then the previous layer (PL) generated in this way is stored. i OM j The first image 102 is used later for training the first deep learning model, as shown below. Figure 4B A more detailed description.

[0059] According to various embodiments, Figure 4B This is a block diagram 400b detailing the method for training the first deep learning model. Figure 4C It is training Figure 4B A further detailed block diagram 404 illustrates the method of the first deep learning model. As described above, the first deep learning model comprises a neural network defined by multiple nodes and multiple weights representing the connections between node pairs within the multiple nodes. The first deep learning model is trained by adjusting the multiple weights to generate an optimal image filter "F" that, when applied to each of the multiple first images 102 in the previous layer, generates a corresponding noise-reduced image that approximates the noise features in the second image 104 of the inspection layer.

[0060] In box 402a, the first image 102 of the previous layer is represented as PL. i Where the subscript "i" is an integer specifying a particular layer. In box 402b, each first image 102 is also composed of an optical mode OM. jThe term "j" is used to characterize the light used to capture the corresponding first image 102, where the subscript "j" indicates a specific optical mode from a set of optical modes used to capture the first image 102. An optical mode refers to a set of parameters characterizing the light used to capture the first image 102, including but not limited to wavelength, intensity, polarization, focal length, angle of incidence, etc. Various types of deep learning models (e.g., CNNs, visual transformers, etc.) are used in their respective embodiments to convert image noise from the various first images 102 into approximate image noise in the second image 104 of the inspection layer.

[0061] Therefore, according to various embodiments, the deep learning model is tailored to each optical mode OM. j Identify various previous layer PLs i The noise features in the first image are identified, and similarly, the noise features in the second image 104 of the inspection layer are identified. A first deep learning model (e.g., see box 404) is then trained to be used as an image filter that transforms the noise features in each image of the first image into noise features in the second image 104 of the inspection layer.

[0062] refer to Figure 4C The first deep learning model shown in box 410 receives two types of information as input. As shown in box 406, the first information includes each corresponding previous layer PL i The design layout image (also known as PL layout mask), and as shown in box 408, the second information includes the above reference. Figure 4A and Figure 4B The aforementioned previous layer (PL) i OM j The first image 102. As shown in box 412, the first deep learning model is for each corresponding previous layer PL. i Individual noise-reduced images are generated, each of which approximates a portion of the noise features of the second image 104 in the inspection layer. In this regard, the deep learning model of box 410 uses optical pattern information (e.g., see...). Figure 4B (Block 402b) to transform each previous layer PL i The noise features are approximated in the second image 104 of the inspection layer. Then, as shown in box 416, corresponding image differences are generated by subtracting each noise-reduced image from the images of the inspection layer, as shown in box 420. The difference images are then used to calculate the cost function 414, as follows.

[0063] The first deep learning model is trained by adjusting the weights in the neural network to minimize the cost function 414. This is based on using multiple optical modes OM. j (As shown in box 416) the captured second images 104 and the noise-reduced image F*PL i(where “F” is applied to PL through the first neural network) i The cost function 414 is calculated by analyzing the differences between the various images 104 (transformed). Figure 4C As shown, there is a residual noise term N. ij The matrix, and by minimizing the residual noise term N ij To train the first neural network. According to various embodiments, gradient descent is used to adjust the weights in the neural network to minimize the residual noise term N. ij For example, in some embodiments, the residual noise term N, which is a function of the weights in the neural network, is... ij The analytical expression is differentiated with respect to the weights to calculate the residual noise term N. ij The gradient is then calculated and applied to various gradient descent algorithms to minimize the residual noise term N. ij This optimizes the neural network to generate noise-reduced images F*PL. i The noise-reduced image is very close to the corresponding noise features in the second image 104 of the inspection layer.

[0064] In their respective embodiments, various functions are used to calculate the residual noise term N. ij For example, in some embodiments, the second image 104 is calculated (i.e., written as OM). j ) and noise-reduced image F*PL i The pixel-level differences between the corresponding images are then calculated. These differences are then summed by squares. The square root of the sum is then calculated to form the residual noise term N. ij In other embodiments, various other functions can be used to generate the residual noise term N. ij As shown in box 418, in the corresponding second image 104 (i.e., written as OM) j Before performing subtraction, the layout information of each previous layer (e.g., the previous layer (PL) mask) is used to align the multiple noise-reducing images PL. i .

[0065] Figure 5C This is a three-dimensional perspective view of an inspection tool 500c according to various embodiments, which includes multiple custom chips (520a, 520b, 520c, 520d) representing respective previous layers (PL1, PL2, PL3, PL4). The inspection tool 500c includes a stage 516 configured to accommodate a wafer 518 having a top layer serving as an inspection layer 200c. The custom chips (520a, 520b, 520c, 520d) are wafer samples, each of which is formed and tested / verified to have a structure equivalent to the corresponding previous layer PLi of wafer 518. Therefore, by scanning the custom chips (520a, 520b, 520c, 520d), [the inspection tool 500c is inspected]. Figure 5C The inspection tool 500c generates the previous layer (PL) corresponding to wafer 518. i OM j The first image 102. In this respect, scanning of the previous layer PL during the fabrication process of wafer 518 is eliminated. i This simplifies and streamlines the inspection process to meet the needs of [the relevant authorities]. Figure 5C In the embodiment verification tool 500c, there are four custom chips (520a, 520b, 520c, 520d), corresponding to the four previous layers (PL1, PL2, PL3, PL4) of wafer 518. Figure 5C The use of the four custom chips (520a, 520b, 520c, 520d) is provided as an example only, and more or fewer custom chips are provided in other embodiments.

[0066] Figure 5D It is based on various embodiments to generate the previous layer (PL) i OM j A block diagram showing the first image 102 and the detailed information of the method 500d for training deep learning models (400b, 500a). Figure 5D The method for 500d is similar to the one mentioned above. Figures 4A to 5B The process described. However, with Figures 4A to 5B The method differs; instead of capturing images of previous layers (PL) during the fabrication process of forming the 518 wafer, images of custom chips (520a, 520b, 520c, 520d) are captured. i OM j The image is used to generate the previous layer (PL). i OM j The first image 102. In this respect, as shown in box 522, for each optical mode OM j Method 500d includes capturing one or more images of wafer 518, as shown in box 524. Similarly, for each optical mode OM... j Method 500d includes capturing one or more images of multiple custom chips (520a, 520b, 520c, 520d), as shown in boxes 522, 526, and 528. From the images collected in box 528, defect-free images of the custom chips (520a, 520b, 520c, 520d) are extracted, as shown in box 530. The image data collected in boxes 522 through 530 is then used to apply the above-mentioned reference. Figure 4B and Figure 5A The method described is shown in box 532 for training deep learning models.

[0067] According to various embodiments, multiple custom chips (520a, 520b, 520c, 520d) include various known defects that can be used for pattern selection and recipe optimization. As described above, using multiple custom chips (520a, 520b, 520c, 520d) avoids the need to perform image capture processing during the fabrication of previous layers of wafer 518. According to various embodiments, the multiple custom chips (520a, 520b, 520c, 520d) are user-selectable and portable. For example, according to various embodiments, different custom chips correspond to different corresponding types of wafers 518. Therefore, the inspection tool 500c can be reconfigured as needed to perform inspection processes on different types of wafers. In various embodiments, the inspection tool 500c also includes one or more processor devices (e.g., see...). Figure 9 The inspection tool 500c is configured to perform the aforementioned processes for training and applying deep learning models. Therefore, according to various embodiments, the inspection tool 500c is configured for real-time model training.

[0068] According to various embodiments, a plurality of custom chips (520a, 520b, 520c, 520d) are selected from a reference batch of wafers used for recipe setting. In this regard, the inspection tool 500c includes a calibration chip slot (not shown) configured to hold the plurality of custom chips (520a, 520b, 520c, 520d) during scanning. According to various embodiments, each of the plurality of custom chips (520a, 520b, 520c, 520d) is diced from a qualified wafer in a candidate prior layer and includes three or more chips (534a, 534b, 534c) to facilitate chip-to-chip (D2D) comparisons to distinguish defect signals and system noise in subsequent deep learning model training. Figure 5D Method 500d includes using each candidate OM i Scan wafer 518 (box 522) to collect wafer images (box 524), scan each previous layer chip (box 526) to generate images corresponding to the previous layer (PL). i OM j The first image 102 (box 528).

[0069] As shown in box 530, method 500d further includes extracting a defect-free image by performing a D2D comparison of similar images captured from different dies (534a, 534b, 534c), thereby decoupling the defect signal from system PL noise. Finally, as shown in box 532, method 500d includes training a deep learning model based on the wafer image (box 524) and the defect-free PL image (box 530). The method for training the deep learning model (box 532) is similar to the one described above. Figure 4B , Figure 4C and Figure 5AThe methods described (404b, 404, 500a). For example, in some embodiments, cost function 414 (e.g., see...) Figure 4C (Refer to the above) Figure 4C The same as described above.

[0070] According to some embodiments, one or more custom chips (520a, 520b, 520c, 520d) are diced from a qualified wafer having a structure corresponding to inspection layer 200c. Images captured by such chips (corresponding to inspection layer 200c) are used to select the optimal optical mode OM. i (Box 522) provides a reference for the noise floor under optimal conditions. According to some embodiments, corresponding to the previous layer (PL) i OM j The chip is configured to be defect-free, and in other embodiments, the previous layer (PL) i OM j The chip is configured to have specific known defects for training deep learning models. For example, in some embodiments, a defect-free custom chip is suitable for characterizing system noise. On the other hand, in other embodiments, a custom chip with known or programmed defects can be used for reference testing of defective signals or for determining a signal-to-noise ratio metric when selecting the optimal optical mode.

[0071] The embodiments described can be used as inspection tools for various processes. For example, in some embodiments, the disclosed embodiments can be used as inspection tools for noise reduction and mode selection applied to electron beam inspection tools. In various embodiments, the placement of custom chips in the inspection tool has various different configurations (e.g., in isolated locations or in an array). In some embodiments, to support a large number of custom chips (e.g., for previous layers of different types of wafers 518), the custom chips are stored in a library in the tool, wherein a mechanism (not shown) is provided for exchanging custom chips between slots and the library. In some embodiments, the custom chips (520a, 520b, 520c, 520d) can also be used for various aspects of tool qualification (e.g., initial tool acceptance, tool matching, tool degradation monitoring, tool calibration, etc.).

[0072] Figure 6This is a flowchart of a method 600 for removing image noise (204a', 204b) from an image 104 of an inspection layer 200c in a semiconductor device (300) according to various embodiments. In operation 602, method 600 generates a first image 102 of a previous layer (200a, 200b) in the semiconductor structure 300. The process continues to operation 604. In operation 604, method 600 generates a second image 104 of the inspection layer 200c. The process continues to operation 606. In operation 606, method 600 transforms the first image 102 using deep learning models (410, 502) to generate a noise-reduced image (412, 508). The process continues to operation 608. In operation 608, method 600 removes image noise (204a', 204b) from the second image 104 based on the noise-reduced image (412, 508).

[0073] According to various embodiments, method 600 further includes aligning the noise-reduced image (412, 508) and the second image 104 to a design layout (406, 418, 506), and performing pixel-level subtraction 512 of the noise-reduced image from the second image 104 to remove image noise (204a', 204b) from the second image 104. According to various embodiments, the deep learning model (410, 502) includes a convolutional neural network or a visual transformer model. According to various embodiments, generating the first image 102 of the previous layer (200a, 200b) in the semiconductor structure 300 further includes capturing an image of a custom chip (520a, 520b, 520c, 520d) having a structure similar to the previous layer (200a, 200b).

[0074] According to various embodiments, method 600 further includes determining a first noise feature 204a in the first image 102, determining a second noise feature (204a', 204b) in the second image 104, and training a deep learning model (410, 502) to generate a noise-reduced image (412, 508) from the first image 102 such that the noise-reduced image (412, 508) approximates the second noise feature (204a', 204b) of the second image 104.

[0075] According to various embodiments, the deep learning models (410, 502) use a self-attention algorithm to determine the correlation between a first noise feature 204a and a second noise feature (204a', 204b), as well as between the first noise feature 202a and the second noise feature (204a', 204b). According to various embodiments, the deep learning models (410, 502) include a neural network defined by multiple nodes and multiple weights representing connections between node pairs within the multiple nodes, and training the deep learning models (410, 502) further includes adjusting multiple weights to minimize a cost function (414, 514) (see, for example, see...). Figure 4C and Figure 5A To minimize the difference between the noise-removed images (412, 508) of the second image 104 and the second noise features (204a', 204b).

[0076] According to various embodiments, method 600 further includes forming a pixel-level difference 512 between the noise-reduced image (412, 508) and the second image 104, and calculating a cost function 414 by forming the sum of squares of the differences (e.g., see...). Figure 4C According to various embodiments, method 600 further includes determining the relationship between changes in a plurality of weights and corresponding changes in cost function 414, and determining a plurality of weight values ​​that minimize cost function 414 by performing a gradient descent algorithm, thereby minimizing cost function. According to various embodiments, generating noise-reduced images (412, 508) further includes training deep learning models (410, 502) using processing and layout information (408, 418, 506) characterizing the first image 102 and the second image 104, such that the deep learning models (410, 502) are configured to determine noise (204a', 204b) introduced into the second image 104 based on features in previous layers (200a, 200b).

[0077] According to various embodiments, method 600 further includes training a deep learning model (410, 502) to determine the correlation between the spatial layout (408, 418, 506) of the previous layers (200a, 200b) and the corresponding second noise features (204a', 204b) of the second image 104. According to various embodiments, method 600 further includes training the deep learning model (410, 502) to determine the correlation between the material composition (202a, 202b) of the previous layers (200a, 200b) and the corresponding second noise features (204a', 204b) of the second image 104.

[0078] Figure 7This is a flowchart of an operation of a method 700 for removing image noise (204a', 204b) from an image 104 of an inspection layer 200c in a semiconductor device (300) according to various embodiments. Method 700 includes training a deep learning model (410, 502) in operations 702, 704, and 706, and reducing image noise in operation 708, as shown below. In operation 702, method 700 collects first image 102 data from each of a plurality of previous layers (200a, 200b) and second image 104 data from the inspection layer 200c. The process continues to operation 704. In operation 704, method 700 identifies a first noise feature 204a in the first image 102 data and a second noise feature (204a', 204b) in the second image 104 data. The process continues to operation 706. In operation 706, method 700 adjusts the parameters of the deep learning model (410, 502) so that the deep learning model transforms the first noise feature 204a to generate a noise-cancelled image (412, 508) that approximates the second noise features (204a', 204b). The process continues to operation 708. In operation 708, method 700 reduces image noise (204a', 204b) in the second image 104 data by performing pixel-level subtraction 512 on the noise-cancelled image (412, 508) in the second image 104 data to generate a corrected image for the inspection layer 200c.

[0079] According to various embodiments, training the deep learning model (410, 502) further includes generating a first weighted sum 412 of the first image 102 data, such that a weight (W1…Wn) associated with each of the previous layers (200a, 200b) is determined based on layout and component (408, 418, 506) information associated with each of the previous layers (200a, 200b); using the first weighted sum 412 of the first image 102 data as input to the deep learning model (410, 502); and adjusting the weights (W1…Wn) to minimize the difference between the noise-cancelled images (412, 508) and the second noise features (204a', 204b) in the second image 104 data.

[0080] According to various embodiments, method 700 further includes collecting at least two separate images 402a of each of the previous layers (200a, 200b) by capturing images of a custom chip (520a, 520b, 520c, 520d) having a structure similar to each of the plurality of previous layers (200a, 200b); capturing at least two separate images using at least two different optical modes; and generating a first weighted sum such that the first image 102 data is weighted according to at least two different optical modes 402b. According to various embodiments, method 700 further includes aligning the first image 102 data, the second image 104 data, and the noise-reduced images (412, 508) to a design layout (406, 418, 506).

[0081] According to various embodiments, training the deep learning models (410, 502) further includes: training the first deep learning model 410 using first image 102 data of each corresponding previous layer (200a, 200b) and the design layout (406, 418, 506) of each corresponding previous layer (200a, 200b) as first input data to generate individual noise-reduced images 412 for each of the previous layers (200a, 200b); and training the second deep learning model 502 to generate a combined noise-reduced image 508, wherein the second deep learning model 502 uses the individual noise-reduced images 412 as second input data. According to various embodiments, during the training of the second deep learning model 502, a second weighted sum of the individual noise-reduced images 412 is adjusted to take into account variations in the minimum feature size CD or height difference between the plurality of previous layers (200a, 200b) and the inspection layer 200c.

[0082] Figure 8This is an operational flowchart of a method 800 for defect detection 514 in a semiconductor structure (200a, 200b, 200c) according to various embodiments. In operation 802, method 800 collects first image 102 data for each of a plurality of previous layers (200a, 200b) of the semiconductor structure (200a, 200b, 200c). The process continues to operation 804. In operation 804, method 800 collects second image 104 data for the inspection layer 200c of the semiconductor structure (200a, 200b, 200c). The process continues to operation 806. In operation 806, method 800 generates noise-reduced images (412, 508) using a deep learning model (410, 502) with the design layout (406, 418, 506) and the first image 102 data as input, and provides the noise-reduced images (412, 508) as output. The process continues to operation 808. In operation 808, method 800 removes image noise (204a', 204b) from the second image 104 data by subtracting 512 noise-reduced images (412, 508) from the second image 104 data to generate a corrected image of inspection layer 200c. The flow continues to operation 810. In operation 810, method 800 performs a defect detection algorithm (e.g., C2C or D2D) on the corrected image of inspection layer 200c to detect at least one defect in inspection layer 200c.

[0083] According to various embodiments, generating noise-reduced images (412, 508) further includes the following steps: generating individual noise-reduced images 408 for each of the preceding layers (200a, 200b) by applying a first deep learning model 410, the first deep learning model 410 using first image 102 data of each preceding layer (200a, 200b) and the corresponding design layout (406, 418, 506) of each preceding layer (200a, 200b) as first input data of the first deep learning model 410; and generating combined noise-reduced images 508 by applying a second deep learning model 502, the second deep learning model 502 using individual noise-reduced images 412 as second input data of the second deep learning model 502.

[0084] According to various embodiments, generating the combined noise-cancelled image 508 further includes collecting at least two separate images (402a, 412, 412) of each of the previous layers (200a, 200b) by capturing images of a custom chip (520a, 520b, 520c, 520d) having a structure similar to each of the plurality of previous layers (200a, 200b); determining the minimum feature size CD of each of the plurality of previous layers (200a, 200b) using at least two different optical modes 402b; and generating the combined noise-cancelled image 508 by providing at least two separate images (402a, 412, 412) and the minimum feature size CD. In these embodiments, the deep learning model (410, 502) is further configured to be based on an optimized weighted sum of individual noise-cancelled images 412 (e.g., see...). Figure 5B Generate a combined noise-cancelled image 508 that takes into account the minimum feature size or height variation between multiple previous layers (200a, 200b) and the inspection layer 200c, and determine an optimized optical mode 402b for each of the multiple previous layers (200a, 200b).

[0085] Details regarding the various neural networks that can be used in other embodiments are shown below. Convolutional Neural Networks (CNNs) are well-suited for image processing tasks, such as defect detection in semiconductor wafers and devices. These models are designed to automatically extract spatial hierarchies of features from images. In the context of semiconductor manufacturing, CNNs can be used to analyze optical or differential images and detect patterns or anomalies corresponding to defects or noise. The convolutional layers in these networks allow the model to learn local features (e.g., edges, textures) from the input image, which are then used in some embodiments for classification or regression tasks, such as defect detection or quality prediction.

[0086] Other embodiments are based on visual transformers, a class of deep learning models specifically designed for analyzing image data. Unlike CNNs, which rely on convolutional operations to capture local patterns, visual transformers utilize a transformer-based architecture that has been successful in natural language processing tasks and is applied to image analysis. Visual transformers process images into sequences of blocks, enabling the model to capture global correlations and long-range relationships between image regions, which is particularly valuable for complex pattern recognition tasks, such as defect detection in semiconductor device manufacturing.

[0087] In the visual transformer, the image is first divided into non-overlapping blocks. These blocks are then flattened into vectors, and positional embeddings are added to each block to preserve the spatial information of its original location in the image. A series of block embeddings are then fed into the transformer encoder, which processes the blocks in parallel, allowing the model to capture interactions between distant regions of the image. The transformer encoder consists of multiple layers, each containing a self-attention mechanism and a feedforward network. The self-attention mechanism enables the model to weigh the importance of different blocks relative to each other, allowing it to capture complex global patterns in the image. These self-attention layers allow the model to focus on the most relevant parts of the image, regardless of their spatial proximity.

[0088] Self-attention mechanisms work by computing attention scores between all pairs of blocks in an image. These attention scores are used to create a weighted representation of each block, allowing the model to learn which regions of the image are important for understanding the overall structure and context. This differs from CNNs, which rely on local receptive domains and may not effectively capture long-range dependencies. By processing images as sequences of blocks, visual transformers can learn global relationships that are useful for tasks such as identifying defects in semiconductor manufacturing or monitoring complex patterns.

[0089] After the converter encoder processes the block embedding sequence, the output typically passes through either a classification head or a regression head, depending on the task. The classification head is responsible for generating predictions, such as the presence or absence of defects, while the regression head can be used for tasks requiring continuous output, such as predicting defect severity. The converter model's output is then used for downstream tasks, such as defect detection, image segmentation, or process optimization in semiconductor manufacturing.

[0090] One advantage of visual transformers compared to traditional CNNs is their ability to capture long-range dependencies and global context from image data. By treating images as sequences of blocks, visual transformers can learn complex relationships that may span a large portion of the image, which is extremely useful for applications where the global structure or context of the image is crucial for accurate analysis. This capability makes visual transformers suitable for tasks such as identifying defects appearing over large areas of a wafer or detecting subtle anomalies that are not limited to local regions.

[0091] Furthermore, visual transformers offer strong scalability and flexibility. The performance of these models improves with increasing available data and computational resources, making them effective in scenarios involving large, high-dimensional image datasets. Visual transformers can also adapt to different image sizes and resolutions by adjusting the size of the blocks and the number of transformer layers.

[0092] In some embodiments related to semiconductor device manufacturing, a vision transformer is applied to analyze optical images from a wafer inspection system, enabling the model to automatically detect and locate defects or process deviations. For example, the vision transformer can be trained to recognize specific defect patterns in wafer images, such as surface irregularities, misaligned features, or contamination. The model's ability to capture local and global patterns in an image allows it to identify complex defects that span multiple regions of the wafer or exhibit subtle variations in appearance. Once trained, the vision transformer analyzes new wafer images to provide automated and reliable defect detection with high accuracy.

[0093] Furthermore, vision transducers are used to monitor semiconductor manufacturing processes in real time, detect deviations from expected patterns, and flag potential problems before they lead to significant defects. By capturing fine-grained and high-level features of images, vision transducers provide a powerful approach to quality control and process optimization.

[0094] In this way, visual transformers offer a novel and effective approach to analyzing image data, particularly in complex tasks such as defect detection and process monitoring in semiconductor manufacturing. Their ability to capture long-term dependencies in images and learn global patterns enables them to excel in applications where traditional CNNs might be less efficient. Through their scalability, flexibility, and global pattern recognition capabilities, visual transformers provide a powerful tool for improving the accuracy and efficiency of semiconductor device manufacturing processes.

[0095] The disclosed embodiments are advantageous because they provide methods (600, 700, 800) for inspecting an inspection layer 200c in a semiconductor structure (e.g., semiconductor device structure 300) based on image information 102 collected from one or more previously formed previous layers (200a, 200b). In this regard, the disclosed systems 1100 and methods (600, 700, 800) transform the image 102 from one or more previous layers (200a, 200b) along with the layout (406, 418, 506) and process critical dimensions (CD) to generate one or more noise-reduced images (412, 412, 421) that are most effective in suppressing noise (204a', 204b) in the inspection layer image 104. The generation of these noise-reduced images (412, 412, 421) uses the deep learning (410, 502) functionality of a visual transformer model that utilizes layout information (406, 418, 506) and is conditioned on the CD data of the wafer being inspected.

[0096] According to various embodiments, a method for optical inspection of a semiconductor structure is disclosed. The method includes: generating a first image of a previous layer in the semiconductor structure; generating a second image of the inspected layer in the semiconductor structure; transforming the first image using a deep learning model to generate a noise-reduced image; and removing image noise from the second image based on the noise-reduced image. According to various embodiments, the method further includes: aligning the noise-reduced image and the second image with a design layout; and performing pixel-level subtraction on the noise-reduced image in the second image to remove image noise from the second image. According to various embodiments, the deep learning model includes a convolutional neural network or a visual transformer model. According to various embodiments, generating the first image of the previous layer in the semiconductor structure also includes capturing an image of a custom chip having a structure similar to the previous layer.

[0097] According to various embodiments, the method further includes: determining a first noise feature in a first image; determining a second noise feature in a second image; and training a deep learning model to generate a noise-reduced image from the first image such that the noise-reduced image approximates the second noise feature of the second image. According to various embodiments, the deep learning model uses a self-attention algorithm to determine the first noise feature, the second noise feature, and the correlation between the first noise feature and the second noise feature.

[0098] According to various embodiments, the deep learning model includes a neural network defined by a plurality of nodes and a plurality of weights representing connections between node pairs within the plurality of nodes; and training the deep learning model further includes: adjusting the plurality of weights to minimize a cost function, the cost function minimizing a difference between a noise-cancelled image and a second image. According to various embodiments, the method further includes: forming a pixel-level difference between the noise-cancelled image and the second image; and calculating the cost function by forming a sum of squares of the difference. According to various embodiments, the method further includes: determining a relationship between changes in the plurality of weights and corresponding changes in the cost function; and minimizing the cost function by performing a gradient descent algorithm to determine the values ​​of the plurality of weights that minimize the cost function.

[0099] According to various embodiments, generating a noise-reduced image further includes: training a deep learning model using process and layout information characterizing the first and second images, such that the deep learning model is configured to determine noise introduced into the second image based on features in a previous layer. According to various embodiments, the method further includes: training the deep learning model to determine the correlation between the spatial layout of the previous layer and corresponding second noise features of the second image. According to various embodiments, the method further includes: training the deep learning model to determine the correlation between the material composition of the previous layer and corresponding second noise features of the second image.

[0100] According to various embodiments, a method for optical inspection of a semiconductor structure is provided. The method includes: training a deep learning model by performing operations including: collecting first image data of each of a plurality of previous layers of the semiconductor structure and second image data of an inspection layer of the semiconductor structure; identifying a first noise feature in the first image data and identifying a second noise feature in the second image data; and adjusting parameters of the deep learning model such that the deep learning model transforms the first noise feature to generate a noise-cancelled image approximating the second noise feature. The method further includes: reducing image noise in the second image by performing pixel-level subtraction on the noise-cancelled image in the second image data to generate a corrected image of the inspection layer.

[0101] According to various embodiments, training the deep learning model further includes: generating a first weighted sum of first image data, such that weights associated with each of the plurality of previous layers are determined based on layout and composition information associated with corresponding previous layers; using the first weighted sum of the first image data as input to the deep learning model; and adjusting the weights to minimize the difference between a noise-reduced image and a second noise feature in the second image data. According to various embodiments, the method further includes: collecting at least two separate images of each of the plurality of previous layers by capturing images of a custom chip having a structure similar to each of the plurality of previous layers; capturing at least two separate images using at least two different optical modes; and generating a first weighted sum, such that the first image data is weighted according to at least two different optical modes. According to various embodiments, the method further includes: aligning the first image data, the second image data, and the noise-reduced image with a design layout.

[0102] According to various embodiments, training the deep learning model further includes: training the first deep learning model using first image data for each corresponding previous layer and the design layout of each corresponding previous layer as first input data to generate individual noise-reduced images for corresponding previous layers among a plurality of previous layers; and training a second deep learning model to generate combined noise-reduced images, wherein the second deep learning model uses the individual noise-reduced images as second input data to the second deep learning model. According to various embodiments, during the training of the second deep learning model, a second weighted sum of the individual noise-reduced images is adjusted to account for variations in the minimum feature size or height difference between the plurality of previous layers and the inspection layer.

[0103] According to various embodiments, a defect detection method for a semiconductor structure is disclosed. The method includes: collecting first image data of each of a plurality of previous layers of the semiconductor structure; collecting second image data of an inspection layer of the semiconductor structure; generating a noise-reduced image using a deep learning model, the deep learning model taking the design layout of the semiconductor structure and the first image data as input and providing the noise-reduced image as output; removing image noise from the second image data by subtracting the noise-reduced image from the second image data to generate a corrected image of the inspection layer; and performing a defect detection algorithm on the corrected image of the inspection layer to detect at least one defect in the inspection layer.

[0104] According to various embodiments, generating a noise-reduced image further includes: generating individual noise-reduced images for corresponding previous layers among a plurality of previous layers by applying a first deep learning model, the first deep learning model using first image data of each corresponding previous layer and a corresponding design layout of each corresponding previous layer as first input data of the first deep learning model; and generating a combined noise-reduced image by applying a second deep learning model, the second deep learning model using individual noise-reduced images as second input data of the second deep learning model.

[0105] According to various embodiments, generating the combined noise-cancelled image further includes: collecting at least two separate images of each of the plurality of previous layers by capturing images of a custom chip having a structure similar to each of the plurality of previous layers using at least two different optical modes; determining the minimum feature size of each of the plurality of previous layers; and generating the combined noise-cancelled image by providing the at least two separate images and the minimum feature size to a deep learning model, the deep learning model being further configured to generate the combined noise-cancelled image based on an optimized weighted sum of the separate noise-cancelled images, the optimized weighted sum taking into account variations in the minimum feature size or height between the plurality of previous layers and the inspection layer, and determining an optimized optical mode for each of the plurality of previous layers.

[0106] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to them within this disclosure without departing from its spirit and scope.

Claims

1. An optical inspection method for semiconductor structures, comprising: Generate a first image of the previous layer in the semiconductor structure; Generate a second image of the inspection layer in the semiconductor structure; The first image is transformed using a deep learning model to generate a noise-reduced image; as well as The noise is removed from the second image based on the noise reduction image.

2. The optical inspection method according to claim 1, further comprising: Align the noise-reduced image and the second image with the design layout; as well as Pixel-level subtraction is performed on the noise-reduced image in the second image to remove the image noise from the second image.

3. The optical inspection method of claim 1, wherein, The deep learning model includes convolutional neural networks or visual transformer models.

4. The optical inspection method according to claim 1, wherein, The first image of the previous layer generated in the semiconductor structure also includes capturing an image of a custom chip having a structure similar to the previous layer.

5. The optical inspection method according to claim 1, further comprising: Determine the first noise feature in the first image; Determine the second noise feature in the second image; as well as The deep learning model is trained to generate the noise-reduced image from the first image, such that the noise-reduced image approximates the second noise feature of the second image.

6. The optical inspection method according to claim 5, wherein, The deep learning model uses a self-attention algorithm to determine the first noise feature and the second noise feature, as well as the correlation between the first noise feature and the second noise feature.

7. The optical inspection method according to claim 5, wherein: The deep learning model includes a neural network, which is defined by multiple nodes and multiple weights representing the connections between node pairs within the multiple nodes; as well as The training of the deep learning model also includes: The weights are adjusted to minimize a cost function that minimizes the difference between the noise-removed image and the second noise feature of the second image.

8. The optical inspection method according to claim 7, further comprising: The pixel-level difference between the noise-reduced image and the second image is formed; as well as The cost function is calculated by forming the sum of squares of the differences.

9. An optical inspection method for semiconductor structures, comprising: Training a deep learning model by performing operations, said operations including: Collect first image data of each of the plurality of previous layers of the semiconductor structure and second image data of the inspection layer of the semiconductor structure; Identify a first noise feature in the first image data, and identify a second noise feature in the second image data; and Adjusting the parameters of the deep learning model so that the deep learning model transforms the first noise feature to generate a noise-cancelled image that approximates the second noise feature; and Image noise in the second image is reduced by performing pixel-level subtraction on the noise-reduced image in the second image data to generate the corrected image of the inspection layer.

10. A method for detecting defects in a semiconductor structure, comprising: Collect first image data for each of the plurality of previous layers of the semiconductor structure; Collect second image data of the inspection layer of the semiconductor structure; A noise-reduced image is generated by a deep learning model, which uses the design layout of the semiconductor structure and the first image data as input and provides the noise-reduced image as output. Image noise in the second image data is removed by subtracting the noise-reduced image from the second image data to generate the corrected image of the inspection layer; as well as A defect detection algorithm is performed on the corrected image of the inspection layer to detect at least one defect in the inspection layer.

Images