Implementation method of semiconductor complementary patterning process

Abstract

The invention discloses an implementation method of a semiconductor complementary patterning process. The implementation method comprises the following steps: providing a substrate; a patterned first mask layer is formed on the substrate; filling the groove of the patterned first mask layer with a filling material; and after the patterned first mask layer is removed, a patterned second mask layer complementary with the patterned first mask layer is formed.

Description

Technical Field

[0001] This invention relates to semiconductor processes, and more particularly to a method for implementing a semiconductor complementary patterning process. Technical Background

[0002] In the semiconductor industry, lithography is a key process in chip manufacturing. The most critical equipment in the process is the lithography machine, whose resolution determines the minimum linewidth (CD) of semiconductor circuits. With the continuous evolution of advanced semiconductor process nodes, the production efficiency of lithography machines is considered an important factor in the product manufacturing process. Therefore, improving the production capacity of lithography machines has become one of the urgent problems to be solved in the semiconductor industry.

[0003] The photoelectric conversion region of a CMOS image sensor (CIS) is the core layer of the CIS. Ion implantation of the N-type photoelectric conversion region requires one layer of photoresist as a barrier, while ion implantation of the P-type photoelectric conversion region requires another layer of photoresist as a barrier. Because high-energy ion implantation is required, the photoresist thickness needs to be very thick, while the linewidth needs to be small, resulting in a high overall aspect ratio, making fabrication very difficult.

[0004] For P-type ion implantation, because the photoresist consists of tiny pillars, it is prone to collapse as the pixel size and linewidth shrink with further process advancements. Furthermore, because the exposure area is smaller than that of N-type, the minimum size of the photoresist crystal (CD) is far more difficult to produce. Currently, the industry mainly addresses this by using double patterning to split the P-type into two layers (doubling the pitch), which can solve the collapse problem. However, doubling the pitch does not significantly improve the minimum size of the CD. Summary of the Invention

[0005] To address the problems existing in the prior art, the present invention provides a method for implementing a semiconductor complementary patterning process, characterized by comprising: providing a substrate; forming a patterned first mask layer on the substrate; filling trenches in the patterned first mask layer with a filling material; and removing the patterned first mask layer to form a patterned second mask layer that is complementary to the patterned first mask layer.

[0006] In some embodiments, forming a patterned first mask layer on the substrate includes: forming a first mask layer on the substrate; forming the patterned first mask layer on the substrate by exposure and development; the first mask layer material is photoresist; and the filler material is a silicon-containing material.

[0007] In some embodiments, the silicon-containing material is a silicon-containing hard mask layer (Si-HM) or a silicon-containing antireflective layer (Si-ARC).

[0008] In some embodiments, the method further includes: performing ion implantation according to the patterned first mask layer to form a first ion-doped region in the substrate; and performing ion implantation according to the patterned second mask layer to form a second ion-doped region in the substrate.

[0009] In some embodiments, the first ion-doped region is a photosensitive unit of an image sensor; the second ion-doped region is an isolation structure between adjacent photosensitive units.

[0010] In some embodiments, the first ion-doped region is N-type and the second ion-doped region is P-type; or, the first ion-doped region is P-type and the second ion-doped region is N-type.

[0011] In some embodiments, the method further includes: performing an etching process or an ion implantation process based on the patterned first mask layer; and / or performing an etching process or an ion implantation process based on the patterned second mask layer.

[0012] In some embodiments, the patterned first mask layer material is photoresist; the etching selectivity ratio of the filler material to the photoresist is greater than 5:1.

[0013] In some embodiments, the linewidth between adjacent photosensitive units is no more than 300 nm.

[0014] In some embodiments, filling the trenches of the patterned first mask layer with a filler material includes: depositing a layer of the filler material on the substrate to fill the trenches of the patterned first mask; etching the filler material layer and stopping on the patterned first mask layer.

[0015] Compared with traditional solutions, the technical solution of this invention can reduce one P-type lithography layer and multiple P-type ion implantations, while increasing the collapse window and reducing the process linewidth. Only the N-type lithography layer needs to be studied, which has multiple process advantages. Attached Figure Description

[0016] Figures 1 to 8 This is a flowchart of the semiconductor complementary patterning process according to an embodiment of the present invention. Detailed Implementation

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are merely some examples or embodiments of the present invention. For those skilled in the art, these drawings can be applied to other similar scenarios without creative effort. Unless obvious from the context or otherwise specified, the same reference numerals in the drawings represent the same structures or operations.

[0018] The present invention provides a method for implementing a semiconductor complementary patterning process, characterized by comprising: providing a substrate; forming a patterned first mask layer on the substrate; filling trenches in the patterned first mask layer with a filling material; and removing the patterned first mask layer to form a patterned second mask layer complementary to the patterned first mask layer.

[0019] The semiconductor complementary patterning process of the present invention can be used in products such as image sensors and dynamic memory.

[0020] The semiconductor complementary patterning process of the present invention can be used in CMOS processes, such as forming source / drain ion implantations for PMOS and NMOS transistors.

[0021] Figures 1 to 8 This is a flowchart of the semiconductor complementary patterning process according to an embodiment of the present invention.

[0022] This invention uses an image sensor as an example for illustration.

[0023] In other embodiments, the semiconductor complementary patterning process of the present invention can also be applied to other semiconductor products.

[0024] refer to Figure 1 A substrate 10 is provided. The substrate 10 may be a semiconductor material, such as silicon, germanium, silicon-germanium, germanium-silicon-on-insulator (SGOI), or a combination thereof. The substrate 10 may include a substrate with multiple epitaxial layers.

[0025] A first mask layer 11 is formed on the substrate 10. Optionally, the first mask layer 11 may include photoresist. Optionally, the mask layer 11 may include a hard mask layer, such as silicon nitride, silicon oxide, silicon oxynitride, etc. A silicon oxide layer 211 and a silicon nitride layer 212 are formed.

[0026] refer to Figure 2 The first mask layer 11 is patterned to form trenches 110. Taking the first mask layer 11 as a photoresist as an example, the photoresist can be developed and exposed to form trenches 110.

[0027] refer to Figure 3Based on the patterned first mask layer 11, ion implantation is performed to form a first ion-doped region within the substrate 10, forming the carrier collection region of the photoelectric conversion region (i.e., the photosensitive unit of the image sensor). The carrier collection region of the photoelectric conversion region can be N-type. The ion implanted element can be phosphorus or arsenic. The linewidth between adjacent photosensitive units is no more than 300 nm. In other embodiments, an etching process can be performed based on the patterned first mask layer 11.

[0028] refer to Figure 4 The trenches 110 of the patterned first mask layer 11 are filled with a filling material 12. The filling material 12 is a silicon-containing material. The silicon-containing material can be a silicon-containing hard mask layer (Si-HM) or a silicon-containing anti-reflective layer (Si-ARC).

[0029] refer to Figure 5 The filling material 12 is etched and stopped on the patterned first mask layer 11.

[0030] refer to Figure 6 After removing the patterned first mask layer 11, a patterned second mask layer 12 (i.e. the remaining filling material 12) is formed that is complementary to the patterned first mask layer 11.

[0031] refer to Figure 7 Based on the patterned second mask layer 12, ion implantation is performed to form a second ion-doped region within the substrate 10, forming an isolation region of the photoelectric conversion region (i.e., an isolation structure between adjacent photosensitive units of the image sensor). The isolation region of the photoelectric conversion region can be P-type. The element implanted can be boron. In other embodiments, an etching process can be performed based on the patterned second mask layer 12.

[0032] It should be noted that the first ion-doped region can be P-type; the second ion-doped region can be N-type.

[0033] refer to Figure 8 Remove the second graphic mask layer 12.

[0034] In some embodiments, the etching selectivity ratio of the filler material 12 to the photoresist is greater than 5:1. The ratio of the etching rate of the filler material 12 to the etching rate of the photoresist is greater than 5:1. The purpose of this high selectivity is to ensure that when using different gases for etching, the first step of etching excess surface filler material does not consume excessive photoresist, and the second step of etching the photoresist with a different gas does not consume excessive filler material.

[0035] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered exemplary and not restrictive in any way. Furthermore, it is clear that the word "comprising" does not exclude other elements and steps, and the word "a" does not exclude a plural. Multiple elements recited in the apparatus claims may also be implemented by a single element. The terms "first," "second," etc., are used to denote names and do not indicate any particular order.

Claims

1. A method for implementing a semiconductor complementary patterning process, characterized in that, include: Provide substrate; A patterned first mask layer is formed on the substrate; The trenches of the patterned first mask layer are filled with a filling material; After removing the patterned first mask layer, a patterned second mask layer complementary to the patterned first mask layer is formed.

2. The method of claim 1, wherein forming a patterned first mask layer on the substrate comprises: A first mask layer is formed on the substrate; The patterned first mask layer is formed on the substrate by exposure and development; The first mask layer material is photoresist; The filler material is a silicon-containing material.

3. The method as described in claim 2, characterized in that, The silicon-containing material is a silicon-containing hard mask layer (Si-HM) or a silicon-containing anti-reflection layer (Si-ARC).

4. The method as described in claim 1, characterized in that, Also includes: Ion implantation is performed based on the patterned first mask layer to form a first ion-doped region within the substrate; Ion implantation is performed based on the patterned second mask layer to form a second ion-doped region within the substrate.

5. The method as described in claim 4, characterized in that, The first ion-doped region is a photosensitive unit of the image sensor; the second ion-doped region is an isolation structure between adjacent photosensitive units.

6. The method as described in claim 4, characterized in that, The first ion-doped region is N-type and the second ion-doped region is P-type; or, the first ion-doped region is P-type and the second ion-doped region is N-type.

7. The method as described in claim 1, characterized in that, Also includes: Based on the patterned first mask layer, an etching process or an ion implantation process is performed; and / or Based on the patterned second mask layer, an etching process or an ion implantation process is performed.

8. The method as described in claim 1, characterized in that, The patterned first mask layer material is photoresist; the etching selectivity ratio of the filler material to the photoresist is greater than 5:

1.

9. The method as described in claim 5, characterized in that, The linewidth between adjacent photosensitive units is no more than 300 nm.

10. The method as described in claim 1, characterized in that, Filling the trenches of the patterned first mask layer with a filling material includes: A layer of the filler material is deposited on the substrate to fill the trenches of the patterned first mask layer; The filling material is etched and stopped on the patterned first mask layer.

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