Method of manufacturing semiconductor device structure and deposition apparatus

Abstract

A semiconductor device structure of an embodiment of the present invention may be manufactured by configuring a semiconductor package on a package tray, where the package tray includes a tray base portion extending laterally below the semiconductor package, a tray mesa portion extending laterally below the semiconductor package, and a holder-shaped support portion extending laterally below the tray mesa portion. The tray includes a tray base portion, a tray table portion projecting upwardly from the tray base portion and including a continuous set of table portion sidewalls, and a bracket-shaped support portion including a continuous set of support portion outer sidewalls, the outer side wall of the supporting part is laterally offset towards the inner side relative to a packaging area defined by all side walls of the semiconductor package; and depositing an electromagnetic interference shielding film on all the sidewall groups of the semiconductor package and the top surface of the semiconductor package in different directions.

Description

Technical Field

[0001] This invention relates to a method for manufacturing a semiconductor device structure and a deposition apparatus. Background Technology

[0002] Electromagnetic interference (EMI) shielding films on semiconductor packages block external electromagnetic waves from interfering with the semiconductor devices within the package. EMI shielding films prevent signal attenuation and ensure the proper functioning of the semiconductor devices within the package in the presence of strong external electromagnetic signals. Summary of the Invention

[0003] The method for manufacturing a semiconductor device structure according to an embodiment of the present invention includes the following steps: A semiconductor package is disposed on a package tray, wherein the package tray includes a tray base portion, a tray platform portion, and a support-like portion. The tray base portion extends laterally below the semiconductor package. The tray platform portion projects upward from the tray base portion and includes a continuous platform sidewall assembly. The support-like portion includes a continuous support outer sidewall assembly. In a plan view, the support outer sidewalls are laterally offset inward relative to the package area defined by all the sidewalls of the semiconductor package. An electromagnetic interference (EMI) shielding films are anisotropically deposited on all the sidewall assemblies of the semiconductor package and on the top surface of the semiconductor package.

[0004] The method for manufacturing a semiconductor device structure according to an embodiment of the present invention includes the following steps: A semiconductor package is disposed on a package tray, wherein the package tray includes a tray base portion, a tray platform portion, and a support-like portion. The tray base portion extends laterally below the semiconductor package, the tray platform portion protrudes upward from the tray base portion and laterally surrounds a recessed area, and the support-like portion is located within the recessed area and protrudes upward from the tray base portion. Anisotropic electromagnetic interference shielding films are deposited on all sidewall assemblies of the semiconductor package and on the top surface of the semiconductor package.

[0005] The deposition apparatus of this invention includes a cavity, a packaging tray, a vacuum pump, and a reactive gas supply manifold. The packaging tray is configured to mount at least one semiconductor package thereon. The packaging tray includes a tray base portion, a tray platform portion, and at least one support bracket portion. The tray base portion projects upward from the tray base portion and laterally surrounds at least one recessed region. Each of the at least one support bracket portions is located within a respective recessed region selected from the at least one recessed region and projects upward from the tray base portion. The vacuum pump is connected to the exhaust region of the cavity. The reactive gas supply manifold is configured to supply reactive gas to the gas inlet side of the cavity and provide a reaction region within the cavity. Attached Figure Description

[0006] The nature of this disclosure will be best understood when read in conjunction with the accompanying drawings in a detailed description. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1A This is a vertical cross-sectional view of a structure including a first carrier substrate and a redistribution structure according to an embodiment of the present disclosure.

[0008] Figure 1B yes Figure 1A A top view of the structural area.

[0009] Figure 2A This is a vertical cross-sectional view of a structural region after a bump structure is formed on an intermediary layer, according to an embodiment of the present disclosure.

[0010] Figure 2B yes Figure 2A A top view of the structural area.

[0011] Figure 3A This is a vertical cross-sectional view of a structural region after a semiconductor die has been attached, according to an embodiment of this disclosure.

[0012] Figure 3B yes Figure 3A A top view of the structural area.

[0013] Figure 3C yes Figure 3A A top view of the alternative configuration area of ​​the structure.

[0014] Figure 3D yes Figure 3A A top view of another alternative configuration area of ​​the structure.

[0015] Figure 3E This is an enlarged vertical cross-sectional view of a high-bandwidth memory die.

[0016] Figure 4 This is a vertical cross-sectional view of the structure after the first bottom filling material has been formed.

[0017] Figure 5A This is a vertical cross-sectional view of the structure after forming an epoxy molding compound (EMC) matrix according to an embodiment of the present disclosure.

[0018] Figure 5B It is along Figure 5A The horizontal cross-sectional view of the structure in the horizontal plane B-B'.

[0019] Figure 6 This is a vertical cross-sectional view of the structural region after the second carrier substrate has been attached and the first carrier substrate has been debonded, according to an embodiment of this disclosure.

[0020] Figure 7 This is a vertical cross-sectional view of the structural region after the formation of the bump structure and the second solder material portion, according to an embodiment of this disclosure.

[0021] Figure 8 This is a vertical cross-sectional view of the structural region after detachment from the second carrier substrate, according to an embodiment of this disclosure.

[0022] Figure 9 This is a vertical cross-sectional view of the structural region during the cutting of the redistribution substrate and EMC matrix according to an embodiment of the present disclosure.

[0023] Figure 10A This is a vertical cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

[0024] Figure 10B It is along Figure 10A A horizontal cross-sectional view of a semiconductor package in the horizontal plane B-B'.

[0025] Figure 11A This is a vertical cross-sectional view of an example deposition apparatus in a first configuration according to an embodiment of the present disclosure.

[0026] Figure 11B This is a vertical cross-sectional view of an example deposition apparatus in a second configuration according to an embodiment of the present disclosure.

[0027] Figure 11C This is a vertical cross-sectional view of the area surrounding the semiconductor package and the package tray area after a semiconductor package is disposed on a package tray in a first example deposition apparatus or a second example deposition apparatus, according to an embodiment of the present disclosure.

[0028] Figure 11D It is along Figure 11C A horizontal cross-sectional view of the packaging tray portion in the middle horizontal plane D-D'.

[0029] Figure 11E yes Figure 11C and 11D A plan view of the larger portion of the packaging tray.

[0030] Figure 12A This is a vertical cross-sectional view of an example deposition apparatus in a first configuration at the end of an electromagnetic interference (EMI) shielding film deposition process, according to an embodiment of the present disclosure.

[0031] Figure 12B This is a vertical cross-sectional view of an example deposition apparatus in a second configuration at the end of an electromagnetic interference (EMI) shielding film deposition process, according to an embodiment of this disclosure.

[0032] Figure 12C This is a vertical cross-sectional view of the area surrounding the semiconductor package and the package tray area in a first configuration at the end of the electromagnetic interference (EMI) shielding film deposition process, according to an embodiment of the present disclosure.

[0033] Figure 12D It is along Figure 12C A horizontal cross-sectional view of the packaging tray portion in the middle horizontal plane D-D'.

[0034] Figure 12E This is a vertical cross-sectional view of the area surrounding the semiconductor package and the package tray area in a second configuration at the end of the electromagnetic interference (EMI) shielding film deposition process, according to an embodiment of the present disclosure.

[0035] Figure 12F This is a vertical cross-sectional view of the area surrounding the semiconductor package and the package tray area in a third configuration at the end of the electromagnetic interference (EMI) shielding film deposition process, according to an embodiment of the present disclosure.

[0036] Figure 13 This is a vertical cross-sectional view of the structure after a semiconductor package has been attached to a package substrate and a second underfill material portion has been formed, according to an embodiment of the present disclosure.

[0037] Figure 14 This is a vertical cross-sectional view of the structure after the capping structure has been attached to the packaging substrate and the semiconductor package, according to an embodiment of the present disclosure.

[0038] Figure 15 This is a vertical cross-sectional view of the structure after the packaging substrate is attached to the printed circuit board (PCB) according to an embodiment of the present disclosure.

[0039] Figure 16 This is a first flowchart illustrating the steps of forming an electromagnetic shielding film on a semiconductor package according to an embodiment of the present disclosure.

[0040] Figure 17This is a second flowchart illustrating the steps of forming an electromagnetic shielding film on a semiconductor package according to an embodiment of the present disclosure. Detailed Implementation

[0041] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are merely examples and not limiting. The drawings are not to scale. Components with the same reference numerals refer to the same components and are assumed to have the same material composition and the same thickness range unless explicitly stated otherwise. All features of the original embodiments are assumed to exist in any derived embodiments unless explicitly disclosed otherwise. Therefore, features described in the drawings and / or description with reference to relevant embodiments support the features in the embodiments. Multiple embodiments are explicitly contemplated in which multiple instances of any described component are repeated unless explicitly stated otherwise. Embodiments that omit non-essential components are explicitly contemplated, even if such embodiments are not explicitly disclosed but are known in the art.

[0042] Furthermore, for ease of explanation, spatially relative terms such as "below," "under," "lower," "above," "upper," and similar expressions may be used herein to describe the selected geometric features of the components shown in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly. Unless otherwise expressly stated, each component with the same component symbol is assumed to have the same material composition and a thickness within the same thickness range.

[0043] Electromagnetic interference (EMI) shielding film is a layer applied to semiconductor packages to block or reduce the impact of external electromagnetic radiation on internal electronic components. EMI shielding films prevent signal attenuation, interference, and malfunctions in semiconductor devices caused by exposure to electromagnetic fields. Widely used in the semiconductor industry, EMI shielding films ensure the reliable operation of sensitive electronic devices by minimizing the effects of electromagnetic interference. EMI shielding films are deposited on semiconductor packages to provide a protective conductive barrier layer that effectively blocks external electromagnetic radiation.

[0044] When EMI shielding films are deposited on semiconductor packages positioned on a tray, issues such as backside contamination of the bump structure, insufficient sidewall coating, and the formation of a continuous EMI film between the package and the tray may occur. Since the EMI film is deposited on the bump structure, backside contamination can lead to electrical short circuit paths and device failure. Insufficient sidewall coating results in poor EMI shielding performance. Furthermore, the formation of a continuous EMI film between the semiconductor package and the tray can introduce burrs during the pick-and-place process. Both of these issues can complicate subsequent processing and assembly.

[0045] According to one aspect of the embodiments of this disclosure, a package tray may be provided. The package tray may include a tray base portion, a tray platform portion having continuous platform sidewalls, and a bracket-shaped support portion. A semiconductor package may be configured on the package tray such that the semiconductor package is supported only by the bracket-shaped support portion. The bracket-shaped support portion may be laterally offset inward relative to the package area defined by all sidewalls of the semiconductor package. This geometry ensures that the solder material portion (e.g., bump structure) array on the bottom of the semiconductor package does not directly contact the package tray, preventing contamination during the deposition of the EMI shielding film. The bracket-shaped support portion contacts the semiconductor package at the bracket-shaped bottom surface segment, avoiding the formation of a continuous film between the package and the tray, thereby preventing burr formation. Anisotropic deposition of the EMI shielding film ensures complete coverage of the semiconductor package sidewalls and top surface, enhancing EMI shielding performance. Therefore, embodiments of this disclosure can advantageously mitigate backside contamination of solder material portions, achieve complete sidewall coverage of the EMI shielding film, and reduce burr formation. Various aspects of this disclosure will now be described in detail with reference to the accompanying drawings.

[0046] Reference Figure 1A and Figure 1B The intermediate structure according to embodiments of this disclosure may include a first carrier substrate 310 and an interposer layer 900 formed on the front surface of the first carrier substrate 310. The first carrier substrate 310 may include an optically transparent substrate, such as a glass substrate or a sapphire substrate. The diameter of the first carrier substrate 310 may range from 150 mm to 290 mm, although smaller and larger diameters may also be used. Furthermore, the thickness of the first carrier substrate 310 may range from 500 micrometers to 2,000 micrometers, although smaller and larger thicknesses may also be used. Alternatively, the first carrier substrate 310 may be provided in the form of a rectangular panel. In these alternative embodiments, the dimensions of the first carrier may be substantially the same.

[0047] A first adhesive layer 311 may be applied to the front surface of a first carrier substrate 310. In one embodiment, the first adhesive layer 311 may be a light-to-heat conversion (LTHC) layer. The LTHC layer may be a solvent-based coating applied using a spin coating method. The LTHC layer can convert ultraviolet light into heat, which may cause the material of the LTHC layer to lose its adhesiveness. Alternatively, the first adhesive layer 311 may include a thermally decomposable adhesive material. For example, the first adhesive layer 311 may include an acrylic pressure-sensitive adhesive that decomposes at elevated temperatures. The detachment temperature of the thermally decomposable adhesive material may be in the range of 150 to 200 degrees Celsius.

[0048] Interchange layer 900 may be formed on the first adhesive layer 311. Specifically, an interchange layer 900 may be formed within each unit region UA, which is a region of repeating units that may be repeated in a two-dimensional array on the first carrier substrate 310. Each interchange layer 900 includes a corresponding portion of a redistribution structure 920, which is a combination of a redistribution dielectric layer 922 and redistribution line interconnects 924. The redistribution dielectric layer 922 is a dielectric material embedded in the redistribution line interconnects 924. In the claims of this application, the redistribution dielectric layer 922 may be referred to as a first dielectric layer or a second dielectric layer. The redistribution dielectric layer 922 comprises a corresponding dielectric polymer material, such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). Other suitable materials may also be within the scope of this disclosure. Each redistribution dielectric layer 922 may be formed by spin-coating and drying the corresponding dielectric polymer material. The thickness of each redistribution dielectric layer 922 can range from 2 micrometers to 40 micrometers, for example, from 4 micrometers to 20 micrometers. Each redistribution dielectric layer 922 can be patterned, for example, by applying and patterning a corresponding photoresist layer thereon, and transferring the pattern in the photoresist layer to the redistribution dielectric layer 922 using an etching process such as an isotropic etching. The photoresist layer can then be removed, for example, by ashing.

[0049] The redistribution interconnect 924 is a metallic interconnect structure, i.e., a metallic structure that provides electrical connections. In the claims of this application, the redistribution interconnect 924 may be referred to as a first metallic interconnect structure or a second metallic interconnect structure. Each redistribution interconnect 924 may be formed by sputtering a metal seed layer, applying and patterning a photoresist layer on the metal seed layer to form an opening pattern in the photoresist layer, electroplating a metallic filler material (such as copper, nickel, or a stack of copper and nickel), removing the photoresist layer (e.g., by ashing), and etching portions of the metal seed layer located between portions of the electroplated metallic filler material. The metal seed layer may, for example, comprise a stack of a titanium barrier layer and a copper seed layer. The thickness of the titanium barrier layer may range from 50 nm to 500 nm, and the thickness of the copper seed layer may also range from 50 nm to 500 nm. The metallic filler material of the redistribution interconnect 924 may include copper, nickel, or a combination of copper and nickel. Other suitable metallic filler materials are within the scope of this disclosure. The thickness of the metal filler material deposited for each redistribution interconnect 924 can range from 2 micrometers to 40 micrometers, for example, 4 micrometers to 10 micrometers, although smaller or larger thicknesses are also possible. The total number of wiring layers in each interposer 900 (i.e., the number of redistribution interconnects 924) can range from 1 to 10. A periodic two-dimensional array (e.g., a rectangular array) of interposers 900 can be formed on the first carrier substrate 310. Each interposer 900 can be formed within a unit region UA. The layer comprising all interposers 900 is referred to herein as an interposer. An interposer comprises a two-dimensional array of interposers 900. In one embodiment, the two-dimensional array of interposers 900 can be a rectangular periodic two-dimensional array of interposers 900 having a first periodicity along a first horizontal direction hd1 and a second periodicity along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1.

[0050] Reference Figure 2A and 2B At least one array of bump structures 938 on each intermediary layer 900 can be formed on the front surface of each intermediary layer 900, i.e., a portion of the redistribution structure 920 within a corresponding unit region UA. A single array of bump structures 938 or multiple arrays of bump structures 938 on each intermediary layer 900 can be formed. In one embodiment, each array of bump structures 938 on each intermediary layer can be formed as a corresponding periodic array, such as a rectangular array.

[0051] Reference Figure 3A and 3BAt least one set of semiconductor dies (701, 703) may be attached to each redistribution structure 920. In one embodiment, the redistribution structure 920 may be arranged in a two-dimensional periodic array, and a plurality of sets of at least one semiconductor die (701, 703) may be attached to the redistribution structure 920 as a two-dimensional periodic rectangular array of sets of at least one semiconductor die (701, 703). Each set of at least one semiconductor die (701, 703) includes at least one semiconductor die. Each set of at least one semiconductor die (701, 703) may include any set of at least one semiconductor die known to those skilled in the art. In one embodiment, each set of at least one semiconductor die (701, 703) may include a plurality of semiconductor dies (701, 703). For example, each set of at least one semiconductor die (701, 703) may include at least one system-on-chip (SoC) die 701 and / or at least one memory die 703. Each system-on-a-chip die 701 may include an application processor die, a central processing unit die, or a graphics processing unit die. In one embodiment, at least one memory die 703 may include a high bandwidth memory (HBM) die comprising a vertical stack of static random access memory (SRAM) dies. In one embodiment, at least one semiconductor die (701, 703) may include at least one system-on-a-chip (SoC) die and one high bandwidth memory (HBM) die, the high bandwidth memory die comprising a vertical stack of static random access memory (SRAM) dies interconnected by microbumps and laterally surrounded by an epoxy molding compound encapsulation frame.

[0052] Each semiconductor die (701, 703) may include a corresponding array of on-die bump structures 780. Each semiconductor die (701, 703) may be positioned face down such that the on-die bump structures 780 face the first solder material portion 940. At least one group of semiconductor dies (701, 703) may be placed within a corresponding cell region UA. The placement of the semiconductor dies (701, 703) may be performed using a pick-and-place device such that each of the on-die bump structures 780 may be placed on the top surface of a corresponding one of the first solder material portions 940.

[0053] Generally, a redistribution structure 920 including an on-intermediate bump structure 938 may be provided, and at least one semiconductor die (701, 703) including a group of corresponding on-die bump structures 780 may be provided. At least one semiconductor die (701, 703) may be bonded to the redistribution structure 920 using a first solder material portion 940, which is bonded to one of the corresponding on-intermediate bump structure 938 and the corresponding on-die bump structure 780.

[0054] At least one semiconductor die (701, 703) group in each group can be attached to the corresponding redistribution structure 920 via a corresponding first solder material portion 940 group. In the plan view, each of at least one buffer film in the unit region UA ​​may be located outside the region in the unit region UA ​​that includes at least one semiconductor die (701, 703). The plan view is a view along a vertical direction, which is a direction perpendicular to the planar top surface of the redistribution structure layer.

[0055] Figure 3C yes Figure 3A A top view of the area with an alternative configuration of the structure. Figure 3D yes Figure 3A A top view of the area with an alternative configuration to the structure. Figure 3C and Figure 3D The configuration shown is merely illustrative and any arrangement of semiconductor dies (701, 703) may be used. Generally, multiple semiconductor dies (701, 703) may be attached to each interposer 900. In one embodiment, the multiple semiconductor dies (701, 703) may include at least one SoC die 701 and at least one memory die 703. In one embodiment, each plurality of semiconductor dies (701, 703) attached to a respective interposer 900 may be arranged within a respective rectangular region such that the sidewalls of a subset of the respective plurality of semiconductor dies (701, 703) are located on the four sides of the respective rectangular region.

[0056] Reference Figure 3E The diagram illustrates a high-bandwidth memory (HBM) die 830, which can be used as a memory die 703. The HBM die 830 may include a vertical stack of static random access memory dies (811, 812, 813, 814, 815) interconnected via microbumps 820 and laterally surrounded by an epoxy molding compound encapsulation frame 816. Gaps between vertically adjacent pairs of RMI dies (811, 812, 813, 814, 815) may be filled by HBM bottom filler portions 822 laterally surrounding the respective sets of microbumps 820. The HBM die 830 may include an array of on-die bump structures 780 configured to engage a subset of an array of on-intermediate layer bump structures 938 within a unit region UA. The HBM die 830 may or may not be configured to provide high bandwidth as defined under JEDEC standards (i.e., standards defined by the JEDEC Solid State Technology Association).

[0057] Reference Figure 4A first underfill material can be applied to each gap between the interposer 900 and at least one set of semiconductor dies (701, 703) bonded to the interposer 900. The first underfill material may include any underfill material known in the art. A first underfill material portion 950 may be formed in each unit region UA ​​between the interposer 900 and the at least one set of semiconductor dies (701, 703) above it. The first underfill material portion 950 may be formed by injecting the first underfill material around a corresponding array of first solder material portions 940 in the corresponding unit region UA. Any known underfill material application method may be used, which may be a capillary underfill method, a molding underfill method, or a printed underfill method.

[0058] In each unit region UA, a first underfill material portion 950 may laterally surround and contact each first solder material portion 940 in the unit region UA. The first underfill material portion 950 may be formed around and contact the first solder material portion 940, the interposer bump structure 938, and the die bump structure 780 in the unit region UA. The first underfill material portion 950 is formed between the semiconductor die (701, 703) and the interposer 900, and is therefore also referred to as a die-to-interposer underfill material portion, or a DI underfill material portion.

[0059] Each interposer 900 in a unit region UA ​​includes an interposer-on-interposer bump structure 938. At least one semiconductor die (701, 703) including a corresponding set of die-on-bump structures 780 is attached to the interposer-on-interposer bump structure 938 via a corresponding set of first solder material portions 940 within each unit region UA. Within each unit region UA, a first underfill material portion 950 laterally surrounds the interposer-on-interposer bump structure 938 and the die-on-bump structures 780 of at least one semiconductor die (701, 703).

[0060] Generally, the underfill material portion 950 may be formed between each pair of facing at least one interposer layer 900 and at least one set of at least one semiconductor die (701, 703). In one embodiment, each interposer layer 900 includes an interposer layer bump structure 938 located above a horizontal plane containing a first horizontal surface 901 of the interposer layer 900, and a horizontal extension of the underfill material portion 950 is located above the horizontal plane containing the first horizontal surface 901 of the interposer layer 900.

[0061] Reference Figure 5A and Figure 5BAn epoxy molding compound (EMC) can be applied to the gap between a set of semiconductor dies (701, 703) and a set of continuous segments of the first bottom filler portion 950.

[0062] EMC may include epoxy-containing compounds that can be hardened (i.e., cured) to provide a dielectric material portion with sufficient hardness and mechanical strength. EMC may include epoxy resin, hardener, silica (as a filler material), and other additives. EMC may be provided in liquid or solid form depending on viscosity and flowability. Liquid EMC offers better handling, good flowability, less voids, better filling, and fewer flow marks. Solid EMC offers less curing shrinkage, better reference distance, and less die drift. High filler content (e.g., 85% by weight) in EMC can shorten molding time, reduce molding shrinkage, and reduce molding warpage. Uniform filler size distribution in EMC can reduce flow marks and enhance flowability. In embodiments where the adhesive layer includes a heat-release material, the curing temperature of the EMC may be lower than the release (peel) temperature of the first adhesive layer 311. For example, the curing temperature of the EMC may be in the range of 125 to 150 degrees Celsius.

[0063] EMC can be cured at a curing temperature to form an EMC matrix 910M, which laterally surrounds and embeds each component of a set of semiconductor dies (701, 703) and a first underfill material portion 950. The EMC matrix 910M includes multiple epoxy molding compound (EMC) die frames that can be laterally abutted against each other. Each EMC die frame is a portion of the EMC matrix 910M located within a corresponding unit region UA. Therefore, each EMC die frame laterally surrounds and embeds a corresponding set of semiconductor dies (701, 703) and a corresponding first underfill material portion 950. The Young's modulus of pure epoxy resin is approximately 3.35 gigapascals (GPa), and by adding additives, the Young's modulus of EMC can be higher than that of pure epoxy resin. The Young's modulus of EMC can be greater than 3.5 gigapascals (GPa).

[0064] A portion of the EMC matrix 910M covering the top surface of the semiconductor dies (701, 703) can be removed by a planarization process. For example, chemical mechanical planarization (CMP) can be used to remove the portion of the EMC matrix 910M covering the horizontal surface. The remaining portion of the EMC matrix 910M, the semiconductor dies (701, 703), the first underfill material portion 950, and the two-dimensional array of the interposer 900 constitute a reconstructed wafer 800W. Each portion of the EMC matrix 910M located within a unit region UA ​​constitutes an EMC die frame.

[0065] Reference Figure 6 A second adhesive layer 321 can be applied to the exposed flat surfaces of the reconstructed wafer 800W (i.e., the exposed surfaces of the EMC matrix 910M, semiconductor dies (701, 703), and the first underfill material portion 950). In one embodiment, the second adhesive layer 321 may contain the same material as the first adhesive layer 311, or it may contain a different material. In embodiments where the first adhesive layer 311 contains a thermally decomposable adhesive material, the second adhesive layer 321 may contain another thermally decomposable adhesive material that decomposes at higher temperatures, or it may contain a photothermal conversion material.

[0066] The second carrier substrate 320 may be attached to the second adhesive layer 321. The second carrier substrate 320 may be attached to the opposite side of the reconstructed wafer 800W relative to the first carrier substrate 310. Generally, the second carrier substrate 320 may include any material used in the first carrier substrate 310. The thickness of the second carrier substrate 320 may be in the range of 500 micrometers to 2000 micrometers, but may also be smaller or larger.

[0067] The first adhesive layer 311 can be decomposed by ultraviolet radiation or by thermal annealing at a debonding temperature. In embodiments where the first carrier substrate 310 comprises an optically transparent material and the first adhesive layer 311 comprises a photothermal conversion layer (LTHC layer), ultraviolet light can be irradiated through the transparent carrier substrate to decompose the first adhesive layer 311. The photothermal conversion layer can absorb ultraviolet radiation and generate heat, which decomposes the material of the photothermal conversion layer and causes the transparent first carrier substrate 310 to separate from the reconstructed wafer 800W. In embodiments where the first adhesive layer 311 comprises thermally decomposable adhesive material, a thermal annealing process at a debonding temperature can be performed to separate the first carrier substrate 310 from the reconstructed wafer 800W.

[0068] Reference Figure 7A bump structure 928 (which may be referred to as a back bump structure) and a second solder material portion 290 can be formed by deposition and patterning of a stack of at least one metallic material, which can be used as the metal bump and solder material layer. The metal filler material used for the bump structure 928 may include copper. Other suitable materials are also within the scope of this disclosure. The thickness of the bump structure 928 may range from 5 micrometers to 100 micrometers, but smaller or larger thicknesses may also be used. The bump structure 928 and the second solder material portion 290 may have a rectangular, rounded rectangular, or circular horizontal cross-sectional shape. Other suitable shapes are also within the scope of this disclosure. In embodiments where the bump structure 928 is formed as a controlled collapse chip connection (C4) pad, the thickness of the bump structure 928 may range from 5 micrometers to 50 micrometers, but smaller or larger thicknesses may also be used. In some embodiments, the bump structure 928 may be or include an under bump metallurgy (UBM) structure. The configuration of the bump structure 928 is not limited to a fan-out structure. Alternatively, the bump structure 928 can be configured for microbump bonding (i.e., C2 bonding) and can have a thickness ranging from 30 micrometers to 100 micrometers, but smaller or larger thicknesses are also possible. In this embodiment, the bump structure 928 can be formed as an array of microbumps (e.g., copper pillars) with lateral dimensions ranging from 10 micrometers to 25 micrometers and a pitch ranging from 20 micrometers to 50 micrometers.

[0069] The bump structure 928 and the second solder material portion 290 may be formed on opposite sides of the EMC substrate 910M and a two-dimensional array formed by multiple sets of semiconductor dies (semiconductor dies 701, semiconductor dies 703) relative to the interposer. The interposer includes a three-dimensional array of interposers 900. Each interposer 900 may be located within a corresponding unit region UA. Each interposer 900 may include a redistribution dielectric layer 922, redistribution wiring interconnects 924 embedded in the redistribution dielectric layer 922, and a bump structure 928. The bump structure 928 may be located on opposite sides of the bump structure 938 on the interposer relative to the redistribution dielectric layer 922 and may be electrically connected to a corresponding bump structure 938 on the interposer.

[0070] Reference Figure 8The second adhesive layer 321 can be decomposed by ultraviolet radiation or by thermal annealing at a detachment temperature. In embodiments where the second carrier substrate 320 includes an optically transparent material and the second adhesive layer 321 includes a photothermal conversion layer (LTHC layer), the second adhesive layer 321 can be decomposed by irradiating the transparent carrier substrate with ultraviolet light. In embodiments where the second adhesive layer 321 includes a thermally decomposable adhesive material, a thermal annealing process can be performed at a detachment temperature to separate the second carrier substrate 320 from the reconstructed wafer 800W.

[0071] Reference Figure 9 The reconstructed wafer 800W, including the bump structure 928, can then be diced along a dicing channel by performing a dicing process. The dicing channel corresponds to the boundary between adjacent pairs of die regions DA. Each dicing unit from the reconstructed wafer 800W may include a semiconductor package 800. In other words, each dicing portion of a combination of a two-dimensional array of multiple semiconductor dies (semiconductor dies 701, semiconductor dies 703), a two-dimensional array of a first underfill material portion 950, and a two-dimensional array of an EMC matrix 910M and an interposer 900 constitutes a semiconductor package 800. Each dicing portion of the EMC matrix 910M constitutes a molded compound die frame 910. Each dicing portion of the interposer (which includes a two-dimensional array of interposers 900) constitutes an interposer 900.

[0072] Reference Figure 10A and Figure 10B The illustration shows how to achieve this by means of... Figure 9 The semiconductor package 800 is obtained by cutting the structure in the processing steps. The semiconductor package 800 includes an interposer 900, which includes an interposer bump structure 938, and at least one semiconductor die (semiconductor die 701, semiconductor die 703), which includes a corresponding set of die-on bump structures 780. The die-on bump structures 780 are attached to the interposer bump structure 938 by a corresponding set of first solder material portions 940. A first underfill material portion 950 laterally surrounds the interposer bump structure 938 and the die-on bump structures 780 of at least one semiconductor die (semiconductor die 701, semiconductor die 703).

[0073] Semiconductor package 800 may include a molded compound die frame 910 that laterally surrounds the at least one semiconductor die (semiconductor die 701, semiconductor die 703) and comprises a molding compound material. In one embodiment, the molding compound die frame 910 may include a sidewall that coincides with the sidewall of the intermediate 900 in a vertical direction (i.e., lies in the same vertical plane as the sidewall of the intermediate 900). Generally, the molding compound die frame 910 may be formed around the at least one semiconductor die (semiconductor die 701, semiconductor die 703) after a first underfill material portion 950 is formed within each semiconductor package 800. The molding compound material contacts a peripheral portion of the flat surface of the intermediate 900.

[0074] Figure 11A This is a vertical cross-sectional view of an example deposition apparatus 1000 in a first configuration according to an embodiment of the present disclosure. Figure 11B This is a vertical cross-sectional view of an example deposition apparatus 1000 in a second configuration according to an embodiment of the present disclosure. Figure 11C This is a vertical cross-sectional view of the area surrounding the semiconductor package 800 and the area of ​​the package tray 600 after the semiconductor package 800 has been disposed on the package tray 600 in a first example deposition apparatus 1000 or a second example deposition apparatus 1000, according to an embodiment of the present disclosure. Figure 11D It is along Figure 11C A horizontal cross-sectional view of the packaging tray 600 portion in the mid-horizontal plane D-D'. Figure 11E yes Figure 11C and Figure 11D A plan view of the larger portion of the 600 medium-sized packaging tray.

[0075] Reference Figures 11A to 11E According to embodiments of the present disclosure, a deposition apparatus 1000 is provided. The deposition apparatus 1000 may have Figure 11A The first configuration shown or Figure 11B The second configuration is shown. Generally, the deposition apparatus disclosed herein includes a chamber enclosure 1010 having an opening for loading and unloading at least one semiconductor die 800. The opening may be located on a sidewall of the chamber 1010 and may be configured to transport a packaging tray 600 having at least one semiconductor package 800. Alternatively, the opening may be provided by raising the upper portion of the chamber 1010 or lowering the lower portion of the chamber 1010. In this embodiment, the upper or lower portion of the chamber 1010 may be tilted or not tilted relative to a fixed portion of the chamber 1010. A vacuum seal may be provided at a position adjacent to the components of the chamber 1010 when the opening is closed.

[0076] At least one semiconductor package 800 can be loaded into cavity 1010 using package tray 600. Package tray 600 can be configured to carry at least one semiconductor package 800. At least one semiconductor package 800 can be loaded using a picking and placing tool when package tray 600 is stationary within cavity 1010 or when package tray 600 is temporarily moved out of cavity 1010 to load at least one semiconductor package 800. At least one semiconductor package 800 can be a single semiconductor package 800 or can be multiple semiconductor packages 800, such as a two-dimensional array of semiconductor packages 800. Typically, at least 16 semiconductor packages 800, such as at least 100 semiconductor packages 800, can be loaded onto package tray 600. Generally, any type of semiconductor package 800 that requires forming an electromagnetic interference (EMI) shielding film can be loaded onto package tray 600. Although this disclosure is described using an embodiment, reference is made to... Figure 10A and Figure 10B Multiple semiconductor packages 800 of the type described can be loaded onto package tray 600, but it should be understood that any semiconductor package type configured for depositing an EMI film thereon can be used instead of the semiconductor package 800 shown.

[0077] According to one aspect of this disclosure, a packaging tray 600 may be configured to have at least one semiconductor package 800 disposed thereon. The packaging tray 600 includes a tray base portion 60B, a tray platform portion 60M that projects upward from the tray base portion 60B and laterally surrounds at least one recessed region RR, and at least one bracket-shaped support portion 60S. In one embodiment, the tray platform portion 60M may be configured as a lattice structure, wherein a first one-dimensional periodic array of a first track portion intersects a second one-dimensional periodic array of a second track portion. The first one-dimensional periodic array of the first track portion extends laterally along a first horizontal direction. The first track portion has a first uniform width and a first uniform spacing along a second horizontal direction perpendicular to the first horizontal direction. The second one-dimensional periodic array of the second track portion extends laterally along a second horizontal direction. The second track portion has a second uniform width and a second uniform spacing along the first horizontal direction.

[0078] Generally, at least one semiconductor package 800 may be disposed on the package tray 600, either outside or inside the cavity 1010. Therefore, at least one semiconductor package 800 may be disposed on the package tray 600 before or after the cavity 1010 is disposed. In an embodiment where at least one semiconductor package 800 is disposed on the package tray 600 outside the cavity 1010, the combination of the at least one semiconductor package 800 and the package tray 600 can be transferred into the space of the cavity 1010 using a robot. Any opening in the cavity 1010 may be sealed, thereby isolating the enclosed space within the cavity from the external environment of the cavity 1010.

[0079] According to one aspect of this disclosure, each semiconductor package 800 may be configured on a respective bracket-shaped support portion 60S. A tray base portion 60B extends laterally beneath at least one semiconductor package 800. A tray platform portion 60M projects upward from the tray base portion 60B and includes at least one set of consecutive platform platform sidewalls 60MS (referred to as a platform platform sidewall group), each group defining a recessed region RR. The tray platform portion 60M may include multiple sets of consecutive platform platform sidewalls 60MS. The total number of consecutive platform platform sidewall groups 60MS may be the same as the total number of recessed regions RR. The total number of recessed regions RR may range from 1 to 1,000, although a larger number may also be used. In one embodiment, the tray platform portion 60M may be configured as a two-dimensional array of intersecting track portions and may laterally surround the two-dimensional array of recessed regions RR.

[0080] Each semiconductor package 800 defines a package area PA, which is the area of ​​each semiconductor package 800 in a plan view (such as a top view). Specifically, each package area PA can be defined by the combination of all sidewalls of each semiconductor package 800 in the plan view, and the area surrounded by the combination of all sidewalls is the package area PA. Each bracket-shaped support portion 60S includes a set of continuous support portion outer sidewalls 60SO, which are laterally offset inward relative to the package area PA of the upper semiconductor package 800. Each of at least one bracket-shaped support portion 60S is located within a respective recessed region RR selected from at least one recessed region RR, and protrudes upward from the tray base portion 60B.

[0081] The deposition apparatus 1000 includes a reaction gas supply manifold 1030, such as a showerhead, configured to supply reaction gas to the gas inlet side of the cavity 1010. A gas flow control system 1020 may be located upstream of the reaction gas supply manifold 1030. The deposition apparatus 1000 includes a vacuum pump 1090 connected to the opposite side of the reaction gas supply manifold 1030. A packaging tray 600 may be positioned within the cavity 1010 to separate a first portion of the space within the cavity 1010 adjacent to the reaction gas supply manifold 1030 from a second portion of the space within the cavity adjacent to the vacuum pump 1090. The first portion of the space within the cavity 1010 constitutes a reaction region 1009, to which the top surface, sidewalls, and support-shaped peripheral bottom surface section of the semiconductor package 800 are actually exposed. The second portion of the space within the cavity 1010 constitutes an exhaust region 1049, serving as a passage for gas pumped from the reaction region 1009 into the vacuum pump 1090.

[0082] In one embodiment, each of at least one bracket-shaped support portion 60S is configured to divide its respective recessed region RR into a first space V1 and a second space V2 when the semiconductor package 800 is placed thereon. The first space V1 is laterally surrounded by each bracket-shaped support portion 60S and excluded from the reaction region 1009, while the second space V2 is entirely located outside each bracket-shaped support portion 60S and included within the reaction region 1009, i.e., is a part of the reaction region 1009.

[0083] In one embodiment, the deposition apparatus 1000 may further include a vacuum manifold 619, which includes at least one opening 609 in the tray base portion 60B. In one embodiment, an opening 609 may be provided in the tray base portion 60B to connect each first space V1 of at least one recessed region RR to a vacuum pump 1090 (e.g., Figure 11A (as shown in the first configuration embodiment) or connected to another vacuum pump 1070 (such as Figure 11B (As shown in the second configuration embodiment).

[0084] In one embodiment, the semiconductor package 800 includes an array of bump structures 928, and an array of solder material portions 290 may be attached to the array of bump structures 928 before the semiconductor package 800 is positioned in the package tray 600, for example, as shown in reference Figure 10A and Figure 10B As described above. In one embodiment, each bracket-shaped support portion 60S includes a set of continuous support portion inner sidewalls 60SI, as shown in the plan view. Figure 11D The horizontal cross-sectional view shown indicates the encapsulation area PA, and the continuous support portion inner sidewall 60SI group is offset laterally by a first horizontal distance ld1 from the continuous support portion outer sidewall 60SO group.

[0085] In one embodiment, the solder material portion 290 array may be entirely located within an area continuously defined in the plan view by a set of support portion inner sidewalls 60SI. For example, the outermost surface segment of the solder material portion 290 may be laterally offset by a second horizontal distance ld2 from a set of vertical planes (i.e., a set of vertical planes defining the package area PA) that includes all sidewalls of each overlay semiconductor package 800. This second lateral offset distance may be greater than the horizontal distance between each support portion inner sidewall 60SI and the nearest vertical plane including the sidewall of the overlay semiconductor package 800.

[0086] In one embodiment, the solder material portion 290 array is positioned such that the solder material portion 290 array does not directly contact any surface of the package tray 600. In one embodiment, when the overlay semiconductor package 800 is disposed on the package tray 600, the bracket-shaped support portion 60S laterally surrounds the entire solder material portion 290 array of the overlay semiconductor package 800.

[0087] In one embodiment, the bracket-shaped support portion 60S includes a bracket-shaped planar top surface FPTS, and when the overlay semiconductor package 800 is disposed on the package tray 600, the entire bracket-shaped planar top surface FPTS contacts the bracket-shaped bottom surface segment of the semiconductor package 800. In one embodiment, each of at least one bracket-shaped support portion 60S includes a respective bracket-shaped planar top surface FPTS, which is located in a horizontal plane including the top surface of the tray platform portion 60M. In other words, each bracket-shaped support portion 60S includes a bracket-shaped planar top surface FPTS, which is located in the same horizontal plane as the top surface of each tray platform portion 60M.

[0088] In one embodiment, when the semiconductor package 800 is disposed on the package tray 600, the solder material portion 290 array may be spaced apart from the tray base portion 60B in the vertical direction. In one embodiment, the entire solder material portion 290 array is located below a horizontal plane that includes the entire contact area between the semiconductor package 800 and the package tray 600.

[0089] In one embodiment, a set of continuous platform sidewalls 60MS of each tray platform portion 60M defines a tray recess region TRA in a plan view. Therefore, the periphery of the tray recess region TRA coincides with the set of continuous platform sidewalls 60MS in the plan view. In one embodiment, the entire periphery of the tray recess region TRA is laterally offset outwards in the plan view from the periphery of the package area PA of the overlying semiconductor package 800.

[0090] In one embodiment, when a semiconductor package 800 is disposed on a package tray 600, each semiconductor package 800 contacts a bracket-shaped support portion 60S. In another embodiment, when a semiconductor package 800 is disposed on a package tray 600, each semiconductor package 800 does not contact any tray base portion 60B or any tray platform portion 60M. In yet another embodiment, each semiconductor package 800 directly contacts the package tray 600 only at the top surface FPTS of the bracket-shaped plane of each bracket-shaped support portion 60S of the package tray 600.

[0091] In one embodiment, the contact between the semiconductor package 800 and the bracket-shaped support portion 60S of the package tray 600 provides a seal to prevent gas from diffusing between the first space V1 of the laterally enclosed recessed area RR inside the bracket-shaped support portion 60S and the second space V2 of the recessed area RR outside the bracket-shaped support portion 60S.

[0092] Figure 12AThis is a vertical cross-sectional view of an example deposition apparatus 1000 in a first configuration according to the embodiments disclosed herein, at the end of the electromagnetic interference (EMI) shielding film deposition process. Figure 12B This is a vertical cross-sectional view of an example deposition apparatus 1000 in a second configuration according to an embodiment of this disclosure at the end of the EMI shielding film deposition process. Figure 12C This is a vertical cross-sectional view of the area surrounding the semiconductor package 800 and the package tray 600 area in the first configuration at the end of the EMI shielding film deposition process, according to the embodiment disclosed herein. Figure 12D It is along Figure 12C A horizontal cross-sectional view of the packaging tray 600 portion in the mid-horizontal plane D-D'. Figure 12E This is a vertical cross-sectional view of the area surrounding the semiconductor package 800 and the package tray 600 area in the second configuration according to the embodiment disclosed herein, at the end of the EMI shielding film deposition process. Figure 12F This is a vertical cross-sectional view of the area surrounding the semiconductor package 800 and the package tray 600 area in the third configuration according to the embodiment disclosed herein, at the end of the EMI shielding film deposition process.

[0093] Reference Figures 12A to 12F Electromagnetic interference (EMI) shielding film 810 can be deposited anisotropically on all sidewall assemblies and the top surface of each semiconductor package 800. Additionally, the EMI shielding film 810 can be deposited on at least a portion of the bottom support-shaped physically exposed surface segment of each semiconductor package 800 exposed to the reaction region 1009. Typically, anisotropic chemical vapor deposition processes, such as plasma-enhanced chemical vapor deposition, can be used to deposit the EMI shielding film 810 on each semiconductor package 800. Reactive gases and optional carrier gases can flow from a gas flow control system 1020 through a reactive gas supply manifold 1030 (which may include a spray head) into the reaction region 1009 located within the cavity 1010 space. The reactive gases include a precursor gas for depositing the EMI shielding film 810.

[0094] Typically, each EMI shielding film 810 is anisotropically deposited on the corresponding semiconductor package 800 by infusing a reactive gas into the cavity 1010. The top surface and sidewalls of each semiconductor package 800 are exposed to a first environment containing the reactive gas and filling the reactive region 1009. The second space V2 of each recessed region RR may be part of the first environment. The central region of the bottom surface of each semiconductor package 800 is exposed to a vacuum environment free of reactive gas. The first space V1 of each recessed region RR may be part of a vacuum environment. Therefore, during the deposition of the EMI shielding film 810, the peripheral support-shaped surface segment of the bottom surface of each semiconductor package 800 is exposed to the first environment. An electromagnetic interference (EMI) shielding material layer 610 may be incidentally deposited on the top surface and sidewalls of each tray platform portion 60M, and on the surface segments of the support-shaped support portion 60S and the tray base portion 60B surrounding the second space V2 of the recessed region RR.

[0095] According to one aspect of this disclosure, the anisotropy of the EMI shielding film deposition process results in the vertical thickness of the horizontally extending portion of each EMI shielding film 810 covering the top surface of the corresponding semiconductor package 800 being greater than the lateral thickness of the vertically extending portion of each EMI shielding film 810 located on the sidewall of the corresponding semiconductor package 800. Furthermore, the vertical thickness of each support-shaped portion of each EMI shielding film 810 contacting the support-shaped peripheral surface segment of the bottom surface of the corresponding semiconductor package 800 may decrease from the outside to the inside.

[0096] The degree of variation in the vertical thickness of each support-shaped portion of each EMI shielding film 810 depends on the degree of lateral diffusion of the reactive gas during the anisotropic deposition process. In other words, the degree of variation in the vertical thickness of each support-shaped portion of each EMI shielding film 810 depends on how the degree of reactive gas depletion varies with the lateral distance from the reactive region 1009 portion that is not shielded by any upper structure in the area shielded by the upper structure (e.g., the upper semiconductor package 800). Figure 12C An embodiment with moderate reactant depletion is described, wherein the vertical thickness of the support-shaped portion of each EMI shielding film 810 becomes zero when the EMI shielding film 810 reaches the outer wall of the corresponding support-shaped portion 60S. Figure 12E A low reactant depletion embodiment is described, wherein the vertical thickness of the support-shaped portion of each EMI shielding film 810 does not become zero at the top periphery of the outer wall of the corresponding support-shaped support portion 60S. In this embodiment, the EMI shielding film 810 may have a small but limited thickness at the junction with the top periphery of the outer wall of the corresponding support-shaped support portion 60S. Figure 12FA highly reactive depletion embodiment is described, wherein the vertical thickness of the support-shaped portion of each EMI shielding film 810 becomes zero before each EMI shielding film 810 reaches the outer wall of the corresponding support-shaped support portion 60S. In this embodiment, another support-shaped bottom segment of the semiconductor package 800 is not covered by the EMI shielding film 810.

[0097] According to one aspect of this disclosure, the EMI shielding film 810 may comprise a metallic material, such as copper (Cu), silver (Ag), or nickel (Ni), which has high conductivity, effectively attenuates EMI, and possesses high mechanical strength, providing structural robustness. Materials such as silver (Ag) and copper (Cu) can be used to provide excellent conductivity, thereby enhancing the shielding effect, especially in high-frequency applications. Copper has excellent electrical and thermal properties. Silver has low oxidation potential and long-term performance stability. Nickel can be used in magnetic shielding applications because its high permeability helps to shield low-frequency magnetic fields. In some embodiments, the EMI shielding film 810 may use a stack comprising multiple metallic materials.

[0098] Other materials, including conductive polymers or carbon-based nanomaterials such as graphene or carbon nanotubes, can be used to replace or complement metallic materials to enhance the flexibility of the EMI shielding film 810 while reducing its weight. For non-metallic applications, conductive polymers such as polyaniline (PANI) and poly(3,4-ethylenedioxythiophene) (PEDOT) can be used as EMI shielding materials due to their lightweight and mechanical flexibility, properties suitable for portable or flexible electronics applications. Carbon-based materials, such as graphene and carbon nanotubes, can be used due to their excellent electrical properties, mechanical strength, and ability to be integrated into composite structures. Using composite layers of multiple materials as the EMI shielding film 810 can enhance its effectiveness in blocking, absorbing, and / or reflecting unwanted electromagnetic waves.

[0099] The EMI shielding film 810 can be deposited using a chemical vapor deposition (CVD) process. The CVD process provides precise thickness control of the EMI shielding film 810. By adjusting process parameters such as temperature distribution, gas flow rate, and pressure across multiple semiconductor packages 800, the thickness uniformity of the EMI shielding film across the multiple semiconductor packages 800 can be maintained. The CVD process can be made anisotropic by providing depletion deposition conditions, under which the reactive gas is depleted in areas not directly exposed to the reactive gas supply manifold 1030. Therefore, fewer reactive gas molecules collide with the physically exposed support-shaped surface segment on the bottom surface of the semiconductor package 800 relative to the sidewalls of the semiconductor package 800. As described above, a thinner EMI shielding film 810 layer with a non-uniform thickness can be deposited on the physically exposed support-shaped surface segment on the bottom surface of the semiconductor package 800.

[0100] In the anisotropic deposition process used to deposit the EMI shielding film 810 on each semiconductor package 800, the high orientation of the vapor-phase reactants in CVD results in complete and uniform deposition on the exposed sidewalls and top surface of the semiconductor package 800, while areas shielded by geometric features or fixtures (such as the support-shaped bottom section of the semiconductor package 800) receive less deposition. This controlled film thickness variation in different regions allows for minimal or no deposition of EMI shielding material around or near the contact area between the semiconductor package 800 and the package tray 600. Therefore, the formation of burrs or unintended bridging between the semiconductor package 800 and the package tray 600 can be eliminated or minimized.

[0101] Furthermore, the bracket-shaped contact area on the top surface FPTS of the bracket-shaped support portion 60S provides isolation of environmental conditions between the first space V1 and the second space V2 of each recessed region RR. Therefore, the geometry of the package tray 600 disclosed herein can prevent contamination or undesirable coating of sensitive components (such as solder material portion 290) by reactive gases during the chemical vapor deposition process.

[0102] The thickness of the horizontally extending portion of each EMI shielding film 810 on the top surface of each semiconductor package 800 can range from 2 micrometers to 10 micrometers, but smaller or larger thicknesses are also possible. The thickness of the horizontally extending portion of each EMI shielding film 810 on the sidewall of each semiconductor package 800 can range from 1 micrometer to 5 micrometers, but smaller or larger thicknesses are also possible. The optimal film thickness of the EMI shielding film 810 can be selected based on the specific electromagnetic interference environment that the semiconductor package 800 may subsequently be exposed to. Generally, thicker films that provide more effective shielding are suitable for high-power applications, while thinner films are suitable for miniaturized devices that require lightweight design.

[0103] The overall shielding effectiveness (SE) of the EMI shielding film 810 can be measured in decibels (dB), with typical values ​​ranging from 40 dB to 90 dB, depending on the material composition and thickness of the EMI shielding film 810. For example, an EMI shielding film 810 including silver may achieve higher shielding effectiveness due to its excellent conductivity, while an EMI shielding film 810 including nickel may be more suitable for applications involving both electrical and magnetic interference because of its dual conductive and magnetic properties.

[0104] Generally speaking, anisotropic CVD deposition processes allow for highly controlled deposition of EMI shielding films, ensuring complete electromagnetic interference protection for the top surface and all sidewalls of each semiconductor package 800 while optimizing material usage.

[0105] Reference Figure 13A packaging substrate 200 is provided. The packaging substrate 200 may be a cored packaging substrate including a core substrate 210, or a coreless packaging substrate excluding a packaging core. Alternatively, the packaging substrate 200 may include a system-on-integrated packaging substrate (SoIS) including a redistribution layer and / or dielectric interlayer, and at least one embedded interposer (such as a silicon interposer). Such a system-on-integrated packaging substrate may include layer-to-layer interconnects using solder material portions, microbumps, underfill material portions (such as molded underfill material portions), and / or adhesive films. Although this disclosure uses substrate packaging to describe the process, it should be understood that the scope of this disclosure is not limited to any particular type of substrate packaging and may include SoIS. The core substrate 210 may include a glass epoxy plate including an array of through-holes. An array of through-core via structures 214 containing metallic material may be disposed in the through-holes. Each through-core via structure 214 may or may not include a cylindrical hollow. Alternatively, a dielectric liner 212 can be used to electrically isolate the through-core via structure 214 from the core substrate 210.

[0106] The packaging substrate 200 may include a board-side surface laminate (SLC) 240 and a chip-side surface laminate (SLC) 260. The board-side SLC may include a board-side insulating layer 242 embedding board-side wiring interconnects 244. The chip-side SLC 260 may include a chip-side insulating layer 262 embedding chip-side wiring interconnects 264. The board-side insulating layer 242 and the chip-side insulating layer 262 may contain a photosensitive epoxy resin material, which may be patterned by photolithography and subsequently cured. The board-side wiring interconnects 244 and the chip-side wiring interconnects 264 may contain copper, which may be deposited within the patterns in the board-side insulating layer 242 or the chip-side insulating layer 262 by electroplating.

[0107] In one embodiment, the package substrate 200 includes chip-side surface-mount layered circuitry 260, which includes chip-side wiring interconnects 264 connected to an array of chip-side bonding pads 268, the array of chip-side bonding pads 268 being bondable to an array of second solder material portions 290, and board-side surface-mount layered circuitry 240, which includes board-side wiring interconnects 244 connected to an array of board-side bonding pads 248. The board-side bonding pads 248 array is configured to allow bonding via solder balls. The chip-side bonding pads 268 array may be configured to allow bonding via C4 solder balls. Generally, any type of package substrate 200 can be used. While this disclosure uses embodiments of the package substrate 200 including chip-side surface-mount layered circuitry 260 and board-side surface-mount layered circuitry 240 for description, embodiments in which one of the chip-side surface-mount layered circuitry 260 and board-side surface-mount layered circuitry 240 is omitted or replaced by, for example, an array of bonding structures of microbumps. In an illustrative example, the chip-side surface layered circuitry 260 can be replaced by an array of microbumps or any other array of bonding structures.

[0108] A semiconductor package 800, including an electromagnetic interference shielding film 810, may be disposed on a package substrate 200, having an array of second solder material portions 290 therebetween. In embodiments where the second solder material portions 290 are formed on bump structures 928 of the semiconductor package 800, the second solder material portions 290 may be disposed on chip-side bonding pads 268 of the package substrate 200. A reflow process may be performed to reflow the second solder material portions 290, thereby inducing bonding between the semiconductor package 800 and the package substrate 200. Each second solder material portion 290 may be bonded to one of the bump structures 928 and one of the chip-side bonding pads 268, respectively. In one embodiment, the second solder material portion 290 may include C4 solder balls, and the semiconductor package 800 may be attached to the package substrate 200 via an array of C4 solder balls. Generally, the semiconductor package 800 may be bonded to the package substrate 200 such that an interposer 900 is bonded to the package substrate 200 via an array of solder material portions (e.g., the second solder material portions 290).

[0109] A second underfill material portion 292 can be formed around the second solder material portion 290 by applying and shaping a second underfill material. The second underfill material portion 292 can be formed by injecting the second underfill material around the array of second solder material portions 290 after reflow of the second solder material portion 290. Any known underfill material application method can be used, such as capillary underfill, molding underfill, or printing underfill.

[0110] A second underfill material portion 292 may be formed between the interposer layer 900 and the package substrate 200. The second underfill material portion 292 may contact each second solder material portion 290 (which may be a C4 solder ball or a C2 solder cap) and may contact the vertical sidewall of the semiconductor package 800. The second underfill material portion laterally surrounds and contacts the array of second solder material portions 290 and the semiconductor package 800.

[0111] In one embodiment, the semiconductor package 800 includes a molded compound die frame 910 that laterally surrounds at least one semiconductor die (701, 703) and contacts a peripheral portion of the top surface of the interposer 900. A second underfill material portion 292 may be formed directly on the sidewall of the molded compound die frame 910.

[0112] Generally, an assembly (e.g., semiconductor package 800) is provided, comprising an interposer 900 and a semiconductor die (701, 703). The assembly may be attached to the package substrate 200 using an array of solder material portions (e.g., a second solder material portion 290).

[0113] Reference Figure 14 The capping structure 880 can be attached to the encapsulation substrate 200 using an adhesive layer 881. The capping structure 880 may include a horizontal cover plate and four sidewalls extending downward from the periphery of the horizontal cover plate. The bottom surface of the horizontal cover plate can be attached to the top surface of the horizontally extending portion of the electromagnetic interference shielding film 810 via a thermal interface material (TIM) layer 882. In one embodiment, the TIM layer 882 may have a thermal conductivity greater than about 2 W / m⋅K, and / or greater than 10 W / m⋅K, and / or greater than 50 W / m⋅K.

[0114] Reference Figure 15 A printed circuit board (PCB) 100 is provided, comprising a PCB substrate 110 and PCB bonding pads 180. The PCB 100 includes printed circuitry (not shown) located on at least one side of the PCB substrate 110. An array of solder joints 190 can be formed to bond an array of board-side bonding pads 248 to the array of PCB bonding pads 180. The solder joints 190 are formed by distributing an array of solder balls between the array of board-side bonding pads 248 and the array of PCB bonding pads 180, and reflowing the solder ball array. Underfill material portions 192 can be formed around the solder joints 190 by applying and shaping an underfill material. A package substrate 200 is attached to the PCB 100 via the array of solder joints 190.

[0115] Figure 16 This is a first flowchart illustrating the steps of forming an electromagnetic shielding film 810 on a semiconductor package 800 according to an embodiment of the present disclosure.

[0116] Refer to step 1610 and Figure 1A-11EThe semiconductor package 800 can be positioned on the package tray 600. The package tray 600 includes a tray base portion 60B extending laterally below the semiconductor package 800, a tray platform portion 60M projecting upward from the tray base portion 60B and including a set of continuous platform sidewalls 60MS, and a bracket-shaped support portion 60S including a set of continuous support outer sidewalls 60SO, the support outer sidewalls 60SO being laterally offset inward from the package area PA defined by all the sidewall groups of the semiconductor package 800 in a plan view.

[0117] Refer to step 1620 and Figure 12A-15 Electromagnetic interference (EMI) shielding film 810 can be deposited anisotropically on all sidewall groups and the top surface of semiconductor package 800.

[0118] Figure 17 This is a second flowchart illustrating the steps of forming an electromagnetic shielding film 810 on a semiconductor package 800 according to an embodiment of the present disclosure.

[0119] Refer to step 1710 and Figure 1A-11E The semiconductor package 800 can be disposed on the package tray 600. The package tray 600 includes a tray base portion 60B extending laterally below the semiconductor package 800, a tray platform portion 60M protruding upward from the tray base portion 60B and laterally surrounding the recessed region RR, and a bracket-shaped support portion 60S located within the recessed region RR and protruding upward from the tray base portion 60B.

[0120] Refer to step 1720 and Figure 12A-15 Electromagnetic interference (EMI) shielding film 810 can be deposited on all sidewall groups and the top surface of semiconductor package 800.

[0121] The embodiments disclosed herein prevent contamination of the back side of the solder material portion 290 during the deposition of the electromagnetic interference shielding film 810, thereby avoiding short circuits and device malfunctions. The package tray 600 of this disclosure is configured to prevent the solder material portion 290 from being exposed to reactive gases during the formation of the electromagnetic interference shielding film 810. Therefore, the electromagnetic interference shielding film 810 is not formed on the solder material portion 290 or on the central surface segment surrounding the array of solder material portions 290 in the bottom surface of the semiconductor package 800.

[0122] Furthermore, the embodiments disclosed herein prevent the formation of a continuous electromagnetic interference (EMI) film between the semiconductor package 800 and the package tray 600. Therefore, burrs can be avoided around the interface between the semiconductor package 800 and the package tray 600, and failures can be avoided when picking up the semiconductor package 800 with the EMI shielding film 810. In other words, since no burrs are formed around the interface between the semiconductor package 800 and the package tray 600, errors can be avoided during the post-processing of the semiconductor package 800 after the formation of the EMI shielding film 810. Specifically, each support-shaped portion 60S may be laterally recessed inward from the sidewall of the upper semiconductor package 800 by a first lateral distance ld1 to avoid the formation of a continuous EMI film between the semiconductor package 800 and the package tray 600, or to minimize the thickness of the continuous EMI film around each interface between the semiconductor package 800 and the package tray 600 to a thickness typically less than 0.1 micrometers, and preferably less than 50 nanometers.

[0123] The embodiments disclosed herein provide complete coating of the entire area of ​​all sidewalls of the semiconductor package 800. This feature enhances shielding performance and provides improved protection against electromagnetic interference by ensuring that the electromagnetic interference shielding film 810 covers the entire area of ​​all sidewalls of the semiconductor package 800, preventing a reduction in electromagnetic interference shielding effectiveness.

[0124] The method for manufacturing a semiconductor device structure according to an embodiment of the present invention includes the following steps: A semiconductor package is disposed on a package tray, wherein the package tray includes a tray base portion, a tray platform portion, and a support-like portion. The tray base portion extends laterally below the semiconductor package. The tray platform portion projects upward from the tray base portion and includes a continuous platform sidewall assembly. The support-like portion includes a continuous support outer sidewall assembly. In a plan view, the support outer sidewalls are laterally offset inward relative to the package area defined by all the sidewalls of the semiconductor package. An electromagnetic interference (EMI) shielding films are anisotropically deposited on all the sidewall assemblies of the semiconductor package and on the top surface of the semiconductor package.

[0125] In some embodiments, wherein: the semiconductor package includes a bump structure array; and the method includes attaching a portion array of solder material to the bump structure array before positioning the semiconductor package in the package tray.

[0126] In some embodiments, wherein: the bracket-shaped support portion includes a continuous set of inner sidewalls of the support portion, which, in a plan view, are laterally offset inward relative to the continuous set of outer sidewalls of the support portion; and in a plan view, the solder material portion array is entirely located within the area defined by the continuous set of inner sidewalls of the support portion.

[0127] In some embodiments, the solder material array does not directly contact any surface of the packaging tray.

[0128] In some embodiments, when the semiconductor package is disposed on the package tray, the bracket-shaped support portion laterally surrounds the entire array of solder material portions.

[0129] In some embodiments, wherein: the bracket-shaped support portion includes a bracket-shaped planar top surface; and when the semiconductor package is disposed on the package tray, the entire bracket-shaped planar top surface is in contact with the bracket-shaped bottom surface segment of the semiconductor package.

[0130] In some embodiments, wherein: when the semiconductor package is disposed on the package tray, the solder material portion array is perpendicularly spaced from the tray base portion; and the entire solder material portion array is located below a horizontal plane including the entire contact area between the semiconductor package and the package tray.

[0131] In some embodiments, wherein: in a plan view, a continuous set of sidewalls of the tray platform portion defines a tray recessed region; and in a plan view, the entire periphery of the tray recessed region is laterally offset outward relative to the periphery of the packaging region.

[0132] In some embodiments, the bracket-shaped support portion includes a bracket-shaped planar top surface, which is located on the same horizontal plane as the top surface of the tray table portion.

[0133] In some embodiments, wherein: when the semiconductor package is disposed on the package tray, the semiconductor package contacts the bracket-shaped support portion; and when the semiconductor package is disposed on the package tray, the semiconductor package does not contact the tray base portion or the tray platform portion.

[0134] The method for manufacturing a semiconductor device structure according to an embodiment of the present invention includes the following steps: A semiconductor package is disposed on a package tray, wherein the package tray includes a tray base portion, a tray platform portion, and a support-like portion. The tray base portion extends laterally below the semiconductor package, the tray platform portion protrudes upward from the tray base portion and laterally surrounds a recessed area, and the support-like portion is located within the recessed area and protrudes upward from the tray base portion. Anisotropic electromagnetic interference (EMI) shielding films are deposited on all sidewall assemblies of the semiconductor package and on the top surface of the semiconductor package.

[0135] In some embodiments, the semiconductor package is in direct contact with the package tray only at the top surface of the bracket-shaped plane of the bracket-shaped support portion of the package tray.

[0136] In some embodiments, the contact between the semiconductor package and the top surface of the bracket-shaped plane of the bracket-shaped support portion of the package tray provides a seal to prevent gas from diffusing between a first space in the recessed region that is laterally surrounded by the bracket-shaped support portion and a second space in the recessed region that is located outside the bracket-shaped support portion.

[0137] In some embodiments, the method further includes configuring the packaging tray in a cavity, wherein: the semiconductor package is configured on the packaging tray before or after the packaging tray is configured in the cavity; and the EMI shielding film is anisotropically deposited by the inflow of a reactive gas into the cavity, such that the top surface and sidewalls of the semiconductor package are exposed to a first environment containing the reactive gas, while the central region of the bottom surface of the semiconductor package is exposed to a vacuum environment free of the reactive gas.

[0138] In some embodiments, during the deposition of the EMI shielding film, a peripheral support-shaped surface segment of the bottom surface of the semiconductor package is exposed to the first environment.

[0139] The deposition apparatus of this invention includes a cavity, a packaging tray, a vacuum pump, and a reactive gas supply manifold. The packaging tray is configured to mount at least one semiconductor package thereon. The packaging tray includes a tray base portion, a tray platform portion, and at least one support bracket portion. The tray base portion projects upward from the tray base portion and laterally surrounds at least one recessed region. Each of the at least one support bracket portions is located within a respective recessed region selected from the at least one recessed region and projects upward from the tray base portion. The vacuum pump is connected to the exhaust region of the cavity. The reactive gas supply manifold is configured to supply reactive gas to the gas inlet side of the cavity and provide a reaction region within the cavity.

[0140] In some embodiments, each of the at least one bracket-shaped support portion includes a respective bracket-shaped planar top surface, the bracket-shaped planar top surface being located in a horizontal plane including the top surface of the tray table portion.

[0141] In some embodiments, the reactive gas includes a precursor gas for depositing an electromagnetic interference (EMI) shielding film.

[0142] In some embodiments, each of the at least one support portion is configured to divide its respective recessed region into a first space and a second space when a semiconductor package is placed thereon; the first space is laterally surrounded by the respective support portion and excluded from the reaction region; and the second space is located entirely outside the respective support portion and is part of the reaction region.

[0143] In some embodiments, a vacuum manifold is also included, which includes at least one opening in the tray base portion and connects each first space of the at least one recessed region to the vacuum pump or another vacuum pump.

[0144] The features of several embodiments have been summarized above to enable those skilled in the art to better understand the nature of this disclosure. Each embodiment described using the term "comprising" also inherently discloses that the term "comprising" may be replaced in some embodiments with "substantially constitutes" or "consisting of," unless otherwise explicitly disclosed herein. Whenever two or more elements are listed as alternatives in the same or different paragraphs, it may also imply a disclosure comprising a list of two or more elements. Whenever the auxiliary verb "may" is used in this disclosure to describe the execution of an element's formation or processing step, embodiments in which the element or processing step is not performed are also explicitly considered, provided that the resulting apparatus or device provides an equivalent result. Therefore, when applied to the execution of an element's formation or processing step, the auxiliary verb "may" should also be interpreted as "may" or "may, or may not," provided that omitting the formation of the element or processing step provides the same or equivalent result, including slightly better and slightly worse results. Those skilled in the art will understand that this disclosure can be used as a basis for designing or modifying other programs and structures to achieve the same purpose and / or attain one of the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions should not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor device structure, characterized in that, include: A semiconductor package is disposed on a package tray, wherein the package tray includes a tray base portion, a tray platform portion, and a bracket-shaped support portion. The tray base portion extends laterally below the semiconductor package. The tray platform portion projects upward from the tray base portion and includes a continuous platform portion sidewall assembly. The bracket-shaped support portion includes a continuous support portion outer sidewall assembly. In a plan view, the support portion outer sidewalls are laterally offset inward relative to the package area defined by all the sidewalls of the semiconductor package. as well as Electromagnetic interference shielding films are deposited anisotropically on all sidewall assemblies and the top surface of the semiconductor package.

2. The method according to claim 1, characterized in that, in: The semiconductor package includes a bump structure array; and The method includes attaching a partial array of solder material to the bump structure array before positioning the semiconductor package in the package tray.

3. The method according to claim 2, characterized in that, in: The bracket-shaped support portion includes a continuous inner wall group of the support portion. In the plan view, the inner wall of the support portion is laterally offset inward relative to the continuous outer wall group of the support portion. as well as In the plan view, the solder material partial array is entirely located within the area defined by the continuous inner sidewall assembly of the support portion.

4. The method according to claim 2, characterized in that, The solder material array therein does not directly contact any surface of the packaging tray.

5. The method according to claim 1, characterized in that, in: In the plan view, the continuous set of sidewalls of the pallet platform portion defines the pallet recess area; and In the plan view, the entire periphery of the tray recessed area is laterally offset outward relative to the periphery of the packaging area.

6. The method according to claim 1, characterized in that, in: When the semiconductor package is positioned on the package tray, the semiconductor package contacts the bracket-shaped support portion; as well as When the semiconductor package is positioned on the package tray, the semiconductor package does not contact the tray base portion or the tray platform portion.

7. A method for manufacturing a semiconductor device structure, characterized in that, include: A semiconductor package is disposed on a package tray, wherein the package tray includes a tray base portion, a tray platform portion and a bracket-shaped support portion, the tray base portion extends laterally below the semiconductor package, the tray platform portion protrudes upward from the tray base portion and laterally surrounds a recessed area, and the bracket-shaped support portion is located within the recessed area and protrudes upward from the tray base portion; as well as Electromagnetic interference shielding films are deposited anisotropically on all sidewall assemblies and the top surface of the semiconductor package.

8. The method according to claim 7, characterized in that, The semiconductor package is in direct contact with the package tray only at the top surface of the bracket-shaped plane of the bracket-shaped support portion of the package tray.

9. A deposition apparatus, characterized in that, include: cavity; A packaging tray configured to mount at least one semiconductor package thereon, wherein the packaging tray includes a tray base portion, a tray platform portion and at least one bracket-shaped support portion, the tray base portion projecting upward from the tray base portion and laterally surrounding at least one recessed region, each of the at least one bracket-shaped support portions being located within a respective recessed region selected from the at least one recessed region and projecting upward from the tray base portion. A vacuum pump is connected to the exhaust zone of the cavity; as well as A reaction gas supply manifold is configured to supply reaction gas to the gas inlet side of the cavity and to provide a reaction zone within the cavity.

10. The deposition apparatus according to claim 9, characterized in that, Each of the at least one bracket-shaped support portion includes a respective bracket-shaped planar top surface, which lies in a horizontal plane including the top surface of the tray table portion.

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