Integrated circuit with memory and shared write port

Abstract

In one embodiment, a semiconductor package is provided that includes a memory wafer and an application wafer that are bonded together to create a system for data processing and memory storage. The memory die hosts a plurality of module groups, each module group having several modules, sharing write ports and independent read ports to allow concurrent read operations. An application wafer operatively in communication with the memory wafer may include various processing units, such as an FPGA core, a GPU, a CPU, and a neural network accelerator. The two wafers may have co-extensive outer peripheries, supporting configurations such as rectangular, square, and circular shapes, and providing large memory capacity. The package may use bumpless bonding techniques to reduce thermal resistance and resistance, and incorporate through-silicon vias (TSVs) for robust interconnects.

Description

Cross-reference to related applications

[0001] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 518,988, filed August 11, 2023, entitled “INTEGRATED CIRCUIT HAVINGMEMORIES AND A SHARED WRITE PORT”, the entire contents of which are incorporated herein by reference.

[0002] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 602,733, filed November 27, 2023, entitled “METHOD AND SYSTEM FORKNOWN-GOOD-DIE TESTABILITY OF FACE-TO-FACE BONDED CHIPLETS”, the entire contents of which are incorporated herein by reference.

[0003] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 602,737, filed November 27, 2023, entitled “SYSTEM AND METHOD FORHAVING CORRECT-BY-CONSTRUCTION TIMING CLOSURE”, the entire contents of which are incorporated herein by reference.

[0004] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 567,649, filed March 20, 2024, entitled “ASSEMBLY HAVING A FACE-TO-FACE BONDED CHIPLET”, which is incorporated herein by reference in its entirety.

[0005] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 637,742, filed April 23, 2024, entitled “INTEGRATED CIRCUIT HAVINGMICROVAULT MEMORIES”, identified by Case No. P24-081-US-PSP, the entire contents of which are incorporated herein by reference.

[0006] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 637,764, filed April 23, 2024, entitled “FEFET STRUCTURES ON INTEGRATED CIRCUITS”, identified by Case No. P24-082-US-PSP, the entire contents of which are incorporated herein by reference.

[0007] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 674,471, filed July 23, 2024, entitled “SYSTEM, METHOD, ANDAPPARATUS FOR WAFER-SCALE MEMORY”, the entire contents of which are incorporated herein by reference. Technical Field

[0008] This disclosure relates to integrated circuits. More specifically, this disclosure relates to integrated circuits having multiple modules, each module having a separate read address space and a shared write address space. Background Technology

[0009] A chiplet is a tiny chip designed to function as a single entity when using advanced packaging techniques. These miniaturized chips are created by dividing a larger chip into several smaller chips, each with its own function or capability. The concept originated from the semiconductor industry's need to overcome the physical limitations of traditional monolithic chip designs and achieve higher levels of integration. The idea behind chiplets is to create modular systems composed of interconnected and interchangeable chips that can be combined in different configurations to create advanced computing systems with improved performance, power efficiency, and functionality.

[0010] Chiplets can be based on different architectures, such as CPUs, GPUs, memory, or I / O, and can be assembled and stacked in various ways depending on specific application requirements. One advantage of the chiplet approach is its ability to mix and match different chiplets from different manufacturers to create custom solutions that meet specific computing needs. This approach also allows for faster time-to-market, reduced development costs, and increased flexibility, as chiplets can be upgraded or replaced without requiring a complete system redesign.

[0011] Chipsets can be used across a variety of industries, including consumer electronics, cloud computing, and data centers, where there is a high demand for high-performance computing and energy efficiency. Chipsets are expected to play a significant role in the future of computing and can unlock new possibilities for creating more powerful and / or more complex electronic devices. Summary of the Invention

[0012] This document discloses integrated circuits, which can be part of a semiconductor device. Methods of manufacturing these circuits, or methods of writing and reading data into and from the circuit, are disclosed herein and can be used in all the examples, embodiments, and aspects described herein.

[0013] In one general aspect, the integrated circuit may include a group of modules having multiple modules, including a first module and a second module. The integrated circuit may also include a shared write port configured to write to the group of modules. The integrated circuit may also include a first read port configured to read from the first module. The integrated circuit may additionally include a second read port configured to read from the second module.

[0014] The implementation may include one or more of the following features. The integrated circuit may have a first read port and a second read port, the first and second read ports being configured to be inactive when a write operation is applied to a shared write port. The integrated circuit may be disposed on a first semiconductor device and may include: a shared write peripheral configured to write to a group of modules via the shared write port, the shared write peripheral being disposed on a silicon substrate of the first semiconductor device; a first read peripheral configured to read a first module via the first read port, wherein the first read peripheral is disposed on the silicon substrate of the first semiconductor device; and a second read peripheral configured to read a second module via the second read port, wherein the second read peripheral is disposed on the silicon substrate of the first semiconductor device, wherein the first module and the second module are disposed on a second layer of the first semiconductor device.

[0015] The integrated circuit can be configured such that the first module is a three-dimensional column of memory bit cells disposed between a first surface of the first semiconductor device and a silicon substrate of the first semiconductor device. The integrated circuit may have a first read port configured to electrically communicate with a second semiconductor device, and / or the second semiconductor device may be configured to be fixed to the first surface of the first semiconductor device.

[0016] One or more interposers may be disposed between a first surface of a first semiconductor device and a second semiconductor device. A first read port may include a read address bus that passes through a second layer of the first semiconductor device. A first read port may include a read data bus that passes through the second layer of the first semiconductor device. A shared write port may be configured to electrically communicate with the second semiconductor device. The second semiconductor device may be configured to be fixed to the first surface of the first semiconductor device. An integrated circuit may include an electrical connection interposer disposed between the first surface of the first semiconductor device and the second semiconductor device. The shared write port may include a write address bus that passes through the second layer of the first semiconductor device. The shared write port may include a write data bus that passes through the second layer of the first semiconductor device.

[0017] The first read port and the second read port can be configured to process reads concurrently with each other. A shared write port can be configured to write to an address space. The shared write port can be configured to write to a first module via a first portion of the address space and to a second module via a second portion of the address space. Each of the multiple modules can include an independent read port for concurrent reading via a corresponding independent read port of any of the multiple modules, wherein the first read port is configured to read from the first module concurrently with another read to the second module using the second read port. A group of modules can be configured to have a single write address space, which is configured to write to multiple modules. The first read port can be configured to have a first read address space, and the second read port is configured to have a second read address space. The first read address space may numerically overlap with the second read address space. The first read address space may coextensively overlap with the second read address space and / or be contiguous with the second read address space.

[0018] Module groups can be formed on a second-layer portion of an integrated circuit device. The integrated circuit can be implemented as a chiplet, which is configured to be face-to-face bonded. The chiplet may include multiple input / output (I / O) bonds, each of which is configured to provide a corresponding read port to a corresponding module in the plurality of modules, and each of which is configured to interface with a complementary corresponding input / output (I / O) bond of a second device to which the chiplet is bonded.

[0019] Integrated circuits can be part of semiconductor devices. Semiconductor devices can be implemented as dies, wafers, or chiplets and can be bonded to second semiconductor devices, such as GPUs (Graphics Processing Units), SoCs (System-on-a-Chip), and GPPUs (General Purpose Processing Units).

[0020] The second semiconductor device can be implemented as a chip die, wafer, ASIC (Application-Specific Integrated Circuit), and FPGA (Field-Programmable Gate Array). The semiconductor device may include multiple input / output (I / O) bonds, each of which is configured to provide a corresponding read port to a corresponding module among multiple modules, and each of the multiple I / O bonds is configured to be electrically connected to a complementary corresponding input / output (I / O) bond of the second semiconductor device.

[0021] The chiplet die has a first side and a second side, wherein the second side is configured to be face-to-face bonded to a second semiconductor device. The chiplet die and the second semiconductor device may be part of a multi-chip package. The semiconductor device may include an electrical connection medium disposed between the chiplet die and the second semiconductor device. A first read port may be disposed on the chiplet die. The chiplet die has a surface, and the first module may include: a memory array having a plurality of memory units arranged within the first module; and read peripheral circuitry configured to read data stored in the memory array via the first read port.

[0022] Footprint is the space on a surface that a device can project onto (e.g., how much xy space the device occupies, whether it extends into a third dimension (e.g., the z-axis)). The footprint of the read peripheral circuitry on the surface may overlap with the footprint of the memory array on the surface. Multiple memory units can be arranged in a three-dimensional configuration. The footprint of the first read port on the surface may overlap with the footprint of the memory array on the surface. The footprint of the read peripheral circuitry on the surface may coexist with the footprint of the memory array on the surface. The footprint of the first read port on the surface may coexist with the footprint of the memory array on the surface. The memory array, read peripheral circuitry, and first read port can be stacked vertically and configured to minimize the module footprint on the surface of the die.

[0023] In some aspects, the write peripheral circuitry can be connected to a shared write port on the surface of the chip die, such that: the write peripheral circuitry defines a first footprint on the surface, wherein the first footprint does not overlap with the footprint of the memory array, nor with the footprint of the first read port, and the shared write port defines a second footprint on the surface, wherein the second footprint does not overlap with the footprint of the memory array, nor with the footprint of the first read port. In some aspects, the first footprint may overlap with the second footprint.

[0024] Multiple memory units can be formed from at least one non-volatile memory unit. These memory units can include various materials, such as ferroelectric materials, magnetic materials, spin-orbit torque materials, spin-transfer torque materials, phase-change materials, and / or antiferroelectric materials. One implementation may include organizing multiple modules into separate partitions, each partition having a dedicated read peripheral, wherein each dedicated read peripheral has an independent clock. Alternatively, each module may have its own dedicated read peripheral. During a reset, the module group can be configured to process only write commands and disable read capabilities. Conversely, when the module group is not in a reset, write capabilities can be disabled. The module group may include at least two different non-volatile memory technologies.

[0025] One implementation may include an integrated circuit with dynamic allocation circuitry to allocate memory blocks to multiple modules based on the use of module groups. Furthermore, the integrated circuit may include a write peripheral connected to dedicated I / O pads, enabling data transfer outside the integrated circuit. The integrated circuit may be formed on a silicon substrate via an additive manufacturing process and may be electrically connected to a second semiconductor device having another integrated circuit.

[0026] The integrated circuit may include a read peripheral for at least one of a plurality of modules, the read peripheral being disposed on a silicon substrate or a second semiconductor device. The second semiconductor device may be implemented as a system-on-a-chip (SoC), a chiplet die, a wafer, an ASIC, or an FPGA.

[0027] In one implementation, multiple modules are formed from non-volatile memory units arranged in a three-dimensional connectivity architecture perpendicular to the silicon substrate and a second semiconductor device, and may utilize at least one of the following: cross-connect, 3D NAND, 3D NOR, 3D AND, and stacked planar layers. The integrated circuit may include a single write peripheral with a dedicated clock or multiple clocks fed to the respective modules in a decoupled timing sequence relative to other modules. Each of the multiple clocks is configured to clock a corresponding read port of the respective module among the multiple modules.

[0028] Another implementation may include a module group formed on a chiplet having a first side and a second side, the second side being configured for bonding to a second semiconductor device. The integrated circuit may also include decoder circuitry, driver circuitry, and register circuitry on the silicon substrate of the chiplet. Alternatively, the module group may be formed on a second layer of the chiplet. The second semiconductor device may have multiple processing elements, wherein when the second semiconductor device is bonded to the chiplet, each processing element includes a corresponding interface for communicating with a corresponding module among the multiple modules on the module group. The chiplet may also have an interface on its second side to a shared write port, thereby interfacing with a complementary interface on the second semiconductor device.

[0029] The second semiconductor device may have an on-chip network configured to provide inter-element communication to multiple processing elements. These multiple processing elements may include at least one embedded FPGA, or one of a soft processor, DSP block, embedded processor, and microcontroller.

[0030] In another implementation, write operations to the module group are performed via a priority arbitration circuit that facilitates access to modules in a predetermined order. The integrated circuit may include a power gating circuit that selectively powers off modules among multiple modules when not in use. Furthermore, the shared write port can be configured to write to a virtual address space that is mapped to physical memory space.

[0031] The integrated circuit may also include control circuitry configured to enable the shared write port during a write operation and disable the shared write port during a read operation to save power. Alternatively, the control circuitry may disable a first read port during a write operation and enable the first read port during a read operation to save power. A power management module may also be included, which selectively powers down the shared write port during a read operation to save power. The write circuitry may be configured to dynamically transfer power distribution from the write operation to the read operation, or to enter a sleep mode and power down the shared write port during a read operation to save power.

[0032] The non-volatile memory utilized in multiple modules can be selected from the group consisting of: FeFET, FeRAM, ReRAM, SOT (spin-orbit torque), and STT (spin-transfer torque). The write peripheral for the module group can be implemented on the silicon substrate and disposed between the module group and a second side of the chiplet. The read peripheral for the first module can be implemented on the silicon substrate and disposed between the module group and a first side of the chiplet, or alternatively, disposed in a second layer. In some implementations, each module has its own dedicated write peripheral utilizing a shared clock. Attached Figure Description

[0033] These and other aspects will become more apparent from the following detailed description of various embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0034] Figure 1 This is a block diagram of an integrated circuit that may be a part of a semiconductor device such as a chiplet, according to embodiments of this disclosure;

[0035] Figure 2 A perspective view of a component according to an embodiment of the present disclosure is shown, the component having Figure 1 An integrated circuit is implemented on a semiconductor device, which is electrically connected to another device to form the component;

[0036] Figure 3 Illustrations of embodiments according to this disclosure are shown. Figure 1 A block diagram of the memory address space of an integrated circuit;

[0037] Figure 4 Illustrations of embodiments according to this disclosure are shown. Figure 1 A block diagram of the memory address space of an integrated circuit with a signal interface;

[0038] Figure 5 Illustrations show integrated circuits that may be part of a semiconductor device such as a chiplet, according to embodiments of the present disclosure; and

[0039] Figure 6 A perspective view of a component according to an embodiment of the present disclosure is shown, the component having Figure 1 Integrated circuits are implemented on semiconductor devices, which are then electrically connected to the system-on-a-chip. Detailed Implementation

[0040] Figure 1A block diagram of an integrated circuit 100 according to one embodiment of the present disclosure is shown. The integrated circuit 100 can be packaged as a bondable chiplet (e.g., face-to-face chiplet bonding). The integrated circuit (IC) 100 includes a module group 106 comprising modules 108, 110, 112, and 114. The IC 100 also has a shared write port 102 configured to write to the module group 106 using a write peripheral 104. Furthermore, it includes read peripherals 116, 118, 120, and 122 and read ports 124, 126, 128, and 130, which are configured to read from modules 108, 110, 112, and 114. The IC 100 also includes an interlock 132.

[0041] Write port 102 can be configured to provide a single write address space to all module groups 106, where each of modules 108, 110, 112, and 114 has dedicated read ports 124, 126, 128, and 130, respectively. Integrated circuit 100 can be packaged as a portion of a chiplet configured to be electrically connected to another integrated circuit device (e.g., another chiplet, or an IC package, with or without electrical contacts, electrical bumps, etc.). The chiplet can be electrically connected to the other device, including, for example, by bonding, soldering, wafer-to-wafer bonding, face-to-face chiplet bonding, chiplet-to-wafer bonding, chiplet-to-interposer bonding, and / or the chiplets can be connected together using an interposer or other interface technologies. When electrically connecting the chiplet to another device, an interposer may not be used, one interposer may be used, or multiple interposers may be used, or other interface technologies common in heterogeneous 3D system-in-package solutions may be utilized.

[0042] Each read port (124, 126, 128, 130) in the chiplet may have electrical contacts on one or more sides of the chiplet. Read ports 124, 126, 128, 130 may use multi-loop pipeline circuitry. When bonded to another device (e.g., wafer, chiplet, scalar, SOC, package, FPGA, etc.), the electrical contacts may be queued in a manner that provides dedicated access to a specific module among modules 108, 110, 112, 114. For example, a processing / computing element may exclusively access module 108 via read port 124, and module 108 may contain neural network weights in its registers. Similarly, different processing / computing elements may exclusively access module 110 via read port 126, and module 110 includes different registers. In this particular embodiment, the arrangement of the electrical contacts ensures that each computing / processing element has dedicated access required to efficiently perform its specific computations, thereby providing a compact, modular, and scalable system that allows different processing elements to maintain dedicated access to specific modules 108, 110, 112, and 114. Without dedicated access, different processing elements might have to queue to use the same resources, which would slow down overall processing speed. By providing dedicated access, the proposed chiplet ensures that each processing element can operate at its maximum capacity without interference from other computing elements in this particular embodiment.

[0043] The write peripheral 104 is a peripheral circuit device responsible for processing data and writing data to memory cells located within modules 108, 110, 112, and 114. The write peripheral 104 may include dedicated contacts that allow a chip electrically connected (e.g., bonded) to a chiplet of the integrated circuit to access the write port 102 via a shared write logic system. This system involves utilizing a shift register-based design with different voltages, preferably a high-voltage design, having shared write address and data components. This shared write logic system is designed to be accessed via a bonded chiplet, another bonded chiplet, and / or via other circuit devices within the same package as integrated circuit 100. The shift register allows the system to move data through a series of stages, where each subsequent stage receives data from the previous stage. By utilizing shift registers, the system can increase data throughput while maintaining a low data transfer rate. The shared write address space refers to the location in the chiplet where data is written.

[0044] In another embodiment, interlock 132 can disable read ports 124, 126, 128, and 130 while data is being written to module group 106 via write port 102. Similarly, interlock 132 can disable write port 102 while read operations are being performed on read ports 124, 126, 128, and 130. The written data can then be accessed concurrently by all processing elements that need to read data via the corresponding read port among read ports 124, 126, 128, and 130. This ensures that all processing elements have their most frequently used data available, regardless of other reads performed concurrently by other processing elements.

[0045] The write peripheral 104 circuitry includes a write driver. This unit receives data to be written and converts that data into appropriate signals that can change the state of the memory cell. Depending on the type of memory technology used, these signals may involve voltage levels, current pulses, or other types of energy. Due to the specific voltage requirements of the chiplet, shared write logic systems may be high-voltage. The write driver must provide sufficient power to reliably change the state of the memory cell, but it must also operate within appropriate parameters to avoid damage or unnecessary wear.

[0046] The write peripheral 104 circuit can also have a data buffer or a write buffer. This component temporarily stores the data to be written, allowing write operations to be performed at an optimal pace. By balancing the rate at which data enters the memory with the rate at which memory cells can be written, the write buffer helps prevent data loss and optimize system performance.

[0047] In some embodiments, the write peripheral 104 may further include a write control unit that orchestrates the sequence of operations during the write process. It generates control signals to activate the write driver at appropriate times, controls the data flow from the write buffer, and coordinates the timing of the write operations. By synchronizing these various activities, the write control unit ensures efficient and reliable write operations.

[0048] The write peripheral 104 may also include data encoding mechanisms to improve reliability and data integrity. For example, these mechanisms encode the data in a way that allows potential errors to be detected and, in some cases, corrected when the data is read later, before it is written to the memory cell. This can be helpful in systems where data integrity is a higher priority, such as in servers or scientific research equipment.

[0049] The write peripheral 104 may also include a timing unit that acts as the system heartbeat, supplying clock signals to synchronize the operation of various components of the system. In some systems, it may include components such as an oscillator, clock generator, or phase-locked loop. The timing unit ensures that all operations occur at appropriate times relative to each other.

[0050] IC 100 can be implemented as a face-to-face bonded chiplet, wherein modules 108, 110, 112, and 114 are formed from non-volatile memory. In some specific embodiments, IC 100 may also have dynamic allocation circuitry to allocate memory blocks to module group 106 based on usage of the module group 106 (e.g., each module 108, 110, 112, and 114 may include dynamic allocation circuitry for dynamically allocating a series of read locations for the respective processing element).

[0051] IC 100 has multiple clocks, each of which feeds into a corresponding module among the multiple modules, thereby providing decoupled timing for each corresponding module relative to the other modules among the multiple modules. Module group 106 can be arranged in any topology known to those skilled in the art. The bit cell density in module group 106 can be up to 10 times higher than that of embedded SRAM cells.

[0052] IC 100 can be formed on a chiplet, which includes a first side and a second side, wherein the second side is configured for bonding to a second semiconductor device. IC 100 may include high-voltage write logic adjacent to the first side of the chiplet. Decoder circuitry, driver circuitry, and register circuitry can be formed on a silicon substrate portion of the chiplet, while module group 106 is formed on a second layer portion of the chiplet. The second semiconductor device may include a plurality of processing elements. Each processing element includes a corresponding interface for communicating with a corresponding module among the plurality of modules on module group 106 when the second semiconductor device is bonded to the chiplet.

[0053] Silicon substrates have traditionally served as the initial stage in IC manufacturing, focusing on creating active components, particularly transistors. Techniques such as diffusion, ion implantation, oxidation, and material deposition are employed to shape complex transistor structures. These processes operate on a very small scale. The application of photolithography, etching, and implantation techniques enables precise definition of transistor structures. Silicon substrates are used to build the fundamental building blocks within ICs for signal processing, amplification, and control. This layer is sometimes referred to as the "front-end process" ("FEOL").

[0054] Next, a second layer can be added in the manufacturing process. This second layer traditionally serves the role of interconnect fabrication, facilitating electrical connections between various IC components. This level traditionally focuses on the creation of passive components, including interconnects, vias, and metal-insulator-metal (MIM) capacitors. The second-layer process typically differs from the process used on the silicon substrate in terms of precision and scale. Interconnects are formed by depositing and patterning metal layers (typically aluminum or copper) to build a wiring network. Dielectric layers, such as silicon dioxide or low-k dielectrics, are introduced to insulate the interconnects and prevent signal interference between different wiring layers. The traditional function of the second layer is to establish the necessary interconnects, enabling the routing and distribution of electrical signals throughout the IC. However, as discussed herein, circuitry can be used within this second layer (sometimes referred to as the “back-end process” or “BEOL”).

[0055] Alternative embodiments of IC 100 can be implemented as stacked dies, a monolithic design, a TSV, or a through-silicon via (TSV). In a stacked die design, several dies can be stacked on top of each other, with each die performing different functions, such as memory and processing. Stacked dies can communicate via wire bonding, microbumps, or bumpless bonding. In a monolithic design, various functions and modules of IC 100 can be integrated onto a single die, resulting in a more compact and power-efficient design.

[0056] In addition, IC 100 may include one or more interlocks 132 to manage conflicts during data read and write operations. Module group 106 may be formed from various non-volatile or semi-volatile (e.g., extremely long refresh periods) memory technologies, such as static random access memory (SRAM), ferroelectric field-effect transistor (FeFET), ferroelectric random access memory (FeRAM), resistive random access memory (ReRAM), spin-orbit torque (SOT) memory, spin-transfer torque (STT) memory, charge traps, floating gate memory, and / or Schottky diodes.

[0057] Module group 106 may utilize a static random access memory (SRAM) topology. The SRAM topology may employ a cross-coupled flip-flop structure (e.g., latch flip-flops) to ensure that the stored data remains intact as long as power is supplied. Therefore, in some specific embodiments, module group 106 may utilize heterogeneous types of memory, including volatile and non-volatile memory types.

[0058] Module group 106 can utilize a flash memory topology. Flash memory is a non-volatile memory technology used in applications requiring data persistence, such as solid-state drives (SSDs) and USB flash drives. The flash memory topology disclosed herein has a matrix of memory cells, each memory cell including a floating-gate transistor or a charge trapping device. Module group 106 can also use wear leveling techniques to extend the lifetime of the memory cells.

[0059] Module group 106 may utilize a ferroelectric random access memory (FeRAM) topology. FeRAM topology utilizes ferroelectric materials capable of maintaining polarization states. In a particular embodiment, such a memory topology may utilize FeFETs to retain state information and program the ferroelectric material. These ferroelectric materials can be used to retain state information and act as memory bit cells.

[0060] Module group 106 can utilize phase change memory (PCM) topology, which is a non-volatile memory technology that uses reversible phase changes in materials to store data. PCM topology can include any phase change material, such as chalcogenide alloys or chalcogenide glasses housed in memory cells.

[0061] Module 106 can utilize a resistive random access memory (ReRAM) topology, which is a non-volatile memory technology based on the resistance switching phenomenon. The ReRAM topology can utilize thin film materials that exhibit reversible resistance changes when an electrical excitation is applied.

[0062] Module group 106 can utilize a spin-orbit torque (SOT) magnetic random access memory (MRAM) topology. SOT-MRAM is a non-volatile memory that uses spin-orbit torque to switch the magnetic state of storage elements. The SOT-MRAM topology can be incorporated into a magnetic tunnel junction (MTJ) structure and utilizes spin-orbit coupling effects for writing and reading data. The MTJ can have a dielectric layer between the magnetically fixed layer and the magnetically free layer. Writing can be accomplished by switching the magnetization of the free magnetic layer by injecting an in-plane current into an adjacent SOT layer. Reading can be accomplished by injecting current into the MTJ. In some specific embodiments, SOT-MRAM can optimize the spin-orbit material by using a current-driven switching scheme while minimizing write power consumption.

[0063] Module group 106 can utilize a spin-transfer torque (STT) magnetic random access memory topology. STT-MRAM is another type of non-volatile memory that relies on spin-transfer torque to manipulate the magnetic state of the storage elements. The STT-MRAM topology can use a magnetic tunnel junction (MTJ) structure, where the magnetization orientation determines the stored data. Furthermore, for example, the orientation of the magnetic layers in the magnetic tunnel junction or spin valve can be changed using spin-polarized current.

[0064] IC 100 may include a single write peripheral 104 with a dedicated clock, or each module 108, 110, 112, 114 may have its own dedicated write peripheral utilizing a shared clock. Figure 1 (Not shown in the image). In addition, module group 106 can be organized into separate partitions, each partition including dedicated read peripherals 116, 118, 120, and 122 with independent clocks.

[0065] Another possible embodiment of IC 100 includes an interface (e.g., the same, different, higher, or lower voltage) to enable data transfer outside the IC 100 package. In other embodiments, IC 100 may also include an integrated microcontroller unit (MCU) or digital signal processor (DSP) for processing data within the IC.

[0066] Figure 2 An embodiment according to this disclosure is shown. Figure 1 The diagram shows a perspective view of component 200 implemented on chiplet 230, where integrated circuit 212 is bonded to second device 226. Integrated circuit 212 is a circuit arrangement within chiplet 230. Second device 226 may be a chiplet, semiconductor wafer, semiconductor package, encapsulated circuit arrangement, etc. For example, second device 226 may be an AI accelerator, such that each processing unit has read access to a module (or a predetermined set) of module group 236. In another embodiment, second device 226 may be a network controller, in which offloading circuitry is present to read data from each module to process incoming / outgoing packets, etc. Component 200 includes module group 236, which has multiple modules, including first module 232 and second module 234. Figure 2 Several modules are shown; however, for clarity, only modules 232 and 234 are indicated by reference numerals. Integrated circuit 212 also includes a shared write port 222. Shared write port 222 is connected to write peripheral 202.

[0067] While the second device 226 can write data to any module within the module group 236 via the address and data buses, using clock and enable signals and the shared write port 222, other methods of writing data can also be considered. For example, serial connections, parallel connections, and various buses or ports can be used, such as DDR (Double Data Rate) interfaces, SRAM (Static Random Access Memory) interfaces, NAND flash memory interfaces, NOR flash memory interfaces, HBM (High Bandwidth Memory) interfaces, GDDR (Gradient Double Data Rate) interfaces, NVMe (Non-Volatile Memory for Graphics) interfaces, SPI, I2C, etc. Each module in the group has a read port with a read address 218 (for sending an address to module 234) and read data 220 (which is data read from chip 232).

[0068] Module group 236 is formed on a chiplet 230 having two sides. Chiplet 230 includes a surface 228, which can be bonded to and is complementary to the second device 226. Chiplet 230 can be formed by forming circuitry on a silicon substrate 204 and then by adding a second layer 206. In other embodiments, these layers can be reversed and / or other layers can be added, removed, etc. Read address 218 and read data 220 are used to read module 232.

[0069] While the second device 226 can read data from module 232 using the clock and enable signals via the address and data buses, other methods of reading data can also be considered. For example, serial connections, parallel connections, and various buses or ports can be used, such as DDR (Double Data Rate) interfaces, SRAM (Static Random Access Memory) interfaces, NAND flash memory interfaces, NOR flash memory interfaces, HBM (High Bandwidth Memory) interfaces, GDDR (Gradient Double Data Rate) interfaces, NVMe (Non-Volatile Memory for Graphics) interfaces, SPI, I2C, etc.

[0070] All read ports (e.g., 218 and 220) are configured to be inactive when a write operation is applied to the shared write port 222. Read ports can also be configured to process reads concurrently with each other. The shared write port 222 is configured to write to the address space, specifically to write to the first module 232 via a first portion of the address space and to the second module 234 via a second portion of the address space. Each module in the plurality of module groups 236 includes an independent read port for concurrent reading via the respective independent read port of any of the plurality of modules.

[0071] Each read port for a given module may include a contact for mating with circuitry found within the second device 226 via metal contacts. Therefore, metal contacts may be present on the top layer 208, configured to mate with metal contacts on the surface 228 of the chiplet 230, allowing for a shared read space with the read spaces of the modules in module group 236. The read spaces of module group 236 may all be shared with each other (as referenced). Figure 3 and Figure 4 (as described).

[0072] In one embodiment, the read peripheral for the first module 232 is implemented on the silicon substrate 204 (sometimes referred to as the front-end process). A second layer 206 (sometimes referred to as the back-end process) can then be built on top of the silicon substrate 204 (and any circuitry) during the manufacturing process and may contain corresponding memory bit cells. In another embodiment, the read peripheral for the first module 232 is implemented in the second layer 206 and is disposed between the module group 236 and the surface 228 of the chiplet 230.

[0073] Module group 236 can be configured to process write commands only during reset. The write command can be a "slow write" command. That is, module group 236 can have a very low write speed relative to its read speed. When module group 236 is used to read data, the write logic can be frozen (or disabled). In some specific embodiments, integrated circuit 212 provides the functionality to allocate memory blocks to module group 236 based on its usage. In other embodiments, the memory addresses, along with the allocation, are fixed. Integrated circuit 212 can be implemented as a face-to-face bonded chiplet 230. Face-to-face bonding can be bumpless wafer bonding.

[0074] Module group 236 may have a single write peripheral 202. In other embodiments, each module of module group 236 may have a dedicated write peripheral utilizing a shared clock. In other embodiments, module group 236 may also be organized into separate partitions, each partition having a dedicated read peripheral, wherein each dedicated read peripheral has an independent clock. A partition may be one, two, or more modules of module group 236.

[0075] The overall architecture of the write peripheral 202 circuitry may include a series of different components, including write drivers, address decoders, sense amplifiers, data input latches, data buses, and / or some combination thereof. Write drivers or write buffers are responsible for transferring data to memory cells. They amplify input signals to achieve a level suitable for the memory cell. Address decoders are used to interpret the memory address fed as input, the address to which data needs to be written. They can be used to select the target memory cell by activating specific rows and columns of the memory array linked to that address. Sense amplifiers are used to identify and amplify signals from memory cells during read operations and also participate in flushing memory cells after a data write operation. Write operations are triggered by a write enable signal. When a write command is initiated, this signal drives the write driver and decoder into the write process. Data input latches can be used as temporary storage units, holding the dataset to be written to memory until the write operation is performed. A data bus with a transmission path can be used to facilitate the movement of data from the data input latches to the memory cells.

[0076] Write operations to module group 236 can be performed via a priority arbitration circuit that facilitates access to modules in a predetermined order, and the shared write port 222 can be configured to write to a virtual address space mapped onto physical memory space. Integrated circuit 212 may include high-voltage write logic used within write peripheral 202, and the second semiconductor device 226 may include multiple processing elements, each including a corresponding interface for communicating with a corresponding module of module group 236. Furthermore, chiplet 230 may include an interface on surface 228 to the shared write port 222 for interfacing with a complementary interface on the second semiconductor device 226.

[0077] Integrated circuit 212 may also include a power gating circuit that selectively shuts off the power of modules in the plurality of module groups 236 when not in use. Furthermore, integrated circuit 212 may have a write peripheral 202 for the module groups 236 connected to dedicated I / O pads to enable external data transfer from the integrated circuit package.

[0078] Integrated circuit 212 may utilize multiple modules of module group 234 that are grouped together. In certain embodiments, these modules may be synchronized with each other. In some cases, all modules are synchronized, while in other instances, only specific modules will be synchronized. For example, when reading data from one module in module group 236, the circuitry on second device 226 may need to be synchronized with that specific module.

[0079] To synchronize the modules, integrated circuit 212 can use various timing techniques. In some cases, multiple clocks can feed each corresponding module of module group 236, thereby allowing each module to have decoupled timing relative to other modules in the group. This decoupling ensures that any delay in one module will not affect the functionality of other modules. It is worth noting that the clocks used may or may not need to be synchronized. In some cases, a common clock can be used to synchronize the modules. In other embodiments, one or more clock signals may be provided by second device 226.

[0080] In alternative embodiments, other synchronization techniques can be used, such as phase comparison of the clock signal or phase-locked loop (PLL) synchronization methods. Another embodiment of the synchronization module in the IC can use delay-locked loop (DLL) synchronization. In this method, a delay element is added to the clock signal path, and the output is compared with the input clock signal. The feedback loop adjusts the delay element until the output of the DLL matches the input, thereby resulting in synchronization of the clock signals.

[0081] In another embodiment, integrated circuit 212 can use a combination of different synchronization techniques to achieve synchronization between modules in module group 236. For example, depending on the specific requirements of the modules, some modules may use PLL synchronization, while others may use clock delay line or DLL synchronization. Furthermore, integrated circuit 212 may also use redundant synchronization techniques to ensure reliability and redundancy in the event of a failure of one method. For example, integrated circuit 212 may use both phase-locked loop (PLL) synchronization and DLL synchronization simultaneously, so that if one method fails, the other method can still maintain synchronization.

[0082] Figure 3 An embodiment according to the present disclosure is illustrated. Figure 1 A block diagram 300 of the memory address space of the integrated circuit is shown. The memory address space includes a write address space 316 and read data address spaces 310, 312, and 314.

[0083] The write address space 316 includes various units that can store data (e.g., weights) and / or instructions. These units are referred to as memory addresses. Module group 302 includes multiple memory modules 304, 306, and 308. The write address space 316 can be distributed among memory modules 304, 306, and 308, such that the write address space 316 spans from 0 to N. M-1. For example... Figure 3 As shown, module group 302 has N memory modules 304, 306, and 308, where N is a positive integer, and each module has a memory size of M. The total number of unique write memory addresses in the write address space will be N. M, the write memory address can range from 0 to N. Integer references of M-1.

[0084] Starting from address 0, the memory addresses written into address space 316 are arranged sequentially up to N. M-1. In other words, the first address is 0, and the last address is N. M-1, covering a total of N There are M addresses. The sorting can be linear (increasing by 1 for each address) or some other specified pattern depending on the implementation.

[0085] Write-to-memory addressing can be implemented in various ways based on the system architecture. One approach used in a particular embodiment is to use a base register and a limit register. The base register holds the minimum legal physical write-to-memory address, and the limit register specifies the size of the range. Therefore, to generate a logical address, you need to add the base address to the relative address. In other embodiments, a memory addressing scheme can be used where the base address is set to 0. Other write-to-memory addressing techniques will be understood by those skilled in the art.

[0086] For any device writing to module group 302, each memory module can have a unique set of write memory addresses, making all memory addresses within module group 302 unique in terms of the data being written. For example, the first module starts at address 0, and the last module starts at address N. The allocation ends at M-1. In some embodiments, the allocation may depend on the memory management system of the device writing data to modules 304, 306, 308, and the allocation ranges from simple fixed partitioning schemes to more complex dynamic partitioning models.

[0087] For example, in a simple linear model where each module (304, 306, or 308) has M addresses of equal size, the first module 304 would have write addresses 0 to M-1, the second module would have write addresses M to 2M-1, and the third module would have write addresses 2M to 3M-1. M-1, and so on. Module N 308 will therefore have (N-1) M to N The write address of M-1.

[0088] It is expected that ordinary technical personnel in related fields can use it from 0 to N Other implementations of the write memory address of M-1 depend on various factors, such as hardware architecture, operating system, memory management scheme, and the nature of the programs running on the system.

[0089] Module group 302 has different read data address spaces 310, 312, and 314. These read address spaces 310, 312, and 314 can be overlapping, contiguous, or shared. Read address spaces 310, 312, and 314 can be independent of each other. The system includes three independent read address spaces, labeled read address spaces 310, 312, and 314. Each of these read address spaces is different from the others, meaning that reads can be performed in each space without affecting the others.

[0090] The read address spaces 310, 312, and 314 can be defined as contiguous blocks of memory addresses, each with its own start and end addresses. Within module group 302, each read address space 310, 312, and 314 can have an address range corresponding to values ​​from 0 to M-1, where M is the maximum value determined by the size of the modules 304, 306, and 308 used.

[0091] In one embodiment, concurrent reads can be implemented as described herein by allowing a processing unit to interface with each read address space 310, 312, 314. The independence of read address spaces 310, 312, 314 ensures that each processing unit can access the data it needs without causing any interference or conflict with other processing units.

[0092] Figure 4 The illustration shows an embodiment according to the present disclosure. Figure 1 A block diagram of the memory address space with signal interfaces in an integrated circuit. Figure 4 The signals used can be used in conjunction with any of the embodiments described herein. However, those skilled in the art will understand that different signaling schemes can be used.

[0093] Module group 402 includes modules 404, 406, and 408 that share a common write peripheral 411. The write peripheral 411 includes a write address bus with the address of the data to be written, a write data bus with the data, and a write clock that causes a write to occur (e.g., on the rising or falling edge of a clock signal). A write occurs only when a write enable signal indicates that a write should occur. Any logic can be used; for example, a high voltage can correspond to 1 and a low voltage can correspond to 0, or vice versa. In some embodiments, the write peripheral 411 may be on chiplet 230, and in other embodiments, the write peripheral 411 may be on a second device 226.

[0094] Module group 402 includes modules 404, 406, and 408, each module having a corresponding read peripheral 410, 412, and 414. Each of the read peripherals 410, 412, and 414 has a read address bus for sending read addresses, a read data bus for receiving data, a read clock for timing the output of digital data, and an output enable as a prerequisite for outputting data. Any logic can be used; for example, a high voltage can correspond to 1 and a low voltage can correspond to 0, and vice versa. In other embodiments, multi-bit or analog data storage can be used. In some embodiments, one or more of the read peripherals 410, 412, and 414 can be on chiplet 230, and in other embodiments, one or more of the read peripherals 410, 412, and 414 are on second device 226.

[0095] Figure 5 An illustration is shown of an integrated circuit 500 that can serve as part of a semiconductor device such as a chiplet, according to one embodiment of the present disclosure. The integrated circuit 500 may be disposed on a semiconductor device (such as a chiplet) having a silicon substrate 506 and a second layer portion 508. Within the integrated circuit 500, an array cross-section forming a module 502 may be present, wherein a three-dimensional column array of memory bit cells 522 has components required for storing memory in a non-volatile, semi-volatile, or other memory format as described herein.

[0096] Even if only a single module 502 is shown, the integrated circuit 500 may also include a group of modules having multiple modules including a first module and a second module, etc. Memory bit cells 522 are written to via shared write ports 512, 516, which include both a write address bus line 512 and a write data bus 516. These buses pass through the second layer 508 and can be connected to a second semiconductor device via an intermediary. The second device has electrical contacts complementary to the electrical contacts on surface 518, allowing it to be electrically coupled to the write address and data buses. Memory bit cells 522 can be read via read ports 524, 526, which include a read address bus line 524 and a read data bus 526. Both of these buses can also pass through the second layer 508 to reach a second semiconductor device coupled to surface 518, which also has complementary electrical contacts to allow it to be electrically coupled to the read address and data buses.

[0097] Various memory technologies can be used for memory bit cells 522, such as a vertically connected architecture structure formed by non-volatile memory unit cells arranged in a three-dimensional column array 522. Memory bit cells 522 can utilize one or more of cross-point, 3D NAND, 3D NOR, 3D AND, and / or stacked planar layers.

[0098] In some embodiments, the integrated circuit 500 is electrically connected to a second semiconductor device ( Figure 5 (Not shown in the image), the second semiconductor device includes another integrated circuit, which may be a system-on-a-chip or a field-programmable gate array (FPGA). In some embodiments, the memory bit cell 522 may be formed of various non-volatile memory types such as FeFET, FeRAM, ReRAM, SOT, or STT. Additionally, alternatively, or optionally, the memory bit cell may be formed of a non-volatile memory unit cell having a 2-terminal device, a 3-terminal device, or a 4-terminal device.

[0099] For example, the memory unit bit cell 522 can be formed of a ferroelectric material, such as a ferroelectric tunnel junction, diode, capacitor, single-gate transistor, or dual-gate transistor. Alternatively, the memory unit bit cell 522 can be formed of a memristor material, such as at least one ReRAM, or of a magnetic material, such as at least one spin-orbit torque device or at least one spin-transfer torque device. Furthermore, the non-volatile memory unit cell 522 can also be formed of a phase-change material or an antiferroelectric material.

[0100] In some alternative embodiments, the nonvolatile memory unit 522 may be formed of other types of materials, such as phase change materials, antiferroelectric materials, or multi-bit PCM materials. The nonvolatile unit may be formed using different structures, such as resistive random access memory (RRAM) technology, magnetic random access memory (MRAM) technology, or ferroelectric random access memory (FRAM) technology.

[0101] Furthermore, in some implementations, 3D NAND technology can be used to form the memory unit bit cell 522. For example, the memory unit bit cell 522 can be formed from stacked memory layers, where each layer includes multiple memory cells that can be accessed using shared bit lines. In such a case, read ports 524, 526 can be coupled to bit lines, and write ports 512, 516 can be coupled to word lines that control access to each layer.

[0102] In another embodiment, the 3D connectivity architecture can be constructed using stacked layers of NAND gates, NOR gates, or AND gates, and in some cases, different types of logic gates can be combined to optimize the functionality of the structure. Furthermore, the 3D connectivity architecture can be formed using through-silicon via (TSV) technology, which allows for vertical interconnection between different layers of the structure.

[0103] Furthermore, the non-volatile memory unit may include 2-terminal devices, such as capacitors or memristor devices connected in series with or not connected in series with additional selector devices (such as diodes); 3-terminal devices, such as floating-gate transistors or transistors with access gates; or 4-terminal devices, such as transistors with two access gates. The type and configuration of the non-volatile memory unit 522 may depend on specific application requirements, including circuit speed, power consumption, and reliability. The memory unit may include either a single ferroelectric transistor or a 6T SRAM cell. The memory unit may be a combination of many different devices, including but not limited to one or more of transistors, memristors, capacitors, etc.

[0104] In some embodiments of this disclosure, ferroelectric materials can be used to form non-volatile memory unit cells 522. Ferroelectric materials can be implemented as any type of device, including but not limited to thin-film devices such as ferroelectric tunnel junctions, capacitors, single-gate transistors, or dual-gate transistors.

[0105] In another embodiment, the non-volatile memory unit 522 may be formed of a memristor material, such as a metal oxide memristor (MOM), a conductive bridged RAM (CBRAM), or a valence-variable memory (VCM), each of which offers different benefits in terms of power consumption, speed, durability, etc.

[0106] Furthermore, in some embodiments, the non-volatile memory unit 522 may be formed of a magnetic material, such as a spin-orbit torque (SOT) device, a spin-transfer torque (STT) device, or a vertical magnetic tunnel junction (p-MTJ).

[0107] In one embodiment, a module group may include a plurality of modules, each of which can be accessed via dedicated read ports 524, 526 having a dedicated read peripheral 520, while sharing the same write ports 512, 516 and a shared write peripheral 510. The shared write ports 512, 516 may be configured to selectively write to one or more modules (including memory bit cells 522) within the module group. Each module may have the same or different sizes, and different module sizes may be configured to optimize the utilization of the memory array under different operating scenarios, etc.

[0108] Furthermore, the integrated circuit 500 can be formed using different manufacturing processes and technologies, including but not limited to CMOS or bipolar-CMOS-DMOS (BCD) processes, silicon-on-insulator (SOI) processes, FinFET processes, silicon-germanium (SiGe) processes, gallium arsenide (GaAs) processes, etc.

[0109] Figure 6 A perspective view of a component 600 according to an embodiment of the present disclosure is shown. The component 600 has features implemented on a semiconductor device (such as chiplet 230). Figure 1 In the integrated circuit, the semiconductor device is electrically connected to the system-on-chip (“SOC”) 610. In this embodiment, the semiconductor device is a small chip 230 electrically connected to the system-on-chip (“SOC”) 610.

[0110] refer to Figure 6 The SOC 610 includes a silicon substrate 602 on which multiple processing elements are formed, including processing element 606. The processing elements can communicate with each other via an on-chip network (“NOC”) 604, which is a communication architecture that guides data transfer between the processing elements. The communication architecture can take various forms, including buses, switches, NOCs, etc. The NOC 604 in the SOC 610 guides data traffic between various nodes (e.g., the processing elements 606) and links, which provide communication paths between the nodes.

[0111] The plurality of processing elements, including processing element 606, can be any suitable type of processor capable of executing instructions, including microprocessors, graphics processing units (GPUs), digital signal processors (DSPs), or application-specific integrated circuits (ASICs).

[0112] Furthermore, the SOC 610 may include various modules, such as module 232, which are grouped together to provide memory functionality to component 600 as described herein. Modules in module group 236 may be coupled to corresponding processing elements to provide them with readable memory. In some embodiments, the coupling between a module (e.g., module 232) and a processing element (e.g., 606) may be achieved via interconnects on silicon substrate 602.

[0113] After the circuitry is formed on the silicon substrate 602, a second layer 608 can be disposed on top of the substrate. The second layer 608 can be any suitable material, such as an insulating material, metal, dielectric, or interconnect layer, and it can be bonded to the chiplet 230. Bonding can be performed using any suitable technique, including but not limited to adhesives, soldering, or forging.

[0114] Overall, component 600 provides for chiplet 230 (which may include Figure 1 The chiplet 230 is integrated with the SOC 610 in various ways. Integrating the chiplet 230 offers various advantages, such as enhanced functionality, higher performance, and lower power consumption. Furthermore, depending on the specific application and design goals of the system, the integration of the chiplet 230 with the SOC 610 can be accomplished in a variety of ways.

[0115] Component 600 may include various variations and modifications depending on the specific requirements of the system. For example, the number, type, and arrangement of processing elements formed on silicon substrate 602 may differ. Similarly, the number, type, and function of modules in module group 236 may differ.

[0116] Furthermore, the second layer 608 can be modified to include additional functionality. For example, the second layer 608 may include passive components such as resistors, capacitors, and inductors, or it may include active components such as transistors or diodes. Incorporating these components into the second layer 608 can further enhance the functionality and performance of the system.

[0117] In another variation, component 600 can be incorporated into a heterogeneous integration approach, where chiplet 230 is manufactured using a different technology than that used in SOC 610. This approach allows for the optimization of different manufacturing technologies for different parts of the system, resulting in improved performance and reduced power consumption.

[0118] Various alternatives and modifications can be devised by those skilled in the art without departing from this disclosure. Therefore, this disclosure is intended to cover all such alternatives, modifications, and variations. Furthermore, while several embodiments of this disclosure have been shown in the figures and / or discussed herein, this is not intended to limit the disclosure thereto, as this disclosure is intended to cover as broadly as possible the scope permitted by the prior art, and the specification should be interpreted accordingly. Therefore, the foregoing description should not be construed as restrictive, but merely as illustrative of particular embodiments. Other modifications will be foreseen by those skilled in the art within the scope and spirit of the appended claims. Other elements, steps, methods, and techniques that are substantially different from those described in the foregoing description and / or the appended claims are also intended to be within the scope of this disclosure.

[0119] The embodiments shown in the figures are merely illustrative of certain examples of this disclosure. Furthermore, the figures described are illustrative only and not restrictive. In the figures, for illustrative purposes, the dimensions of some elements may be exaggerated and not drawn to scale. Additionally, depending on the context, elements shown in the figures with the same reference numerals may be the same element or may be similar elements.

[0120] When the term "comprising" is used in this specification and claims, it does not exclude other elements or steps. When referring to a singular noun (e.g., "a," "an," or "the"), the use of an indefinite or definite article includes the plural form of that noun unless otherwise specified. Therefore, the term "comprising" should not be construed as limited to the items listed thereafter; it does not exclude other elements or steps, and thus the scope of "device comprising items A and B" should not be limited to a device that includes only components A and B. This expression means that, with respect to this disclosure, the only relevant components of the device are A and B.

[0121] Furthermore, the terms “first,” “second,” “third,” etc., used in the specification or claims are provided to distinguish similar elements and are not necessarily used to describe order or chronological sequence. It should be understood that such terms are interchangeable where appropriate (unless otherwise explicitly disclosed), and the embodiments of this disclosure described herein can operate in other sequences and / or arrangements different from those described or illustrated herein.

[0122] Each feature and example, and combination thereof, described herein can be considered to be covered by this disclosure. This disclosure therefore relates to the following non-limiting numbered aspects:

[0123] 1. An integrated circuit, comprising: a module group having a plurality of modules, the plurality of modules including a first module and a second module; a shared write port configured to write to the module group; a first read port configured to read from the first module; and a second read port configured to read from the second module.

[0124] 2. The integrated circuit according to aspect 1, wherein the first read port and the second read port are configured to be inactive when a write operation is applied to the shared write port.

[0125] 3. The integrated circuit according to aspect 1, wherein the first read port and the second read port are configured to process reads concurrently with respect to each other.

[0126] 4. The integrated circuit according to aspect 1, wherein the shared write port is configured to write to an address space, the shared write port being configured to write to the first module via a first portion of the address space, and to write to the second module via a second portion of the address space.

[0127] 5. The integrated circuit according to aspect 1, wherein each of the plurality of modules includes an independent read port for concurrent reading via a corresponding independent read port of any of the plurality of modules, wherein the first read port is configured to read from the first module concurrently with another read of the second module using the second read port.

[0128] 6. The integrated circuit according to aspect 1, wherein the module group is configured to have a single write address space, the single write address space being configured to write to the plurality of modules.

[0129] 7. The integrated circuit according to aspect 6, wherein the first read port is configured to have a first read address space, and the second read port is configured to have a second read address space.

[0130] 8. The integrated circuit according to aspect 7, wherein the first read address space and the second read address space overlap numerically.

[0131] 9. The integrated circuit according to aspect 7, wherein the first read address space and the second read address space are co-extended.

[0132] 10. The integrated circuit according to aspect 7, wherein the first read address space is contiguous with the second read address space.

[0133] 11. The integrated circuit according to aspect 1, wherein the module group is formed on a second layer portion of the integrated circuit device.

[0134] 12. The integrated circuit according to aspect 1, wherein the integrated circuit is implemented as a chiplet, the chiplet being configured for face-to-face bonding.

[0135] 13. The integrated circuit according to aspect 12, wherein the chiplet further includes a plurality of input / output (I / O) bonding elements, wherein each of the plurality of input / output (I / O) bonding elements is configured to provide a corresponding read port to a corresponding module of the plurality of modules, wherein each of the plurality of input / output (I / O) bonding elements is configured to interface with a complementary corresponding input / output (I / O) bonding element of a second device, the second device being bonded to the chiplet.

[0136] 14. A semiconductor device comprising: an integrated circuit according to aspect 1.

[0137] 15. The semiconductor device according to aspect 14, wherein the semiconductor device is implemented as a die.

[0138] 16. The semiconductor device according to aspect 14, wherein the semiconductor device is implemented as a wafer.

[0139] 17. The semiconductor device according to aspect 14, wherein the semiconductor device is implemented as a small chip die.

[0140] 18. The semiconductor device according to aspect 17, wherein the small chip die is bonded to the second semiconductor device.

[0141] 19. The semiconductor device according to aspect 18, wherein the second semiconductor device is selected from the group consisting of a GPU (“Graphics Processing Unit”), a SoC (“System-on-Chip”), and a GPPU (“General Purpose Processing Unit”).

[0142] 20. The semiconductor device according to aspect 18, wherein the second semiconductor device is implemented as a small chip die.

[0143] 21. The semiconductor device according to aspect 18, wherein the second semiconductor device is implemented as a wafer.

[0144] 22. The semiconductor device according to aspect 18, wherein the second semiconductor device is an ASIC (“Application-Specific Semiconductor Chip”).

[0145] 23. The semiconductor device according to aspect 18, wherein the second semiconductor device is an FPGA (“Field Programmable Gate Array”).

[0146] 24. The semiconductor device according to aspect 18 further includes a plurality of input / output (I / O) bonding elements, wherein each of the plurality of input / output (I / O) bonding elements is configured to provide a corresponding read port to a corresponding module of the plurality of modules, wherein each of the plurality of input / output (I / O) bonding elements is configured to be electrically connected to a complementary corresponding input / output (I / O) bonding element of the second semiconductor device.

[0147] 25. The semiconductor device according to aspect 18, wherein the small die has a first side and a second side, wherein the second side is configured to be face-to-face bonded to the second semiconductor device.

[0148] 26. The semiconductor device according to aspect 25, wherein the small chip die and the second semiconductor device are part of a multi-chip package.

[0149] 27. The semiconductor device according to aspect 18 further includes an electrical connection medium disposed between the small die and the second semiconductor device.

[0150] 28. The semiconductor device according to aspect 17, wherein the first read port is disposed on the chip die having a surface, the first module comprising: a memory array including a plurality of memory unit cells arranged within the first module; and a read peripheral circuit means configured to read data stored in the memory array via the first read port.

[0151] 29. The semiconductor device according to aspect 28, wherein the space occupied by the read peripheral circuitry on the surface overlaps with the space occupied by the memory array on the surface.

[0152] 30. The semiconductor device according to aspect 28, wherein the space occupied by the first read port on the surface overlaps with the space occupied by the memory array on the surface.

[0153] 31. The semiconductor device according to aspect 28, wherein the space occupied by the read peripheral circuitry on the surface is co-extended with the space occupied by the memory array on the surface.

[0154] 32. The semiconductor device according to aspect 28, wherein the space occupied by the first read port on the surface is co-extended with the space occupied by the memory array on the surface.

[0155] 33. The semiconductor device according to aspect 28, wherein the memory array, the read peripheral circuitry, and the first read port are vertically stacked and configured to minimize the module footprint on the surface of the chip die.

[0156] 34. The semiconductor device according to aspect 28 further includes a write peripheral circuit means connected to the shared write port on the surface of the chip die, wherein: the write peripheral circuit means defines a first occupancy space on the surface, the first occupancy space not overlapping with the occupancy space of the memory array and not overlapping with the occupancy space of the first read port, and the shared write port defines a second occupancy space on the surface, the second occupancy space not overlapping with the occupancy space of the memory array and not overlapping with the occupancy space of the first read port.

[0157] 35. The semiconductor device according to aspect 28, wherein the plurality of memory units are formed by at least one non-volatile memory unit.

[0158] 36. The semiconductor device according to aspect 34, wherein the first occupancy space overlaps with the second occupancy space.

[0159] 37. The semiconductor device according to aspect 28, wherein the memory unit cell comprises a ferroelectric material.

[0160] 38. The semiconductor device according to aspect 28, wherein the memory unit cell comprises at least one of the following: a magnetic material, a spin-orbit torque material, a spin-transfer torque material, a phase change material, and an antiferroelectric material.

[0161] 39. The semiconductor device according to any one of aspects 28 to 38, wherein the plurality of memory unit cells are arranged in a three-dimensional configuration.

[0162] 40. The integrated circuit according to aspect 1, wherein the plurality of modules are organized into separate partitions, each partition having a dedicated read peripheral.

[0163] 41. The integrated circuit according to aspect 40, wherein each dedicated read peripheral has an independent clock.

[0164] 42. The integrated circuit according to aspect 1, wherein each of the plurality of modules has a dedicated read peripheral.

[0165] 43. The integrated circuit according to aspect 1, wherein the module group is configured to process write commands only during a reset, whereby read capability is disabled during the reset.

[0166] 44. The integrated circuit according to aspect 43, wherein the module group is configured to disable write capability when the module group is not in the reset.

[0167] 45. The integrated circuit according to aspect 1, wherein the module group includes at least two different non-volatile memory technologies.

[0168] 46. ​​The integrated circuit according to aspect 1 further includes a dynamic allocation circuit device for allocating memory blocks to the plurality of modules based on the use of the module group.

[0169] 47. The integrated circuit according to aspect 1 further includes a write peripheral of the module group, the write peripheral being connected to a dedicated I / O pad to enable data transfer outside the package of the integrated circuit.

[0170] 48. The integrated circuit according to aspect 1, wherein the integrated circuit is formed on a silicon substrate via an additive manufacturing process.

[0171] 49. The integrated circuit according to aspect 48, wherein the integrated circuit is electrically connected to a second semiconductor device, the second semiconductor device comprising another integrated circuit.

[0172] 50. The integrated circuit according to aspect 49 further includes a readout peripheral for at least one of the plurality of modules disposed on the silicon substrate.

[0173] 51. The integrated circuit according to aspect 49 further includes a read peripheral device for at least one of the plurality of modules disposed on the second semiconductor device.

[0174] 52. The integrated circuit according to aspect 1, wherein the integrated circuit is electrically connected to a second semiconductor device, the second semiconductor device comprising another integrated circuit.

[0175] 53. The integrated circuit according to aspect 52, wherein the second semiconductor device is a system-on-a-chip.

[0176] 54. The integrated circuit according to aspect 52, wherein the second semiconductor device is implemented as a small chip die.

[0177] 55. The integrated circuit according to aspect 52, wherein the second semiconductor device is implemented as a wafer.

[0178] 56. The integrated circuit according to aspect 52, wherein the second semiconductor device is an ASIC (“Application-Specific Semiconductor Chip”).

[0179] 57. The integrated circuit according to aspect 52, wherein the second semiconductor device is an FPGA (“Field Programmable Gate Array”).

[0180] 58. The integrated circuit according to aspect 52, wherein the plurality of modules are formed by non-volatile memory units arranged in a three-dimensional connectivity architecture perpendicular to the silicon substrate and the second semiconductor device.

[0181] 59. The integrated circuit according to aspect 52, wherein the plurality of modules are formed using at least one of the following: cross-point, 3D NAND, 3D NOR, 3D AND, and stacked planar layers.

[0182] 60. The integrated circuit according to aspect 1, wherein the plurality of modules have a single write peripheral.

[0183] 61. The integrated circuit according to aspect 60, wherein the single write peripheral has a dedicated clock.

[0184] 62. The integrated circuit according to aspect 1 further includes a plurality of clocks, wherein each of the plurality of clocks feeds a corresponding module among the plurality of modules, whereby each corresponding module has timing decoupled from the other modules among the plurality of modules, wherein each of the plurality of clocks is configured to clock control a corresponding read port of the corresponding module among the plurality of modules.

[0185] 63. The integrated circuit according to aspect 1, wherein the module group is formed on a chiplet having a first side and a second side, the second side being configured for bonding to a second semiconductor device.

[0186] 64. The integrated circuit according to aspect 63 further includes a decoder circuit, a driver circuit, and a register circuit on the silicon substrate of the chip.

[0187] 65. The integrated circuit according to aspect 64, wherein the module group is formed on the second layer of the chiplet.

[0188] 66. The integrated circuit according to aspect 63, wherein the second semiconductor device includes a plurality of processing elements, such that when the second semiconductor device is bonded to the chiplet, each processing element includes a corresponding interface for communicating with a corresponding module among the plurality of modules on the module group.

[0189] 67. The integrated circuit according to aspect 63, wherein the chiplet includes an interface on the second side to the shared write port, thereby interfacing with a complementary interface on the second semiconductor device.

[0190] 68. The integrated circuit according to aspect 63, wherein the second semiconductor device includes an on-chip network.

[0191] 69. The integrated circuit according to aspect 68, wherein the second semiconductor device includes a plurality of processing elements, wherein the on-chip network is configured to provide inter-element communication to the plurality of processing elements.

[0192] 70. The integrated circuit according to aspect 69, wherein the plurality of processing elements includes at least one embedded FPGA.

[0193] 71. The integrated circuit according to aspect 69, wherein the plurality of processing elements includes at least one of: a soft processor, a DSP block, an embedded processor, and a microcontroller.

[0194] 72. The integrated circuit according to aspect 1, wherein write operations to the module group are performed by a priority arbitration circuit that facilitates access to the modules in a predetermined order.

[0195] 73. The integrated circuit according to aspect 1 further includes a power gating circuit device that selectively de-energizes one of the plurality of modules when not in use.

[0196] 74. The integrated circuit according to aspect 1, wherein the shared write port is configured to write to a virtual address space that is mapped to a physical memory space.

[0197] 75. The integrated circuit according to aspect 1 further includes a control circuit configured to enable the shared write port during a write operation and disable the shared write port during a read operation, thereby saving energy.

[0198] 76. The integrated circuit according to aspect 1 further includes a control circuit configured to disable the first read port during a write operation and enable the first read port during a read operation, thereby saving energy.

[0199] 77. The integrated circuit according to aspect 1 further includes a power management module configured to selectively power off the shared write port during a read operation, thereby saving energy.

[0200] 78. The integrated circuit according to aspect 1 further includes a write circuit means configured to dynamically transfer power allocation from a write operation to a read operation, thereby saving energy.

[0201] 79. The integrated circuit according to aspect 1 further includes a write circuit means configured to enter a sleep mode and power off the shared write port during a read operation, thereby saving energy.

[0202] 80. The integrated circuit according to aspect 1, wherein the plurality of modules are formed by a non-volatile memory selected from the group consisting of: FeFET, FeRAM, ReRAM, SOT (spin-orbit torque) and STT (spin-transfer torque).

[0203] 81. The integrated circuit according to aspect 1, wherein the write peripheral for the module group is implemented on a silicon substrate.

[0204] 82. The integrated circuit according to aspect 81, wherein the integrated circuit is formed within a chiplet having a first side and a second side, wherein the second side is configured to be bonded to another integrated circuit disposed within a package, wherein the write peripheral is disposed between the module group and the second side of the chiplet.

[0205] 83. The integrated circuit according to aspect 1, wherein the read peripheral for the first module is implemented on a silicon substrate.

[0206] 84. The integrated circuit according to aspect 83, wherein the integrated circuit is formed within a chiplet having a first side and a second side, wherein the second side is configured to be bonded to another integrated circuit disposed within a package, wherein the read peripheral is disposed between the module group and the first side of the chiplet.

[0207] 85. The integrated circuit according to aspect 1, wherein the read peripheral for the first module is implemented in the second layer.

[0208] 86. The integrated circuit according to aspect 85, wherein the integrated circuit is formed within a chiplet having a first side and a second side, wherein the second side is configured to be bonded to another integrated circuit disposed within a package, wherein the read peripheral is disposed between the module group and the first side of the chiplet.

[0209] 87. The integrated circuit according to aspect 1, wherein each module has its own dedicated write peripheral.

[0210] 88. The integrated circuit according to aspect 87, wherein each dedicated write peripheral is configured to utilize a shared clock.

[0211] 89. An integrated circuit according to any one of aspects 1 to 27, 30, 32, 35 to 40, 43 to 46, 48 to 49, 52 to 60, 62 to 80, or 87 to 88, wherein the integrated circuit is disposed on a first semiconductor device, the integrated circuit further comprising: a shared write peripheral configured to write to the module group via the shared write port, the shared write peripheral being disposed on a silicon substrate of the first semiconductor device; a first read peripheral configured to read the first module via the first read port, wherein the first read peripheral is disposed on the silicon substrate of the first semiconductor device; and a second read peripheral configured to read the second module via the second read port, wherein the second read peripheral is disposed on the silicon substrate of the first semiconductor device, wherein the first module and the second module are disposed on a second layer of the first semiconductor device.

[0212] 90. The integrated circuit according to aspect 89, wherein the first module is a three-dimensional column of memory bit cells disposed between a first surface of the first semiconductor device and a silicon substrate of the first semiconductor device.

[0213] 91. The integrated circuit according to aspect 89, wherein the first read port is configured to electrically communicate with a second semiconductor device, the second semiconductor device being configured to be fixed to a first surface of the first semiconductor device.

[0214] 92. The integrated circuit according to aspect 91 further includes an intermediary disposed between the first surface of the first semiconductor device and the second semiconductor device.

[0215] 93. The integrated circuit according to aspect 89, wherein the first read port includes a read address bus that passes through the second layer of the first semiconductor device.

[0216] 94. The integrated circuit according to aspect 89, wherein the first read port includes a read data bus that passes through the second layer of the first semiconductor device.

[0217] 95. The integrated circuit according to aspect 89, wherein the shared write port is configured to electrically communicate with a second semiconductor device, the second semiconductor device being configured to be fixed to a first surface of the first semiconductor device.

[0218] 96. The integrated circuit according to aspect 95 further includes an electrical connection medium disposed between the first surface of the first semiconductor device and the second semiconductor device.

[0219] 97. The integrated circuit according to aspect 89, wherein the shared write port includes a write address bus that passes through the second layer of the first semiconductor device.

[0220] 98. The integrated circuit according to aspect 89, wherein the shared write port includes a write data bus that passes through the second layer of the first semiconductor device.

[0221] 99. A method comprising: forming an integrated circuit according to any one of aspects 1 to 98.

[0222] 100. A method of using an integrated circuit according to any one of aspects 1 to 98, the method comprising: writing to the module group; and reading from the module group.

Claims

1. An integrated circuit, comprising: A module group, wherein the module group has multiple modules, the multiple modules including a first module and a second module; A shared write port, configured to write to the module group; A first read port, configured to read from the first module; as well as The second read port is configured to read from the second module.

2. The integrated circuit of claim 1, wherein the first read port and the second read port are configured to be inactive when a write operation is applied to the shared write port.

3. The integrated circuit of claim 1, wherein the first read port and the second read port are configured to process reads concurrently with respect to each other.

4. The integrated circuit of claim 1, wherein the shared write port is configured to write to an address space, the shared write port is configured to write to the first module via a first portion of the address space, and to write to the second module via a second portion of the address space.

5. The integrated circuit of claim 1, wherein each of the plurality of modules includes an independent read port for concurrent reading via a corresponding independent read port of any of the plurality of modules, wherein the first read port is configured to read from the first module concurrently with another read of the second module using the second read port.

6. The integrated circuit of claim 1, wherein the module group is configured to have a single write address space, the single write address space being configured to write to the plurality of modules.

7. The integrated circuit of claim 6, wherein the first read port is configured to have a first read address space, and the second read port is configured to have a second read address space.

8. The integrated circuit according to claim 7, wherein the first read address space and the second read address space overlap numerically.

9. The integrated circuit according to claim 7, wherein the first read address space and the second read address space are co-extended.

10. The integrated circuit according to claim 7, wherein the first read address space is contiguous with the second read address space.

11. The integrated circuit of claim 1, wherein the module group is formed on a second layer portion of the integrated circuit device.

12. The integrated circuit of claim 1, wherein the integrated circuit is implemented as a chiplet, the chiplet being configured for face-to-face bonding.

13. The integrated circuit of claim 12, wherein the chiplet further comprises a plurality of input / output I / O bonding elements, wherein each of the plurality of input / output I / O bonding elements is configured to provide a corresponding read port to a corresponding module of the plurality of modules, wherein each of the plurality of input / output I / O bonding elements is configured to interface with a complementary corresponding input / output I / O bonding element of a second device, the second device being bonded to the chiplet.

14. A method for forming an integrated circuit, the method comprising: A module group is formed, the module group having multiple modules, the multiple modules including a first module and a second module; A shared write port is formed, and the shared write port is configured to write to the module group; A first read port is formed, and the first read port is configured to read from the first module; as well as A second read port is formed, and the second read port is configured to read from the second module.

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