SSI encoder data measurement method, system, device and medium
By simulating clock signals using the MOSI pins of the SPI master station and using pre-built extraction rules, the problem of non-standard SSI data frame matching was solved, enabling efficient SSI encoder data measurement and improving communication speed and real-time performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SICHUAN ZERO POINT AUTOMATION SYST CO LTD
- Filing Date
- 2026-01-28
- Publication Date
- 2026-04-21
AI Technical Summary
Existing technologies struggle to accurately match SSI data frames of non-standard lengths, leading to low communication efficiency, complex timing control, and potential data alignment errors.
By periodically sending preset bytecode through the MOSI pin of the SPI master station, a precise and uniform clock signal is generated. Combined with pre-built extraction rules, data bits are extracted from the serial data stream, adapting to SSI encoders with arbitrary bit lengths such as 13, 15, and 25, and data is sent/received using SPI hardware.
It achieves efficient data communication, reduces CPU resource consumption, improves communication speed and real-time performance, and ensures complete coverage of data frames.
Smart Images
Figure CN121898313A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of data measurement technology, and specifically to an SSI encoder data measurement method, system, device, and medium. Background Technology
[0002] SSI encoders are widely used sensors for high-precision position detection. Their output is synchronous serial data, requiring a dedicated SSI interface controller or FPGA to implement clock generation and data acquisition. Traditional solutions require dedicated hardware support, which is costly and increases system complexity when integrated with the main controller.
[0003] To reduce system complexity, existing technologies employ schemes that use general-purpose digital interfaces (such as SPI and GPIO) to simulate SSI communication. One common method is to directly use the clock output line (SCLK) of the SPI interface as the clock signal for the SSI encoder. However, this method has inherent drawbacks: the data frame length of a standard SPI master controller is usually limited by hardware and can only be configured to a fixed standard length such as 8 bits or 16 bits; while the data length of different SSI encoder models varies, often being non-standard bit widths such as 13 bits, 15 bits, and 25 bits. When using SCLK to simulate the clock, the SPI controller must generate a continuous clock within each fixed-length data frame, making it difficult to accurately match non-standard length SSI data frames, resulting in low communication efficiency, complex timing control, and potential data alignment errors.
[0004] Therefore, the present invention aims to provide an SSI encoder data measurement method, system, device, and medium to solve the aforementioned problems. Summary of the Invention
[0005] The technical problem this invention aims to solve is that existing technologies struggle to accurately match non-standard length SSI data frames, leading to low communication efficiency, complex timing control, and potential data alignment errors. The invention provides an SSI encoder data measurement method, system, device, and medium. By extracting valid data bits from a continuous serial data stream according to pre-defined extraction rules, it can seamlessly adapt to SSI encoders of arbitrary bit lengths such as 13, 15, and 25. Utilizing the MOSI pin with specific bytecode (e.g., 0x33), it generates precise and uniform clock pulses, and the number of clock cycles can be precisely controlled by controlling the number of bytes sent, ensuring complete coverage of the entire SSI data frame. Compared to existing purely software solutions using GPIO bit toggling to simulate a clock, this invention utilizes SPI hardware for sending / receiving data, resulting in lower CPU resource consumption, higher communication speed, and better real-time performance.
[0006] This invention is achieved through the following technical solution:
[0007] A method for measuring SSI encoder data, the method being used for data measurement between an SPI master station and an SSI encoder, wherein the MOSI pin of the SPI master station is connected to the clock input terminal of the SSI encoder, and the MISO pin of the SPI master station is connected to the data output terminal of the SSI encoder, the measurement method comprising:
[0008] The SPI master periodically sends a preset bytecode to the MOSI pin, and the MOSI pin generates a clock signal based on the preset bytecode and sends it to the SSI encoder.
[0009] The SSI encoder generates a serial data stream based on a clock signal and sends it to the SPI master station.
[0010] After receiving the serial data stream, the SPI master station extracts multiple data bits from the serial data stream according to the pre-built extraction rules;
[0011] Multiple data bits are combined in a serial data stream timing sequence to form an SSI encoder data frame. The combined SSI encoder data frame is then checked and decoded to obtain the actual measurement value.
[0012] Furthermore, the SPI master periodically sends a preset bytecode to the MOSI pin. The MOSI pin then simulates and generates a clock signal based on the preset bytecode and sends it to the SSI encoder, specifically:
[0013] The SPI master periodically sends binary data bytes to the MOSI pin. The MOSI pin uses the bit changes of the binary data bytes to generate periodic high and low levels. The periodic high and low levels are used to simulate a clock signal, which is then sent to the SSI encoder.
[0014] Furthermore, the communication parameters of the SPI master station are configured to be mode parameters that match the timing of the SSI encoder.
[0015] Furthermore, the pre-constructed extraction rule specifically involves dividing the serial data stream according to a preset clock cycle length and extracting data bits of a preset sampling point from the serial data stream within each divided region.
[0016] Furthermore, the preset clock cycle length is four clock cycles.
[0017] Furthermore, the preset sampling point is the third rising edge of the clock within the divided area.
[0018] The present invention also provides an SSI encoder data measurement system, which is used in the SSI encoder data measurement method described in any one of the above claims, the system comprising:
[0019] The clock signal simulation module is used by the SPI master station to periodically send preset bytecode to the MOSI pin. The MOSI pin simulates and generates a clock signal based on the preset bytecode and sends it to the SSI encoder.
[0020] The serial data stream transmission module is used by the SSI encoder to generate a serial data stream based on a clock signal and send it to the SPI master station.
[0021] The data bit extraction module is used by the SPI master station to extract multiple data bits from the serial data stream according to the pre-built extraction rules after receiving the serial data stream;
[0022] The data measurement module is used to combine multiple data bits according to the timing of the serial data stream to form an SSI encoder data frame, and to verify and decode the combined SSI encoder data frame to obtain the actual measurement value.
[0023] The present invention also provides a computer device, including a system memory and a processor, wherein the system memory stores a computer program, and the processor executes the computer program to implement the steps of any of the methods described above.
[0024] The present invention also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of any of the methods described above.
[0025] The present invention also provides a computer program product containing instructions that, when executed by a cluster of computer devices, cause the cluster of computer devices to perform the method described in any of the preceding claims.
[0026] Compared with the prior art, the present invention has the following advantages and beneficial effects:
[0027] In this invention, valid data bits are extracted from a continuous serial data stream according to a preset extraction rule, which can seamlessly adapt to SSI encoders with any bit length, such as 13, 15, or 25. Precise and uniform clock pulses can be generated using the MOSI pin through a specific byte code (such as 0x33), and the number of clock cycles can be precisely controlled by controlling the number of bytes sent, ensuring complete coverage of the entire SSI data frame. Compared to the pure software solution using GPIO bit toggling to simulate a clock in existing technologies, this invention utilizes SPI hardware to send / receive data, which consumes less CPU resources, has a higher communication rate, and better real-time performance. Attached Figure Description
[0028] To more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In the drawings:
[0029] Figure 1 This is a schematic diagram showing the connection between the SPI master station and the SSI encoder in this embodiment;
[0030] Figure 2 This is a schematic diagram of the method flow for an SSI encoder data measurement method in this embodiment;
[0031] Figure 3 This is a timing reference diagram of the MOSI analog SSI clock in this embodiment;
[0032] Figure 4 This is a schematic diagram of the module connections of an SSI encoder data measurement system in this embodiment;
[0033] Figure 5 This is a schematic diagram of the structure of a computer device in this embodiment. Detailed Implementation
[0034] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.
[0035] In this disclosure, unless otherwise stated, the use of terms such as "first," "second," etc., to describe various elements is not intended to limit the positional, temporal, or importance relationships of these elements; such terms are merely used to distinguish one element from another. In some examples, the first element and the second element may refer to the same instance of that element, while in other cases, based on the context, they may refer to different instances.
[0036] The terminology used in the description of the various examples in this disclosure is for the purpose of describing particular examples only and is not intended to be limiting. Unless the context explicitly indicates otherwise, an element may be one or more unless the number of elements is specifically limited. Furthermore, the term "and / or" as used in this disclosure covers any one of the listed items and all possible combinations thereof.
[0037] Example 1
[0038] See Figure 1 , Figure 1 A connection diagram between the SPI master station and the SSI encoder is shown. The MOSI pin of the SPI master station is connected to the clock input of the SSI encoder, and the MISO pin of the SPI master station is connected to the data output of the SSI encoder. The power supply and ground of the SSI encoder are connected according to actual requirements. It should be noted that in this embodiment, the dedicated clock line (SCLK) of the SPI is not used; instead, the data output line (MOSI) is used to simulate the clock signal. It should also be noted that in this embodiment, the communication parameters (clock polarity CPOL, phase CPHA) of the SPI master station are configured to match the timing of the SSI encoder, typically mode 3, i.e., CPOL=1, CPHA=1.
[0039] See Figure 2 , Figure 2 A flowchart illustrating a method for measuring SSI encoder data is shown. This method is used for data measurement between an SPI master and an SSI encoder. The measurement method includes:
[0040] S1: The SPI master periodically sends a preset bytecode to the MOSI pin, and the MOSI pin generates a clock signal based on the preset bytecode and sends it to the SSI encoder;
[0041] Specifically, in this embodiment, the SPI master periodically sends binary data bytes to the MOSI pin. The MOSI pin uses the bit changes of the binary data bytes to generate periodic high and low levels. The periodic high and low levels are used to simulate a clock signal, which is then sent to the SSI encoder. (See [link to documentation]). Figure 3 , Figure 3 A timing reference diagram of the MOSI analog SSI clock is shown.
[0042] It should be noted that in this embodiment, the binary data byte is a specific data byte 0x33 (binary 00110011). In other embodiments, it can also be set to other byte codes for transmission, and no further restrictions are imposed here. It should also be noted that the length and rate of the transmitted bytes can be flexibly set as needed and are not constrained by the number of bits in the SSI data.
[0043] S2: The SSI encoder generates a serial data stream based on the clock signal and sends it to the SPI master station;
[0044] S3: After receiving the serial data stream, the SPI master station extracts multiple data bits from the serial data stream according to the pre-built extraction rules;
[0045] Specifically, in this embodiment, after the SPI master station receives the serial data stream, it extracts the data bits output by the SSI encoder at the rising edge of the third clock cycle within each consecutive four clock cycles (corresponding to the four bits sent by MOSI) according to the actual data bit length requirements of the SSI encoder.
[0046] It should be noted that in this embodiment, the preset clock cycle length can also be other clock cycle lengths, such as two clock cycles or six clock cycles. The specific value depends on the actual needs and is not restricted in this case. At the same time, data bits can be output according to the sampling points agreed upon in the protocol. The preset sampling points can also be determined according to the actual needs and are not restricted in this case. This extraction rule can be flexibly configured by software to adapt to different SSI protocol variants.
[0047] S4: Combine multiple data bits according to the serial data stream timing to form an SSI encoder data frame. Verify and decode the combined SSI encoder data frame to obtain the actual measurement value.
[0048] Specifically, in this embodiment, all extracted data bits are combined in chronological order to form a complete SSI encoder data frame; the combined data frame is then checked (e.g., CRC, parity check) and decoded according to the SSI encoder protocol to obtain the actual measured values (e.g., absolute position, angle, etc.).
[0049] Specifically, in this embodiment, valid data bits are extracted from a continuous serial data stream according to a preset extraction rule, which can seamlessly adapt to SSI encoders with any bit length, such as 13, 15, or 25. Precise and uniform clock pulses can be generated using the MOSI pin through a specific byte code (such as 0x33), and the number of clock cycles can be precisely controlled by controlling the number of bytes sent, ensuring complete coverage of the entire SSI data frame. Compared to the pure software solution using GPIO bit toggling to simulate a clock in the prior art, this invention utilizes SPI hardware to send / receive data, which consumes less CPU resources, has a higher communication rate, and better real-time performance.
[0050] Example 2
[0051] See Figure 4 The present invention also provides an SSI encoder data measurement system, which is used in the SSI encoder data measurement method described in any one of the above claims, the system comprising:
[0052] The clock signal simulation module 100 is used for the SPI master station to periodically send preset bytecode to the MOSI pin, and the MOSI pin simulates and generates a clock signal based on the preset bytecode and sends it to the SSI encoder.
[0053] The serial data stream transmission module 200 is used by the SSI encoder to generate a serial data stream based on a clock signal and send it to the SPI master station.
[0054] The data bit extraction module 300 is used to extract multiple data bits from the serial data stream after the SPI master station receives the serial data stream according to the pre-built extraction rules.
[0055] The data measurement module 400 is used to combine multiple data bits according to the timing of the serial data stream to form an SSI encoder data frame, and to verify and decode the combined SSI encoder data frame to obtain the actual measurement value.
[0056] It should be noted that the modules in the system of Embodiment 2 correspond to the steps in the method of Embodiment 1. The steps in the method of Embodiment 1 have been described in detail in Embodiment 1, and the module content in the system will not be described in detail in this Embodiment 2.
[0057] Example 3
[0058] See Figure 5 This embodiment also provides a computer device, including a system memory 1005 and a processor 1001. The system memory 1005 stores a computer program, and the processor 1001 executes the computer program to implement the steps of any of the methods described above.
[0059] It should be noted that the processor 1001 is used to execute the steps in the above method embodiments according to the instructions in the program code. Alternatively, when the processor 1001 executes the computer program, it implements the functions of each module / unit in the above system / device embodiments.
[0060] Specifically, in this embodiment, the computer program can be divided into one or more modules / units, which are stored in the system memory 1005 and executed by the processor 1001 to complete this application. The one or more modules / units can be a series of computer program instruction segments capable of performing specific functions, which describe the execution process of the computer program in the terminal device.
[0061] The terminal device can be a desktop computer, laptop, handheld computer, or cloud server, etc. The terminal device may include, but is not limited to, a processor 1001 and a system memory 1005. Those skilled in the art will understand that this does not constitute a limitation on the terminal device; it may include more or fewer components than shown in the figures, or a combination of certain components, or different components. For example, the terminal device may also include an input / output device 1003, a network access device 1002, a bus 1006, etc.
[0062] The processor 1001 can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.
[0063] System memory 1005 can be an internal storage unit of the terminal device, such as a hard drive or RAM. System memory 1005 can also be a storage device 1004 of the terminal device, such as an external hard drive, SmartMedia Card (SMC), Secure Digital (SD) card, or FlashCard. Furthermore, system memory 1005 can include both internal storage units and storage device 1004. System memory 1005 is used to store computer programs and other programs and data required by the terminal device. System memory 1005 can also be used to temporarily store data that has been output or will be output.
[0064] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.
[0065] Example 4
[0066] This embodiment provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the methods described above.
[0067] The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or any combination thereof. More specific examples of computer-readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), registers, hard disks, optical fibers, compact disc read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof, or any other form of computer-readable storage medium in the art.
[0068] An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and storage medium can reside within an application-specific integrated circuit (ASIC). In embodiments of the invention, the computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device.
[0069] Example 5
[0070] This embodiment also provides a computer program product containing instructions that, when executed by a cluster of computer devices, cause the cluster of computer devices to perform the method described in Embodiment 1.
[0071] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A method for measuring SSI encoder data, characterized in that, The method is used for data measurement between an SPI master station and an SSI encoder. The MOSI pin of the SPI master station is connected to the clock input terminal of the SSI encoder, and the MISO pin of the SPI master station is connected to the data output terminal of the SSI encoder. The measurement method includes: The SPI master periodically sends a preset bytecode to the MOSI pin, and the MOSI pin generates a clock signal based on the preset bytecode and sends it to the SSI encoder. The SSI encoder generates a serial data stream based on a clock signal and sends it to the SPI master station. After receiving the serial data stream, the SPI master station extracts multiple data bits from the serial data stream according to the pre-built extraction rules; Multiple data bits are combined in a serial data stream timing sequence to form an SSI encoder data frame. The combined SSI encoder data frame is then checked and decoded to obtain the actual measurement value.
2. The SSI encoder data measurement method according to claim 1, characterized in that, The SPI master periodically sends a preset bytecode to the MOSI pin. The MOSI pin then simulates and generates a clock signal based on the preset bytecode and sends it to the SSI encoder. Specifically: The SPI master periodically sends binary data bytes to the MOSI pin. The MOSI pin uses the bit changes of the binary data bytes to generate periodic high and low levels. The periodic high and low levels are used to simulate a clock signal, which is then sent to the SSI encoder.
3. The SSI encoder data measurement method according to claim 1, characterized in that, The communication parameters of the SPI master station are configured to match the timing of the SSI encoder.
4. The SSI encoder data measurement method according to claim 1, characterized in that, The pre-built extraction rule is as follows: the serial data stream is divided according to a preset clock cycle length, and the data bits of the preset sampling point are extracted from the serial data stream in each divided region.
5. The SSI encoder data measurement method according to claim 1, characterized in that, The preset clock cycle length is four clock cycles.
6. The SSI encoder data measurement method according to claim 1, characterized in that, The preset sampling point is the third rising edge of the clock within the defined region.
7. An SSI encoder data measurement system, characterized in that, This system is used in an SSI encoder data measurement method according to any one of claims 1-6, the system comprising: The clock signal simulation module is used by the SPI master station to periodically send preset bytecode to the MOSI pin. The MOSI pin simulates and generates a clock signal based on the preset bytecode and sends it to the SSI encoder. The serial data stream transmission module is used by the SSI encoder to generate a serial data stream based on a clock signal and send it to the SPI master station. The data bit extraction module is used by the SPI master station to extract multiple data bits from the serial data stream according to the pre-built extraction rules after receiving the serial data stream; The data measurement module is used to combine multiple data bits according to the timing of the serial data stream to form an SSI encoder data frame, and to verify and decode the combined SSI encoder data frame to obtain the actual measurement value.
8. A computer device comprising a system memory and a processor, wherein the system memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method described in any one of claims 1 to 6.
10. A computer program product containing instructions, characterized in that, When the instructions are executed by a cluster of computer devices, the cluster of computer devices causes the cluster of computer devices to perform the method as described in any one of claims 1 to 6.