Preparation method and application of vertically integrated small photonic chip

Abstract

The invention discloses a preparation method and application of a vertical integrated photonic small chip, and relates to the field of preparation of vertical integrated photonic small chips, and the preparation method comprises the steps: sequentially forming a temporary bonding layer and a metal seed layer on a carrier wafer; preparing a multi-layer optical waveguide structure; aligning and bonding to the optical waveguide structure through a wafer-level hybrid bonding process; forming a three-dimensional copper column interconnection array around the photon chip, and carrying out molding packaging; stripping the carrier wafer and the temporary bonding layer; a redistribution layer is formed on the exposed surface, an optical fiber coupling groove is formed through laser etching, a three-dimensional copper column interconnection array is used as an optical alignment mark in the machining process, an optical fiber array is placed in the optical fiber coupling groove, and self-alignment coupling and fixing are achieved; according to the vertical integrated photon chip manufacturing method, the defects in the aspects of optical coupling, electrical performance, thermal management and testability in the prior art are overcome, and a brand new technical path is provided for high-performance, high-reliability and low-cost in-package optical interconnection.

Description

Technical Field

[0001] This invention relates to the field of fabrication technology of vertically integrated photonic chips, and in particular to a fabrication method and application of a vertically integrated photonic chip. Background Technology

[0002] With increasingly stringent requirements for data transmission bandwidth and energy efficiency from applications such as data center interconnects, high-performance computing, and artificial intelligence training, traditional electrical signal-based chip interconnects face severe challenges such as bandwidth bottlenecks, excessive power consumption, and signal attenuation. Introducing optical interconnect technology into chip packaging, achieving optical fiber replacing copper, has become a key direction for the development of next-generation information technology.

[0003] Current technologies primarily involve placing photonic chips and electronic chips side-by-side or stacked on a silicon or organic interposer. Electrical interconnection is achieved through high-density wiring within the interposer, and optical connection to external optical fibers is achieved through optical coupling structures located at the chip edge or top surface. However, this approach has significant drawbacks in practical applications: submicron-level alignment between the optical fiber and the photonic chip relies on manual post-processing, making large-scale manufacturing difficult; electrical signals require long-distance transmission through the interposer, and parasitic parameters limit the transmission rate; stress caused by mismatched thermal expansion coefficients of the packaging materials affects optical path stability; and there is a lack of wafer-level optoelectronic co-testing methods compatible with advanced packaging processes. These problems severely restrict the commercial application of high-performance, low-cost in-package optical interconnect technology. Summary of the Invention

[0004] To address the aforementioned challenges, this invention provides a method for fabricating and applying vertically integrated photonic chips. By vertically stacking and integrating photonic chips and multilayer optical waveguide structures within a package, and constructing a three-dimensional copper pillar interconnect array, the inherent defects of interposer technology in optical coupling, electrical performance, thermal management, and testability in the prior art are fundamentally solved. This provides a novel technical path for high-performance, high-reliability, and low-cost in-package optical interconnects.

[0005] To achieve the above objectives, the present invention provides a method for fabricating a vertically integrated photonic chip, comprising the following steps: S1: A temporary bonding layer and a metal seed layer are sequentially formed on the carrier wafer; S2: A multilayer optical waveguide structure is fabricated on a metal seed layer. The optical waveguide structure integrates reconfigurable optical path units, which include waveguide-type phase modulators or resonator structures. S3: Employs a wafer-level hybrid bonding process to align and bond the photonic chip to the optical waveguide structure; S4: Form a three-dimensional copper pillar interconnect array around the photonic chip and perform molding encapsulation; S5: Strip the carrier wafer and temporary bonding layer to expose the upper surface of the photonic chip and optical waveguide structure; S6: A redistribution layer is formed on the exposed surface, and a microwave transmission line and impedance matching structure are integrated in the redistribution layer; S7: A fiber coupling groove is formed on the side wall of the packaging structure by laser processing; the processing uses a three-dimensional copper pillar interconnect array as an optical alignment mark to achieve high-precision positional association between the coupling groove and the internal optical waveguide; the fiber array is placed into the fiber coupling groove to achieve self-aligned coupling and fixation; S8: Perform wafer-level testing and dicing to obtain vertically integrated photonic chips.

[0006] Preferably, the optical waveguide structure includes: A silicon nitride waveguide layer is formed on the metal seed layer by plasma-enhanced chemical vapor deposition. A grating coupler and a transmission waveguide are formed in the silicon nitride waveguide layer by photolithography and etching processes. The polymer cladding is formed by spin coating and UV curing, and the polymer cladding is doped with organic dopants. After curing, the thermal stress of the cladding and the silicon nitride waveguide layer is balanced.

[0007] Preferably, the wafer-level hybrid bonding process includes: The bonding surfaces of the dielectric layer and the metal bonding surface of the photonic chip are subjected to partitioned plasma activation treatment; oxygen-containing plasma is used to perform surface activation treatment on the bonding surface of the dielectric layer to improve its adhesion performance. The oxide layer on the metal bonding surface is removed by reducing plasma to ensure the reliability of metal contact; a ring-shaped dielectric stress buffer structure is constructed around the metal bonding area to balance thermal mismatch stress through mechanical constraint and suppress wafer-level warping during the bonding process. Under set process temperature and pressure conditions, a transient liquid-phase bonding reaction is triggered on the metal bonding surface to form a high-melting-point, high-reliability interconnect structure.

[0008] Preferably, the three-dimensional copper pillar interconnect array includes: The copper pillars are arranged according to functional zones and have different structures, including three types: signal transmission pillars, power distribution pillars and thermal management pillars. The distribution density of the three copper pillars is arranged in a gradient according to the power consumption cloud map of the photonic chip. The copper pillars extend in the Z direction and penetrate the molded packaging layer. Their top surfaces are exposed after planarization to form electrical connection exposed pads. An optical clearance window area without copper pillars is set in the region corresponding to the optical waveguide transmission path.

[0009] Preferably, the signal transmission pillar is a solid structure with a diameter smaller than that of the power distribution pillar, and its surface roughness is treated to reduce high-frequency transmission loss; the power distribution pillar is filled with phase change material microcapsules to increase heat capacity and suppress temperature drift caused by transient current; the thermal management pillar is a hollow structure filled with a high thermal conductivity material to form a vertical heat conduction channel; a diffusion barrier layer is provided between the copper pillar array and the molding encapsulation layer to prevent metal ions from diffusing into the optical window area.

[0010] Preferably, the redistribution layer includes: A low dielectric polymer is used as the dielectric layer; a metal stack structure is formed on the dielectric layer, and a microwave transmission line is fabricated by photolithography and etching processes; the microwave transmission line adopts a coplanar waveguide structure, the characteristic impedance is matched to the target value, and a distributed impedance matching structure is integrated to compensate for high frequency loss.

[0011] Preferably, the fiber optic coupling slot includes: A V-groove array is formed by etching the sidewall of the package using a femtosecond laser. The V-groove has a target tilt angle and the sidewall roughness meets the optical requirements. A UV-curable refractive index matching adhesive is coated in a V-groove. The adhesive contains a polymer matrix, a toughening agent, and a photoinitiator. After the fiber array is inserted into the V-groove, self-alignment is achieved by using the geometric features of the three-dimensional copper pillar interconnect array as a positioning reference. It is then cured and fixed by ultraviolet irradiation to achieve the target insertion loss level.

[0012] Preferably, wafer-level testing includes: Within the dicing area of ​​the wafer, a spiral delay linear process monitoring waveguide and test pads are co-fabricated. The monitoring waveguide utilizes the optical path accumulation effect to highly sensitively monitor phase deviations caused by process fluctuations. Electrical tests were performed on the three-dimensional copper pillar interconnect array by contacting the test pads with a probe card. A photoelectric testing system with integrated fiber optic probes is used to perform photoelectric co-characterization of reconfigurable optical path units.

[0013] Based on the above test results, a wafer map is constructed and defects are marked and yield is graded. Based on the grading results, the chip screening and cutting paths in the subsequent packaging process are planned.

[0014] Preferably, the waveguide-type phase modulator of the reconfigurable optical path unit adopts a combination structure of silicon nitride waveguide and polymer cladding. Thermo-optical modulation is achieved by organic dopants in the polymer cladding, and an isolation structure to suppress thermal crosstalk is set between the waveguide arms, so that the phase modulator can achieve π phase shift under the target driving voltage and the response time meets the requirements of high-speed optical signal processing.

[0015] The application of a vertically integrated photonic chip fabrication method in the in-package optical interconnect of an optical data communication system.

[0016] Therefore, the present invention, employing the above-described method for fabricating and applying a vertically integrated photonic chip, has the following beneficial effects: (1) This invention uses a three-dimensional copper pillar array as a geometric reference and a femtosecond laser to etch a self-aligned V-groove structure on the side of the package, thereby achieving submicron-level precise positioning of the fiber array and the optical waveguide, supporting wafer-level batch operations, and significantly improving coupling efficiency and manufacturing yield.

[0017] (2) This invention replaces the traditional horizontal wiring of the interposer layer with a three-dimensional copper pillar array to achieve ultra-short vertical interconnection between the photonic chip and external devices, significantly reducing parasitic capacitance and inductance, supporting high-speed electrical signal transmission of 56 Gbps and above, and improving the overall system bandwidth and energy efficiency.

[0018] (3) This invention effectively suppresses warpage and thermal stress during the packaging process by designing waveguide cladding materials with complementary thermal stress, adopting a ring dielectric layer stress compensation bonding structure, and integrating phase change material thermal management pillars, thereby ensuring long-term stability of the optical path and wavelength consistency.

[0019] (4) This invention integrates a spiral delay linear monitoring waveguide and test pad in the cutting channel, and combines fiber optic probes and radio frequency testing system to achieve parallel testing of optoelectronic performance and early defect screening during the manufacturing process, thereby improving process controllability and product yield.

[0020] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0021] Figure 1 This is a schematic flowchart of a method for fabricating a vertically integrated photonic chip according to the present invention. Detailed Implementation

[0022] The following detailed description of embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0023] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention pertains.

[0024] The terms "comprising" or "including" as used in this invention mean that the element preceding the term encompasses the element listed after the term, and do not exclude the possibility of encompassing other elements. Terms such as "inner," "outer," "upper," and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. In this invention, unless otherwise explicitly specified and limited, the term "attached" and similar terms should be interpreted broadly. For example, it can refer to a fixed connection, a detachable connection, or an integral part; it can refer to a direct connection or an indirect connection through an intermediate medium; it can refer to the internal communication of two elements or the interaction relationship between two elements. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0025] Example A method for fabricating a vertically integrated photonic chip, such as Figure 1 As shown, it includes the following steps: S1: A temporary bonding layer and a metal seed layer are sequentially formed on the carrier wafer; Standard-sized silicon wafers were selected as the carrier wafers due to their excellent mechanical stability, thermal conductivity, and compatibility with semiconductor process lines. The silicon wafers underwent standard RCA cleaning, followed by the growth of a 100-200 nm thick thermally oxidized SiO layer as an insulating layer. The temporary bonding layer employed a heat-release type temporary bonding material, consisting of two layers: a lower layer consisting of a 5-10 μm thick layer of polydimethylsiloxane or a specialized thermoplastic polymer spin-coated; and an upper layer consisting of a 1-2 μm thick layer of photosensitive benzocyclobutene spin-coated onto the polymer layer, followed by soft baking to create a smooth surface. The metal seed layer was deposited using magnetron sputtering, sequentially depositing a 20 nm thick titanium layer as an adhesion layer on the cured temporary bonding layer surface, followed by a 200 nm thick copper layer as a conductive seed layer.

[0026] S2: A multilayer optical waveguide structure is fabricated on a metal seed layer. The optical waveguide structure integrates reconfigurable optical path units, which include waveguide-type phase modulators or resonator structures. Optical waveguide structures include: A silicon nitride waveguide layer is formed on the metal seed layer by plasma-enhanced chemical vapor deposition. A grating coupler and a transmission waveguide are formed in the silicon nitride waveguide layer through photolithography and etching processes; the metal seed layer is patterned into a square electrode array with a side length of 50-200 μm and an electrode spacing of 100-500 μm, and is electrically connected to the redistribution layer through a three-dimensional copper pillar interconnect array.

[0027] The polymer coating, formed by spin coating and UV curing, is doped with an organic dopant, and the thermal stress of the coating and the silicon nitride waveguide layer is balanced after curing. The organic dopant is an azobenzene derivative or liquid crystal E7 microcapsules, with a doping concentration of 0.5-2 wt%, and UV curing is carried out in a nitrogen atmosphere to avoid oxidation.

[0028] The waveguide-type phase modulator of the reconfigurable optical path unit adopts a combination structure of silicon nitride waveguide and polymer cladding. Thermo-optical modulation is achieved through organic dopants in the polymer cladding, and an isolation structure is set between the waveguide arms to suppress thermal crosstalk. This enables the phase modulator to achieve π phase shift under the target driving voltage, and the response time meets the requirements of high-speed optical signal processing.

[0029] S3: Employs a wafer-level hybrid bonding process to align and bond the photonic chip to the optical waveguide structure; Wafer-level hybrid bonding processes include: The bonding surfaces of the dielectric layer and the metal bonding surface of the photonic chip are subjected to partitioned plasma activation treatment; oxygen-containing plasma is used to perform surface activation treatment on the bonding surface of the dielectric layer to improve its adhesion performance. The oxide layer on the metal bonding surface is removed using reducing plasma to ensure the reliability of metal contact; a ring-shaped dielectric stress buffer structure is constructed around the metal bonding area to balance thermal mismatch stress through mechanical constraint and suppress wafer-level warping during the bonding process. Under set process temperature and pressure conditions, a transient liquid-phase bonding reaction is triggered on the metal bonding surface to form a high-melting-point, high-reliability interconnect structure.

[0030] Specifically, this step is the core link in achieving high-precision three-dimensional integration of photonic chips and wafer-level optical waveguide structures. It simultaneously solves three major challenges—optical alignment, electrical interconnection, and mechanical stress—through an innovative hybrid bonding scheme.

[0031] Activation of the dielectric bonding surface is specifically performed using oxygen-containing plasma. Activation of the metal bonding surface is specifically performed using reducing hydrogen-based plasma. After activation, the chip and wafer must be temporarily stored in a high-purity nitrogen glove box and bonding must be completed within 4 hours to prevent surface recontamination or oxidation.

[0032] The stress compensation structure is a ring-shaped dielectric layer surrounding the metal bonding region. Its inner diameter is the same as the diameter of the metal bonding region, and its outer diameter is 10-50 micrometers larger than the inner diameter, thus forming a rigid constraint ring with a width of 5-25 micrometers. This ring structure and the global dielectric layer of the bonding surface are made of the same silicon dioxide material and are strictly coplanar. During the bonding cooling process, its high modulus characteristics constrain the local tensile stress generated by the thermal shrinkage of the metal region within the ring area and induce radial compressive stress to offset it. This transforms the macroscopic long-range stress that causes wafer warpage into localized microscopic stress, keeping the overall warpage of the 300 mm wafer-level bonding within 10 micrometers.

[0033] The metal bonding surfaces are joined using a transient liquid-phase bonding process. This process is performed within a preset temperature range of 280-320°C, optimized to simultaneously meet bonding requirements and protect the waveguide polymer material. Before bonding, a 100-300 nm thick tin layer is pre-placed on the surface of the metal seed layer on the wafer side as an interlayer. During bonding, under a pressure of 5-15 MPa, molten Sn rapidly interdiffused with the copper surfaces on both sides, forming a high-melting-point Cu-Sn intermetallic compound, achieving a transition from a transient liquid phase to a stable solid phase. This process is completed within 3-10 minutes, resulting in a bonding point contact resistance of less than 1 milliohm and thermal stability far exceeding the process temperature. Furthermore, the temperature is strictly controlled throughout the process below the polymer cladding thermal degradation threshold, ensuring high performance of the electrical interconnects and the integrity of the optical structure.

[0034] S4: Form a three-dimensional copper pillar interconnect array around the photonic chip and perform molding encapsulation; The three-dimensional copper pillar interconnect array includes: The copper pillars are arranged according to functional zones and have different structures, including three types: signal transmission pillars, power distribution pillars and thermal management pillars. The signal transmission pillar is a solid structure with a diameter smaller than that of the power distribution pillar. Its surface roughness is treated to reduce high-frequency transmission loss. The power distribution pillar is filled with phase change material microcapsules to increase heat capacity and suppress temperature drift caused by transient current. The thermal management pillar is a hollow structure filled with a high thermal conductivity material to form a vertical heat conduction channel. A diffusion barrier layer is provided between the copper pillar array and the molded encapsulation layer to prevent metal ions from diffusing into the optical window area.

[0035] The three-dimensional copper pillar interconnect array employs differentiated structural designs based on functional requirements to synergistically optimize electrical, thermal, and optical performance. The signal transmission pillars are solid copper pillars with a smaller diameter than the power distribution pillars. Their surfaces undergo electrochemical polishing and micro-etching to control surface roughness below 50 nanometers, effectively suppressing transmission losses caused by the high-frequency skin effect. The power distribution pillars have a larger diameter (typically 40-60 micrometers) and are innovatively filled with phase change material microcapsules. This structure significantly increases the pillar's heat capacity, absorbing instantaneous Joule heat during sudden changes in chip load, thereby suppressing power supply noise and photonic device wavelength drift caused by rapid temperature drift. The thermal management pillars are hollow copper pillars. After chemical plating to enhance adhesion, the inner walls are filled with a high thermal conductivity filler composed of silver nanowires or diamond particles, forming a vertical, efficient heat conduction channel from the chip junction region directly to the outer heat sink of the package. In addition, at the interface between the entire copper pillar array and the surrounding molded encapsulation layer (EMC), a nanoscale diffusion barrier layer composed of silicon nitride or diamond-like carbon is provided. This layer can effectively block the migration of copper ions under the action of temperature and electric field, preventing them from diffusing into the optical window area without copper pillars, thereby avoiding the adverse effects of metal contamination on the transmission loss of optical waveguide.

[0036] The distribution density of the three types of copper pillars is arranged in a gradient according to the power consumption cloud map of the photonic chip. The copper pillars extend in the Z direction and penetrate the molded packaging layer, with the top exposed for electrical connection. An optical window area without copper pillars is set in the region corresponding to the optical waveguide transmission path.

[0037] In the 3D copper pillar interconnect array layout, the planar distribution density of signal transmission pillars, power distribution pillars, and thermal management pillars is not uniform, but rather intelligently gradient-based according to the fine power consumption cloud map of the photonic chip. Specifically, through preliminary chip-level thermoelectric co-simulation, the steady-state and transient power consumption distribution of each functional block on the chip surface is accurately mapped. In high-power and high-current-density regions, the distribution density of power distribution pillars and thermal management pillars is increased accordingly, forming a local high-density support network to provide sufficient current delivery capacity and heat dissipation paths; in low-power or heat-sensitive photonic device regions (such as micro-ring resonators), the pillar density is reduced to minimize mechanical stress interference. All copper pillars penetrate the entire molded package layer vertically (Z-axis), and their tops are precisely exposed on the package surface after grinding and polishing, forming electrical contact points with excellent coplanarity, laying the foundation for subsequent interconnection with the redistribution layer or external chips.

[0038] Meanwhile, to ensure the transmission quality of optical signals, a copper pillar-free optical window area is specially designed in the packaging layout. The position of this area strictly corresponds to the transmission path of the optical waveguide on the photonic chip (especially the light-emitting area above the vertical grating coupler or the optical path extension area of ​​the edge coupler). During the layout design, design rules are checked to ensure that no copper pillars fall into this window area, thereby completely eliminating the adverse effects of metal structures on the light field such as scattering, absorption, and mode field distortion. The molding packaging material in the optical window area is also carefully selected, using a specific polymer with low optical loss and high light transmittance, and is designed with refractive index matching with the optical waveguide layer to jointly construct a low-loss, high-fidelity optical transmission channel from the inside of the chip to the package surface.

[0039] S5: Strip the carrier wafer and temporary bonding layer to expose the upper surface of the photonic chip and optical waveguide structure; The carrier wafer is peeled off from the temporary bonding layer to ultimately expose the functional upper surfaces of the photonic chip and optical waveguide structure. Specifically, a 248nm excimer laser is first used to perform back-side scanning irradiation through the carrier wafer, with the laser energy density controlled at 300-600 mJ / cm². 2 The process involves 5-20 pulses to induce photochemical decomposition or interface weakening of the temporary bonding layer's absorber layer. Subsequently, the entire structure is placed on a heating stage at 80-150°C, and a vertical mechanical peeling force of 10-50 N is applied to achieve clean separation of the carrier wafer and the functional layer. After peeling, the exposed photonic chip surface and the upper surface of the optical waveguide structure undergo low-pressure plasma cleaning with an Ar / H2 mixed gas to thoroughly remove residual bonding layer debris and organic contaminants. This ultimately controls the roughness of the exposed functional surface to below 1 nanometer, providing an atomically smooth and clean interface for the subsequent high-quality fabrication of the redistribution layer.

[0040] S6: A redistribution layer is formed on the exposed surface, and a microwave transmission line and impedance matching structure are integrated in the redistribution layer; The redistribution layer includes: A low dielectric polymer is used as the dielectric layer; a metal stack structure is formed on the dielectric layer, and a microwave transmission line is fabricated by photolithography and etching processes; the microwave transmission line adopts a coplanar waveguide structure, the characteristic impedance is matched to the target value, and a distributed impedance matching structure is integrated to compensate for high frequency loss.

[0041] A high-performance redistribution layer was fabricated on the surface of exposed photonic chip and optical waveguide structures. This redistribution layer uses low-dielectric-constant and low-loss photosensitive polyimide or benzocyclobutene as the dielectric material, forming a flat dielectric substrate with a precise via structure through spin coating, soft baking, exposure, and development processes. Subsequently, a copper metal stack with a thickness of 3-5 micrometers was constructed on the dielectric layer using physical vapor deposition combined with electroplating. The metal layer was then patterned using deep ultraviolet lithography and precision etching techniques, simultaneously forming conventional interconnect wiring and the critical microwave transmission line structure. The microwave transmission line employs a coplanar waveguide design, and its signal line width and ground band spacing were rigorously optimized through electromagnetic simulation to ensure precise impedance matching to 50Ω, meeting the fundamental requirement of impedance continuity for high-speed electrical signal transmission.

[0042] To achieve superior high-frequency signal integrity, the redistribution layer integrates a distributed impedance matching structure within the coplanar waveguide. This structure comprises three main parts: First, at the interface between the transmission line and the three-dimensional copper pillar signal transmission pillar, a length-controllable tapered impedance transformer is designed. The smooth transition of impedance through a gradual change in linewidth effectively suppresses interface reflections. Second, an embedded thin-film resistor-capacitor equalization network is periodically distributed along the transmission line. Precisely designed RC values ​​pre-emphasize the signal at high frequencies, compensating for high-frequency attenuation caused by dielectric loss and conductor roughness, thereby significantly widening the usable bandwidth. Third, in the grounding region of the coplanar waveguide, a dense array of grounding vias connected to the underlying copper pillar grounding pillar at subwavelength intervals constructs an ultra-low impedance ground return path to suppress modal resonance and common-mode noise. These distributed structures work together to ensure excellent insertion loss and return loss performance of the microwave transmission line in the 28-56 Gbps and higher frequency ranges.

[0043] S7: A fiber coupling groove is formed on the side wall of the packaging structure by laser processing; the processing uses a three-dimensional copper pillar interconnect array as an optical alignment mark to achieve high-precision positional association between the coupling groove and the internal optical waveguide; the fiber array is placed into the fiber coupling groove to achieve self-aligned coupling and fixation; The fiber optic coupling slot includes: A V-groove array is formed by etching the sidewall of the package using a femtosecond laser. The V-groove has a target tilt angle and the sidewall roughness meets the optical requirements. A UV-curable refractive index matching adhesive is coated in a V-groove. The adhesive contains a polymer matrix, a toughening agent, and a photoinitiator. After the fiber array is inserted into the V-groove, self-alignment is achieved by using the geometric features of the three-dimensional copper pillar interconnect array as a positioning reference. It is then cured and fixed by ultraviolet irradiation to achieve the target insertion loss level.

[0044] A self-aligned fiber coupling structure is formed by performing femtosecond laser precision etching on the side of the package structure, achieving precise fixation of the fiber array. Specifically, using a femtosecond laser system with the precise three-dimensional coordinates of pre-designed corner pillars or dedicated alignment pillars serving as spatial references in the three-dimensional copper pillar interconnect array as the processing origin, scanning etching is performed on the side of the package to form a series of V-groove arrays with target tilt angles and sidewall roughness that meets the optical requirement of Ra < 50nm after subsequent laser parameter optimization. Subsequently, a specially formulated UV-curable refractive index matching adhesive is precisely coated into the V-grooves. Next, a pre-face-treated multi-channel fiber array is inserted into the V-grooves. During this process, the vision system on the fiber array fixture continuously uses the unique geometric contours formed by the exposed three-dimensional copper pillar array surface and its sidewalls as a real-time positioning reference to drive a precision displacement stage to perform sub-micron level adjustments, achieving lateral and longitudinal self-alignment of the fiber core and the optical waveguide end face. After alignment, the refractive index matching adhesive is rapidly cured by irradiation with an ultraviolet LED surface light source, which firmly fixes the fiber array in the package, ultimately ensuring that the average insertion loss of a single channel is consistently below 0.5dB, and achieving excellent long-term mechanical stability and thermal cycling reliability.

[0045] S8: Perform wafer-level testing and dicing to obtain vertically integrated photonic chips.

[0046] Wafer-level testing includes: Within the dicing area of ​​the wafer, a spiral delay linear process monitoring waveguide and test pads are co-fabricated. The monitoring waveguide utilizes the optical path accumulation effect to highly sensitively monitor phase deviations caused by process fluctuations. Electrical tests were performed on the three-dimensional copper pillar interconnect array by contacting the test pads with a probe card. A photoelectric testing system with integrated fiber optic probes is used to perform photoelectric co-characterization of reconfigurable optical path units.

[0047] Based on the above test results, a wafer map is constructed and defects are marked and yield is graded. Based on the grading results, the chip screening and cutting paths in the subsequent packaging process are planned.

[0048] Within the wafer dicing area, a spiral delay linear optical waveguide and its electrically connected test pad array are pre-fabricated using a manufacturing process fully synchronized with the chip's functional areas. The spiral waveguide significantly increases the optical path, amplifying minute refractive index or dimensional fluctuations during manufacturing into measurable phase errors, thus achieving highly sensitive optical monitoring of process consistency. During testing, a high-performance probe card simultaneously contacts the test pads within the dicing area and the top of the exposed three-dimensional copper pillar interconnect array in the chip's functional areas, performing electrical tests covering DC parameters, on-resistance, and low-speed functionality. Simultaneously, a vector network analyzer RF test system integrating multi-channel fiber optic probes injects test optical signals into the monitoring waveguide of the dicing area, coupling them via a pre-defined optical path to a reconfigurable optical path unit inside the chip. RF control signals are then applied synchronously, completing a comprehensive and coordinated test of modulation efficiency, dynamic response, and optoelectronic S-parameters. All electrical and optical test data are integrated in real time. Through analysis algorithms, each chip unit is marked for defects and graded for performance (e.g., A / B / C grade) on a wafer digital map. Finally, based on the yield distribution map, the dicing path is intelligently optimized to prioritize the division of high-performance chip clusters while avoiding areas with dense defects. This allows for the direct acquisition of a single vertically integrated photonic chip with a known performance level after dicing, which can be used for subsequent packaging applications.

[0049] Therefore, this invention employs the aforementioned method and application for fabricating a vertically integrated photonic chip. By innovatively achieving vertical hybrid integration of photonic chips and multilayer optical waveguides within a wafer-level packaging architecture, and synergistically optimizing key aspects such as three-dimensional electrical interconnects, self-aligned optical coupling, thermal stress management, and wafer-level testing, it systematically solves the bottlenecks of traditional integration schemes in terms of optoelectronic coupling efficiency, high-speed electrical signal integrity, thermomechanical stability, and manufacturability. The fabricated vertically integrated photonic chip not only possesses high-density, low-loss optoelectronic I / O capabilities but also supports dynamic optical interconnects and processing functions through built-in reconfigurable optical path units. This provides a high-bandwidth, low-power, and mass-manufacturable core hardware foundation for high-performance computing, data center optical interconnects, and next-generation optical computing systems, demonstrating significant technological advancement and industrial application value.

[0050] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the technical solutions of the present invention, and these modifications or equivalent substitutions cannot cause the modified technical solutions to deviate from the spirit and scope of the technical solutions of the present invention.

Claims

1. A method for fabricating a vertically integrated photonic chip, characterized in that, Includes the following steps: S1: A temporary bonding layer and a metal seed layer are sequentially formed on the carrier wafer; S2: A multilayer optical waveguide structure is fabricated on a metal seed layer. The optical waveguide structure integrates reconfigurable optical path units, which include waveguide-type phase modulators or resonator structures. S3: Employs a wafer-level hybrid bonding process to align and bond the photonic chip to the optical waveguide structure; S4: Form a three-dimensional copper pillar interconnect array around the photonic chip and perform molding encapsulation; S5: Strip the carrier wafer and temporary bonding layer to expose the upper surface of the photonic chip and optical waveguide structure; S6: A redistribution layer is formed on the exposed surface, and a microwave transmission line and impedance matching structure are integrated in the redistribution layer; S7: A fiber coupling groove is formed on the side wall of the packaging structure by laser processing; the processing uses a three-dimensional copper pillar interconnect array as an optical alignment mark to achieve high-precision positional association between the coupling groove and the internal optical waveguide; the fiber array is placed into the fiber coupling groove to achieve self-aligned coupling and fixation; S8: Perform wafer-level testing and dicing to obtain vertically integrated photonic chips.

2. The method for fabricating a vertically integrated photonic chip according to claim 1, characterized in that, Optical waveguide structures include: A silicon nitride waveguide layer is formed on the metal seed layer under low stress via plasma-enhanced chemical vapor deposition. A grating coupler and a transmission waveguide are formed in the silicon nitride waveguide layer by photolithography and etching processes. The polymer cladding is formed by spin coating and UV curing, and the polymer cladding is doped with organic dopants. After curing, the thermal stress of the cladding and the silicon nitride waveguide layer is balanced.

3. The method for fabricating a vertically integrated photonic chip according to claim 2, characterized in that, Wafer-level hybrid bonding processes include: The bonding surfaces of the dielectric layer and the metal bonding surface of the photonic chip are subjected to partitioned plasma activation treatment; oxygen-containing plasma is used to perform surface activation treatment on the bonding surface of the dielectric layer to improve its adhesion performance. The oxide layer on the metal bonding surface is removed using reducing plasma to ensure the reliability of metal contact; a ring-shaped dielectric stress buffer structure is constructed around the metal bonding area to balance thermal mismatch stress through mechanical constraint and suppress wafer-level warping during the bonding process. Under set process temperature and pressure conditions, a transient liquid-phase bonding reaction is triggered on the metal bonding surface to form a high-melting-point, high-reliability interconnect structure.

4. The method for fabricating a vertically integrated photonic chip according to claim 3, characterized in that, The three-dimensional copper pillar interconnect array includes: The copper pillars are arranged according to functional zones and have different structures, including three types: signal transmission pillars, power distribution pillars and thermal management pillars. The distribution density of the three copper pillars is arranged in a gradient according to the power consumption cloud map of the photonic chip. The copper pillars extend in the Z direction and penetrate the molding packaging layer. Their top surfaces are exposed after planarization to form electrical connection exposed pads. An optical clearance window area without copper pillars is set in the region corresponding to the optical waveguide transmission path.

5. The method for fabricating a vertically integrated photonic chip according to claim 4, characterized in that, The signal transmission pillar is a solid structure with a diameter smaller than that of the power distribution pillar. The surface roughness is treated to reduce high-frequency transmission loss. The power distribution pillar is filled with phase change material microcapsules to increase heat capacity and suppress temperature drift caused by transient current. The thermal management pillar is a hollow structure filled with a high thermal conductivity material to form a vertical heat conduction channel. A diffusion barrier layer is provided between the copper pillar array and the molded encapsulation layer to prevent metal ions from diffusing into the optical window area.

6. The method for fabricating a vertically integrated photonic chip according to claim 5, characterized in that, The redistribution layer includes: A low dielectric polymer is used as the dielectric layer; a metal stack structure is formed on the dielectric layer, and a microwave transmission line is fabricated by photolithography and etching processes; the microwave transmission line adopts a coplanar waveguide structure, the characteristic impedance is matched to the target value, and a distributed impedance matching structure is integrated to compensate for high frequency loss.

7. The method for fabricating a vertically integrated photonic chip according to claim 6, characterized in that, Fiber optic coupling slots include: A V-groove array is formed by etching the sidewall of the package using a femtosecond laser. The V-groove has a target tilt angle and the sidewall roughness meets the optical requirements. A UV-curable refractive index matching adhesive is coated in a V-groove. The adhesive contains a polymer matrix, a toughening agent, and a photoinitiator. After the fiber array is inserted into the V-groove, self-alignment is achieved by using the geometric features of the three-dimensional copper pillar interconnect array as a positioning reference. It is then cured and fixed by ultraviolet irradiation to achieve the target insertion loss level.

8. The method for fabricating a vertically integrated photonic chip according to claim 7, characterized in that, Wafer-level testing includes: Within the dicing area of ​​the wafer, a spiral delay linear process monitoring waveguide and test pads are co-fabricated. The monitoring waveguide utilizes the optical path accumulation effect to highly sensitively monitor phase deviations caused by process fluctuations. Electrical tests were performed on the three-dimensional copper pillar interconnect array by contacting the test pads with a probe card. A photoelectric testing system with integrated fiber optic probes is used to perform photoelectric co-characterization of reconfigurable optical path units; Based on the above test results, a wafer map is constructed and defects are marked and yield is graded. Based on the grading results, the chip screening and cutting paths in the subsequent packaging process are planned.

9. The method for fabricating a vertically integrated photonic chip according to claim 8, characterized in that, The waveguide-type phase modulator of the reconfigurable optical path unit adopts a combination structure of silicon nitride waveguide and polymer cladding. Thermo-optical modulation is achieved through organic dopants in the polymer cladding, and an isolation structure is set between the waveguide arms to suppress thermal crosstalk. This enables the phase modulator to achieve π phase shift under the target driving voltage, and the response time meets the requirements of high-speed optical signal processing.

10. An application of a method for fabricating a vertically integrated photonic chip, characterized in that, The application of a vertically integrated photonic chip fabricated using the fabrication method of any one of claims 1-9 in the in-package optical interconnect of an optical data communication system.

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