TBC battery and preparation method thereof

Abstract

The invention discloses a TBC battery and a preparation method thereof, and belongs to the technical field of solar photovoltaic batteries. The preparation method comprises the following steps: depositing a tunneling layer and a polycrystalline silicon layer on the back surface of an alkali-polished N-type silicon-based substrate; carrying out boron doping and high-temperature oxidation to form a borosilicate glass layer; performing laser etching to form a P-type doped region and an etching region; carrying out alkali washing on the etching region, and depositing a tunneling oxide layer and a phosphorus-doped N-type doping layer; performing crystallization treatment; borosilicate glass layer cleaning is carried out on the P-type doped region, winding plating is carried out on the front surface, and alkali texturing is completed; and depositing an AlOx layer and a SiNx layer on the back surface and the front surface of the product. According to the method, the technological process is simple, compared with the mode that a PVD precise direction coating mode is adopted in the market to achieve isolation of the PN area, one picosecond laser etching procedure can be omitted, the equipment investment can be obviously reduced, the production efficiency can be improved, and the TOPCon technology of an existing PVD route can be upgraded to the TBC technology.

Description

Technical Field

[0001] This invention relates to the field of solar photovoltaic cell technology, and more specifically, to a TBC cell and its preparation method. Background Technology

[0002] TBC technology (TOPCon-BC technology) is a new high-efficiency battery technology that combines high-efficiency TOPCon technology with back-junction back-contact technology. TBC utilizes the excellent passivated contact structure of TOPCon batteries, with all electrodes fabricated on the back of the battery. There are no grid lines on the front surface of the battery, avoiding the light-blocking loss caused by the grid lines on the front of conventional batteries. This not only results in a more aesthetically pleasing appearance but also significantly improves the current.

[0003] However, current TBC (Total Biochemical Curing) methods generally require multiple picosecond laser etching passes, resulting in high equipment investment, complex processes, and high production costs. Therefore, this invention is proposed. Summary of the Invention

[0004] The purpose of this invention is to provide a TBC battery and its preparation method. The existing TOPCon battery production line equipment has been successfully upgraded to make it suitable for the preparation of TBC batteries, which greatly reduces equipment investment and production costs, simplifies the process, and improves production efficiency.

[0005] This invention can be implemented as follows:

[0006] In a first aspect, the present invention provides a method for preparing a TBC battery, which includes the following steps:

[0007] On the back side of an alkaline-polished N-type silicon substrate, a tunneling layer and a polycrystalline silicon layer are sequentially deposited; then boron doping and high-temperature oxidation are performed to form a borosilicate glass layer as a mask for the P-region; then laser etching is performed to form a P-type doped region and etched regions on both sides of the P-type doped region on the back side.

[0008] The etched area is then subjected to alkaline washing to remove the residual P-type doped layer and borosilicate glass layer, exposing the N-type silicon substrate.

[0009] A tunneling oxide layer and a phosphorus-doped N-type doped layer are sequentially deposited on the back side of the alkaline-washed N-type silicon substrate.

[0010] Crystallization treatment was performed on the amorphous silicon doped in the P-type and N-type doped layers;

[0011] After crystallization, the borosilicate glass layer on the back of the product is cleaned to remove the wrap-around plating on the front and complete the alkaline texturing on the front.

[0012] AlO was deposited on both the front and back sides of the product after the front side was alkali-textured. x Layer, then deposit SiN separatelyx The layers are then screen-printed, light-injected, and laser-assisted sintering is performed.

[0013] In an optional embodiment, the boron doping temperature is 900°C to 1035°C.

[0014] In an optional implementation, the laser etching power is 90W to 130W and the frequency is 475KHz to 525KHz.

[0015] In an optional implementation, a tunneling oxide layer and a phosphorus-doped N-type doped layer are deposited using PVD deposition.

[0016] In an optional embodiment, the crystallization temperature is 800℃~920℃ and the crystallization time is 70min~100min.

[0017] In an optional embodiment, the temperature of the alkaline solution used for alkaline polishing is 50°C to 70°C; the alkaline polishing time is 200s to 270s; and the etching amount of alkaline polishing is 0.2g to 0.3g.

[0018] And / or, the temperature of the alkaline solution used for alkaline washing is 50℃~70℃; the alkaline washing time is 95s~160s; and the etching angle after alkaline washing is 15°~60°.

[0019] And / or, the temperature of the alkaline solution used for alkaline texturing is 70℃~90℃, the processing time for alkaline texturing is 480s~520s, the etching amount for alkaline texturing is 0.5g~0.7g, and the surface reflectivity of the N-type silicon substrate after texturing is 8.5%~10%.

[0020] Secondly, the present invention provides a TBC battery, which is prepared by any of the preparation methods described in the foregoing embodiments.

[0021] In an optional implementation, the TBC battery includes:

[0022] N-type silicon substrate;

[0023] Front-side AlO₂ is sequentially arranged from the inside to the outside on the front side of an N-type silicon substrate. x Layer and front SiN x layer;

[0024] P-type doped regions and N-type doped regions are disposed on the back side of an N-type silicon substrate, with N-type doped regions on both sides of the P-type doped region; wherein, the N-type doped region is provided with a tunneling oxide layer, an N-type polycrystalline silicon layer, and a back AlO layer from the inside to the outside. x Layer and back SiN x The P-type doped region consists of, from the inside out, a tunneling layer, a P-type polysilicon layer, and a back AlO layer. x Layer and back SiNx layer;

[0025] The P-type doped region also has a first gate electrode, which passes through the back SiN. x Layer and back AlO x The layer is in direct contact with the P-type polycrystalline silicon layer; the N-type doped region also has a second gate electrode, which passes through the back SiN layer. x Layer and back AlO x The layer is in direct contact with the N-type polycrystalline silicon layer.

[0026] In an optional implementation, the TBC battery includes at least one of the following features:

[0027] Feature 1: The thickness of the tunneling layer is 1.2 nm to 1.8 nm;

[0028] Feature 2: The thickness of the polycrystalline silicon layer is 150nm to 300nm;

[0029] Feature 3: The thickness of the borosilicate glass layer is 50nm to 70nm;

[0030] Feature 4: The sheet resistance of the borosilicate glass layer is 300Ω / sq~450Ω / sq;

[0031] Feature 5: The thickness of the tunneling oxide layer is 1.2 nm to 2 nm;

[0032] Feature 6: The thickness of the phosphorus-doped N-type doped layer is 150 nm to 250 nm;

[0033] Feature 7: Frontal AlO x Layer and back AlO x The thickness of the layer is independently 2nm to 11nm;

[0034] Feature 8: Backside SiN x The thickness of the layer is 70nm to 85nm;

[0035] Feature 9: Backside SiN x The refractive index of the layer is 1.92%–2.32%;

[0036] Feature 10: Front-facing SiN x The thickness of the layer is 75nm to 90nm;

[0037] Feature 11: Front-side SiN x The refractive index of the layer is 1.9% to 2.1%.

[0038] In an optional implementation, the TBC battery further includes at least one of the following features:

[0039] Feature 12: In both the P-type and N-type polysilicon layers, the doping concentration of polysilicon is independently 5 × 10⁻⁶. 18 / cm 3 ~9×10 20 / cm 3 ;

[0040] Feature 13: In both the P-type and N-type polycrystalline silicon layers, the crystallinity of the polycrystalline silicon is independently 80% to 100%;

[0041] Feature 14: The doping concentration of the tunneling oxide layer gradually varies within a range of 5 × 10⁻⁶. 15 / cm 3 ~5×10 20 / cm 3 ;

[0042] Feature 15: The width of the N-type doped region is 180μm to 220μm, and the width of the P-type doped region is 2 to 5 times the width of the N-type doped region.

[0043] The beneficial effects of this invention include:

[0044] This invention creatively proposes a simple and low-cost method for fabricating TBC cells. This method eliminates the need for a boron diffusion layer on the front side and pre-texturing processes; the front surface of the silicon substrate has no doped layer, only a passivation layer. Furthermore, the back-side P+ mask is formed using a doped BSG layer, eliminating the need for a pre-SiN coating process. In addition, compared to the market-standard PVD precision orientation coating method for PN region isolation, this method reduces a picosecond laser etching step, significantly lowering equipment investment and improving production efficiency. It can upgrade the existing PVD-based TOPCon technology to TBC technology, greatly reducing equipment investment and production costs, simplifying the process, and improving production efficiency. The resulting TBC cells exhibit excellent photoelectric performance. Attached Figure Description

[0045] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a schematic diagram of the structure of the TBC battery provided by the present invention;

[0047] Figure 2 The process flow diagram of the TBC battery preparation method provided by the present invention.

[0048] Icon: 1 - N-type silicon substrate; 2 - Front AlO x Layer; 3-Front-side SiN x 4-Tunneling layer; 5-P-type polycrystalline silicon layer; 6-Backside AlO x Layer; 7-backside SiN x Layer; 8-First gate electrode; 9-Tunneling oxide layer; 10-N-type polysilicon layer; 11-Second gate electrode. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Where specific conditions are not specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall apply. Reagents or instruments whose manufacturers are not specified are all conventional products that can be purchased commercially.

[0050] The TBC battery and its preparation method provided by the present invention will be described in detail below.

[0051] This invention provides a TBC battery (such as...) Figure 1 For the preparation method shown, please refer to the instructions below. Figure 2 Its preparation process includes the following steps:

[0052] S1: On the back side of the alkaline polished N-type silicon substrate 1, a tunneling layer 4 and a polycrystalline silicon layer are deposited sequentially.

[0053] In some optional embodiments, the alkaline solution used for alkaline polishing includes water, an aqueous KOH solution, and additives, wherein the volume ratio of water, the aqueous KOH solution, and the additives can be (340–350):(14–18):(4–5). The mass concentration of KOH in the aqueous KOH solution can be 1.5%–2.5%. The additives used for alkaline polishing can be commonly used additives in the art.

[0054] In some alternative embodiments, the temperature of the alkaline solution used for alkaline polishing can be 50°C to 70°C, such as 50°C, 55°C, 60°C, 65°C or 70°C, or other values ​​within the range of 50°C to 70°C.

[0055] The alkaline polishing time can be 200s to 270s, such as 200s, 210s, 220s, 230s, 240s, 250s, 260s or 270s, or other values ​​within the range of 200s to 270s.

[0056] The etching amount for alkaline polishing can be 0.2g to 0.3g, such as 0.2g, 0.25g or 0.3g, or other values ​​within the range of 0.2g to 0.3g.

[0057] The surface reflectance of the N-type silicon substrate 1 after alkaline polishing is 35% to 45%, such as 35%, 38%, 40%, 42% or 45%, or other values ​​within the range of 35% to 45%.

[0058] A better back-side polishing effect can be obtained by performing alkaline polishing under the above conditions.

[0059] In the above S1, both the tunneling layer 4 (SiO2) and the polycrystalline silicon layer (intrinsic polysilicon) can be deposited using LPCVD (low-pressure chemical vapor deposition).

[0060] In some alternative embodiments, the thickness of the tunneling layer 4 can be 1.2nm to 1.8nm, such as 1.2nm, 1.3nm, 1.4nm, 1.5nm, 1.6nm, 1.7nm or 1.8nm, or other values ​​within the range of 1.2nm to 1.8nm.

[0061] In some alternative implementations, the thickness of the polysilicon layer can be 150nm to 300nm, such as 150nm, 170nm, 200nm, 220nm, 2500nm or 3000nm, or other values ​​within the range of 150nm to 300nm.

[0062] By setting the thickness of the tunneling layer 4 and the polysilicon layer to the range described above, it is beneficial to enable polysilicon to have better passivation effect and resistance to metal recombination.

[0063] S2: Boron doping is performed, followed by high-temperature oxidation to form a borosilicate glass layer (BSG layer) that serves as a mask for the P-region.

[0064] In some alternative implementations, boron doping is performed by boron diffusion, followed by high-temperature oxidation to form a borosilicate glass layer.

[0065] The boron doping temperature can be between 900℃ and 1035℃, such as 900℃, 920℃, 950℃, 980℃, 1000℃ or 1035℃, or other values ​​within the range of 900℃ to 1035℃.

[0066] The thickness of the borosilicate glass layer can be 50nm to 70nm, such as 50nm, 55nm, 60nm, 65nm or 70nm, or other values ​​within the range of 50nm to 70nm.

[0067] The sheet resistance of the borosilicate glass layer can be from 300Ω / sq to 450Ω / sq, such as 300Ω / sq, 320Ω / sq, 350Ω / sq, 380Ω / sq, 400Ω / sq, 420Ω / sq or 450Ω / sq, or other values ​​within the range of 300Ω / sq to 450Ω / sq.

[0068] By controlling the borosilicate glass layer within the aforementioned sheet resistance range, a better emitter doping concentration can be obtained.

[0069] S3: Perform laser etching to form a P-type doped region on the back side and etched regions on both sides of the P-type doped region.

[0070] Remove the mask borosilicate glass layer and P-type doped layer from the two etched regions. The remaining P-type doped layer can form a PN junction with the N-type silicon substrate 1.

[0071] In some alternative implementations, a green picosecond laser is used for etching to modify the layer to be etched.

[0072] In some alternative implementations, the laser etching power can be 90W to 130W, such as 90W, 95W, 100W, 105W, 110W, 115W, 120W, 125W, 127W, 129W or 130W, or other values ​​within the range of 90W to 130W.

[0073] The frequency of laser etching can be 475KHz to 525KHz, such as 475KHz, 480KHz, 490KHz, 595KHz, 505KHz, 515KHz or 525KHz, or other values ​​within the range of 475KHz to 525KHz.

[0074] S4: Perform alkaline washing on the etched area to remove the residual P-type doped layer and borosilicate glass layer, exposing the N-type silicon substrate (preferably exposing a flat N-type silicon substrate).

[0075] In some optional embodiments, the alkaline solution used for alkaline washing comprises water, an aqueous KOH solution, and a polishing additive, wherein the volume ratio of water, the aqueous KOH solution, and the polishing additive can be (345–355):(14–18):(3–5). The mass concentration of KOH in the aqueous KOH solution can be 1.5%–2.5%. The polishing additive used for alkaline washing can be any commonly used additive in the art.

[0076] In some optional embodiments, the temperature of the alkaline solution used for alkaline washing can be 50°C to 70°C, such as 50°C, 55°C, 60°C, 65°C or 70°C, or other values ​​within the range of 50°C to 70°C.

[0077] The alkaline washing time can be 95s to 160s, such as 95s, 100s, 110s, 120s, 130s, 140s, 150s or 160s, or other values ​​within the range of 95s to 160s.

[0078] The etching angle after alkaline washing can be 15° to 60°, such as 15°, 20°, 25°, 30°, 35°, 40°, 45°, 50°, 55° or 60°, or other values ​​within the range of 15° to 60°.

[0079] S5: A tunneling oxide layer 9 and a phosphorus-doped N-type doped layer are sequentially deposited on the back side of the alkaline-washed N-type silicon substrate.

[0080] In some alternative implementations, a tunneling oxide layer 9 and a phosphorus-doped N-type doped layer (N+ amorphous silicon layer) are precisely deposited using PVD deposition. Specifically, the directional nature of PVD deposition is used to precisely deposit in-situ amorphous silicon in the N-region on the back side, ensuring that no N-type poly silicon is deposited in the PN isolation region, followed by gas passivation of the relevant areas.

[0081] In some alternative embodiments, the thickness of the tunneling oxide layer 9 can be 1.2 nm to 2 nm, such as 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm or 2 nm, or other values ​​in the range of 1.2 nm to 2 nm.

[0082] The thickness of the phosphorus-doped N-type doped layer can be 150nm to 250nm, such as 150nm, 180nm, 200nm, 220nm or 250nm, or other values ​​within the range of 150nm to 250nm.

[0083] By setting the tunneling oxide layer 9 and the doped amorphous silicon layer in the above manner, a better field passivation effect can be obtained.

[0084] S6: Crystallize the amorphous silicon doped in the P-type and N-type doped layers.

[0085] Specifically, a high-temperature annealing process is used to crystallize the P-region and N-region doped amorphous silicon.

[0086] In some alternative embodiments, the crystallization temperature can be 800℃ to 920℃, such as 800℃, 820℃, 840℃, 860℃, 880℃, 900℃ or 920℃, or other values ​​within the range of 800℃ to 920℃.

[0087] The crystallization time can be 70 min to 100 min, such as 70 min, 75 min, 80 min, 85 min, 90 min, 95 min or 100 min, or other values ​​within the range of 70 min to 100 min.

[0088] S7: Clean the borosilicate glass layer on the back of the product after crystallization, remove the front-side plating, and complete the front-side alkaline texturing.

[0089] In some alternative embodiments, the borosilicate glass layer in the relevant area is cleaned and the plating is removed using an acid cleaning solution, which is exemplary composed of HF, HNO3, H2SO4, and H2O in a volume ratio of 12:30:6:19.

[0090] In some optional embodiments, the alkaline solution used for front-side alkaline texturing includes water, an aqueous KOH solution, and a texturing additive, wherein the volume ratio of water, the aqueous KOH solution, and the texturing additive can be (350–360):(5–6):(1.5–2.5). The mass concentration of KOH in the aqueous KOH solution can be 0.8%–1.2%. The texturing additive used for front-side alkaline texturing can be any commonly used additive in the art.

[0091] In some alternative embodiments, the temperature of the alkaline solution used for alkaline texturing can be 70°C to 90°C, such as 70°C, 75°C, 80°C, 85°C or 90°C, or other values ​​within the range of 70°C to 90°C.

[0092] The processing time for alkali texturing can be 480s to 520s, such as 480s, 485s, 490s, 495s, 500s, 505s, 510s, 515s, or 520s, or other values ​​within the range of 480s to 520s.

[0093] The etching amount of alkali texturing can be 0.5g to 0.7g, such as 0.5g, 0.55g, 0.6g, 0.65g or 0.7g, or other values ​​within the range of 0.5g to 0.7g.

[0094] The surface reflectivity of the texturized N-type silicon substrate can be 8.5% to 10%, such as 8.5%, 9%, 9.5% or 10%, or other values ​​within the range of 8.5% to 10%.

[0095] By fabricating the fabric using the above method, a better anti-reflective effect on the front side can be obtained.

[0096] S8: AlO2 is deposited on both the back and front sides of the product after the front alkaline texturing is completed. x Layer, then deposit SiN separately x layer.

[0097] In some alternative implementations, the front AlO x Layer 2 and back AlO x The thickness of layer 6 can be independently 2nm to 11nm, such as 2nm, 4nm, 6nm, 8nm, 10nm or 11nm, or other values ​​within the range of 2nm to 11nm.

[0098] In some alternative implementations, the back side SiN x The thickness of layer 7 can be 70nm to 85nm, such as 70nm, 72nm, 75nm, 78nm, 80nm, 82nm or 85nm, or other values ​​within the range of 70nm to 85nm.

[0099] Backside SiN x The refractive index of layer 7 can be 1.92% to 2.32%, such as 1.92%, 1.95%, 2%, 2.05%, 2.1%, 2.15%, 2.2%, 2.25%, 2.3%, or 2.32%, or other values ​​within the range of 1.92% to 2.32%.

[0100] In some alternative implementations, the front-side SiN x The thickness of layer 3 can be 75nm to 90nm, such as 75nm, 78nm, 80nm, 82nm, 85nm, 88nm or 90nm, or other values ​​in the range of 75nm to 90nm.

[0101] Front SiN x The refractive index of layer 3 can be 1.9% to 2.1%, such as 1.9%, 1.92%, 1.95%, 2%, 2.05% or 2.1%, or other values ​​within the range of 1.9% to 2.1%.

[0102] S9: Performs screen printing, light injection, and laser-assisted sintering.

[0103] Accordingly, the TBC battery prepared by the above-described preparation method provided by the present invention comprises:

[0104] N-type silicon substrate 1;

[0105] Front-side AlO2 is sequentially arranged from the inside to the outside on the front side of the N-type silicon substrate 1. x Layer 2 and front SiN x Layer 3;

[0106] P-type doped regions and N-type doped regions are disposed on the back side of the N-type silicon substrate 1, with N-type doped regions on both sides of the P-type doped region; wherein, the N-type doped region is provided with a tunneling oxide layer 9, an N-type polycrystalline silicon layer 10, and a back AlO layer from the inside to the outside. x Layer 6 and back SiN x Layer 7; The P-type doped region is provided with, from the inside out, a tunneling layer 4, a P-type polysilicon layer 5, and a back AlO layer. x Layer 6 and back SiN x Layer 7;

[0107] The P-type doped region also has a first gate electrode 8, which passes through the back SiN. x Layer 7 and back AlO x Layer 6 is in direct contact with the P-type polysilicon layer 5; the N-type doped region also has a second gate electrode 11, which passes through the back SiN layer. x Layer 7 and back AlO x Layer 6 is in direct contact with the N-type polysilicon layer 10.

[0108] Specifically, the first gate electrode 8 is located in the back-side P-type doped region and is fabricated using silver paste or silver-aluminum paste; this electrode serves as the emitter electrode. The first gate electrode 8 penetrates the back-side SiN... x Layer 7 and back AlO x Layer 6 is in direct contact with P-type polycrystalline silicon layer 5 (later laser-assisted sintering can be used, or a pre-film opening scheme can be added to reduce contact resistance).

[0109] The second gate electrode 11 is located in the back N-type doped region and is fabricated using silver paste. This electrode serves as the back field electrode. The second gate electrode 11 passes through the back SiN... x Layer 7 and back AlO x Layer 6 is in direct contact with N-type polycrystalline silicon layer 10 (later laser-assisted sintering can be combined with a pre-film opening scheme to reduce contact resistance).

[0110] In some alternative embodiments, the doping concentration of the polysilicon in the P-type polysilicon layer 5 and the N-type polysilicon layer 10 can be independently 5 × 10⁻⁶. 18 / cm 3 ~9×10 20 / cm 3 For example, 5×10 18 / cm 3 7.5×10 18 / cm 3 1×10 19 / cm 3 5×10 19 / cm 3 1×10 20 / cm3 2×10 20 / cm 3 5×10 20 / cm 3 7.5×10 20 / cm 3 Or 9×10 20 / cm 3 Etc., can also be 5×10 18 / cm 3 ~9×10 20 / cm 3 Other values ​​within the range.

[0111] In some alternative embodiments, the crystallinity of the polysilicon in the P-type polysilicon layer 5 and the N-type polysilicon layer 10 can be independently 80% to 100%, such as 80%, 85%, 90%, 95% or 100%, or other values ​​in the range of 80% to 100%.

[0112] In some alternative embodiments, the doping concentration gradient range of the tunneling oxide layer 9 can be 5 × 10⁻⁶. 15 / cm 3 ~5×10 20 / cm 3 For example, 5×10 15 / cm 3 7.5×10 15 / cm 3 1×10 16 / cm 3 5×10 16 / cm 3 1×10 17 / cm 3 5×10 17 / cm 3 1×10 18 / cm 3 5×10 18 / cm 3 1×10 19 / cm 3 5×10 19 / cm 3 1×10 20 / cm 3 Or 5×10 15 / cm 3 Etc., can also be 5×10 15 / cm 3 ~5×10 20 / cm 3 Other values ​​within the range.

[0113] In some alternative implementations, the width of the N-type doped region (denoted as Wn) can be 150 μm to 800 μm, such as 150 μm, 200 μm, 300 μm, 400 μm, 500 μm, 600 μm, 700 μm or 800 μm, or other values ​​within the range of 150 μm to 800 μm.

[0114] The width of the P-type doped region (denoted as Wp) can be 2 to 5 times the width of the N-type doped region, such as 2 times, 2.5 times, 3 times, 3.5 times, 4 times, 4.5 times or 5 times, or other values ​​within the range of 2 to 5 times.

[0115] The width of the isolation band between the N-type doped region and the P-type doped region is denoted as Wq. This isolation distance can be 2μm, 5μm, 8μm, 12μm, 16μm, 20μm, 25μm or 30μm, or other values ​​in the range of 2μm to 30μm.

[0116] It should be noted that when Wn is constant, the width Wp of the adjacent emitter region decreases. The reduction in emitter region size leads to a decrease in the probability of minority carrier collection, thereby affecting the short-circuit current Jsc density of the battery. When Wn is constant, the width Wp of the adjacent emitter region increases. More electrons above the emitter region need to be transported laterally to the back field electrode for collection. This process increases the series resistance of the battery, resulting in a decrease in the fill factor. By controlling the width relationship between Wp and Wn within the above range, this invention can achieve better conversion efficiency.

[0117] Continuing from the above, the fabrication method provided by this invention does not involve a boron diffusion layer on the front side, nor does it employ a pre-texturing process (i.e., texturing is the first step). In this invention, the front surface of the silicon substrate has no doped layer, only a passivation layer; the technical route uses a post-texturing method. Furthermore, the back-side P+ mask is formed using a doped BSG layer, eliminating the need for a pre-SiN coating step. The method provided by this invention successfully upgrades existing TOPCon cell production line equipment, making it suitable for TBC cell fabrication, significantly reducing equipment investment and production costs, simplifying the process flow, and improving production efficiency. It represents the best solution for upgrading Topcon technology using the 4% PVD route in the market.

[0118] The features and performance of the present invention will be further described in detail below with reference to embodiments.

[0119] Example 1

[0120] This embodiment provides a TBC battery, combined with Figure 1 It includes:

[0121] N-type silicon substrate 1;

[0122] Front-side AlO2 is sequentially arranged from the inside to the outside on the front side of the N-type silicon substrate 1. x Layer 2 and front SiN x Layer 3;

[0123] P-type doped regions and N-type doped regions are disposed on the back side of the N-type silicon substrate 1, with N-type doped regions on both sides of the P-type doped region; wherein, the N-type doped region is provided with a tunneling oxide layer 9, an N-type polycrystalline silicon layer 10, and a back AlO layer from the inside to the outside. x Layer 6 and back SiN x Layer 7; The P-type doped region is provided with, from the inside out, a tunneling layer 4, a P-type polysilicon layer 5, and a back AlO layer. x Layer 6 and back SiN x Layer 7;

[0124] The P-type doped region also has a first gate electrode 8, which passes through the back SiN. x Layer 7 and back AlO x Layer 6 is in direct contact with the P-type polysilicon layer 5; the N-type doped region also has a second gate electrode 11, which passes through the back SiN layer. x Layer 7 and back AlO x Layer 6 is in direct contact with the N-type polysilicon layer 10.

[0125] Example 2

[0126] This invention provides a method for preparing the TBC battery in Example 1, combined with Figure 2 ,include:

[0127] S1: On the back side of the alkaline polished N-type silicon substrate 1, a tunneling layer 4 and a polycrystalline silicon layer are sequentially deposited using LPCVD.

[0128] The alkaline polishing solution consisted of water, KOH aqueous solution, and additives in a volume ratio of 345:16:4.5, with a KOH mass concentration of 2%. The alkaline polishing solution was kept at 60°C for 240 seconds, with an etching amount of 0.25g. The surface reflectivity of the N-type silicon substrate 1 after alkaline polishing was approximately 40%.

[0129] The thickness of the tunneling layer 4 is 1.5 nm, and the thickness of the polycrystalline silicon layer is 200 nm.

[0130] S2: Boron doping is performed by boron diffusion. After the boron diffusion is completed, high-temperature oxidation is carried out to form a borosilicate glass layer (BSG layer) as a mask for the P-region.

[0131] The boron doping temperature is 1000℃, the thickness of the borosilicate glass layer is 60nm, and the sheet resistance of the borosilicate glass layer is 400Ω / sq.

[0132] S3: A green picosecond laser is used for laser etching to form a P-type doped region on the back side and etched regions on both sides of the P-type doped region. The mask borosilicate glass layer and the P-type doped layer of the two etched regions are removed. The remaining P-type doped layer forms a PN junction with the N-type silicon substrate 1.

[0133] The laser etching power is 120W, and the laser etching frequency is 500KHz.

[0134] S4: Perform alkaline washing on the etched area to remove the residual P-type doped layer and borosilicate glass layer, exposing the N-type silicon substrate (preferably exposing a flat N-type silicon substrate).

[0135] The alkaline solution used for alkaline cleaning consists of water, KOH aqueous solution, and polishing additives in a volume ratio of 350:16:4. The mass concentration of KOH in the KOH aqueous solution is approximately 2%. The temperature of the alkaline solution used for alkaline cleaning is 60℃, the cleaning time is 130s, and the etching angle after alkaline cleaning is 40°.

[0136] S5: On the back side of the alkaline-washed N-type silicon substrate, a tunneling oxide layer 9 and a phosphorus-doped N-type doped layer (N+ amorphous silicon layer) are precisely deposited using PVD deposition.

[0137] The thickness of the tunneling oxide layer 9 is 1.5 nm, and the thickness of the phosphorus-doped N-type doped layer is 200 nm.

[0138] S6: High-temperature annealing process is used to crystallize the amorphous silicon doped in the P-type doped layer and the N-type doped layer.

[0139] The crystallization treatment temperature was 850℃, and the crystallization treatment time was 85 minutes.

[0140] S7: Use an acid cleaning solution to clean the borosilicate glass layer on the back side of the product after crystallization and remove the front side coating, thus completing the front side alkaline texturing.

[0141] The acid cleaning solution consists of HF, HNO3, H2SO4, and H2O in a volume ratio of 12:30:6:19. The alkaline solution used for front-side alkaline texturing consists of water, KOH aqueous solution, and texturing additives in a volume ratio of 354:5.5:2. The mass concentration of KOH in the KOH aqueous solution is approximately 1%.

[0142] The temperature of the alkaline solution used for alkaline texturing is 80℃, the processing time for alkaline texturing is 500s, the etching amount for alkaline texturing is 0.6g, and the surface reflectivity of the N-type silicon substrate 1 after texturing on the front side is 9%.

[0143] S8: AlO2 is deposited on both the back and front sides of the product after the front alkaline texturing is completed. x Layer, then deposit SiN separately x layer.

[0144] Among them, the front AlO x Layer 2 and back AlO x Layer 6 is 5nm thick, with SiN on the back side. x Layer 7 has a thickness of 80nm and is backed by SiN. x Layer 7 has a refractive index of 2%, and the front side is SiN. x Layer 3 has a thickness of 80nm and is a SiN layer on the front side. x The refractive index of layer 3 is 2%.

[0145] S9: Screen printing, light injection, and laser-assisted sintering are performed on the products that have completed the deposition process.

[0146] The first gate electrode 8 is prepared by screen printing with silver paste, and the second gate electrode 11 is prepared by screen printing with silver paste.

[0147] In both the P-type polysilicon layer 5 and the N-type polysilicon layer 10 described above, the doping concentration of the polysilicon is 5 × 10⁻⁶. 19 / cm 3 The crystallinity of the polycrystalline silicon is 90%. The doping concentration of the tunneling oxide layer 9 is 5 × 10⁻⁶. 18 / cm 3 The width of the N-type doped region (denoted as Wn) is 200 μm, and the width of the P-type doped region (denoted as Wp) is four times the width of the N-type doped region (800 μm). The width of the isolation band Wq between the N-type and P-type doped regions is 8 μm.

[0148] Example 3

[0149] The difference between this embodiment and Embodiment 2 is as follows:

[0150] S1: On the back side of the alkaline polished N-type silicon substrate 1, a tunneling layer 4 and a polycrystalline silicon layer are sequentially deposited using LPCVD.

[0151] The alkaline polishing solution consisted of water, KOH aqueous solution, and additives in a volume ratio of 340:14:4, with a KOH mass concentration of 1.5%. The alkaline polishing solution was kept at 50°C for 270 seconds, with an etching amount of 0.2 g. The surface reflectivity of the N-type silicon substrate 1 after alkaline polishing was approximately 35%.

[0152] The thickness of the tunneling layer 4 is 1.2 nm, and the thickness of the polycrystalline silicon layer is 150 nm.

[0153] S2: Boron doping is performed by boron diffusion. After the boron diffusion is completed, high-temperature oxidation is carried out to form a borosilicate glass layer (BSG layer) as a mask for the P-region.

[0154] The boron doping temperature is 900℃, the thickness of the borosilicate glass layer is 50nm, and the sheet resistance of the borosilicate glass layer is 300Ω / sq.

[0155] S3: A green picosecond laser is used for laser etching to form a P-type doped region on the back side and etched regions on both sides of the P-type doped region. The mask borosilicate glass layer and the P-type doped layer of the two etched regions are removed. The remaining P-type doped layer forms a PN junction with the N-type silicon substrate 1.

[0156] The laser etching power is 115W, and the laser etching frequency is 475KHz.

[0157] S4: Perform alkaline washing on the etched area to remove the residual P-type doped layer and borosilicate glass layer, exposing the N-type silicon substrate (preferably exposing a flat N-type silicon substrate).

[0158] The alkaline solution used for alkaline cleaning consists of water, KOH aqueous solution, and polishing additives in a volume ratio of 345:14:3. The mass concentration of KOH in the KOH aqueous solution is approximately 1.5%. The temperature of the alkaline solution used for alkaline cleaning is 50℃, the cleaning time is 95 seconds, and the etching angle after alkaline cleaning is 15°.

[0159] S5: On the back side of the alkaline-washed N-type silicon substrate, a tunneling oxide layer 9 and a phosphorus-doped N-type doped layer (N+ amorphous silicon layer) are precisely deposited using PVD deposition.

[0160] The thickness of the tunneling oxide layer 9 is 1.2 nm, and the thickness of the phosphorus-doped N-type doped layer is 150 nm.

[0161] S6: High-temperature annealing process is used to crystallize the amorphous silicon doped in the P-type doped layer and the N-type doped layer.

[0162] The crystallization treatment temperature was 800℃ and the crystallization treatment time was 100min.

[0163] S7: Use an acid cleaning solution to clean the borosilicate glass layer on the back side of the product after crystallization and remove the front side coating, thus completing the front side alkaline texturing.

[0164] The acid cleaning solution consists of HF, HNO3, H2SO4, and H2O in a volume ratio of 12:30:6:19. The alkaline solution used for front-side alkaline texturing consists of water, KOH aqueous solution, and texturing additives in a volume ratio of 350:5:1.5. The mass concentration of KOH in the KOH aqueous solution is approximately 0.8%.

[0165] The temperature of the alkaline solution used for alkaline texturing was 70℃, the processing time for alkaline texturing was 520s, the etching amount for alkaline texturing was 0.5g, and the surface reflectivity of the N-type silicon substrate 1 after texturing on the front side was 8.5%.

[0166] S8: AlO2 is deposited on both the front and back sides of the product after the front alkaline texturing is completed. x Layer, then deposit SiN respectively x layer.

[0167] Among them, the front AlO x Layer 2 and back AlO x Layer 6 is 2nm thick, with SiN on the back side. x Layer 7 has a thickness of 70nm and a backside SiN layer. x Layer 7 has a refractive index of 1.92% and is a front-side SiN layer. x Layer 3 has a thickness of 75nm and is a SiN layer on the front side. x The refractive index of layer 3 is 1.9%.

[0168] S9: Screen printing, light injection, and laser-assisted sintering are performed on the products that have completed the deposition process.

[0169] The first gate electrode 8 is prepared by screen printing using silver-aluminum paste, and the second gate electrode 11 is prepared by screen printing using silver paste.

[0170] In both the P-type polysilicon layer 5 and the N-type polysilicon layer 10, the polysilicon doping concentration is 5 × 10⁻⁶. 18 / cm 3 The crystallinity of the polycrystalline silicon is approximately 80%. The doping concentration of the tunneling oxide layer 9 is 5 × 10⁻⁶. 15 / cm 3 The width of the N-type doped region (denoted as Wn) is 180 μm, and the width of the P-type doped region (denoted as Wp) is 5 times the width of the N-type doped region (900 μm). The width of the isolation band Wq between the N-type and P-type doped regions is 8 μm.

[0171] Example 4

[0172] The difference between this embodiment and Embodiment 2 is as follows:

[0173] S1: On the back side of the alkaline polished N-type silicon substrate 1, a tunneling layer 4 and a polycrystalline silicon layer are sequentially deposited using LPCVD.

[0174] The alkaline polishing solution consisted of water, KOH aqueous solution, and additives in a volume ratio of 350:18:5, with a KOH mass concentration of 2.5%. The alkaline polishing solution was kept at a temperature of 70°C, the polishing time was 200 seconds, the etching amount was 0.3 g, and the surface reflectivity of the N-type silicon substrate 1 after alkaline polishing was approximately 45%.

[0175] The thickness of the tunneling layer 4 is 1.8 nm, and the thickness of the polycrystalline silicon layer is 250 nm.

[0176] S2: Boron doping is performed by boron diffusion. After the boron diffusion is completed, high-temperature oxidation is carried out to form a borosilicate glass layer (BSG layer) as a mask for the P-region.

[0177] The boron doping temperature is 1035℃, the thickness of the borosilicate glass layer is 70nm, and the sheet resistance of the borosilicate glass layer is 450Ω / sq.

[0178] S3: A green picosecond laser is used for laser etching to form a P-type doped region on the back side and etched regions on both sides of the P-type doped region. The mask borosilicate glass layer and the P-type doped layer of the two etched regions are removed. The remaining P-type doped layer forms a PN junction with the N-type silicon substrate 1.

[0179] The laser etching power is 125W, and the laser etching frequency is 525KHz.

[0180] S4: Perform alkaline washing on the etched area to remove the residual P-type doped layer and borosilicate glass layer, exposing the N-type silicon substrate (preferably exposing a flat N-type silicon substrate).

[0181] The alkaline solution used for alkaline cleaning consists of water, KOH aqueous solution, and polishing additives in a volume ratio of 355:18:5. The mass concentration of KOH in the KOH aqueous solution is approximately 2.5%. The temperature of the alkaline solution used for alkaline cleaning is 70℃, the cleaning time is 160s, and the etching angle after alkaline cleaning is 60°.

[0182] S5: On the back side of the alkaline-washed N-type silicon substrate, a tunneling oxide layer 9 and a phosphorus-doped N-type doped layer (N+ amorphous silicon layer) are precisely deposited using PVD deposition.

[0183] The thickness of the tunneling oxide layer 9 is 1.7 nm, and the thickness of the phosphorus-doped N-type doped layer is 220 nm.

[0184] S6: High-temperature annealing process is used to crystallize the amorphous silicon doped in the P-type doped layer and the N-type doped layer.

[0185] The crystallization treatment temperature was 920℃ and the crystallization treatment time was 70 minutes.

[0186] S7: Use an acid cleaning solution to clean the borosilicate glass layer on the back of the product after crystallization and remove the front-side plating, thus completing the front-side alkaline texturing.

[0187] The acid cleaning solution consists of HF, HNO3, H2SO4, and H2O in a volume ratio of 12:30:6:19. The alkaline solution used for front-side alkaline texturing consists of water, KOH aqueous solution, and texturing additives in a volume ratio of 360:6:2.5. The mass concentration of KOH in the KOH aqueous solution is approximately 1.2%.

[0188] The temperature of the alkaline solution used for alkaline texturing was 90℃, the processing time for alkaline texturing was 480s, the etching amount for alkaline texturing was 0.7g, and the surface reflectivity of the N-type silicon substrate 1 after texturing on the front side was 10%.

[0189] S8: AlO2 is deposited on both the front and back sides of the product after the front alkaline texturing is completed. x Layer, then deposit SiN respectively x layer.

[0190] Among them, the front AlO x Layer 2 and back AlO x Layer 6 is 11nm thick, with SiN on the back side. x Layer 7 has a thickness of 85nm and a backside SiN layer. x Layer 7 has a refractive index of 2.32% and is a front-side SiN layer. x Layer 3 has a thickness of 90nm and is a SiN layer on the front side. x The refractive index of layer 3 is 2.1%.

[0191] S9: Screen printing, light injection, and laser-assisted sintering are performed on the products that have completed the deposition process.

[0192] The first gate electrode 8 is prepared by screen printing with silver paste, and the second gate electrode 11 is prepared by screen printing with silver paste.

[0193] In both the P-type polysilicon layer 5 and the N-type polysilicon layer 10, the polysilicon doping concentration is 9 × 10⁻⁶. 20 / cm 3 The crystallinity of the polycrystalline silicon is 100%. The doping concentration of tunnel oxide layer 9 is 5 × 10⁻⁶. 20 / cm 3 The width of the N-type doped region (denoted as Wn) is 220 μm, and the width of the P-type doped region (denoted as Wp) is twice the width of the N-type doped region (440 μm). The width of the isolation band Wq between the N-type and P-type doped regions is 8 μm.

[0194] Test case

[0195] The TBC cells prepared in Examples 2-4 were subjected to performance testing. Specifically, the open-circuit voltage (Voc), short-circuit current (Isc), series resistance (Rs), parallel resistance (Rsh), fill factor (FF), and photoelectric conversion efficiency (Ncell) of the TBC cells after light injection were tested using the Halm online IV testing system under the conditions of 25°C, AM1.5, and one standard sun. The results are shown in Table 1.

[0196] Table 1 Test Results

[0197]

[0198] As can be seen from Table 1, the TBC battery prepared by the method provided by the present invention has high open-circuit voltage, short-circuit current, fill factor and photoelectric conversion efficiency, indicating that the method provided by the present invention can be implemented and promoted.

[0199] In summary, the fabrication method provided by this invention does not involve a boron diffusion layer on the front side, nor does it employ a pre-texturing process (i.e., texturing is the first step). The front surface of the silicon substrate in this invention has no doped layer, only a passivation layer, and its technical approach uses a post-texturing method. Furthermore, the back-side P+ mask is formed using a doped BSG layer, eliminating the need for a pre-SiN coating step. The method provided by this invention successfully upgrades existing TOPCon cell production line equipment, making it suitable for TBC cell fabrication, significantly reducing equipment investment and production costs, simplifying the process flow, and improving production efficiency. It represents the best solution for upgrading Topcon technology using the 4% PVD route in the market.

[0200] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for preparing a TBC battery, characterized in that, Includes the following steps: On the back side of an alkaline-polished N-type silicon substrate, a tunneling layer and a polycrystalline silicon layer are deposited sequentially; then boron doping and high-temperature oxidation are performed to form a borosilicate glass layer that serves as a mask for the P-region. Laser etching is then performed to form a P-type doped region on the back side and etched regions on both sides of the P-type doped region; The etched area is subjected to alkaline washing to remove the residual P-type doped layer and borosilicate glass layer, exposing the N-type silicon substrate. A tunneling oxide layer and a phosphorus-doped N-type doped layer are sequentially deposited on the back side of the alkaline-washed N-type silicon substrate. Crystallization treatment was performed on the amorphous silicon doped in the P-type and N-type doped layers; After crystallization, the borosilicate glass layer on the back of the product is cleaned to remove the wrap-around plating on the front and complete the alkaline texturing on the front. AlO was deposited on both the front and back sides of the product after the front side was alkali-textured. x Layer, then deposit SiN separately x The layers are then screen-printed, light-injected, and laser-assisted sintering is performed.

2. The preparation method according to claim 1, characterized in that, The temperature for boron doping is 900℃~1035℃.

3. The preparation method according to claim 1, characterized in that, The laser etching power is 90W to 130W, and the frequency is 475KHz to 525KHz.

4. The preparation method according to claim 1, characterized in that, A tunneling oxide layer and a phosphorus-doped N-type doped layer were deposited using PVD deposition.

5. The preparation method according to claim 1, characterized in that, The crystallization temperature is 800℃~920℃, and the crystallization time is 70min~100min.

6. The preparation method according to claim 1, characterized in that, The temperature of the alkaline solution used for alkaline polishing is 50℃~70℃; the alkaline polishing time is 200s~270s; and the etching amount for alkaline polishing is 0.2g~0.3g. And / or, the temperature of the alkaline solution used for alkaline washing is 50℃~70℃; the alkaline washing time is 95s~160s; and the etching angle after alkaline washing is 15°~60°. And / or, the temperature of the alkaline solution used for alkaline texturing is 70℃~90℃, the processing time for alkaline texturing is 480s~520s, the etching amount for alkaline texturing is 0.5g~0.7g, and the surface reflectivity of the N-type silicon substrate after texturing is 8.5%~10%.

7. A TBC battery, characterized in that, It is prepared by the preparation method according to any one of claims 1 to 6.

8. The TBC battery according to claim 7, characterized in that, The TBC battery includes: N-type silicon substrate; The front AlO groups are sequentially arranged from the inside to the outside on the front side of the N-type silicon substrate. x Layer and front SiN x layer; A P-type doped region and an N-type doped region are disposed on the back side of the N-type silicon substrate, with the N-type doped region disposed on both sides of the P-type doped region; wherein, the N-type doped region is provided with a tunneling oxide layer, an N-type polycrystalline silicon layer, and a back AlO layer sequentially from the inside to the outside. x Layer and back SiN x The P-type doped region is provided with, from the inside out, a tunneling layer, a P-type polysilicon layer, and a back AlO layer. x Layer and back SiN x layer; The P-type doped region is also provided with a first gate electrode, which passes through the back SiN. x Layer and back AlO x The layer is in direct contact with the P-type polycrystalline silicon layer; the N-type doped region is also provided with a second gate electrode, which passes through the back SiN layer. x Layer and back AlO x The layer is in direct contact with the N-type polycrystalline silicon layer.

9. The TBC battery according to claim 8, characterized in that, The TBC battery includes at least one of the following features: Feature 1: The thickness of the tunneling layer is 1.2 nm to 1.8 nm; Feature 2: The thickness of the polycrystalline silicon layer is 150nm to 300nm; Feature 3: The thickness of the borosilicate glass layer is 50nm to 70nm; Feature 4: The sheet resistance of the borosilicate glass layer is 300Ω / sq to 450Ω / sq; Feature 5: The thickness of the tunneling oxide layer is 1.2 nm to 2 nm; Feature 6: The thickness of the phosphorus-doped N-type doped layer is 150 nm to 250 nm; Feature 7: The frontal AlO x Layer and the back side AlO x The thickness of the layer is independently 2nm to 11nm; Feature 8: The back side SiN x The thickness of the layer is 70nm to 85nm; Feature 9: The back side SiN x The refractive index of the layer is 1.92%–2.32%; Feature 10: The front-side SiN x The thickness of the layer is 75nm to 90nm; Feature 11: The front-side SiN x The refractive index of the layer is 1.9% to 2.1%.

10. The TBC battery according to claim 8 or 9, characterized in that, The TBC battery also includes at least one of the following features: Feature 12: In both the P-type and N-type polycrystalline silicon layers, the doping concentration of the polycrystalline silicon is independently 5 × 10⁻⁶. 18 / cm 3 ~9×10 20 / cm 3 ; feature 13: In the P-type polycrystalline silicon layer and the N-type polycrystalline silicon layer, the crystallinity of the polycrystalline silicon is independently 80% to 100%; Feature 14: The doping concentration of the tunneling oxide layer gradually varies within a range of 5 × 10⁻⁶. 15 / cm 3 ~5×10 20 / cm 3 ; feature 15: The width of the N-type doped region is 180μm to 220μm, and the width of the P-type doped region is 2 to 5 times the width of the N-type doped region.

Images