Pseudo-random sequence generation method and device, and medium
By using the digital root method and Galois field polynomials to generate pseudo-random sequences within the processor, the problem of wasted storage and bandwidth resources in existing technologies is solved, achieving efficient pseudo-random sequence generation and reducing computational latency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-25
- Publication Date
- 2026-04-21
AI Technical Summary
The pseudo-random sequence generation method in existing communication protocols needs to be stored in the cache in advance, which leads to a waste of storage and bandwidth resources and cannot meet the processing latency requirements.
Using the digital root method and Galois field polynomials, pseudo-random sequences are generated in real time inside the processor through modular and matrix operations. Parallel computing is achieved using a two-dimensional generator matrix, avoiding waste of storage and bandwidth resources.
It reduces the computational latency of pseudo-random sequence generation, saves storage and bandwidth resources, and meets the processor's real-time generation requirements.
Smart Images
Figure CN121900724A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of communication technology, and in particular to a method, device and medium for generating pseudo-random sequences. Background Technology
[0002] In existing wireless or wired communications, the data to be transmitted needs to be additively scrambled before transmission to increase robustness and reliability. In some wireless communications, a specific reference signal is often added to the data stream to facilitate reception. This reference signal is often generated using pseudo-random m-sequences or gold sequences. The initial values and initial offsets used in generating pseudo-random sequences vary. Current communication protocols only provide serial generation methods for each gold sequence; however, serial generation cannot meet the design requirements for processing latency in many scenarios.
[0003] To solve the above problems, the current common practice is to generate the gold sequence in advance and store it in SRAM or DDRRAM. When the application is needed, the data is read from SRAM or DDRRAM and then read into the corresponding processor. However, the data needs to be extracted based on the initial offset, which wastes cache space, valuable bus bandwidth and processing power. Summary of the Invention
[0004] The technical problem to be solved by the present invention is to provide a method, device and medium for generating pseudo-random sequences, which can generate them in real time inside the processor, avoiding the waste of storage resources and bandwidth resources.
[0005] The technical solution adopted by this invention to solve its technical problem is: to provide a pseudo-random sequence generation method, including the following steps: Based on the primitive polynomial of the Galois field, the weight vectors of different powers are calculated through modular arithmetic to obtain the bit weight value of each bit and construct a one-dimensional weight matrix. The offset value is decomposed into multiple powers of 2 and summed. The initial vector at the offset position is obtained by combining the bit weight value at each bit position. Based on the generation bit width requirement, the one-dimensional weight matrix is extended into a two-dimensional generation matrix based on the principle of the digital root method. Based on the two-dimensional generation matrix, the matrix under different bit weights is recursively calculated using matrix exponentiation operations, thereby generating a weight matrix under different processing bit widths. The pseudo-random sequence starting point is generated by multiplying the initial vector at the offset position with the weight matrix under different processing bit widths; Using a recursive formula, a pseudo-random sequence is generated starting from the origin of the pseudo-random sequence.
[0006] The modular arithmetic is represented as: ,in, For the first The bit weight value at the bit position. The primitive polynomial of the Galois field is expressed as: , These are the generating coefficients of the primitive polynomial.
[0007] The two-dimensional generator matrix is represented as follows: ,in, It is a two-dimensional generating matrix. These are the generating coefficients of the primitive polynomial.
[0008] The weight matrix under different processing bit widths is represented as follows: ,in, For the first Weight matrix with bit width It is a two-dimensional generating matrix.
[0009] The recursive formula is expressed as follows: ,in, for A pseudo-random sequence at time t. For bit width The weight matrix below.
[0010] The technical solution adopted by the present invention to solve its technical problem is: to provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the above-mentioned pseudo-random sequence generation method.
[0011] The technical solution adopted by the present invention to solve its technical problem is: to provide a computer-readable storage medium on which a computer program is stored, wherein the computer program, when executed by a processor, implements the steps of the above-mentioned pseudo-random sequence generation method.
[0012] Beneficial effects Due to the adoption of the above technical solution, the present invention has the following advantages and positive effects compared with the prior art: The present invention completes the one-dimensional to two-dimensional conversion of different m-sequence generation matrices based on the digital root method, and transforms the serial structure defined by the protocol into a two-dimensional parallel structure with different processing bit widths. This method can realize parallel computing, reduce the computational latency when generating pseudo-random sequences, and avoid the waste of storage resources and bandwidth resources. Attached Figure Description
[0013] Figure 1 This is a flowchart of the pseudo-random sequence generation method according to the first embodiment of the present invention. Detailed Implementation
[0014] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.
[0015] The first embodiment of the present invention relates to a pseudo-random sequence generation method that utilizes the principle of modulo operation using the number root method.
[0016] The digit root method is a classic concept in the decimal system, used in fast calculations up to the modulo 9 level. The essence of the digit root is to add the decimal digits together to obtain a single digit. If this digit is 9, then the modulo 9 is 0; otherwise, the modulo 9 equals the digit. For example, for the decimal number 1234, the first summation is performed: 1 + 2 + 3 + 4 = 10. Since 10 > 9, a second summation is performed: 1 + 0 = 1. Since 1 < 9, the calculation ends, and the final modulo value is 1.
[0017] Extending this concept and data principle to the process of modulo 3 in binary numbers, taking modulo 3 as an example, we calculate the weight of each bit in modulo 3 for each binary number. Assuming the input binary number is 8 bits, the weight of each bit is... The weights are 1, 2, 4, 8, ..., 128. Taking these weights modulo 3 yields remainders of 1, 2, 1, 2, 1, 2, 1, 2. According to number theory, 2 = -1 mod 3. Therefore, the weight of each bit in the 8-bit number can be equivalently represented as 1, -1, 1, -1, 1, -1, 1, -1. For an input 8-bit binary number, the algorithm for taking the modulo 3 becomes the following formula: Mod(din,3) = {1'b0,din(0)} – {1'b0,din(1)} + … {1'b0,din(2)} – {1'b0,din(3)} + … {1'b0,din(4)} – {1'b0,din(5)} + … {1'b0,din(6)} – {1'b0,din(7)}.
[0018] For example, for din = 8'hff, the first summation is 1-1+1-1+...=0. Since 0<3, the remainder calculation ends, and the remainder is 0. Similarly, for din = 8'h07, the first summation is 0-0+0-0+1-0+1-1=1. Since 1<3, the remainder calculation ends, and the remainder is 1.
[0019] The pseudo-random sequence generation method in this embodiment applies the algorithm's idea and principle to the modulo operation of Galois binary polynomials. For any Galois primitive polynomial, there is a one-dimensional code generator polynomial as follows: ; in, These are the generating coefficients of the primitive polynomials, which are often 0 or 1 in the binary field. All Galois-field primitive polynomials are irreducible. The value is 1, and the cycle period is... .
[0020] like Figure 1 As shown, the pseudo-random sequence generation method of this embodiment includes the following steps: Step 1: Based on the primitive polynomial of the Galois field, calculate the weight vectors of different powers through modular arithmetic to obtain the bit weight value of each bit, and construct a one-dimensional weight matrix.
[0021] In practical applications, it is often necessary to generate pseudo-random sequences from offset positions. Therefore, we consider using the digital root method to obtain the initial offset value at the offset position. Assuming that the bit width required at the maximum offset position is n1 bits, we need to calculate the bit weight values from 0 bit, 1 bit, 2 bit to n1-1 bit. The calculation steps are as follows: calculate This yields the weight vector at bit 0. ;calculate This yields the weight vector at bit 1. ;calculate This yields the weight vector at the 2-bit position. ;calculate This yields the weight vector at the 3-bit position. And so on, until the final calculation. The weight vector at bit n1-1 is obtained. Construct a one-dimensional weight matrix based on the above vectors.
[0022] Step 2: Use binary decomposition to split the offset value into multiple powers of 2, and combine them with the bit weight value at each bit position to obtain the initial vector at the offset position.
[0023] In this step, any offset value is decomposed into binary enable signals with an n1-bit width. The offset value of the initial value under each bit weight is recursively calculated, and this value is used as the initial vector at the offset position. The calculation principle is as follows: After processing in steps 1 and 2, the initial vector at the offset position can be obtained, and the required pseudo-random sequence can be generated from the offset position.
[0024] Step 3: Based on the required bit width, the one-dimensional weight matrix is expanded into a two-dimensional generator matrix using the principle of the digital root method. This step converts the one-dimensional weight matrix into a two-dimensional matrix that actually generates the bit width. Taking the process of obtaining the two-dimensional weight matrix as an example, the calculation process is as follows: calculate Remainder vector ;calculate Remainder vector ;calculate Remainder vector And so on, until the calculation Remainder vector The above calculations yield a processing bit width of... The two-dimensional generator matrix is represented as follows: ; The number of rows represents the direction of parallelism expansion for processing bit width, and the number of columns represents the effective order of the polynomial. This matrix can be automatically expanded according to different processing bit widths.
[0025] Step 4: Based on the two-dimensional generation matrix, recursively calculate the matrix under different bit weights using matrix exponentiation operations to generate weight matrices under different processing bit widths.
[0026] After obtaining the two-dimensional generator matrix, the weights of other binary bits under different polynomials can be calculated recursively to obtain the weight matrix under different processing bit widths. The calculation formula is as follows: ; in, A value of 0 indicates the weight matrix at bit 0. An equal value of 1 indicates a weight matrix at position 1. The value is 2, representing the weight matrix at 2 bits.
[0027] For 3GPP, the first m-sequence has g0=g3=1, and the rest g1, g2, g4, ..., g30 are all equal to 0, corresponding to a 31-bit polynomial vector of 31'h9; the second m-sequence has g0=g1=g2=g3, and the rest g4, g5, ..., g30 are all equal to 0, corresponding to a 31-bit polynomial vector of 31'hF, with the highest order of both polynomials being 31; for the DVB S2X BB scrambling polynomial, it is an m-sequence with g0=g1=1, and the rest g2, g3, ..., g14 are all equal to 0, corresponding to a 15-bit polynomial vector of 15'h3, with a polynomial order of 15; for DVB... The S2X superframe scrambling polynomial has the following characteristics: the first m-sequence has g0=g3=1, and the rest g1, g2, g4, ..., g20 are all equal to 0, corresponding to a 20-bit polynomial vector of 20'h9; the second m-sequence has g0=g2=g11=g17, and the rest g1, g3, g4, ..., g20 are all equal to 0, corresponding to a 20-bit polynomial vector of 20'h20805; the polynomial order is 20.
[0028] Since the orders of each m-sequence are different, the design is based on the highest order of 31. Based on the known one-dimensional polynomial vectors 31'h9, 31'hF, 15'h3, 20'h9, 20'h20805, and different orders, bit weight matrices with different bit weights can be generated offline in advance or online and stored in the ASIC as a constant vector array. During online generation, multiplication is performed in the binary Galois field according to the polynomial order and the configured one-dimensional polynomial vector. During offline generation, Python tools can be used to obtain weight matrices with multiple bit widths according to the order of each polynomial and the one-dimensional polynomial vector, using matrix multiplication.
[0029] Step 5: Generate the pseudo-random sequence starting point by multiplying the initial vector at the offset position with the weight matrix under different processing bit widths.
[0030] Step 6: Using a recursive formula, generate a pseudo-random sequence starting from the beginning of the pseudo-random sequence, where the recursive formula is expressed as: ,in, for A pseudo-random sequence at time t. For bit width The weight matrix below.
[0031] It is not difficult to see that the present invention completes the one-dimensional to two-dimensional conversion of the generation matrix of different m-sequences based on the digital root method, transforming the serial structure defined by the protocol into a two-dimensional parallel structure with different processing bit widths. This method can realize parallel computing, reduce the computational latency when generating pseudo-random sequences, and avoid the waste of storage and bandwidth resources.
[0032] A second embodiment of the present invention relates to an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the pseudo-random sequence generation method of the first embodiment.
[0033] The third embodiment of the present invention relates to a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the pseudo-random sequence generation method of the first embodiment.
[0034] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage and optical storage) containing computer-usable program code.
[0035] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0036] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction methods implemented in a process. Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0037] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1The steps of the function specified in one or more boxes.
[0038] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A method for generating pseudo-random sequences, characterized in that, Includes the following steps: Based on the primitive polynomial of the Galois field, the weight vectors of different powers are calculated through modular arithmetic to obtain the bit weight value of each bit and construct a one-dimensional weight matrix. The offset value is decomposed into multiple powers of 2 and summed. The initial vector at the offset position is obtained by combining the bit weight value at each bit position. Based on the generation bit width requirement, the one-dimensional weight matrix is extended into a two-dimensional generation matrix based on the principle of the digital root method. Based on the two-dimensional generation matrix, the matrix under different bit weights is recursively calculated using matrix exponentiation operations, thereby generating a weight matrix under different processing bit widths. The pseudo-random sequence starting point is generated by multiplying the initial vector at the offset position with the weight matrix under different processing bit widths; Using a recursive formula, a pseudo-random sequence is generated starting from the origin of the pseudo-random sequence.
2. The pseudo-random sequence generation method according to claim 1, characterized in that, The modular arithmetic is represented as: ,in, For the first The bit weight value at the bit position. The primitive polynomial of the Galois field is expressed as: , These are the generating coefficients of the primitive polynomial.
3. The pseudo-random sequence generation method according to claim 1, characterized in that, The two-dimensional generator matrix is represented as follows: ,in, It is a two-dimensional generating matrix. These are the generating coefficients of the primitive polynomial.
4. The pseudo-random sequence generation method according to claim 1, characterized in that, The weight matrix under different processing bit widths is represented as follows: ,in, For the first Weight matrix with bit width It is a two-dimensional generating matrix.
5. The pseudo-random sequence generation method according to claim 1, characterized in that, The recursive formula is expressed as follows: ,in, for A pseudo-random sequence at time t. For bit width The weight matrix below.
6. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the pseudo-random sequence generation method as described in any one of claims 1-5.
7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the pseudo-random sequence generation method as described in any one of claims 1-5.