Heterogeneous computing core, computing method based on heterogeneous computing core and related equipment

Abstract

The invention provides a heterogeneous computing core, a computing method based on the heterogeneous computing core and related equipment, the heterogeneous computing core comprises a control module, a tensor computing module and a vector computing module which are mutually connected, and the control module, the tensor computing module and the vector computing module are respectively connected with an L1 cache; the control module is used for fetching, decoding, distributing and accessing the control instruction; the tensor calculation module is used for receiving a tensor type control instruction distributed by the control module and controlling a tensor calculation unit to read data from a tensor register for calculation; and the vector calculation module is used for receiving the vector type control instruction distributed by the control module and controlling the vector calculation unit to read data from the vector register for calculation. According to the heterogeneous computing core provided by the invention, a heterogeneous computing core group can be formed, interaction is carried out through the tensor registers in the heterogeneous computing core group, and under the condition that the L1 cache is limited, repeated memory access of different computing cores to the L2 cache is reduced.

Description

Technical Field

[0001] This invention relates to the field of computing chip technology, and in particular to a heterogeneous computing core, a computing method based on the heterogeneous computing core, and related equipment. Background Technology

[0002] The development of fields such as artificial intelligence is driving up the performance demands of AI computing chips, and the efficiency of data interaction between computing cores is crucial to their overall performance. In existing AI computing chip architectures, computing cores share an L2 cache, and data interaction between cores requires transmission to the L2 cache via an on-chip communication network, making L2 the core hub for interaction. However, the ever-increasing demand for on-chip computing resources from AI computing tasks, and the extreme pursuit of higher utilization of on-chip computing resources, conflict with the limited on-chip cache capacity. This has led to a surge in the amount of interaction between on-chip computing cores, placing immense pressure on the bandwidth of the on-chip communication network. Consequently, transmission latency has increased, computing throughput has been limited, and problems are more pronounced in high-frequency, small-granularity interaction scenarios. At the same time, the high bandwidth pressure has caused a surge in power consumption, and high-frequency L2 read / write operations further exacerbate the power burden, resulting in a significant increase in the deployment and application costs of the system. Summary of the Invention

[0003] This invention provides a heterogeneous computing core, a computing method based on the heterogeneous computing core, and related equipment to overcome the deficiencies in the prior art.

[0004] This invention provides a heterogeneous computing core, including a control module, a tensor computing module, and a vector computing module. The control module, the tensor computing module, and the vector computing module are interconnected, and each of the control module, the tensor computing module, and the vector computing module is connected to an L1 cache. The control module is used to fetch, decode, distribute, and access memory control instructions. The tensor calculation module includes a tensor calculation unit and a tensor register. The tensor calculation module is used to receive control instructions of tensor type distributed by the control module, and control the tensor calculation unit to read data from the tensor register for calculation. The vector calculation module includes a vector calculation unit and a vector register. The vector calculation module is used to receive control instructions of the vector type distributed by the control module, and control the vector calculation unit to read data from the vector register for calculation.

[0005] According to a heterogeneous computing core provided by the present invention, the heterogeneous computing core further includes a scalar computing module, the scalar computing module includes a scalar computing unit, a scalar register, and a scalar instruction scheduling unit, the scalar computing module is connected to the control module and the L1 cache respectively, and the scalar computing unit, the scalar register, and the scalar instruction scheduling unit are interconnected. The scalar instruction scheduling unit is used to receive scalar type control instructions distributed by the control module; The scalar register is used to store scalar type data; The scalar calculation module is used to perform calculations on the scalar type data based on the control instructions of the scalar type.

[0006] According to a heterogeneous computing core provided by the present invention, the tensor computing module further includes a tensor instruction scheduling unit and a tensor memory access unit. The tensor computing unit, the tensor register, and the tensor memory access unit are respectively connected to the instruction scheduling unit, and the tensor register is connected to the tensor computing unit. The tensor instruction scheduling unit is used to receive tensor-type control instructions distributed by the control module; The tensor memory access unit is used to access the control instructions of the tensor type. The tensor register is used to store tensor type data; The tensor calculation module is used to perform calculations on the tensor type data based on the control instructions of the tensor type.

[0007] According to a heterogeneous computing core provided by the present invention, the vector computing module further includes a vector instruction scheduling unit, and the vector computing unit, the vector register, and the vector instruction scheduling unit are interconnected. The vector instruction scheduling unit is used to receive vector-type control instructions distributed by the control module; The vector register is used to store vector type data; The vector calculation module is used to perform calculations on the vector type data based on the control instructions of the vector type.

[0008] According to a heterogeneous computing core provided by the present invention, the control module includes an instruction fetch and decode unit, a thread scheduling and dispatch unit, and a vector and tensor memory access unit connected in sequence. The thread scheduling and dispatch unit is connected to the tensor computing module and the vector computing module respectively, and the vector and tensor memory access unit is connected to the L1 cache. The instruction fetching and decoding unit is used to read control instructions from the instruction cache, decode the control instructions, and send the decoded control instructions to the thread scheduling and dispatching unit. The thread scheduling and distribution unit is used to distribute the control instructions to the tensor calculation module, the vector calculation module, or the vector and tensor memory access unit according to the instruction type of the control instructions. The vector and tensor memory access unit is used to receive control instructions distributed by the thread scheduling and distribution unit.

[0009] This invention also provides a computing method based on heterogeneous computing kernels, comprising: Obtain the calculation control instructions for matrix multiplication; Based on the computation control instructions, the heterogeneous computing core group is controlled to perform matrix multiplication operations to obtain the result matrix of the matrix multiplication operations; wherein, the heterogeneous computing core group includes 4 heterogeneous computing cores as described in any of the preceding items, and the tensor registers of each heterogeneous computing core are connected in the order of operation.

[0010] According to a computation method based on heterogeneous computing cores provided by the present invention, the step of controlling a heterogeneous computing core group to perform matrix multiplication operations based on the computation control instructions to obtain the result matrix of the matrix multiplication operations includes: The matrix multiplication is split to obtain multiple matrix multiplication fragments; Based on the computation control instructions, the heterogeneous computing core groups corresponding to each matrix multiplication piece are controlled to perform the corresponding matrix multiplication operations to obtain the result matrix; wherein, the heterogeneous computing core groups interact with each other based on the association relationship of the matrix multiplication pieces.

[0011] The present invention also provides a computing device based on heterogeneous computing cores, comprising: The acquisition module is configured to acquire calculation control instructions for matrix multiplication operations; The computing module is configured to control the heterogeneous computing core group to perform matrix multiplication operations based on the computing control instructions, and obtain the result matrix of the matrix multiplication operation; wherein, the heterogeneous computing core group includes 4 heterogeneous computing cores as described in any of the preceding items, and the tensor registers of each heterogeneous computing core are connected in the order of operation.

[0012] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the computing method based on heterogeneous computing cores as described above.

[0013] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the computing method based on heterogeneous computing cores as described above.

[0014] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the computing method based on heterogeneous computing cores as described above.

[0015] This invention provides a heterogeneous computing core, a computing method based on the heterogeneous computing core, and related equipment. The heterogeneous computing core control module and the independent backend vector computing module and tensor computing module are integrated. The frontend control module performs tasks such as instruction fetching, decoding, distribution, and memory access. The tensor computing module and vector computing module complete corresponding calculations based on the received control instructions. When the tensor computing module and vector computing module receive control instructions, they control the corresponding computing units (tensor computing units and vector computing units) to read data from their respective registers and perform effective calculations. The tensor registers and vector registers are used to store the direct operation data and intermediate results being processed by the corresponding tensor computing unit and vector computing unit. The heterogeneous computing cores provided by this invention can form heterogeneous computing core groups. Through the interaction of tensor registers in the heterogeneous computing core groups, the repeated memory accesses of different computing cores to the L2 cache are reduced when the L1 cache is limited. This reduces bandwidth pressure, memory access latency, and waiting of computing resources due to slow data loading, thereby improving the utilization of computing resources. The interaction between heterogeneous computing core groups through registers realizes the effective replacement of L1 cache by registers, reducing the dependence on L1 cache capacity. At the same time, it further reduces repeated memory accesses to the L2 cache. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is one of the structural schematic diagrams of the heterogeneous computing core provided by the present invention.

[0018] Figure 2 This is the second schematic diagram of the heterogeneous computing core provided by the present invention.

[0019] Figure 3 This is a flowchart illustrating the computation method based on heterogeneous computing kernels provided by the present invention.

[0020] Figure 4 This is a schematic diagram of matrix partitioning based on four heterogeneous computing cores provided by the present invention.

[0021] Figure 5 This is a schematic diagram of the structure of two heterogeneous computing core groups provided by the present invention.

[0022] Figure 6 This is a schematic diagram of the structure of the computing device based on heterogeneous computing cores provided by the present invention.

[0023] Figure 7This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0025] Figure 1 This is a structural diagram of a heterogeneous computing core according to an exemplary embodiment. For example... Figure 1 As shown, in an exemplary embodiment, the heterogeneous computing core includes a control module, a tensor computing module, and a vector computing module. The control module, the tensor computing module, and the vector computing module are interconnected, and each of the control module, the tensor computing module, and the vector computing module is connected to an L1 cache. The control module is used to fetch, decode, distribute, and access memory control instructions. The tensor calculation module includes a tensor calculation unit and a tensor register. The tensor calculation module is used to receive control instructions of tensor type distributed by the control module, and control the tensor calculation unit to read data from the tensor register for calculation. The vector calculation module includes a vector calculation unit and a vector register. The vector calculation module is used to receive control instructions of the vector type distributed by the control module, and control the vector calculation unit to read data from the vector register for calculation.

[0026] In this embodiment of the invention, the heterogeneous computing core includes a front-end control module and a back-end independent vector computation module and tensor computation module, such as... Figure 1 As shown. The front-end control module performs instruction pipeline tasks such as instruction fetching, decoding, dispatching, and memory access, while the back-end tensor calculation module and vector calculation module complete the corresponding calculations based on the received control instructions; When the tensor calculation module and vector calculation module receive the control command, they monitor the data storage status of the local registers (tensor register and vector register) and control the corresponding calculation units (tensor calculation unit and vector calculation unit) to read data from the registers and perform effective calculations.

[0027] Vector computation units can process data from a vector (one-dimensional array) simultaneously. Tensor computation units can directly perform large-scale matrix multiplication or convolution operations, such as calculating a 16x16 or larger matrix multiplication at a time. Tensor registers and vector registers are used to store the direct operation data and intermediate results being processed by the corresponding tensor computation unit and vector computation unit. The L1 cache is used to store recently used and upcoming data and instructions from heterogeneous computing cores. The L1 cache is faster than the L2 cache, reducing the number of accesses to the shared L2 cache, thereby reducing latency, saving power, and alleviating bandwidth pressure on the L2 cache.

[0028] In an exemplary embodiment of the present invention, the heterogeneous computing core further includes a scalar computing module, which includes a scalar computing unit, a scalar register, and a scalar instruction scheduling unit. The scalar computing module is connected to the control module and the L1 cache, respectively, and the scalar computing unit, the scalar register, and the scalar instruction scheduling unit are interconnected. The scalar instruction scheduling unit is used to receive scalar type control instructions distributed by the control module; The scalar register is used to store scalar type data; The scalar calculation module is used to perform calculations on the scalar type data based on the control instructions of the scalar type.

[0029] In embodiments of the present invention, such as Figure 2 As shown, the scalar instruction scheduling unit receives scalar-type control instructions distributed by the control module, and the scalar computation unit calculates individual scalar-type data based on the control instructions received by the scalar instruction scheduling unit. The scalar register is used to store the direct operation data and intermediate results being processed by the scalar computation unit.

[0030] In an exemplary embodiment of the present invention, the tensor computation module further includes a tensor instruction scheduling unit and a tensor memory access unit. The tensor computation unit, the tensor register, and the tensor memory access unit are respectively connected to the instruction scheduling unit, and the tensor register is connected to the tensor computation unit. The tensor instruction scheduling unit is used to receive tensor-type control instructions distributed by the control module; The tensor memory access unit is used to access the control instructions of the tensor type. The tensor register is used to store tensor type data; The tensor calculation module is used to perform calculations on the tensor type data based on the control instructions of the tensor type.

[0031] In this embodiment of the invention, the tensor instruction scheduling unit receives control instructions of tensor type distributed by the control module, and the scalar tensor computation unit calculates the tensor type data based on the control instructions received by the tensor instruction scheduling unit. The tensor register is used to store the direct operation data and intermediate results being processed by the tensor computation unit.

[0032] In this embodiment of the invention, after the tensor calculation module completes a single calculation, it monitors the idle state of the vector register. When the vector register is idle, such as... Figure 2 As shown, data is synchronized to the vector register via three types of buses for subsequent data processing; when the vector register is busy, the data is written back to the L1 cache, waiting for the vector calculation module to read it for subsequent data processing.

[0033] In an exemplary embodiment of the present invention, the vector calculation module further includes a vector instruction scheduling unit, and the vector calculation unit, the vector register, and the vector instruction scheduling unit are interconnected. The vector instruction scheduling unit is used to receive vector-type control instructions distributed by the control module; The vector register is used to store vector type data; The vector calculation module is used to perform calculations on the vector type data based on the control instructions of the vector type.

[0034] In this embodiment of the invention, the vector instruction scheduling unit receives vector-type control instructions distributed by the control module, and the vector tensor computation unit calculates tensor-type data based on the control instructions received by the tensor instruction scheduling unit. The vector register is used to store the direct operation data and intermediate results being processed by the tensor computation unit.

[0035] In an exemplary embodiment of the present invention, the control module includes an instruction fetch and decode unit, a thread scheduling and dispatch unit, and a vector and tensor memory access unit connected in sequence. The thread scheduling and dispatch unit is connected to the tensor calculation module and the vector calculation module, respectively, and the vector and tensor memory access unit is connected to the L1 cache. The instruction fetching and decoding unit is used to read control instructions from the instruction cache, decode the control instructions, and send the decoded control instructions to the thread scheduling and dispatching unit. The thread scheduling and distribution unit is used to distribute the control instructions to the tensor calculation module, the vector calculation module, or the vector and tensor memory access unit according to the instruction type of the control instructions. The vector and tensor memory access unit is used to receive control instructions distributed by the thread scheduling and distribution unit.

[0036] In this embodiment of the invention, an instruction cache is formed based on the RISC-V instruction set and extended instruction set. The instruction fetch and decode unit reads the control instruction from the instruction cache according to the jump of the instruction PC, decodes the read control instruction through the instruction decoder, parses the opcode and operand of the control instruction, and generates the corresponding control signal according to the decoding result to coordinate the subsequent components to complete the operation required by the instruction.

[0037] The thread scheduling and dispatch unit distributes control instructions to the corresponding computation modules based on their instruction types. For example, scalar control instructions are distributed to the scalar computation module, vector control instructions to the vector computation module, and tensor control instructions to the tensor computation module. Simultaneously, the thread scheduling and dispatch unit distributes control instructions that require data exchange with memory (such as loading and storing) to the vector and tensor memory access units for storage.

[0038] In this embodiment of the invention, after receiving a control instruction, the vector and tensor memory access unit reads data from the L1 cache and sends it to the register of the vector / tensor calculation module. The calculation module receives the control instruction, monitors the data storage status of its local registers, and controls the calculation unit to read data from the registers for effective calculation.

[0039] In this embodiment of the invention, the instruction scheduling unit and vector and tensor memory access unit of each computing module cache multiple control instructions. When computing or memory access is busy, instruction reception backpressure is applied to prevent the instruction scheduling and distribution module from continuing to send instructions.

[0040] Figure 3 This is a flowchart illustrating a computing method based on heterogeneous computing cores according to an exemplary embodiment. Figure 3 As shown in an exemplary embodiment, the computing method based on heterogeneous computing cores includes steps 310 to 320, which are described in detail below.

[0041] Step 310: Obtain the calculation control instructions for matrix multiplication; Step 320: Based on the computation control instructions, control the heterogeneous computing core group to perform matrix multiplication operations to obtain the result matrix of the matrix multiplication operation; wherein, the heterogeneous computing core group includes 4 heterogeneous computing cores as described in any of the preceding items, and the tensor registers of each heterogeneous computing core are connected in the order of operation.

[0042] In this embodiment of the invention, matrix multiplication is performed by accumulating the matrix multiplication of D = A × B + C. The tensor calculation module has an independent memory access unit, controlling the L1 cache to directly read the fragmented data from the next-level cache or video memory. The size of the data loaded into the tensor register each time is an integer multiple of the maximum data fragment that the tensor calculation module can process in a single operation. During loading, N times the address space of the maximum B matrix data fragment that the tensor calculation module can process in a single operation is reserved for data synchronization between heterogeneous computing cores, such as... Figure 4 As shown, the address space occupancy is represented by the shaded area in B1. The data fragments loaded by the four heterogeneous computing cores are as follows: upon initial loading, heterogeneous computing core-1 loads data fragments A1, B1, and C11; heterogeneous computing core-2 loads data fragments A2, B2, and C12; and so on.

[0043] Since the four heterogeneous computing cores share the same L1 cache, upon receiving a memory access instruction request from a tensor computing module, the L1 cache sequentially loads matrix slices A, B, and C for each tensor computing module. During the loading process, matrix slices A, B, and C are overwritten sequentially and are not backed up in the L1 cache.

[0044] The tensor computation module, through instruction scheduling, controls the tensor computation units to sequentially read fragmented matrix data from tensor registers and perform effective computations. The tensor instruction scheduling unit distributes multi-core synchronization instructions and monitors the execution progress of the tensor computation modules within the heterogeneous computing core group. Taking heterogeneous computing core-1 as an example, after the local tensor computation module completes N minimum-granularity calculations, it sets the zeroth bit of the data to high at a fixed address X in the register of heterogeneous computing core-2 and a fixed address Y in heterogeneous computing core-1 via a type of bus within the heterogeneous computing core, marking the completion of a single bit's computation. Simultaneously, it begins monitoring the local register address X for a completion marker. Sequentially, after the next N minimum-granularity calculations, the fixed address X in the register of heterogeneous computing core-2 and the fixed address Y in heterogeneous computing core-1 are updated, setting the higher bit of the data to high.

[0045] When the data at local register address X is detected to be non-zero, the data at address Y is read and ANDed. When the zeroth bit is high, matrix B data from heterogeneous computing core-2 is read at a size N times the smallest granularity and stored in the register of heterogeneous computing core-1, with the storage location being N times the free address space. After reading, the zeroth bit of the data at address Y is cleared, and the data at address Y in the register of heterogeneous computing core-2 is monitored. When the zeroth bit is detected to be cleared, the zeroth bit of the data at local register address X is cleared. Monitoring of the data at local register address X continues.

[0046] When the data at local register address X is detected to be non-zero and its first bit is high, read matrix B data from heterogeneous computing core-2, read a size N times the smallest granularity, and store it in the register of heterogeneous computing core-1, in the free address space of the current B matrix at the first N times the smallest granularity. After reading, clear the first bit of the data at address Y, and monitor the data at address Y in the register of heterogeneous computing core-2. When the first bit is cleared, clear the first bit of the data at local register address X. Continue monitoring the data at local register address X.

[0047] Similarly, heterogeneous computing core-1 reads matrix B data from heterogeneous computing core-2, loads matrix C21 data slice through L1 cache, and begins matrix calculation of A1×B2+C21.

[0048] During the above calculation process, other heterogeneous computing cores simultaneously perform the aforementioned monitoring and data reading, completing the sequential forwarding of matrix B among the four heterogeneous computing cores. This process is repeated three times, completing all calculations for matrix D and yielding the final matrix D.

[0049] In this embodiment of the invention, the register interaction of heterogeneous computing core groups reduces repeated accesses to the L2 cache by different computing cores when the L1 cache is limited, thereby reducing bandwidth pressure, reducing memory access latency, reducing waiting of computing resources due to slow data loading, and improving the utilization of computing resources. Through register interaction, heterogeneous computing core groups realize the effective replacement of L1 cache by registers, reducing dependence on L1 cache capacity, and further reducing repeated memory accesses to L2 cache.

[0050] In an exemplary embodiment of the present invention, the step of controlling a heterogeneous computing kernel group to perform matrix multiplication based on the computation control instructions to obtain the result matrix of the matrix multiplication operation includes: The matrix multiplication is split to obtain multiple matrix multiplication fragments; Based on the computation control instructions, the heterogeneous computing core groups corresponding to each matrix multiplication piece are controlled to perform the corresponding matrix multiplication operations to obtain the result matrix; wherein, the heterogeneous computing core groups interact with each other based on the association relationship of the matrix multiplication pieces.

[0051] In this embodiment of the invention, the upper-layer software breaks down a large matrix multiplication into multiple smaller-granularity matrix multiplication pieces, adapting them to a single tensor computation module on the hardware to perform matrix multiplication accumulation calculation of D=A×B+C. A heterogeneous computing core group completes the operation of one matrix multiplication piece.

[0052] like Figure 5As shown, splitting matrix multiplication into two matrix multiplication fragments corresponds to two heterogeneous computing core groups. After the third book forwarding is completed within the heterogeneous computing core group, the register access bus between different heterogeneous computing cores is switched, and register status and data are read and written through the two types of buses between the heterogeneous computing cores.

[0053] Taking heterogeneous computing core-1 of heterogeneous computing core group-1 as an example, after the local tensor calculation module completes N minimum-granularity calculations, it sets the zeroth bit of the data to high at fixed address X of the register of heterogeneous computing core-1 in heterogeneous computing core group-2 and fixed address Y of the local register through the Class II bus within the heterogeneous computing core, marking the completion of a single bit calculation. Simultaneously, it begins monitoring address X of the local register for a completion flag. This data synchronization process is the first synchronization of heterogeneous computing core-1 as described above. After synchronization, three data synchronizations are performed within the heterogeneous computing core group to complete the entire calculation process.

[0054] In this embodiment of the invention, four heterogeneous computing cores constitute a heterogeneous computing core group, which is connected to the L1 cache via a Crossbar bus. Different heterogeneous computing core groups have heterogeneous computing cores in the same location connected to a tensor register via an interconnect bus.

[0055] In this embodiment of the invention, within a heterogeneous computing core group, an interconnect bus based on tensor register interaction connects four heterogeneous computing cores based on the order of operations, supporting tensor register data interaction across heterogeneous computing cores. Simultaneously, tensor registers and vector registers within a core are interconnected, supporting data interaction within the core. Based on the memory access unit corresponding to the register interaction, according to the memory access instruction, data interaction between L1 cache and registers, as well as data interaction between intra-core registers and inter-core registers, is possible.

[0056] This invention achieves efficient data transmission between matrix slices through data interaction of inter-core tensor registers, effectively reducing the bandwidth access frequency of computing cores to multi-level cache networks and the dependence on L1 cache capacity, thereby reducing communication power consumption. It has broad application prospects in the storage and communication fields of AI computing chips.

[0057] The computing device based on heterogeneous computing cores provided by the present invention will be described below. The computing device based on heterogeneous computing cores described below can be referred to in correspondence with the computing method based on heterogeneous computing cores described above. It should be noted that the device provided in the embodiments below and the method provided in the embodiments above belong to the same concept, and the specific way in which each module and unit performs operations has been described in detail in the method embodiments, and will not be repeated here.

[0058] In one exemplary embodiment of the present invention, please refer to Figure 6 , Figure 6This is a computing device based on heterogeneous computing cores, as illustrated in an exemplary embodiment, comprising the following modules.

[0059] The module 610 is configured to acquire calculation control instructions for matrix multiplication operations; The computing module 620 is configured to control the heterogeneous computing core group to perform matrix multiplication operations based on the computing control instructions, and obtain the result matrix of the matrix multiplication operation; wherein, the heterogeneous computing core group includes 4 heterogeneous computing cores as described in any of the preceding items, and the tensor registers of each heterogeneous computing core are connected in the order of operation.

[0060] In an exemplary embodiment of the present invention, the computing module 620 includes: The splitting submodule is configured to split the matrix multiplication to obtain multiple matrix multiplication fragments; The computation submodule is configured to control the heterogeneous computation core group corresponding to each matrix multiplication piece to perform the corresponding matrix multiplication operation based on the computation control instructions, so as to obtain the result matrix; wherein, the heterogeneous computation core groups interact with each other based on the association relationship of the matrix multiplication pieces.

[0061] Figure 7 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 7 As shown, the electronic device may include a processor 710, a communications interface 720, a memory 730, and a communication bus 740, wherein the processor 710, the communications interface 720, and the memory 730 communicate with each other via the communication bus 740. The processor 710 can call logical instructions in the memory 730 to execute a computation method based on a heterogeneous computing core, the method including: obtaining computation control instructions for matrix multiplication operations; Based on the computation control instructions, the heterogeneous computing core group is controlled to perform matrix multiplication operations to obtain the result matrix of the matrix multiplication operation; wherein, the heterogeneous computing core group includes four heterogeneous computing cores as described in any one of the preceding claims, and the tensor registers of each heterogeneous computing core are connected in the order of operation.

[0062] Furthermore, the logical instructions in the aforementioned memory 730 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, essentially, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0063] On the other hand, the present invention also provides a computer program product, the computer program product including a computer program, the computer program being able to be stored on a non-transitory computer-readable storage medium, and when the computer program is executed by a processor, the computer is able to execute the computation method based on heterogeneous computing cores provided by the above methods, the method including: obtaining computation control instructions for matrix multiplication operations; Based on the computation control instructions, the heterogeneous computing core group is controlled to perform matrix multiplication operations to obtain the result matrix of the matrix multiplication operation; wherein, the heterogeneous computing core group includes four heterogeneous computing cores as described in any one of the preceding claims, and the tensor registers of each heterogeneous computing core are connected in the order of operation.

[0064] In another aspect, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to perform the computational methods based on heterogeneous computing cores provided by the above methods, the method comprising: acquiring computational control instructions for matrix multiplication operations; Based on the computation control instructions, the heterogeneous computing core group is controlled to perform matrix multiplication operations to obtain the result matrix of the matrix multiplication operation; wherein, the heterogeneous computing core group includes four heterogeneous computing cores as described in any one of the preceding claims, and the tensor registers of each heterogeneous computing core are connected in the order of operation.

[0065] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0066] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0067] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A heterogeneous computing core, characterized in that, It includes a control module, a tensor calculation module, and a vector calculation module, which are interconnected and each is connected to an L1 cache. The control module is used to fetch, decode, distribute, and access memory control instructions. The tensor calculation module includes a tensor calculation unit and a tensor register. The tensor calculation module is used to receive control instructions of tensor type distributed by the control module, and control the tensor calculation unit to read data from the tensor register for calculation. The vector calculation module includes a vector calculation unit and a vector register. The vector calculation module is used to receive control instructions of the vector type distributed by the control module, and control the vector calculation unit to read data from the vector register for calculation.

2. The heterogeneous computing core according to claim 1, characterized in that, The heterogeneous computing core further includes a scalar computing module, which includes a scalar computing unit, a scalar register, and a scalar instruction scheduling unit. The scalar computing module is connected to the control module and the L1 cache, respectively, and the scalar computing unit, the scalar register, and the scalar instruction scheduling unit are interconnected. The scalar instruction scheduling unit is used to receive scalar type control instructions distributed by the control module; The scalar register is used to store scalar type data; The scalar calculation module is used to perform calculations on the scalar type data based on the control instructions of the scalar type.

3. The heterogeneous computing core according to claim 1, characterized in that, The tensor computation module further includes a tensor instruction scheduling unit and a tensor memory access unit. The tensor computation unit, the tensor register, and the tensor memory access unit are respectively connected to the instruction scheduling unit, and the tensor register is connected to the tensor computation unit. The tensor instruction scheduling unit is used to receive tensor-type control instructions distributed by the control module; The tensor memory access unit is used to access the control instructions of the tensor type. The tensor register is used to store tensor type data; The tensor calculation module is used to perform calculations on the tensor type data based on the control instructions of the tensor type.

4. The heterogeneous computing core according to claim 1, characterized in that, The vector calculation module further includes a vector instruction scheduling unit, and the vector calculation unit, the vector register, and the vector instruction scheduling unit are interconnected. The vector instruction scheduling unit is used to receive vector-type control instructions distributed by the control module; The vector register is used to store vector type data; The vector calculation module is used to perform calculations on the vector type data based on the control instructions of the vector type.

5. The heterogeneous computing core according to any one of claims 1 to 4, characterized in that, The control module includes an instruction fetch and decode unit, a thread scheduling and dispatch unit, and a vector and tensor memory access unit connected in sequence. The thread scheduling and dispatch unit is connected to the tensor calculation module and the vector calculation module, respectively. The vector and tensor memory access unit is connected to the L1 cache. The instruction fetching and decoding unit is used to read control instructions from the instruction cache, decode the control instructions, and send the decoded control instructions to the thread scheduling and dispatching unit. The thread scheduling and distribution unit is used to distribute the control instructions to the tensor calculation module, the vector calculation module, or the vector and tensor memory access unit according to the instruction type of the control instructions. The vector and tensor memory access unit is used to receive control instructions distributed by the thread scheduling and distribution unit.

6. A computational method based on heterogeneous computing kernels, characterized in that, include: Obtain the calculation control instructions for matrix multiplication; Based on the computation control instructions, the heterogeneous computing core group is controlled to perform matrix multiplication operations to obtain the result matrix of the matrix multiplication operation; wherein, the heterogeneous computing core group includes four heterogeneous computing cores as described in any one of claims 1 to 5, and the tensor registers of each heterogeneous computing core are connected in the order of operation.

7. The computation method based on heterogeneous computing kernels according to claim 6, characterized in that, The step of controlling the heterogeneous computing core group to perform matrix multiplication based on the computation control instructions to obtain the result matrix of the matrix multiplication includes: The matrix multiplication is split to obtain multiple matrix multiplication fragments; Based on the computation control instructions, the heterogeneous computing core groups corresponding to each matrix multiplication piece are controlled to perform the corresponding matrix multiplication operations to obtain the result matrix; wherein, the heterogeneous computing core groups interact with each other based on the association relationship of the matrix multiplication pieces.

8. A computing device based on heterogeneous computing cores, characterized in that, include: The acquisition module is configured to acquire calculation control instructions for matrix multiplication operations; The computing module is configured to control the heterogeneous computing core group to perform matrix multiplication operations based on the computing control instructions, and obtain the result matrix of the matrix multiplication operation; wherein, the heterogeneous computing core group includes four heterogeneous computing cores as described in any one of claims 1 to 5, and the tensor registers of each heterogeneous computing core are connected in the order of operation.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the computing method based on heterogeneous computing cores as described in any one of claims 6 to 7.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the computation method based on heterogeneous computing cores as described in any one of claims 6 to 7.

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