Low-delay de-jitter circuit in LED backlight driving system

Abstract

The invention discloses a low-delay de-jittering circuit used in an LED backlight driving system. The low-delay de-jittering circuit comprises a latch and a selector, an input signal containing glitch pulses is input to the input end of the latch and the selection control end of the selector; when the input signal is in a first level state, the selector controls a first enable signal input to a first signal channel of the selector as an output signal of the selector; when the input signal is in a second level state, the selector controls a second enable signal input to a second signal channel of the selector as an output signal of the selector; and the output end of the selector is connected to the enabling control end of the latch.

Description

Technical Field

[0001] This invention relates to the field of LED driving technology, and in particular to a low-delay de-jitter circuit in an LED backlight driving system. Background Technology

[0002] Liquid crystal displays (LCDs) are the most prevalent type of display panel in modern applications. The liquid crystal material used in LCD panels is not self-emissive and requires a backlight to provide illumination. LED backlights, with their advantages of energy saving, environmental friendliness, and high performance, are widely used in LCD display panels. The performance of the LED backlight driving circuit is crucial to the LCD display panel's performance.

[0003] During the process of digital signal level changes, glitches may occur near the edges due to factors such as wire length, parasitic capacitance and resistance, or interference. Figure 1 As shown, LED backlight driving systems require digital modulation signals to adjust LED brightness. Therefore, if glitches in the digital signal cannot be effectively filtered out, they will severely affect the accuracy of the LED backlight driving. Traditional de-jitter circuits, which use clock sampling followed by a digital counter to eliminate jitter, introduce significant delays.

[0004] Therefore, there is a need in the existing technology for a low-latency de-jitter circuit that can be applied to LED backlight driving systems. Summary of the Invention

[0005] The technical objective of this invention is to provide a low-latency de-jitter circuit that can be applied to LED backlight driving systems to remove glitches in digital signals, thereby ensuring the accuracy of LED backlight driving.

[0006] To achieve the above-mentioned technical objectives, the present invention provides a low-delay dejitter circuit for an LED backlight driving system, comprising:

[0007] latches and selectors;

[0008] An input signal containing glitch pulses is input to the input terminal of the latch and the selection control terminal of the selector;

[0009] When the input signal is at a first level, the selector controls the first enable signal input to the first signal channel of the selector to be the output signal of the selector; when the input signal is at a second level, the selector controls the second enable signal input to the second signal channel of the selector to be the output signal of the selector.

[0010] The output of the selector is connected to the enable control terminal of the latch.

[0011] In one embodiment, the first enable signal remains at a first level state at least during the glitch pulse segment, and the second enable signal remains at a second level state at least during the glitch pulse segment.

[0012] In one embodiment, the first enable signal and the second enable signal are configured to flip after a fixed time period following the flip of the input signal.

[0013] In one embodiment, the first enable signal and the second enable signal can be set to the same first level state to disable the debouncing function of the latch.

[0014] In one embodiment, the first enable signal and the second enable signal can be set to the same second level state to lock the output state of the latch.

[0015] The present invention also provides a low-latency dejitter circuit for an LED backlight driving system, comprising:

[0016] latches and selectors;

[0017] An input signal containing glitch pulses is input to the input terminal of the latch; the output signal output from the output terminal of the latch is fed back to the selection control terminal of the selector;

[0018] When the output signal is at a first level, the selector controls the second enable signal input to the first signal channel of the selector to be the output signal of the selector; when the output signal is at a second level, the selector controls the first enable signal input to the second signal channel of the selector to be the output signal of the selector.

[0019] The output of the selector is connected to the enable control terminal of the latch.

[0020] In one embodiment, the first enable signal remains at a first level state at least during the glitch pulse segment, and the second enable signal remains at a second level state at least during the glitch pulse segment.

[0021] In one embodiment, the first enable signal and the second enable signal are configured to flip after a fixed time period following the flip of the input signal.

[0022] In one embodiment, the first enable signal and the second enable signal can be set to the same first level state to disable the debouncing function of the latch.

[0023] In one embodiment, the first enable signal and the second enable signal can be set to the same second level state to lock the output state of the latch.

[0024] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description, claims and drawings. Attached Figure Description

[0025] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with the embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0026] Figure 1 This is a schematic diagram of digital signal glitches in existing technology;

[0027] Figure 2 This is a schematic diagram of the low-delay debounce circuit according to the first embodiment of the present invention;

[0028] Figure 3 This is a signal timing diagram of the low-delay dejitter circuit according to the first embodiment of the present invention;

[0029] Figure 4 This is a schematic diagram of the low-delay debounce circuit according to the second embodiment of the present invention;

[0030] Figure 5 This is a signal timing diagram of the low-delay dejitter circuit according to the second embodiment of the present invention. Detailed Implementation

[0031] To make the objectives and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings.

[0032] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And when a second element, component, area, layer, or portion is discussed, it does not imply that the first element, component, area, layer, or portion necessarily exists in this invention.

[0033] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0034] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0035] Example 1

[0036] like Figure 2As shown, the low-latency debouncing circuit of this embodiment includes a latch and a selector. An input signal containing a glitch pulse is input to the input terminal of the latch and the selection control terminal of the selector. When the input signal is at a first level, the selector controls a first enable signal input to the first signal channel of the selector as the output signal of the selector. When the input signal is at a second level, the selector controls a second enable signal input to the second signal channel of the selector as the output signal of the selector. The output terminal of the selector is connected to the enable control terminal of the latch.

[0037] like Figure 3 As shown, the first enable signal remains at a first level state at least during the glitch pulse segment, and the second enable signal remains at a second level state at least during the glitch pulse segment.

[0038] The first enable signal and the second enable signal can be configured to toggle after a fixed duration following the input signal's toggle. Alternatively, they can be configured to toggle after a fixed duration following the output signal's toggle. Furthermore, the fixed durations of the first enable signal and the second enable signal can be set to be different.

[0039] The first enable signal and the second enable signal can be set to the same first level state to disable the debouncing function of the latch, or the first enable signal and the second enable signal can be set to the same second level state to lock the output state of the latch.

[0040] Example 2

[0041] like Figure 4 As shown, the low-latency debouncing circuit of this embodiment includes a latch and a selector. An input signal containing glitches is input to the input terminal of the latch; the output signal output from the output terminal of the latch is fed back to the selection control terminal of the selector; when the output signal is at a first level, the selector controls the second enable signal input to the first signal channel of the selector as the output signal of the selector; when the output signal is at a second level, the selector controls the first enable signal input to the second signal channel of the selector as the output signal of the selector; the output terminal of the selector is connected to the enable control terminal of the latch.

[0042] like Figure 5 As shown, the first enable signal remains at a first level state at least during the glitch pulse segment, and the second enable signal remains at a second level state at least during the glitch pulse segment.

[0043] The first enable signal and the second enable signal can be configured to toggle after a fixed duration following the input signal's toggle. Alternatively, they can be configured to toggle after a fixed duration following the output signal's toggle. Furthermore, the fixed durations of the first enable signal and the second enable signal can be set to be different.

[0044] The first enable signal and the second enable signal can be set to the same first level state to disable the debouncing function of the latch, or the first enable signal and the second enable signal can be set to the same second level state to lock the output state of the latch.

[0045] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A low-delay dejitter circuit for use in an LED backlight driving system, characterized in that, It includes: latches and selectors; An input signal containing glitch pulses is input to the input terminal of the latch and the selection control terminal of the selector; When the input signal is at a first level, the selector controls the first enable signal input to the first signal channel of the selector to be the output signal of the selector; when the input signal is at a second level, the selector controls the second enable signal input to the second signal channel of the selector to be the output signal of the selector. The output of the selector is connected to the enable control terminal of the latch.

2. The low-delay debounce circuit according to claim 1, characterized in that, The first enable signal remains at a first level state at least during the glitch pulse segment, and the second enable signal remains at a second level state at least during the glitch pulse segment.

3. The low-delay dejitter circuit according to claim 1, characterized in that, The first enable signal and the second enable signal are configured to flip after a fixed time after the input signal flips.

4. The low-delay dejitter circuit according to claim 1, characterized in that, The first enable signal and the second enable signal can be set to the same first level state to disable the debouncing function of the latch.

5. The low-delay debounce circuit according to claim 1, characterized in that, The first enable signal and the second enable signal can be set to the same second level state to lock the output state of the latch.

6. A low-delay dejitter circuit for use in an LED backlight driving system, comprising: latches and selectors; An input signal containing glitch pulses is input to the input terminal of the latch; The output signal from the output terminal of the latch is fed back to the selection control terminal of the selector; When the output signal is at a first level, the selector controls the second enable signal input to the first signal channel of the selector to be the output signal of the selector; when the output signal is at a second level, the selector controls the first enable signal input to the second signal channel of the selector to be the output signal of the selector. The output of the selector is connected to the enable control terminal of the latch.

7. The low-delay dejitter circuit according to claim 6, characterized in that, The first enable signal remains at a first level state at least during the glitch pulse segment, and the second enable signal remains at a second level state at least during the glitch pulse segment.

8. The low-delay debounce circuit according to claim 6, characterized in that, The first enable signal and the second enable signal are configured to flip after a fixed time after the input signal flips.

9. The low-delay dejitter circuit according to claim 6, characterized in that, The first enable signal and the second enable signal can be set to the same first level state to disable the debouncing function of the latch.

10. The low-delay dejitter circuit according to claim 6, characterized in that, The first enable signal and the second enable signal can be set to the same second level state to lock the output state of the latch.

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