Configurable noise suppression integrated circuit based on time-sharing control and dynamic isolation

Abstract

The invention discloses a configurable noise suppression integrated circuit and method based on time-sharing control and dynamic isolation, and relates to the field of electronic technology and integrated circuit design. The circuit adopts a time-sharing control and dynamic physical isolation architecture, and the core comprises a pre-charging and starting module, double energy storage units (EC1, EC2), a time-sharing control and isolation module, a voltage detection module and a trigger state maintaining module. By controlling the two energy storage units to charge and discharge alternately, a conduction path from input power supply noise to a load is cut off physically, so that the ultra-low output noise of 0.5 muVrms to 5 muVrms and the ultra-high power supply ripple rejection ratio (PSRR) of 110 dB to 140 dB are realized within the bandwidth of 10 Hz to 100 KHz. According to the invention, a monolithic full-integration mode or a core control chip and external discrete expansion mode can be configured, the ultra-high performance and the excellent application flexibility are realized, and the ultra-high-performance ultra-high-precision electronic circuit is especially suitable for high-precision electronic systems such as medical imaging, precision test instruments, high-end audio and radio frequency communication and the like.

Description

Technical Field

[0001] This invention relates to the fields of electronic technology and integrated circuit design, specifically to a monolithically integrated power management integrated circuit employing a time-division control and dynamic isolation architecture, and more particularly to a configurable noise suppression integrated circuit that achieves ultra-low noise and ultra-high power supply ripple rejection ratio through a configurable and optimizeable layout structure. More precisely, this invention relates to a noise suppression integrated circuit employing a time-division control and dynamic isolation architecture, which can be configured in a monolithically fully integrated mode or in a core control chip plus external discrete expansion mode, aiming to achieve ultra-low output noise and ultra-high power supply ripple rejection ratio. Background Technology

[0002] In high-precision electronic systems, such as medical imaging equipment (MRI, CT), precision testing instruments (semiconductor parameter analyzers, spectrum analyzers), high-end audio equipment, and radio frequency communication systems (GPS receivers, radar), power supply purity is one of the key factors determining the system's performance limits. Power supply noise can directly couple into the signal chain, degrading the system's signal-to-noise ratio (SNR), dynamic range, and measurement accuracy.

[0003] Currently, widely used power supply noise suppression technologies mainly rely on linear regulators (LDOs) and switching power supplies (SMPSs). LDOs have a simple structure and low noise, but their power supply ripple rejection ratio (PSRR) drops sharply above tens of kiloHz, typically making it difficult to maintain a PSRR above 80dB above 100kHz. Furthermore, the dropout characteristics of LDOs result in low efficiency, significant heat generation in high-current applications, and increased junction temperature further degrades their PSRR performance. While SMPSs are highly efficient, their inherent switching action generates high-frequency electromagnetic interference (EMI). Although π-type filters or ferrite beads can be used in subsequent stages to suppress this interference, achieving a PSRR >100dB across the entire bandwidth (especially the high-frequency range) is extremely difficult, and the output noise voltage is typically much higher than 10μVrms.

[0004] The fundamental challenge facing existing integrated circuit technology is:

[0005] 1. Inherent limitations of the architecture: Traditional power supplies use a "common path" approach to noise filtering, which performs noise filtering "at the same time and on the same path," and has a theoretical performance limit.

[0006] 2. Material, Process, and Parasitic Parameter Limits: The parasitic inductance (L_parasitic) and capacitance (C_parasitic) within integrated circuits make it difficult to achieve ideal high-frequency isolation at the chip level. There is a trade-off between the on-resistance (Rds_on) of integrated switches and the chip area; for small-area switches, Rds_on introduces significant on-state voltage drop and heat loss, affecting efficiency.

[0007] 3. Design conflict between stability and performance: To improve the PSRR of an integrated circuit, the gain and bandwidth of the error amplifier need to be increased, but this often sacrifices the phase margin of the loop, causing stability problems. Changes in the equivalent series resistance (ESR) and equivalent series inductance (ESL) of the output capacitor further exacerbate this contradiction.

[0008] 4. Thermal management and noise coupling: Integrating power switches and precision analog circuits on the same chip can cause the heat generated by the power switches to rise the junction temperature of the integrated circuit chip, leading to changes in carrier mobility and threshold voltage drift. This not only degrades the performance of the analog circuits, but the thermal noise generated by the power switches will also be directly superimposed on the output.

[0009] It is particularly important to note that even though the circuit principle of "time-division control and dynamic isolation" has theoretical advantages, integrating it onto a single silicon chip presents a series of severe challenges not encountered in discrete circuits: Parasitic parameters dominate performance: Distributed inductance, parasitic capacitance, and substrate coupling within the chip severely degrade high-frequency isolation, making it difficult to achieve ideal "dynamic physical isolation" within the chip. Extremely high timing accuracy is required: Delay differences among multiple chips in discrete solutions can lead to control signal race conditions, while in monolithic integration, the control of switching dead time needs to achieve nanosecond or even picosecond precision; any deviation will result in shoot-through current or output glitches. Thermal management and noise coupling: Integrating power switches, precision analog circuits, and digital logic onto the same chip means that the heat generated by the power devices directly affects the performance of sensitive analog circuits through the substrate, introducing thermal noise. A trade-off between area and performance: Achieving low on-resistance requires large-size power transistors, but this introduces huge parasitic capacitance and chip area costs; the capacity of on-chip energy storage elements is also strictly limited by area.

[0010] Therefore, there is an urgent need in the field for a solution designed specifically for integrated circuit implementation that can be synergistically optimized from transistor-level circuitry, layout, and system architecture to overcome the aforementioned integration challenges, so that the advantages of the "time-division control and dynamic isolation" architecture can be fully utilized on a single chip. Summary of the Invention

[0011] Purpose of the invention

[0012] 1. A monolithic integrated power management architecture based on the concepts of "time-sharing control" and "dynamic physical isolation" is provided to fundamentally avoid noise conduction.

[0013] 2. The architecture is specifically implemented in two configurable modes: a fully integrated monolithic chip and a core control chip plus discrete expansion components, to meet the needs of different application scenarios.

[0014] 3. Through the above architecture, an ultra-low output noise voltage of 0.5μVrms to 5μVrms and an ultra-high PSRR of 110dB to 140dB are achieved within a bandwidth of 10Hz to 100KHz.

[0015] Advantages of the present invention

[0016] Compared with the prior art, the configurable noise suppression integrated circuit provided by the present invention has the following significant advantages: 1. Breakthrough in performance limits brought about by integrated circuit implementation.

[0017] On-chip low parasitic isolation switches: Through deep N-well isolation, a multi-finger CMOS transmission gate array, and a common-center symmetrical layout design, the parasitic capacitance (Cds) of the switching transistors is reduced to the fly-far level, and the on-resistance (Rds) is reduced to the milliohm level. This chip-level parasitic parameter control is the physical basis for ensuring that "dynamic physical isolation" can still achieve a PSRR of over 110dB at high frequencies (such as 100kHz).

[0018] Nanosecond-level precise dead time control: By pre-setting the dead time in the on-chip design, the "shoot-through" phenomenon of power switches during dynamic cyclic switching is completely eliminated at the hardware level, achieving switching reliability that discrete solutions cannot match.

[0019] 2. Configurability and Design Paradigm Innovation

[0020] 2.1 Configurable working mode: Through design and configuration, two different modes can be realized: fully integrated mode and core control mode, to adapt to different loads and application scenarios.

[0021] 2.2 Configurable performance parameters: Key parameters can be configured through flexible operating modes and external expansion.

[0022] 2.3 Configurable External Devices under Standardized Interface: In core control mode, external high-performance discrete devices (such as GaN HEMTs and mechanical relays) can be transformed into "peripherals" of the system through precisely defined pin interfaces, achieving flexibility that exceeds the performance limits of a single silicon-based process.

[0023] 3. Excellent thermal management and reliability

[0024] In core control mode, all power dissipation (including switching losses and transient absorption losses) is innovatively transferred to the outside of the chip, achieving "cold operation" of the control chip. The chip junction temperature can be controlled within 10°C of ambient temperature. This not only ensures the performance stability of the precision control circuit and avoids thermal noise injection, but also allows the core chip to be manufactured using low-power logic processes of 28nm or even more advanced processes, significantly improving the overall system reliability, with a mean time between failures (MTBF) of up to 10. 6More than 1 hour.

[0025] 4. Enhance diagnostic and protective capabilities

[0026] The pre-charge and startup module and the voltage detection module both have built-in precision reference voltage units to realize real-time monitoring of the output voltage. The integrated circuit pins can be flexibly set to facilitate the addition of input or output current monitoring. The voltage and current monitoring functions provide the integrated circuit with reliable system diagnostic and protection capabilities.

[0027] 5. Creative comparison and advantages with discrete component implementation schemes

[0028] It should be further noted that, as an integrated circuit invention of national strategic importance, this invention is fundamentally different from discrete component circuits. Although the core ideas of "time-division control" and "dynamic physical isolation" can theoretically be considered as a circuit principle that can be implemented with discrete components, this invention, based on integrating more semiconductor units, solves several inherent technical defects that cannot be overcome when using discrete components by constructing them into a configurable integrated circuit. This achieves a qualitative leap in performance, reliability, and integration, as detailed below:

[0029] 5.1, Fundamental improvement in system timing determinism and reliability:

[0030] The drawbacks of discrete solutions are that multiple independent comparators, logic gates, and drivers are connected through PCB traces. The transmission delays of each chip are different and difficult to match, which can easily lead to control signal competition hazards. At the moment of switching, nanosecond-level conduction overlap (i.e., "shoot-through") occurs, which poses a safety risk of burning out the power transistor.

[0031] The present invention achieves this by integrating all control logic modules on a single silicon substrate using semiconductor technology, enabling nanosecond-level precise matching of path delays. More importantly, the integrated circuit incorporates a dedicated dead-time control circuit, forcibly inserting a complete turn-off period for all switches at the hardware level. This fundamentally eliminates the fatal failure mode of shoot-through short circuits, achieving switching reliability unattainable by discrete solutions.

[0032] 5.2, Breakthrough of key performance parameters and effective suppression of parasitic parameters:

[0033] The drawbacks of discrete solutions are that they are limited by the performance limitations of general discrete components (such as large input offset voltage and slow response speed of comparators), and the distributed inductance (ESL) and stray capacitance introduced by PCB layout can cause severe voltage ringing and ground bounce noise, which seriously degrades the power supply ripple rejection ratio and output noise performance at high frequencies.

[0034] The present invention employs a pre-configured circuit design. The voltage detection module integrates a comparator with automatic zero-reset or chopper amplitude stabilization technology, achieving an input offset voltage below 5μV and a response time of less than 1μs, ensuring accurate and timely state switching. The time-division control and isolation module utilizes a multi-finger layout CMOS transmission gate array, combined with deep N-well isolation and guard ring technology, reducing the parasitic capacitance (Cds) of the switching transistor to the flyfar level and the on-resistance (Rds_on) to the milliohm level. This chip-level parasitic parameter control is the theoretical basis for ensuring that "dynamic physical isolation" can still achieve a PSRR of over 110dB at high frequencies (e.g., 100kHz), which is impossible to achieve with noisy discrete PCB solutions.

[0035] 5.3 Safety mechanisms for pre-charging and startup processes:

[0036] The drawbacks of discrete solutions: Even with high-cost component stacking, it is difficult to achieve high-precision and high-reliability system power-on startup timing management. Simple RC delay cannot ensure that the energy storage unit EC1 reaches a stable voltage state, which can easily lead to system startup with defects, threatening load safety.

[0037] This invention integrates a pre-charging and startup module with redundant monitoring and intelligent timing management. This module employs dual-channel independent high-precision bandgap reference sources (temperature drift <20ppm / ℃) and a hysteretic window comparator to independently and accurately monitor the voltages of the two energy storage units. Its built-in startup control logic unit strictly executes logical decisions and soft-start delays, ensuring that the system is only authorized to start under the safest conditions, providing a "safety gatekeeper" function for the load device that discrete solutions cannot offer.

[0038] 5.4, ​​Achieving Configurability of Paths and Paradigm Innovation in System Design:

[0039] Disadvantages of discrete solutions: The solutions are fixed and rigid; once the design is completed, the performance ceiling is locked. If you want to change the switching devices or adjust the filtering parameters, you need to redesign the entire PCB, which results in a long development cycle and high costs.

[0040] This invention revolutionizes design paradigms by dividing the system into two configurable modes. Mode 1 provides a one-stop solution, lowering the application threshold. In Mode 2, the invention defines itself as the intelligent core of the "core control integrated circuit chip," transforming external discrete power devices (such as GaN HEMTs, mechanical relays, and supercapacitors) into powerful peripherals as "external discrete device expansion components" through precisely defined pin interfaces (such as CTRL, EC1_COM, VDET_IN). This allows users to incorporate traditionally passive components such as energy storage unit capacity, equivalent series resistance, and the on-resistance and isolation of switching devices as active design variables into the calculation model of system operating cycles and performance. This enables a broad range of applications, from low-power sensing to high-power circuits, within a single architecture, achieving extreme flexibility unavailable in discrete solutions.

[0041] Technical solution

[0042] To achieve the above objectives, the present invention adopts the following technical solution:

[0043] I. Dual-unit alternation mechanism:

[0044] The core working principle of this invention is based on two energy storage units, EC1 and EC2, which, using integrated circuit technology and under the precise management of logic control circuits, alternately perform charging and discharging tasks in a time-sharing manner. The system constructs two physically and temporally independent energy processing paths: a "charging path" and a "discharging path." When one unit, EC1, is connected to the load through the "discharging path" to discharge, the other unit, EC2, is connected to the input power source through the "charging path" to charge. This cycle repeats continuously, with the two circuits achieving complete dynamic switching and physical isolation through a switch. Through this mechanism, the load is always continuously powered by a "clean" power source that is completely isolated from input noise.

[0045] II. Time-sharing and collaborative mechanisms:

[0046] Regardless of the implementation mode, EC1 and EC2, under the precise scheduling of the time-sharing control and isolation modules, dynamically and cyclically switch based on the output voltage, strictly adhering to the working discipline of "one charge, one discharge, alternating rotation." The system's time-sharing coordination is achieved by an on-chip closed-loop control system. This control system uses the output voltage as a feedback signal and monitors it in real time through an integrated high-precision voltage detection module. When the voltage of the working unit is detected to discharge to a threshold set by the on-chip reference source, the integrated trigger and state holding module generates a switching command. An integrated dead-time control circuit ensures that no short circuits or other faults occur during the switching process before driving the time-sharing control and isolation module to perform the state switch. This fully integrated control loop ensures the accuracy, reliability, and seamlessness of the switching action, achieving continuous power supply.

[0047] The system adopts a state switching strategy based on the detected output voltage. When the voltage of one energy storage unit discharges to a preset threshold, the system automatically switches to another fully charged energy storage unit to continue supplying power, ensuring the continuity of power supply. At the same time, the CLC filtering module is used to eliminate switching noise.

[0048] III. Innovation Points:

[0049] 1. A "on-chip-off-chip collaborative" architecture is proposed. The first mode of this invention integrates a small-capacity, high-performance energy storage module, a CLC filtering module (such as a MIM capacitor), and a transient suppression module within the integrated circuit. On-chip energy storage supports low-power loads, while off-chip energy storage supports high-power loads, achieving full-scenario load coverage from low to high power. Off-chip CLC filtering collaboration supports configuring different performance parameters to achieve higher filtering performance. On-chip transient suppression saves PCB area and BOM cost, on-chip integration eliminates parasitic parameter limitations, resulting in faster response, while off-chip expansion enhances the system's adaptability.

[0050] 2. A configurable integrated circuit implementation scheme is achieved. This invention does not provide a single fixed-function chip, but rather defines a configurable integrated circuit platform. This integrated circuit can be configured between two modes: "monolithically integrated" and "core control," or selected through hardware design. This innovation enables a single chip design to cover a wide range of application scenarios, from nanoampere-level low-power sensing to ampere-level power output, achieving unprecedented application flexibility.

[0051] 3. Internalizing external component parameters as active design variables for integrated circuits. In core control mode, this invention, through architectural design, deeply integrates and dominates the internal duty cycle (T_discharge) and performance model of the integrated circuit, parameters traditionally considered passive and uncontrollable (such as the capacity C of the energy storage unit, equivalent series resistance ESR, and equivalent series inductance ESL). This enables the integrated circuit to actively adapt to and utilize the characteristics of different external components, transforming external selection into a means of regulating system performance. This significantly enhances the predictability, optimizability, and customizability of systems built based on this integrated circuit, achieving a paradigm shift from "chip design" to "system-level solutions."

[0052] The brilliance of this technical solution lies in the following: it solves the problems of power noise and continuous power supply with a clever system architecture (time-sharing isolation); it addresses the challenges of fragmented application scenarios with a configurable hardware platform; and it transforms traditional external constraints into designable system variables with a system-level design philosophy, achieving a balance between performance and flexibility.

[0053] This is a very mature, well-thought-out technical solution with high commercial and application value.

[0054] IV. Specific Model

[0055] This invention provides a power management system and its implementation method, comprising the following modules: a pre-charging and startup module (1), an energy storage module (2), a time-sharing control and isolation module (3), a transient suppression module (4), a triggering and state holding module (5), a voltage detection module (6), a CLC filtering module (7), and a load switching module (8). The energy storage module includes a first energy storage unit EC1 and a second energy storage unit EC2; the time-sharing control and isolation module includes an electrically linked first switching switch SPDT1 and a second switching switch SPDT2, both of which are SPDT switches. The transient suppression module and the CLC filtering module are typically directly connected to the output terminal VOUT / SW_COM_OUT. This invention focuses on the innovation of the power management architecture. For the inherent general input / output protection structures of integrated circuits, those skilled in the art can design them according to processes and standards, and will not be elaborated upon here.

[0056] Specifically, it can be configured into two implementation modes.

[0057] Mode 1: Monolithic Fully Integrated Circuit Chip

[0058] See attached Figure 1 In this mode, the integrated circuit serves as a complete power management system, with all eight core functional modules integrated onto a single semiconductor substrate. This provides a highly integrated power management system and achieves monolithic integration of power management functions. The modules are electrically connected via internal metal interconnects, and their interconnect parasitic parameters are controlled within the design range through co-simulation and optimization.

[0059] 1. Pre-charge and start-up module (1)

[0060] The pre-charging and startup module, in the initial state of the system, employs a pre-charging mechanism with redundant monitoring and intelligent timing management to ensure that the system only authorizes power supply to the load and enters the dynamic cyclic switching operating mode after the energy storage unit EC1 reaches a preset stable voltage state. Simultaneously, independent dual-channel monitoring provides redundant safety guarantees for system operation, fundamentally avoiding system startup failures, output voltage drops, or frequent abnormal switching due to insufficient energy storage unit power, thus ensuring the safe and stable operation of the load equipment.

[0061] This module is a mixed-signal system integrating analog detection and digital logic. Through an on-chip pre-configured precision voltage reference unit, a low-offset comparator unit employing automatic zeroing technology, and a startup control logic unit composed of finite state mechanisms, it executes a pre-charge mechanism with redundant monitoring and intelligent timing management during the initial power-up phase. This mechanism ensures that the system is only authorized to enter the dynamic cyclic switching operating mode after the energy storage unit reaches the stable voltage state set by the on-chip reference source, fundamentally guaranteeing the safe and stable operation of the load device. It mainly consists of the following three on-chip sub-units:

[0062] 1.1 Precision Voltage Reference Unit

[0063] 1.1.1 Function: Provides a pre-configured reference voltage with high stability and low temperature drift for voltage comparison.

[0064] 1.1.2 Core Technology: Employing, for example, a second-order temperature-compensated bandgap reference circuit to achieve a stable reference over a wide temperature range.

[0065] 1.1.3 Implementation Details: To achieve independent and accurate monitoring of EC1 and EC2, this unit is pre-configured with two independent reference voltages: Vref1 is dedicated to voltage detection of EC1, and Vref2 is dedicated to voltage detection of EC2. The two reference voltages can be pre-configured to be the same voltage, or they can be set to different values ​​according to system design requirements, thereby supporting asymmetric charging and discharging strategies.

[0066] 1.2 Comparator Unit

[0067] 1.2.1 Function: Compares the actual voltage of the energy storage unit with a precision reference voltage in real time and outputs a digital decision signal. 1.2.2 Core Technology: Employs a low-offset comparator architecture with dual-channel, automatic zero-reset technology. Each channel independently monitors the voltage status of one energy storage unit (EC1 or EC2).

[0068] 1.2.3 Anti-interference design: The comparator can be designed with hysteresis window characteristics to enhance anti-interference capability.

[0069] 1.2.4 Performance metrics: The comparator's transmission delay has been optimized to ensure real-time system startup and status determination.

[0070] 1.3 Start-up control logic unit

[0071] 1.3.1 Function: In the initial state of system power-on, receive the decision signal from the comparator unit, execute safe startup timing logic, and generate a global enable signal.

[0072] 1.3.2 Core Technology: This unit is implemented using a finite state machine.

[0073] 1.3.3 Core Control Logic: When the output of the comparator channel used for EC1 reaches a preset valid logic level, the system is deemed to meet the startup conditions. The initial state of EC2 does not affect startup. When external button startup or other external control is required, corresponding input AND gate control logic can be added. After the system has started and entered the dynamic cyclic switching operation state, if the voltage of either EC1 or EC2 does not reach the preset voltage value, it will not affect the normal operation of the cyclic switching. However, if the voltages of both EC1 and EC2 are lower than the preset voltage values, the unit immediately determines that the system does not meet the dynamic cyclic switching conditions. 1.3.4 Timing Management: After the voltage conditions are met, the logic unit starts a configurable delay timer. This delay mechanism ensures that the voltage of the energy storage unit is completely stable before the load is applied, effectively absorbing possible instantaneous disturbances and realizing the "soft start" function.

[0074] 1.3.5 Output Signal: This unit generates a global start enable signal SYS_EN, which outputs two logic levels: 0 and 1. When it is 1, it is enabled; when it is 0, it is disabled. This signal is a power enable signal and serves as a power supply gating signal for subsequent modules. It adopts a hierarchical power-on strategy. Only when SYS_EN is enabled (i.e., valid) will subsequent modules and loads be powered on sequentially. When SYS_EN is disabled (i.e., invalid), subsequent modules and loads will be powered off, significantly reducing the system's standby power consumption.

[0075] 1.3.6 Finite State Machine Implementation: This unit implements safe startup timing control using a three-state finite state machine. Its core feature is that system startup depends solely on EC1 voltage reaching the required level, while system shutdown depends on the failure of both EC1 and EC2 voltages. The detailed definition of the state machine is as follows:

[0076] State S0: INIT (Initialization)

[0077] System behavior: Enters this state after power-on or reset. Outputs the global enable signal SYS_EN = 0.

[0078] State transition: When the EC1 voltage reaches the preset value (i.e., COMP1 = 1), the state machine starts an internally configurable delay timer and transitions to state S1. The state of EC2 (COMP2) is not checked during this stage.

[0079] State S1: READY_DELAY (Ready Delay)

[0080] System behavior: Maintain SYS_EN = 0. This state is used to achieve a "soft start" and ensure stable EC1 voltage.

[0081] State transition:

[0082] If the delay timer times out and COMP1 remains at 1, then transition to state S2.

[0083] If COMP1 becomes 0 during the delay period, the timer is immediately reset and the system returns to state S0.

[0084] State S2: SYSTEM_ENABLED (System Enabled)

[0085] System behavior: Outputs SYS_EN=1, authorizing subsequent system operations. The system enters dynamic cyclic switching mode.

[0086] State transition: The state machine transitions back to state S0 and shuts down the system only when COMP1 = 0 and COMP2 = 0 (i.e., both energy storage units are low on energy).

[0087] 1.3.7 State Transition Diagram:

[0088] See attached Figure 3 .

[0089] 1.4 Module Workflow and Collaboration Mechanism

[0090] 1.4.1 Power-on Initialization Phase: The system is initially connected to the external power supply VIN. The pre-charge and startup module, as well as the time-sharing control and isolation module, are powered on first, but their output SYS_EN internal signal is in an invalid state. In the initial state, the time-sharing control and isolation module's switch is in a specific default position (e.g., the external power supply is connected to EC1 through SPDT1, and SPDT2 is disconnected), thus establishing the pre-charge path VIN->SPDT1->EC1, while ensuring that this path is isolated from the load.

[0091] 1.4.2 Independent pre-charging and monitoring phase: The external power supply starts charging EC1 through the default path of the time-sharing control and isolation module, and charges EC2 after the system enters the dynamic cyclic switching mode.

[0092] 1.4.3 State Decision Stage: Start the control logic unit to continuously sample the output state of the comparator.

[0093] 1.4.4 System Readiness and Authorization Phase: When the EC1 voltage reaches the preset value and remains there for more than the set delay time (independent of the EC2 state), the start control logic unit sets the SYS_EN signal to active.

[0094] 1.4.5 Subsequent Action Phase: After SYS_EN becomes active, the core control circuit of the system begins to operate. At this time, the external START pulse signal can be effectively responded to, triggering the system to formally enter the dynamic cyclic switching working cycle of alternating charging and discharging. Thereafter, SYS_EN will only become inactive when both EC1 and EC2 voltages are lower than preset values.

[0095] 1.5 Innovation Points and Advantages

[0096] 1.5.1 Redundant Safety Design: A completely independent dual-channel monitoring mechanism is adopted. The startup logic relies only on EC1, avoiding system startup failure due to initial failure of EC2; during operation, the dual monitoring mechanism ensures that the system is safely shut down only when both energy storage units are depleted, providing redundant safety guarantees at the hardware level.

[0097] 1.5.2 High precision and stability: Temperature-compensated reference and hysteresis comparator are used to ensure the accuracy and anti-interference of voltage detection under various environmental conditions.

[0098] 1.5.3 Intelligent timing management: A configurable startup delay mechanism is introduced to effectively avoid unstable startup at voltage critical points or when glitches are present.

[0099] 1.5.4 Low power consumption design: The SYS_EN signal is used to perform precise power gating on subsequent circuits, which significantly reduces the system's standby power consumption.

[0100] 1.5.5 Configurability and Flexibility: Key parameters such as reference voltage, hysteresis voltage, and startup delay can be set through on-chip fixed settings, non-volatile memory, or configuration registers accessed via the SPI digital interface, thereby adapting to different application requirements.

[0101] 2. Energy storage module (2)

[0102] The energy storage module described in this invention serves as the energy storage center and clean power source of the system, providing a dual-unit energy storage solution that is deeply integrated with the system architecture. It comprises a first energy storage unit EC1 and a second energy storage unit EC2. In a monolithically integrated mode, this module innovatively employs high-density on-chip capacitors (such as metal-insulator-metal capacitors or deep-groove capacitors) as integrated energy storage elements. This on-chip energy storage core can provide continuous power to micro-loads and can instantaneously provide peak current. Its core functions are to effectively decouple high-frequency noise, suppress voltage glitches, and maintain local voltage stability during transient state switching, thereby ensuring the reliable operation of the control logic and micro-load circuitry. EC1 and EC2 can be designed symmetrically to ensure logical simplicity and consistent behavior, or they can be configured asymmetrically to achieve an optimal balance between chip area and performance.

[0103] To expand the application scope, the monolithic fully integrated mode can also connect external high-capacity energy storage components (such as ceramic capacitors, tantalum capacitors, and supercapacitors) through dedicated EC1_P and EC2_P pins to form a hierarchical energy storage network.

[0104] 3. Time-sharing control and isolation module (3)

[0105] The time-sharing control and isolation module is the core of this invention, realizing intelligent energy scheduling and physical isolation on a single chip. Its core purpose is to accurately execute the "time-sharing control" and "dynamic isolation" functions through a highly integrated low-parasitic switch, thereby achieving physical disconnection and seamless switching of the charging and discharging paths, laying the hardware foundation for achieving ultra-high power supply rejection ratio (PSRR).

[0106] This module is a complex system that integrates power switching, digital control, and analog drive.

[0107] 3.1 Core Switching Network

[0108] Both the first switching switch (SPDT1) and the second switching switch (SPDT2) are constructed using CMOS transmission gate arrays to achieve bidirectional, low-resistance, diode-free current transmission. To reduce on-resistance and parasitic capacitance, the power transistors employ a multi-cell parallel layout to improve switching speed and high-frequency isolation. In the layout design, isolation technology and guard rings are used to suppress substrate noise coupling and latch-up effects.

[0109] 3.2 Intelligent Gate Drive Circuit

[0110] This circuit employs a multi-stage buffer chain structure to provide fast and controllable gate drive for the switching transistor array. The drive circuit can have programmable switching rate control to optimize the balance between electromagnetic interference (EMI) and switching losses.

[0111] 3.3 Dead Time Control Circuit

[0112] This circuit ensures that there are no instantaneous "shoot-through" current paths during switching state transitions. Upon receiving a switching command, it first generates a fixed dead time during which all main power switches remain off. Only after the dead time expires does the target path's switch turn on. This dead time is generated by a stable timing source within the chip, ensuring reliability under all operating conditions.

[0113] 3.4 Module Workflow and Coordination Mechanism Steady-state operation: Under any steady state, the corresponding switch is in the conducting state, achieving physical isolation.

[0114] Trigger switching: The trigger and state maintenance module issues a switching command.

[0115] Dead time intervention and controllable switching: The dead time control circuit intervenes and turns off all switches; after the dead time delay, the gate drive circuit turns on the switch of the target path at a controlled switching rate.

[0116] Entering a new steady state: The system enters another completely isolated steady state, completing one switching cycle.

[0117] 4. Triggering and State Preservation Module (5)

[0118] This module is the decision-making core and state memory unit of the control logic of this system. Its core invention purpose is to provide a highly anti-interference and deterministic logic control mechanism.

[0119] 4.1 Core Logical Architecture

[0120] The core of the module is a sequential logic circuit with memory function, such as a T flip-flop. Each valid trigger edge causes a deterministic flip and latch of the output state, eliminating multiple flips caused by trigger signal issues.

[0121] 4.2 Input Anti-interference and Synchronization Circuit

[0122] The module front end integrates multi-level signal conditioning circuits, such as Schmitt triggers and synchronizer chains, to filter out noise glitches, reduce metastability risks, and ensure global timing stability.

[0123] 4.3 Output Drive and State Holding

[0124] The module output is connected to a buffer / driver to provide sufficient current to drive subsequent loads. The output state is continuously maintained by the core logic and is unaffected by changes in the input signal.

[0125] 5. Voltage detection module (6)

[0126] This module detects the final load voltage and includes a pre-configured precision voltage reference unit and voltage comparator unit. Unlike the voltage detection in the pre-charge and startup modules, this module detects the filtered output voltage. When the output voltage falls below a set value, a trigger signal is generated and sent to the input of the trigger and state holding module. The VDET_IN pin is the detection voltage input for the voltage detection module.

[0127] 6. Transient Suppression Module (4)

[0128] The transient suppression module is the overvoltage protection circuit of this system in a monolithic integrated scenario.

[0129] 6.1 On-chip integrated protection core

[0130] The module integrates a hybrid signal protection circuit that combines active and passive signals within the chip, forming a defense-in-depth system.

[0131] 6.1.1 Active clamping circuit (first stage): As a rapid defense line, when the node voltage is detected to exceed the preset clamping threshold, the circuit quickly turns on the discharge source to precisely clamp the voltage.

[0132] 6.1.2 Integrated TVS structure (second stage): as the final energy absorber, used to cope with extreme transients of extremely high energy.

[0133] 7. CLC Filtering Module (7)

[0134] The CLC filter module is the final noise filter for this system in a monolithic integrated scenario.

[0135] 7.1 On-chip integrated filter core

[0136] This module employs a multi-stage low-pass filter topology based on integrated passive components (such as spiral inductors and MIM capacitors) to specifically suppress high-frequency noise and residual out-of-band interference generated during switching.

[0137] 7.2 External Expansion and System-Level Collaboration

[0138] To overcome the limitations of integrated component values, the module provides an external expansion interface through the VOUT pin, supporting the connection of large-capacity external capacitors, thereby forming a division of labor and cooperation between on-chip high-frequency suppression and external low-frequency maintenance.

[0139] The integrated circuit pins in this configuration mode include, but are not limited to: VIN (main power input pin), VOUT (clean power output pin), GND (power ground pin), START (start signal input pin), EC1_P, EC2_P (external energy storage expansion pins).

[0140] 8. Load switch module (8)

[0141] The load switch module is a key module for achieving safe load management and energy efficiency control in this system. Its core invention objective is to serve as the final controlled interface between the system output and the load, and to perform safe and lossless on / off control of the load power supply based on the global enable signal (SYS_EN) generated by the pre-charging and startup modules.

[0142] 8.1 Module Functions and Positioning

[0143] This module is connected in series after the time-sharing control and isolation module and before the CLC filtering module, i.e.: time-sharing control module -> load switch module -> transient suppression module -> CLC filtering module -> load. It is not a power switch that performs time-sharing switching (this function is implemented by the time-sharing control and isolation module), but rather acts as a master switch to ensure that the load is energized only when the system is fully ready (SYS_EN is active) and is quickly and safely disconnected from power when the system is shut down or enters a protection state.

[0144] 8.2 Core Circuit Architecture

[0145] At the core of the module is an integrated high-performance power MOSFET and its driving and control circuitry.

[0146] Power switching transistors: MOSFETs with low on-resistance (Rds_on) are used to minimize voltage drop and power loss in the on-state.

[0147] Intelligent drive circuit: Receives the SYS_EN signal from the startup control logic unit and provides a fast, controlled slew rate drive for the gate of the power MOSFET. By optimizing the switching speed, it effectively suppresses current overshoot and voltage ringing during switching on and off, reducing electromagnetic interference (EMI) while ensuring fast response.

[0148] Integrated Protection Functions (Preferred Solution): To further enhance system reliability and safety, this module can integrate additional protection features, such as: Overcurrent Protection: Through an integrated current detection circuit, the module can automatically shut down when the load current exceeds a preset safety threshold. Reverse Current Interception: Prevents current from flowing back into the chip from the load terminal, protecting the internal circuitry. Thermal Shutdown: Automatically cuts off the load power supply when the chip junction temperature exceeds a safe limit.

[0149] 8.3 System Collaborative Working Mechanism

[0150] The load switch module has a close collaborative relationship with other modules in the system, especially the pre-charging and startup modules: During startup: After the system is powered on, SYS_EN is in an invalid state (such as logic 0), and the load switch remains off. At this time, although the time-sharing control and isolation module may be charging the energy storage unit, the load and the system output are physically isolated, fundamentally avoiding the impact on the load when the system voltage is unstable.

[0151] Normal operation phase: When the pre-charge conditions are met, SYS_EN jumps to an active state (such as logic 1), the load switch is turned on, and the stable "clean" power supply is delivered to the load, and the system enters the dynamic cyclic switching mode.

[0152] Shutdown and protection phase: When the system needs to be shut down (e.g., SYS_EN becomes ineffective due to the depletion of dual energy storage units) or the module itself triggers protection (e.g., overcurrent), the load switch quickly shuts off, enabling the load to be powered down rapidly and ensuring the safety of the load and the system itself.

[0153] 8.4 Innovation Points and Advantages

[0154] Enhanced system safety: It provides clear load on / off control points, ensuring the safety logic of "no loading if not ready", avoiding potential power-on surge impacts and undervoltage operation risks.

[0155] Optimized energy efficiency management: The SYS_EN signal enables precise gating of load power supply, completely cutting off the static current path to the load in the system standby or off state, further reducing the overall standby power consumption of the system.

[0156] Enhanced system integrity: As part of a monolithic fully integrated solution, its integrated protection functions (such as overcurrent and thermal shutdown) provide another line of defense, reducing reliance on external discrete protection components and improving system reliability and integration.

[0157] Clear functional boundaries: The functions of the time-sharing control and isolation module are clearly distinguished: the time-sharing control and isolation module is responsible for the alternating scheduling of energy paths and noise isolation, while the load switch module is responsible for the final enable and safety isolation of load power supply. Together, they form a complete and safe power supply link.

[0158] Mode 2: Core control integrated circuit chip plus external discrete components

[0159] See attached Figure 2 As an alternative implementation to Mode 1, this mode decouples the system into two parts: a "core control integrated circuit chip" and "external discrete device expansion components." Simultaneously, the time-sharing control and isolation module is split into a time-sharing control logic unit (3a) and an external power switch array (3b). The core control integrated circuit focuses on realizing the system's intelligent control, status monitoring, and logic scheduling functions, while tasks such as high-power processing, large-capacity energy storage, and high-performance filtering are handled by external discrete components. This architecture completely eliminates the limitations of integrated circuit technology on the performance of passive components, allowing for the free selection of optimal external components according to the application scenario, thus covering a wide range of application scenarios from medium to high power.

[0160] 1. Core control integrated circuit chip

[0161] The core control integrated circuit chip, acting as the "brain" of the system, fully integrates the system's control, sensing, and decision-making modules. These modules are all composed of low-power analog and digital circuits, and can achieve high integration and low power consumption using standard CMOS technology. Its core integrated components include:

[0162] Precharge and Start-up Module (1): Its function is the same as described in Mode 1. It monitors the voltage of the external energy storage unit EC1 through the EC2_COM pin and generates a global enable signal SYS_EN. This module ensures that the system only starts in a safe state. Voltage Detection Module (6): Its function is the same as described in Mode 1. It samples the final load voltage through the VDET_IN pin and compares it with an internal reference. It generates a switching trigger signal when the output voltage drops.

[0163] Trigger and state holding module (5): Its function is the same as described in mode 1, receiving the trigger signal from the voltage detection module and generating a deterministic state switching command.

[0164] Time-sharing control logic unit (3a): This unit integrates the core control part of the "time-sharing control and isolation module (3)" in Mode 1, specifically including:

[0165] Dead time control circuit: Ensures that a fixed dead time is inserted after the switching command is issued to prevent the external power switch from shooting through.

[0166] Gate drive logic: Generates synchronous logic signals for controlling external power switches.

[0167] Timing management: Coordinate the timing of control signals, dead time, and drive signals.

[0168] (Note: This unit does not include high-current power switching actuators; these are external components.)

[0169] 2. External discrete component expansion assembly

[0170] External discrete device expansion components, acting as the "body and limbs" of the system, are responsible for performing power tasks such as energy storage, path switching, transient suppression, and filtering. Specifically, they include:

[0171] Energy storage module (2): includes an external first energy storage unit EC1 and a second energy storage unit EC2.

[0172] External power switch array (3b): As the power execution part of the "time-sharing control and isolation module (3)", it receives drive signals from the chip's CTRL pin. This array must be designed or configured so that, in the initial power-on state, the input power supply (VIN) can charge the first energy storage unit EC1 through a default path (e.g., the normally closed terminal NC of SPDT1), while ensuring that the connection to the load is disconnected.

[0173] External load switch (8a): A power switch (such as a MOSFET) controlled by the chip's SYS_EN pin, connected in series after the external power switch array and before the CLC filter module, i.e.: external power switch array (3b) -> external load switch (8a) -> transient suppression module (4) -> CLC filter module (7) -> load, replacing the load switch module (8). This switch ensures that the load is powered only when the system is ready.

[0174] Transient suppression module (4): An external transient voltage suppression diode or array used to absorb voltage spikes during the switching process.

[0175] CLC filter module (7): an external inductor-capacitor-capacitor filter network used to filter out switching noise and high-frequency interference at the output end and to prevent high-frequency signal leakage at the load end.

[0176] 3. Selection and characteristics of external energy storage components

[0177] The external energy storage units EC1 and EC2 can be any energy storage element with rechargeable and rechargeable characteristics, and their selection directly determines the system performance.

[0178] Supercapacitors: Preferred for applications requiring high power density, extremely long cycle life, and moderate hold time. Their low equivalent series resistance facilitates high current discharge.

[0179] Lithium-ion / lithium-polymer batteries: Preferred for applications requiring high energy density and extremely long battery life. An external battery management system (BMS) is required to ensure safety.

[0180] Low ESR / ESL ceramic capacitor banks or film capacitor banks: preferred for applications with extreme requirements for size, reliability, no aging effect and ultra-low noise, and short retention time.

[0181] The three key parameters of the external energy storage unit directly dominate and are internalized as system performance variables:

[0182] Capacity (C): Proportional to the discharge time T_discharge, determining the duration for which the system can continuously supply power without input. T_discharge = C * (V_start - V_end) / I_load.

[0183] Equivalent series resistance (ESR): Directly affects the load regulation and dynamic response characteristics of the output voltage. The lower the ESR, the smaller the voltage drop caused by sudden changes in load current.

[0184] Self-discharge rate: determines the energy storage unit's ability to retain charge in an idle state, and affects the system's startup reliability after a long standby period.

[0185] 4. Pin Definitions of the Core Control Integrated Circuit Chip

[0186] The integrated circuit chip pins in this configuration mode include, but are not limited to:

[0187] VIN: Power supply pin for the chip's internal logic circuitry. To accommodate high current requirements, the system input power supply is separated from the power path here.

[0188] SW_COM_IN: External power switch array common input pin. This pin defines the system's energy input node and must be externally connected to the input common point of the power switch array.

[0189] EC1_COM: First energy storage unit connection pin. Directly connects to the common terminal of the first energy storage unit EC1 and the corresponding power switch.

[0190] EC2_COM: Second energy storage unit connection pin. Directly connects to the common terminal of the second energy storage unit EC2 and the corresponding power switch.

[0191] SW_COM_OUT: Common output pin of external power switch array. This pin is the relay station for switched power. It must be connected to the common output point of the power switch array and sent to the external load switch.

[0192] CTRL1, CTRL2: External power switch control pins. Output logic signals controlled and synchronized by internal dead time. These signals need to be amplified by an external gate driver or buffer before synchronously driving the external power switch array. SYS_EN: Enable signal pin. This signal enables other internal circuit modules of the chip and directly controls the external load switch, thereby achieving graded power-on and power-off of the system, significantly reducing system standby power consumption and ensuring safe system operation.

[0193] VDET_IN: Filter feedback input pin, input impedance > 1MΩ. This pin is crucial; it must be directly connected to the voltage point ultimately applied to the load, i.e., the output of the external CLC filter module. It provides the most accurate load voltage sample to the internal voltage sensing module, ensuring that the switching action is based on the actual voltage at the load end, which is key to achieving high-precision, seamless switching.

[0194] GND: Chip reference ground.

[0195] 5. Brief Description of System Workflow

[0196] In this mode, the switched power output from the SW_COM_OUT pin first flows through the external load switch, then undergoes spike suppression by the transient suppression module, and finally noise filtering by the CLC filter module. The resulting clean voltage is supplied directly to the load and also fed back to the internal voltage detection module via the VDET_IN pin. The chip controls the external power switch array via the CTRL pin to achieve time-sharing alternating charging and discharging; simultaneously, it controls the external load switch via the SYS_EN pin to achieve safe management of the load power supply.

[0197] Parameter design of the present invention

[0198] 1. Work cycle design

[0199] Switching period T = T_charge + T_discharge + T_deadtime

[0200] Design constraint: T_charge + T_deadtime <T_discharge×0.9

[0201] Typical parameters: T_charge = 1ms, T_discharge = 10ms, T_deadtime = 100ns

[0202] 2. Calculation of discharge time

[0203] T_discharge=C×(V_start-V_end) / I_load

[0204] Where: C is the energy storage capacity, V_start = 2.5V, V_end = 2.2V

[0205] For a 100μF capacitor and a 100mA load, T_discharge = 300μs

[0206] 3. Charging time calculation

[0207] Current-limiting resistor mode: T_charge ≈ -R_limit × C × ln(1 - V_start / V_in)

[0208] Where: R_limit = 10Ω, C = 100μF, V_in = 3.3V, V_start = 2.5V

[0209] The calculated T_charge ≈ 1.2ms

[0210] 4. CLC Filter Design

[0211] Characteristic impedance Z0 = sqrt(L / C_series), matched to the load impedance.

[0212] Cutoff frequency Fc = 1 / (2π×sqrt(L×C_series))

[0213] Typical values: L = 1 μH, C = 10 μF, Fc = 50 kHz Attached Figure Description

[0214] Figure 1 Functional block diagram of Mode 1 of the present invention

[0215] Figure 2 Functional block diagram of Mode 2 of the present invention

[0216] Figure 3 Pre-charge and startup module state transition diagram

[0217] Figure 1 describe:

[0218] The diagram illustrates the internal module block diagram of the monolithically integrated chip. The diagram clearly shows the integration relationships within the chip for the pre-charge and startup module, energy storage module (EC1, EC2), time-division control and isolation module (SPDT1, SPDT2), transient suppression module, triggering and state holding module, voltage detection module, CLC filtering module, and load switching module. The connections between external pins VIN, VOUT, GND, START, EC1_P, and EC2_P and the internal modules are clearly marked.

[0219] Figure 2 describe:

[0220] This diagram illustrates the system connection between the core control chip and external discrete components. The core control chip is at the center of the diagram, with its pins (such as SW_COM_IN, SW_COM_OUT, CTRL, EC1_COM, EC2_COM, VDET_IN) connected to external discrete component expansion modules. The diagram clearly shows the one-to-one correspondence between the function of each pin and the external component. Detailed Implementation

[0221] The embodiments of the present invention will now be described in conjunction with the accompanying drawings. Those skilled in the art will understand that these descriptions are exemplary and not intended to limit the scope of protection of the present invention.

[0222] Example 1: Monolithic Fully Integrated Mode

[0223] Reference Figure 1 This embodiment provides a highly integrated monolithic fully integrated power management chip.

[0224] The chip integrates the pre-charging and startup module (1), energy storage module (2), time-division control and isolation module (3), transient suppression module (4), triggering and state holding module (5), voltage detection module (6), CLC filtering module (7) and load switch module (8) onto a single semiconductor substrate through semiconductor manufacturing processes.

[0225] The energy storage module (2) includes a first energy storage unit EC1 and a second energy storage unit EC2, which are implemented by metal-insulator-metal capacitors or deep trench capacitors integrated inside the chip. The typical capacity range is 100pF to 100nF. The EC1_P and EC2_P pins support external capacitors with larger capacity to expand the energy storage capacity.

[0226] The core of the time-division control and isolation module (3) consists of two sets of single-pole double-throw switches (SPDT1, SPDT2), which are constructed using a CMOS transmission gate array with deep N-well isolation and a multi-finger layout to control parasitic capacitance at the flyfar level and on-resistance at the milliohm level. The dead-time control circuit integrated inside the module ensures that a fixed dead time, typically 100 nanoseconds, is inserted during state switching to completely eliminate shoot-through current. Before entering the dynamic cyclic switching mode at the initial power-on, SPDT1 defaults to connecting the external power supply to EC1 to ensure that the pre-charging and startup module can charge EC1 normally.

[0227] The pre-charge and startup module (1) operates as follows: After the system is powered on, the external power supply VIN charges EC1 through the default path. The comparator unit inside the module compares the voltage of EC1 with Vref1 generated by the precision bandgap reference source. When the voltage of EC1 reaches the target, its internal finite state machine transitions from the initialization state (S0) through the ready delay state (S1) to the system enable state (S2), and outputs a valid global enable signal (SYS_EN). After that, the system waits for the external START start pulse signal and officially enters the dynamic cyclic switching state.

[0228] During normal operation, the voltage detection module (6) continuously monitors the final output voltage VOUT. When VOUT drops below the threshold due to the discharge of the energy storage unit, a trigger signal enables the trigger and state holding module (5) (e.g., a T flip-flop) to flip, thereby driving the time-sharing control and isolation module (3) to perform path switching. Voltage spikes generated during the switching process are absorbed by the transient suppression module (4), and high-frequency noise is filtered out by the CLC filtering module (7). The load switching module (8) is controlled by the SYS_EN signal to ensure that the load is powered only after the system is fully ready.

[0229] This embodiment achieves superior performance with output noise below 5μVrms and power supply ripple rejection ratio above 110dB within a bandwidth of 10Hz to 100KHz through a collaborative design on a single chip. It is particularly suitable for low-power load scenarios that are extremely sensitive to size and noise.

[0230] Example 2: Core control chip plus external discrete components mode

[0231] Reference Figure 2 In this embodiment, the system is decoupled into a core control integrated circuit chip and an external discrete device expansion component.

[0232] The core control chip integrates the "brain" of the system, including: a pre-charge and startup module (1), a voltage detection module (6), a trigger and state holding module (5), and a time-division control logic unit (3a). This chip can be manufactured using advanced low-power CMOS technology.

[0233] The external discrete device expansion assembly serves as the "body" of the system, including:

[0234] External power switch array (3b): can use MOSFETs with low Rds_on to achieve high-efficiency power SPDT switching.

[0235] Energy storage module (2): EC1 and EC2 are external high-performance components. Supercapacitors, lithium-ion batteries or low-ESR ceramic capacitor banks can be selected according to application requirements. Their capacity (C) and equivalent series resistance (ESR) directly dominate the system's discharge time (T_discharge) and dynamic performance.

[0236] External load switch (8a): A power MOSFET controlled by the chip's SYS_EN pin.

[0237] Transient suppression module (4) and CLC filter module (7): Implemented using externally discrete passive components and TVS diodes to achieve better filtering performance and higher power handling capability.

[0238] The chip outputs a dead-time controlled logic signal via the CTRL pin to drive an external gate driver to control the external power switch array (3b). The voltage detection module (6) directly samples the final load voltage at the output of the external CLC filter network via the VDET_IN pin, ensuring the accuracy of the switching decision.

[0239] The advantage of this embodiment lies in its relocation of power dissipation and most passive components outside the chip, enabling the core control chip to operate "coldly," which greatly improves the system's reliability and mean time between failures (MTBF). Furthermore, by flexibly selecting external components, the system can easily adapt to a wide range of applications, from medium to high power, achieving unprecedented design flexibility.

[0240] It should be noted that in this article, terms such as "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0241] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications and substitutions should be covered within the scope of the claims of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

[0242] In summary, this invention does not provide an abstract circuit principle, but rather transforms the advanced concept of "time-division control and dynamic isolation" into a stable, reliable, high-performance, and industrially viable integrated circuit technology solution. Its core innovation lies in the systematic solution, through the synergistic optimization of transistor-level circuitry, layout, and system architecture, to the timing matching, parasitic parameters, system security, and design flexibility issues that are insurmountable in discrete implementation paths. This achieves a breakthrough in power supply noise suppression performance and organic system unification.

[0243] This invention, through innovative time-sharing control and dynamic isolation architecture, successfully resolves the inherent contradiction between pursuing ultra-low noise, ultra-high power supply ripple rejection ratio (PSRR), and high application flexibility in traditional power supply architectures. The proposed two configurable modes provide precise solutions for a wide range of applications, from low-power sensing to high-power output, representing a new direction for power supply noise suppression technology towards high performance and platformization. The configurable integrated circuit of this invention, with its more complete and flexible handling of timing control, parasitic parameter suppression, security mechanisms, and system coordination, represents a qualitative leap in performance, reliability, and integration compared to discrete component implementations. It is clearly a revolutionary breakthrough that is more precise, more complete, more reliable, and has a wider range of applications.

Claims

1. A configurable noise suppression integrated circuit based on time-division control and dynamic isolation, characterized in that, include: A pre-charge and start-up module (1) is used to monitor the voltage of at least the first energy storage unit (EC1) when the system is powered on, and generate a global enable signal (SYS_EN) after it reaches a first preset reference voltage to authorize the system to start; an energy storage module (2) includes a first energy storage unit (EC1) and a second energy storage unit (EC2) for alternating charging and discharging; a time-sharing control and isolation module (3) is connected to the pre-charge and start-up module (1) and the energy storage module (2) and is used to control a switching network in response to a switching command to dynamically switch between at least two states: in the first state, a charging path from the input power supply (VIN) to the first energy storage unit (EC1) and a discharging path from the second energy storage unit (EC2) to the load are constructed; In the second state, a charging path is constructed from the input power supply (VIN) to the second energy storage unit (EC2), and a discharging path is constructed from the first energy storage unit (EC1) to the load; wherein the charging path and the discharging path are physically and temporally isolated from each other; and the time-sharing control and isolation module (3) includes a dead-time control circuit for inserting a dead time during state switching to turn off all main power switches; a voltage detection module (6) for detecting the final output voltage and generating a trigger signal when the voltage is lower than a second preset reference voltage; a trigger and state holding module (5) connected to the voltage detection module (6) and the time-sharing control and isolation module (3) for generating and holding the switching command in response to the trigger signal; wherein the pre-charging and startup module (1), the energy storage module (2), the time-sharing control and isolation module (3), the voltage detection module (6), and the trigger and state holding module (5) are integrated on a single semiconductor substrate; and wherein the integrated circuit is configured to support at least one operating mode, which is selected by the chip's pin connections or internal configuration.

2. The configurable noise suppression integrated circuit according to claim 1, characterized in that, The time-sharing control and isolation module (3) includes a dead-time control circuit, which inserts a dead-time period in which all main power switches are turned off when the switch state is changed in response to the switching command, so as to prevent shoot-through current.

3. The configurable noise suppression integrated circuit according to claim 1, characterized in that, The pre-charge and start-up module (1) includes a finite state machine, whose state transition logic is: after the system is powered on or reset, it enters the initialization state (S0), and the global enable signal (SYS_EN) is invalid; When only the voltage of the first energy storage unit (EC1) reaches the first preset reference voltage, the system transitions to the ready delay state (S1). After the delay condition is met in the ready delay state (S1), the system transitions to the system enable state (S2) and outputs a valid SYS_EN signal. The system only returns to the initialization state (S0) when the voltages of the first energy storage unit (EC1) and the second energy storage unit (EC2) are both lower than their respective preset reference voltages.

4. The configurable noise suppression integrated circuit according to claim 1, characterized in that, The integrated circuit is configured as a monolithic fully integrated mode, wherein: the energy storage module (2) includes a capacitor integrated inside the chip; and the integrated circuit also includes a transient suppression module (4), a CLC filter module (7) and a load switch module (8) integrated inside the same chip.

5. The configurable noise suppression integrated circuit according to claim 1, characterized in that, The integrated circuit is configured as a core control chip, wherein: the function of the time-division control and isolation module (3) is decoupled into a time-division control logic unit (3a) integrated inside the chip and an external power switch array (3b) located outside the chip; the time-division control logic unit (3a) outputs a drive signal to the external power switch array (3b) through a control pin (CTRL); the energy storage module (2), the transient suppression module (4) and the CLC filter module (7) are all implemented by external discrete components located outside the chip.

6. The configurable noise suppression integrated circuit according to claim 5, characterized in that, The global enable signal (SYS_EN) is also output through a dedicated pin to control an external load switch (8a) located outside the chip, so as to achieve safe on / off control of the power supply to the load.

7. The configurable noise suppression integrated circuit according to claim 5, characterized in that, The voltage detection module (6) directly samples the final load voltage at the output of the external CLC filter module (7) through a high-impedance input pin (VDET_IN).

8. The configurable noise suppression integrated circuit according to claim 1, characterized in that, The switching network in the time-division control and isolation module (3) is implemented using a CMOS transmission gate array based on deep N-well isolation and multi-finger layout.

9. A power management method, implemented using a configurable noise suppression integrated circuit as described in any one of claims 1 to 8, characterized in that, Includes the following steps: Upon system power-up, a pre-charging process is executed. The system is authorized to start only when the voltage of the first energy storage unit (EC1) reaches the specified value. The system then enters a dynamic cyclic switching working state: First state: The input power supply (VIN) charges the first energy storage unit (EC1), while the second energy storage unit (EC2) discharges for the load. The load voltage is monitored in real time, and a switching trigger signal is generated when the load voltage is lower than a preset threshold. After a dead time, the system switches to the second state. Second state: The input power supply (VIN) charges the second energy storage unit (EC2), while the first energy storage unit (EC1) discharges for the load. This cycle repeats, providing clean power to the load alternately through two physically isolated paths in a time-sharing manner.

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