Continuous time three-order Sigma-delta ADC modulator and implementation method

Abstract

The invention relates to a continuous time three-order Sigma-delta ADC (Analog to Digital Converter) modulator. The continuous time three-order Sigma-delta ADC modulator comprises a loop filter and a quantizer, the loop filter adopts a first-order differential active integrator, and an input signal is subjected to first-order integration of the first-order differential active integrator to generate an output signal; the quantizer comprises a passive second-order noise shaping and feedback DAC (Digital-to-Analog Converter), and the passive second-order noise shaping performs second-order passive noise shaping and quantization to realize second-order integration and third-order integration of the modulator and output a digital signal; the feedback DAC converts the digital signal into a continuous-time analog signal, the analog signal is fed back to the input end of the loop filter, the analog signal is subtracted from the output of the feedback DAC, and then the analog signal enters the loop filter to be accumulated and filtered. By adopting the first-order differential active integrator and combining passive second-order noise shaping, second-order and third-order integrals are realized, and the method has the advantages that the signal to quantization noise ratio is improved, the loop stability is ensured, and the circuit complexity and power consumption are reduced.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a continuous-time third-order Sigma-delta ADC modulator and its implementation method. Background Technology

[0002] With the development of various mobile devices such as wearable devices and in-vehicle devices, the demand for receivers with low power consumption, small footprint, and high bandwidth in communication systems is constantly increasing. In the receiver link, a high dynamic range analog-to-digital converter (ADC) is indispensable, and continuous-time Sigma-delta modulators, with their inherent anti-aliasing filtering capabilities and continuous-time domain processing advantages, have become a common choice for receiver ADC architectures. This architecture, by avoiding the high-frequency switching problems of switched-capacitor circuits in discrete-time structures, can support larger signal bandwidths and higher sampling frequencies, thus better adapting to the application requirements of wireless communication scenarios.

[0003] Currently, there are generally three methods to improve the signal-to-quantization noise ratio (SQNR) of a Sigma-delta ADC:

[0004] One approach is to increase the sampling frequency to improve the oversampling rate (OSR). However, the need for high bandwidth and low power consumption limits the oversampling rate.

[0005] Second, increasing the order of the integrator can achieve stronger noise shaping; however, as the order increases, the loop filter is prone to stability problems.

[0006] Third, increase the number of bits in the quantizer. Commonly used quantizer structures include successive approximation register analog-to-digital converters (SAR ADCs) and flash ADCs. For SAR ADCs, due to their speed limitations, they are usually limited to eight bits or less. For Flash ADCs, due to the exponential increase in circuit size with the number of bits, they are usually limited to four bits or less. Therefore, increasing the number of bits in the quantizer has limited effect on improving SQNR.

[0007] In addition, passive noise-shaping SAR ADCs use passive loop filters to achieve noise shaping similar to Sigma-delta ADCs to improve the accuracy of SAR ADCs, but they usually only implement first-order noise shaping, which has a limited effect on improving SQNR.

[0008] Therefore, there is a lack of a solution in the existing technology that can effectively achieve high-order noise shaping while taking into account loop stability and circuit complexity control, making it difficult to meet the comprehensive requirements of modern communication systems for high-performance analog-to-digital converters. Summary of the Invention

[0009] Therefore, the purpose of this invention is to provide a continuous-time third-order Sigma-delta ADC modulator, which solves the problem of difficult-to-achieve stable and efficient high-order noise shaping in the prior art, improves the signal-to-quantization noise ratio, ensures loop stability, and reduces circuit complexity and power consumption.

[0010] To address the aforementioned technical problems, this invention provides a continuous-time third-order Sigma-delta ADC modulator, comprising: a loop filter and a quantizer. The loop filter is used to perform first-order integration (i.e., low-pass filtering) on ​​the difference between the input signal and the feedback signal. The quantizer is used to sample, quantize, and accumulate and feed back the quantization error of the first-order integrated signal. The loop filter employs a first-order differential active integrator, the input of which is connected to the input signal u(t). The input signal u(t) is integrated in the continuous-time domain by the first-order differential active integrator to generate the output signal x(t). The quantizer includes a passive second-order noise-shaping SAR. The system employs an ADC and a feedback DAC. The output signal x(t) is sampled to obtain y[n], which serves as the input signal to the quantizer. A passive second-order noise-shaping SAR ADC performs second-order passive noise shaping and quantization on y[n], achieving the second and third-order integration of the modulator, and simultaneously outputting an N-bit analog-to-digital converter (ADC) digital signal v[n]. The feedback DAC converts the digital signal v[n] into a continuous-time analog signal and feeds it back to the input of the loop filter. The difference between the input signal u(t) and the output of the feedback DAC is then fed into the loop filter for accumulation and filtering. This invention effectively resolves the contradiction between high-order noise shaping and loop stability by using a first-order differential active integrator as the loop filter and combining it with a passive second-order noise-shaping SAR ADC to achieve second and third-order integration. This results in improved signal-to-quantization noise ratio, guaranteed loop stability, and reduced circuit complexity and power consumption.

[0011] In one embodiment of the present invention, the first-order differential active integrator includes a first input resistor R1, a second input resistor R2, a first integrating capacitor C1, a second integrating capacitor C2, and an operational amplifier. One end of the first input resistor R1 and the second input resistor R2 are respectively connected to the differential input signal, and the other end of the first input resistor R1 and the second input resistor R2 are respectively connected to the differential input terminal of the operational amplifier. The differential input terminal of the operational amplifier is connected in series with the first integrating capacitor C1 and the second integrating capacitor C2 and connected in series with the differential output terminal of the operational amplifier. A first resistor Re1 for excessive loop delay compensation is connected in series in the branch where the first integrating capacitor C1 is located, and a second resistor Re2 for excessive loop delay compensation is connected in series in the branch where the second integrating capacitor C2 is located. The first resistor Re1 and the second resistor Re2 reduce the phase lag by adjusting the zero point of the loop filter, which is equivalent to reducing the loop delay.

[0012] In one embodiment of the present invention, the noise transfer function of the first-order loop of the first-order differential active integrator is: NTF1(z) = (1-z) / ( ... -1 ).

[0013] In one embodiment of the present invention, the passive second-order noise-shaping SAR ADC includes a first sampling switch S0p, a second sampling switch S0n, a first capacitor array CDACP, a second capacitor array CDACN, a first first-order passive integrating capacitor Cint1p, a second first-order passive integrating capacitor Cint1n, a first second-order passive integrating capacitor Cint2p, a second second-order passive integrating capacitor Cint2n, a first first-order integrating capacitor switch S1p, a second first-order integrating capacitor switch S1n, a first second-order integrating capacitor switch S2p, a second second-order integrating capacitor switch S2n, a comparator, and SAR logic circuitry. The first sampling switch S0p is connected to the upper plate of the first capacitor array CDACP, and the second sampling switch S0n is connected to the upper plate of the second capacitor array CDACN. The lower plates of the first capacitor array CDACP and the second capacitor array CDACN are respectively connected to a reference voltage Vref via switches. Simultaneously, the first sampling switch S0p and the second sampling switch S0n are connected to the first input terminal of the comparator. The first sampling switch S0p is also connected to the first first-order integrating capacitor switch S1p. p and the first second-order integrator capacitor switch S2p, the second sampling switch S0n is connected to the second first-order integrator capacitor switch S1n and the second second-order integrator capacitor switch S2n, the other end of the first first-order integrator capacitor switch S1p is connected to the upper plate of the first first-order passive integrator capacitor Cint1p, the other end of the first second-order integrator capacitor switch S2p is connected to the upper plate of the first second-order passive integrator capacitor Cint2p, the other end of the second first-order integrator capacitor switch S1n is connected to the upper plate of the second first-order passive integrator capacitor Cint1n, the other end of the second second-order integrator capacitor switch S2n is connected to the upper plate of the second second-order passive integrator capacitor Cint2n, and the first first-order passive integrator capacitor Cint1p and the second first-order passive integrator capacitor Cint1n are connected to the upper plate of the second second-order passive integrator capacitor Cint2n. n is connected to the second input terminal of the comparator, the first second-order passive integrating capacitor Cint2p and the second second-order passive integrating capacitor Cint2n are connected to the third input terminal of the comparator, the output of the comparator is connected to the input terminal of the SAR logic circuit, the output of the SAR logic circuit is used to control the lower plate switching of the first capacitor array CDACP and the second capacitor array CDACN, and the SAR logic circuit outputs an N-bit analog-to-digital conversion signal.

[0014] In one embodiment of the invention, the comparator has three pairs of differential inputs, the gain ratio of the first input pair, the second input pair, and the third input pair being 1:g1:g2.

[0015] In one embodiment of the present invention, the capacitance values ​​of the first first-order passive integrating capacitor Cint1p, the second first-order passive integrating capacitor Cint1n, the first second-order passive integrating capacitor Cint2p, and the second second-order passive integrating capacitor Cint2n are equal, and the capacitance value of the first first-order passive integrating capacitor Cint1p, the second first-order passive integrating capacitor Cint1n, the first second-order passive integrating capacitor Cint2p, and the second second-order passive integrating capacitor Cint2n is b / (1-b) times the total capacitance value of the first capacitor array CDACP and the second capacitor array CDACN, where b is the noise shaping zero-point coefficient.

[0016] In one embodiment of the present invention, the noise transfer function of the passive second-order noise-shaping SAR ADC is: NTF2=(1–b*z) -1 ) 2 / {1+(1-b)*[(1-b)*g2+g1–2*b / (1-b)]*z -1 +b 2 *[1-g1*(1-b) / b]*z -2}

[0017] In one embodiment of the present invention, the values ​​of the first input pair g1 and the second input pair g2 of the comparator are such that the denominator of NTF2 is 1, i.e.: g1 = b / (1-b); g2 = b / (1-b). 2 The final noise transfer function of the modulator is: NTF = NTF1 * NTF2 = (1 - z) -1 )*(1-b*z -1 ) 2 .

[0018] The present invention also provides a method for implementing a continuous-time third-order Sigma-delta ADC modulator, comprising the following steps:

[0019] During the sampling phase CLKS, the first sampling switch S0p and the second sampling switch S0n are closed to sample the input voltage onto the upper plates of the first capacitor array CDACP and the second capacitor array CDACN, respectively.

[0020] During the CLKC phase transition, the first sampling switch S0p and the second sampling switch S0n are disconnected. The first input terminal of the comparator successively acquires the upper plate voltages of the first capacitor array CDACP and the second capacitor array CDACN, and performs successive approximation comparisons. Based on the digital signal of the output comparison result, the residual voltage of the upper plate is obtained after the CLKC phase transition ends.

[0021] After the transition phase CLKC, the first-order and second-order integrals of passive noise shaping are performed on phases Φ1 and Φ2, respectively.

[0022] During the integration of phase Φ1, the first first-order integrating capacitor switch S1p and the second first-order integrating capacitor switch S1n are closed, while the first second-order integrating capacitor switches S2p ​​and S2n are opened. The upper plate of the first capacitor array CDACP and the upper plate of the first first-order passive integrating capacitor Cint1p are connected to the positive input terminal of the second input pair of the comparator. The upper plate of the second capacitor array CDACN and the upper plate of the second first-order passive integrating capacitor Cint1n are connected to the negative input terminal of the second input pair of the comparator. The residual voltage V of the first-order integration is obtained on the upper plates of the first first-order passive integrating capacitor Cint1p and the second first-order passive integrating capacitor Cint1n. Φ1 ;

[0023] During the integration of phase Φ2, the first first-order integrating capacitor switch S1p and the second first-order integrating capacitor switch S1n are disconnected, and the first second-order integrating capacitor switches S2p ​​and S2n are closed. The upper plate of the first capacitor array CDACP, the upper plate of the first second-order passive integrating capacitor Cint2p, and the positive input terminal of the third input pair of the comparator are connected. The upper plate of the second capacitor array CDACN, the upper plate of the second second-order passive integrating capacitor Cint2n, and the negative input terminal of the third input pair of the comparator are connected. The residual voltage V of the second-order integration is obtained on the upper plates of the first second-order passive integrating capacitor Cint2p and the second second-order passive integrating capacitor Cint2n. Φ2 ;

[0024] When the next conversion phase arrives, the comparator dynamically adds the residual voltage of the first and second order integrals to the voltage to be converted through the three input pairs of the comparator to complete the second-order noise shaping.

[0025] In one embodiment of the present invention, the residual voltage of the first-order integral is: V Φ1 =V CDAC *C / [C+b / (1-b)*C)]=(1-b)*V CDAC The residual voltage of the second-order integral: V Φ2 =V Φ1 *C / [C+b / (1-b)*C)]=(1-b) 2 *V CDAC .

[0026] The continuous-time third-order Sigma-delta ADC modulator of the present invention has the following advantages compared with the prior art:

[0027] Compared to the traditional third-order Sigma-delta ADC structure that requires multiple active integrators and multiple feedback DACs, this method combines a second-order passive noise-shaping SAR ADC in the quantizer, uses passive capacitors and a three-input pair comparator to achieve the second and third order integration of the modulator, retains the first-order loop filter in the continuous time domain to process large bandwidth signals and provide certain anti-aliasing characteristics, and the entire third-order modulator uses only one active integrator and one feedback DAC, which greatly saves power consumption and area, and also avoids the stability problems caused by the multi-stage active integrator with process angle and temperature changes. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a block diagram of the continuous-time third-order Si gma-delta ADC modulator of the present invention;

[0030] Figure 2 This is a circuit diagram of the continuous-time third-order Si gma-delta ADC modulator of the present invention;

[0031] Figure 3 This is the timing diagram of the second-order passive noise shaping quantizer of the present invention. Detailed Implementation

[0032] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0033] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0034] It should be noted that the following description covers various aspects of embodiments within the scope of the appended claims. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0035] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0036] Additionally, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that practice can be carried out without these specific details.

[0037] Reference Figure 1 As shown, the continuous-time third-order Sigma-delta ADC modulator of the present invention includes: a first-stage loop filter 100 and a second-stage quantizer 200; the loop filter 100 is a first-order filter used to perform first-order filtering on the difference between the input signal and the feedback signal to process large-bandwidth signals and provide anti-aliasing characteristics. The loop filter 100 can be understood as a module for preprocessing the input signal. Its main function is to perform preliminary integration on the difference between the input signal and the feedback signal to generate a continuously changing intermediate signal for subsequent sampling. In practical applications, the loop filter 100 can be implemented in various ways, such as using an operational amplifier-based integrator circuit, a charge pump-based integrator circuit, or a current mirror-based integrator circuit. Its main purpose is to achieve continuous-time domain processing of the input signal, thereby avoiding high-frequency switching problems in discrete-time structures. The quantizer 200 is used to quantize the sampled signal and accumulate and feedback the quantization error to further improve the signal-to-noise ratio. The entire continuous-time third-order Sigma-delta ADC modulator uses only one operational amplifier and one feedback DAC to achieve third-order noise shaping, effectively saving power consumption and area, and avoiding the stability problems caused by multi-stage active integrators.

[0038] Specifically, the loop filter 100 employs a first-order differential active integrator. The input of the first-order differential active integrator is connected to the input signal u(t), and the input signal u(t) is integrated in the continuous-time domain by the first-order differential active integrator to generate the output signal x(t). The quantizer 200 includes a passive second-order noise-shaping SAR ADC and a feedback DAC. The output signal x(t) is sampled to obtain y[n], which serves as the input signal of the quantizer 200. The passive second-order noise-shaping SAR ADC performs second-order passive noise shaping and quantization on y[n], realizing the second-order and third-order integration of the modulator, and simultaneously outputs an N-bit analog-to-digital converter digital signal v[n]. The feedback DAC converts the digital signal v[n] into a continuous-time analog signal and feeds it back to the input of the loop filter 100. The input signal u(t) is subtracted from the output of the feedback DAC before entering the loop filter for accumulation and filtering. The output of the passive second-order noise-shaping SAR ADC is both the input of the feedback DAC and a continuous-time third-order Sigma-delta converter. The final output of the ADC modulator. The positive output of the feedback DAC is connected to the negative input of the operational amplifier in the form of negative feedback, and the negative output is connected to the positive input of the operational amplifier. This invention achieves overall third-order noise shaping by limiting the loop filter to a first-order structure and combining it with a passive noise shaping mechanism in the quantizer. It effectively avoids the stability risks of high-order loop filters, and simultaneously utilizes the low-bit quantization capability of the passive second-order noise-shaping SAR ADC to passively extend the integration order, overcoming the limitation of quantizer bit depth on signal quality. Compared with existing technologies, this scheme significantly improves noise shaping capability without increasing the order of the loop filter or the complexity of the quantizer, meeting the application requirements of low power consumption and high bandwidth.

[0039] The aforementioned passive second-order noise-shaping SAR ADC relies solely on passive components such as switches and capacitors for noise shaping. It can be implemented through various combinations of switch, capacitor, and comparator input structures. Its primary purpose is to achieve high-order noise shaping without increasing quantizer complexity, and its performance is less affected by variations in process technology, voltage, and temperature. A feedback DAC can be understood as a module that converts digital signals to analog signals. Its main function is to feed the quantization result back to the input of the loop filter 100, subtracting it from the original input signal to form the quantization error. In practical applications, feedback DACs can be implemented in various ways, such as using a switched-capacitor-based DAC, a resistor divider network-based DAC, or a current source array-based DAC. The main purpose is to achieve seamless digital-to-analog signal conversion, thereby closing the loop.

[0040] The general principle of this invention is as follows:

[0041] The loop filter 100 employs a first-order differential active integrator. The input signal u(t) is connected to the input of this first-order differential active integrator, and after completing the first-order integration in the continuous-time domain, the output signal x(t) is generated. This process achieves preliminary suppression of low-frequency quantization noise. Further, the quantizer 200 consists of a passive second-order noise-shaping SAR ADC and a feedback DAC. The output signal x(t) is sampled and used as the input signal y[n] of the quantizer 200. Specifically, the passive second-order noise-shaping SAR ADC performs second-order passive noise shaping and quantization operations on y[n], thereby realizing the second-order and third-order integration of the modulator, and simultaneously outputting an N-bit analog-to-digital converter (ADC) digital signal v[n]. As a preferred implementation, the feedback DAC converts the digital signal v[n] into a continuous-time analog signal and feeds it back to the input of the loop filter 100, thus forming a closed-loop error feedback mechanism. The input signal u(t) is subtracted from the output of the feedback DAC and then re-enters the loop filter for accumulation and filtering, pushing the quantization noise to the high-frequency band. Through the above process, the loop filter 100 ensures system stability, while the passive second-order noise-shaping SAR ADC in the quantizer 200 supplements the remaining integration order, constructing a third-order noise transfer function as a whole, effectively suppressing the quantization noise spectrum and improving signal quality.

[0042] Reference Figure 2As shown, the first-order differential active integrator includes a first input resistor R1, a second input resistor R2, a first integrating capacitor C1, a second integrating capacitor C2, and an operational amplifier 300. The first input resistor R1 and the second input resistor R2 are key components providing a stable input path for the differential input signal. Specifically, one end of the first input resistor R1 and the second input resistor R2 are connected to the differential input signal, and the other end of the first input resistor R1 and the second input resistor R2 are connected to the differential input terminal of the operational amplifier 300. The first integrating capacitor C1 and the second integrating capacitor C2 can be understood as the core components for implementing the first-order integration function, with the purpose of... To perform continuous-time domain accumulation and filtering of the input signal, the differential input terminal of operational amplifier 300 is connected in series with a first integrating capacitor C1 and a second integrating capacitor C2, respectively, and then connected to the differential output terminal of operational amplifier 300. A first resistor Re1 is connected in series in the branch containing the first integrating capacitor C1 to compensate for excessive loop delay, and a second resistor Re2 is connected in series in the branch containing the second integrating capacitor C2 to compensate for excessive loop delay. The first resistor Re1 and the second resistor Re2 reduce the phase lag of the modulator loop by adjusting the zero point of the loop filter 100, which is equivalent to reducing the loop delay. Since there is a half-cycle excessive loop delay between sampling and quantization in a continuous-time third-order Sigma-delta ADC modulator, this excessive loop delay degrades the system stability. This invention compensates for the excessive loop delay by connecting the first integrating capacitor C1 and the second integrating capacitor C2 in series with the first integrating capacitor C1 and the second integrating capacitor C2, respectively, thereby improving loop stability. The first resistor Re1 and the second resistor Re2 are components specifically designed to compensate for excessive loop delay. They can be implemented using adjustable resistors, with the aim of dynamically adjusting the zero position of the loop filter 100 to eliminate phase errors caused by delay.

[0043] There are several methods for compensating for loop delay in continuous-time Sigma-delta ADC modulators, such as introducing an additional feedback DAC path. This first-order differential active integrator solves the loop stability problem caused by excessive loop delay by introducing a compensation resistor in the integrating capacitor branch, thus ensuring stable operation of the modulator while avoiding additional power consumption requirements. Specifically, the first input resistor R1 and the second input resistor R2 are directly connected to the differential input signal, providing an input path for the signal and transmitting the input signal to the differential input terminal of the operational amplifier 300. The differential input terminal of the operational amplifier 300 is connected to the differential output terminal through the first integrating capacitor C1 and the second integrating capacitor C2, forming a standard first-order integration function to realize continuous-time domain accumulation and filtering of the input signal. The key point is that the branch containing the first integrating capacitor C1 is connected in series with the first resistor Re1, and the branch containing the second integrating capacitor C2 is connected in series with the second resistor Re2. These two resistors are specifically designed to compensate for excessive loop delay, because excessive loop delay usually originates from the signal processing delay of the quantizer 200 and the feedback DAC, resulting in loop phase shift. By precisely setting the resistance values ​​of the first resistor Re1 and the second resistor Re2, the zero-point position of the loop filter 100 can be dynamically adjusted, introducing a leading phase, thereby adjusting the feedback coefficient of the modulator. This achieves precise compensation for the half-cycle delay, improves the signal-to-noise ratio, and stabilizes the loop. This adjustment mechanism ensures that the noise transfer function is close to ideal characteristics, maintains the integrity of third-order noise shaping, and enables the modulator to operate reliably in high-bandwidth applications without introducing additional power consumption requirements. By introducing compensation resistors into the loop filter 100, this invention not only solves the stability problem caused by excessive loop delay but also improves the overall performance of the modulator, enabling it to exhibit higher stability and stronger noise shaping capabilities in high-bandwidth applications.

[0044] The noise transfer function is a mathematical expression describing the propagation and distribution characteristics of quantized noise in a system. It can be implemented by designing the zero-pole configuration of the loop filter. In practical applications, this function can be adjusted by modifying the parameters of components such as resistors and capacitors in the loop filter to achieve the desired noise shaping effect and maintain overall stability. In this invention, the noise transfer function of the first-order loop of the first-order differential active integrator is: NTF1(z) = (1-z... -1 By setting the noise transfer function of the first-order differential active integrator as: NTF1(z) = (1-z) -1This achieves effective control over the spectral distribution of quantization noise. The functional form effectively shifts low-frequency quantization noise to the high-frequency region, significantly reducing noise power within the signal bandwidth. Based on this, the loop filter 100 and quantizer 200 work together to ensure the smooth progress of subsequent second-order noise shaping. Simultaneously, this specific form of noise transfer function provides matching conditions for the zero-point configuration of the passive second-order noise-shaping SAR ADC, avoiding loop stability problems caused by transfer function deviations, thereby improving the system's robustness.

[0045] Reference Figure 2As shown, the passive second-order noise-shaping SAR ADC includes a first sampling switch S0p, a second sampling switch S0n, a first capacitor array CDACP, a second capacitor array CDACN, a first first-order passive integrating capacitor Cint1p, a second first-order passive integrating capacitor Cint1n, a first second-order passive integrating capacitor Cint2p, a second second-order passive integrating capacitor Cint2n, a first first-order integrating capacitor switch S1p, a second first-order integrating capacitor switch S1n, a first second-order integrating capacitor switch S2p, a second second-order integrating capacitor switch S2n, a comparator 400, and a SAR logic circuit 500. The first sampling switch S0p is connected to the upper plate of the first capacitor array CDACP, and the second sampling switch S0n is connected to the upper plate of the second capacitor array CDACN. The lower plates of the first capacitor array CDACP and the second capacitor array CDACN are respectively connected to the reference voltage Vref through switches. Simultaneously, the first sampling switch S0p and the second sampling switch S0n are connected to the first input terminal of the comparator 400. The first sampling switch S0p is also connected to the first first-order integrating capacitor switch S1p. p and the first second-order integrator capacitor switch S2p, the second sampling switch S0n is connected to the second first-order integrator capacitor switch S1n and the second second-order integrator capacitor switch S2n, the other end of the first first-order integrator capacitor switch S1p is connected to the upper plate of the first first-order passive integrator capacitor Cint1p, the other end of the first second-order integrator capacitor switch S2p is connected to the upper plate of the first second-order passive integrator capacitor Cint2p, the other end of the second first-order integrator capacitor switch S1n is connected to the upper plate of the second first-order passive integrator capacitor Cint1n, the other end of the second second-order integrator capacitor switch S2n is connected to the upper plate of the second second-order passive integrator capacitor Cint2n, and the first first-order passive integrator capacitor Cint1p and the second first-order passive integrator capacitor Cint1n are connected to each other. The first second-order passive integrating capacitor Cint2p and the second second-order passive integrating capacitor Cint2n are connected to the second input terminal of comparator 400. The output of comparator 400 is connected to the input terminal of SAR logic circuit 500. The output of SAR logic circuit 500 is used to control the lower plate switching of the first capacitor array CDACP and the second capacitor array CDACN, and SAR logic circuit 500 outputs an N-bit analog-to-digital conversion signal. Specifically, the first sampling switch S0p and the second sampling switch S0n capture the input signal to the upper plate of the first capacitor array CDACP and the second capacitor array CDACN during the sampling phase, providing initial conditions for the subsequent noise shaping process. The lower plate of the first capacitor array CDACP and the second capacitor array CDACN is connected to the reference voltage Vref through a switching network. Combined with the control signal of SAR logic circuit 500, charge redistribution in the successive approximation process is realized.The key is that the first-order passive integrator Cint1p and the second-order passive integrator Cint1n are connected to the second input of comparator 400 through a corresponding switching network, completing the first stage of noise shaping in the integration phase Φ1. Meanwhile, the first-order passive integrator Cint2p and the second-order passive integrator Cint2n are connected to the third input of comparator 400 through a corresponding switching network, achieving the second stage of noise shaping in the integration phase Φ2. The three-input design of comparator 400 allows the residual voltages of different orders to be dynamically added. Combined with the successive approximation process of the SAR logic circuit 500, the quantization noise is pushed to the high-frequency region, thus significantly improving the noise shaping effect without increasing the number of bits in the quantizer. This design cleverly utilizes the characteristics of passive components, avoiding the additional power consumption caused by active components, and achieving high-order noise shaping through precise switching timing control.

[0046] Specifically, comparator 400 has three pairs of differential inputs, with a gain ratio of 1:g1:g2 for the first, second, and third input pairs. These three pairs of differential inputs refer to three independent signal access channels within comparator 400, each with differential input capability. The purpose is to achieve simultaneous processing and dynamic integration of multiple signals. In practical applications, the three pairs of differential inputs can be implemented using a multi-input cascaded structure based on operational amplifiers or a multi-input synthesis circuit based on current-mode technology. The gain ratio of 1:g1:g2 means that the three pairs of differential inputs scale the input signals with unity gain, g1 times the gain, and g2 times the gain, respectively. This ensures that the signals strictly match the mathematical model of the noise transfer function during dynamic addition. The specific values ​​of g1 and g2 can be derived using noise shaping theory and optimized according to circuit design requirements.

[0047] The comparator 400 of this invention achieves synchronous access and processing of the input voltage, first-order integral residual voltage, and second-order integral residual voltage through three pairs of differential input terminals. The first input pair directly transmits the input voltage with unity gain, ensuring the integrity of the original signal; the second input pair scales the first-order integral residual through gain g1, making its weight precisely correlated with the first-order zero coefficient in the noise transfer function; the third input pair scales the second-order integral residual through gain g2, making its weight mathematically correspond to the second-order zero coefficient in the noise transfer function. This multi-input pair architecture and the proportional design of the gain and integrating capacitor effectively avoid the need for an additional active integrator as in traditional methods. Simultaneously, the gain ratio design is based on noise shaping theory. By setting g1 and g2 to a specific functional relationship, the synthesized voltage after dynamic addition strictly follows the mathematical model of the second-order noise transfer function, thus achieving efficient shaping of quantization noise and optimization of loop stability without increasing circuit complexity. The comparator 400 in this structure solves the technical problem of passive second-order noise-shaping SAR ADCs in achieving second and third-order integration, where the comparator 400, with only a single input pair structure, cannot simultaneously receive and dynamically add the input voltage, first-order integration residual voltage, and second-order integration residual voltage. By introducing three pairs of differential input terminals and their gain ratio design, not only is the noise shaping accuracy improved, but the loop stability is also significantly enhanced, providing a reliable guarantee for the overall performance improvement of the continuous-time third-order Sigma-delta ADC modulator.

[0048] The capacitance values ​​of the first-order passive integrating capacitor Cint1p, the second-order passive integrating capacitor Cint1n, the first-order passive integrating capacitor Cint2p, and the second-order passive integrating capacitor Cint2n are all equal. Furthermore, the capacitance value of these four integrating capacitors is b / (1-b) times the total capacitance value of the first capacitor array CDACP and the second capacitor array CDACN, where b is the noise shaping zero-point coefficient. By setting the capacitance values ​​of these four integrating capacitors to be completely equal, strict symmetry of the differential signal processing path is ensured, avoiding common-mode errors and signal distortion caused by capacitor mismatch. Simultaneously, the integrating capacitor value is precisely set to b / (1-b) times the total capacitance of the capacitor array. This ratio is directly related to the noise shaping zero-point coefficient b, allowing the sampled voltage to naturally form a specific attenuation pattern through the charge distribution mechanism during the integral phase. When the capacitor value is configured in this ratio, the dynamic distribution process of the sampled voltage on the integrating capacitor achieves the theoretically expected voltage attenuation without additional compensation circuitry. This design ensures that the noise transfer function simplifies to an ideal form when combined with the comparator's 400 gain ratio, effectively shaping the quantization noise to the high-frequency region, thereby improving the modulator's noise suppression capability and stability.

[0049] The noise transfer function (NTF) is a mathematical expression describing a system's ability to shape and suppress quantization noise, which can be achieved through proper configuration of circuit parameters. The noise transfer function of a passive second-order noise-shaping SAR ADC is: NTF² = (1 – b*z) / 2. -1 ) 2 / {1+(1-b)*[(1-b)*g2+g1–2*b / (1-b)]*z -1 +b 2 *[1-g1*(1-b) / b]*z -2 The noise shaping zero-point coefficient *b* can be understood as a key parameter used to adjust the depth of noise shaping. Specifically, it can be achieved by adjusting the capacitor ratio or the feedback coefficient, with the aim of optimizing the fit between noise suppression and signal bandwidth requirements. The comparator gain parameters *g1* and *g2* refer to the gain ratio of different input pairs of the comparator. They can be achieved by designing the input stage circuit structure of the comparator or adjusting the bias current, with the aim of adjusting the pole positions through synergistic action to ensure loop stability.

[0050] This invention establishes the mathematical foundation for a passive second-order noise-shaping SAR ADC by integrating the noise-shaping zero-point coefficient b with the comparator gain parameters g1 and g2, thus solving the problem of balancing noise-shaping effectiveness and loop stability. The numerator (1–b*z) -1 ) 2 The second-order structure design can dynamically adjust the zero-point position according to the value of the noise shaping zero-point coefficient b, so that the noise suppression can accurately adapt to the signal bandwidth requirements and avoid insufficient noise shaping depth caused by a fixed zero point. In the denominator, (1-b)*[(1-b)*g2+g1–2*b / (1-b)]*z -1 The term adjusts the first-order pole coefficients through the synergistic effect of comparator gains g1 and g2, ensuring that the poles are positioned close to the complex conjugate pole pair at z=1, thereby maintaining loop stability; simultaneously, b 2 *[1-g1*(1-b) / b]*z -2 The formula controls the second-order pole coefficients based on the functional relationship between g1 and b, preventing the risk of oscillations caused by higher-order poles. Overall, this formula directly links the adjustable parameters of the circuit to the system's transfer characteristics, enabling a balance between noise suppression and stability through the flexible configuration of b, g1, and g2 when implementing second-order noise shaping. By rationally configuring the capacitance values ​​of the first-order passive integrating capacitor Cint1p, the second-order passive integrating capacitor Cint1n, the first-order passive integrating capacitor Cint2p, and the second-order passive integrating capacitor Cint2n, as well as the gain ratio of comparator 400, precise zero- and pole configuration guided by the noise transfer function model is achieved. This design not only improves the noise shaping effect but also effectively avoids loop stability problems, thereby significantly improving the signal-to-quantization noise ratio.

[0051] When the values ​​of the first input pair g1 and the second input pair g2 of the comparator 400 of the present invention make the denominator of NTF2 zero, that is: g1 = b / (1-b); g2 = b / (1-b) 2 The final noise transfer function of the modulator is: NTF = NTF1 * NTF2 = (1 - z) -1 )*(1-b*z -1 ) 2 Comparator 400 refers to a circuit structure with multiple pairs of differential inputs, which can be implemented using a three-pair differential input design. The gain ratio of the first input pair g1 and the second input pair g2 is a mathematically calculated condition aimed at ensuring that the denominator of the noise transfer function NTF2 is 1, thereby ensuring system stability and improving noise shaping. In practical applications, the specific values ​​of g1 and g2 are set based on the noise shaping zero-point coefficient b, with the aim of simplifying NTF2 to a pure second-order zero-point form (1-b*z). -1 ) 2This avoids the introduction of extra poles in the denominator, which could negatively impact system performance.

[0052] This invention addresses the stability issues that may arise from the denominator term in the noise transfer function and the degradation of noise shaping performance by setting the gain parameters g1 and g2 of the comparator 400. Specifically, when g1 and g2 are set to b / (1-b) and b / (1-b) respectively... 2 In this case, the noise transfer function NTF2 of the passive second-order noise-shaping SAR ADC is simplified, with noise shaping behavior controlled only by zeros, thus avoiding the oscillation risk caused by improper parameters in traditional designs. Based on this, the final noise transfer function NTF of the modulator is obtained by multiplying NTF1 and NTF2, forming the third-order noise transfer function (1-z). -1 )*(1-b*z -1 This result not only achieves the ideal third-order noise shaping effect, but also demonstrates significant advantages in low-power and high-bandwidth applications. It effectively solves the stability problem that may be caused by the denominator term in the noise transfer function and achieves efficient third-order noise shaping, providing a better technical path for continuous-time Sigma-delta ADC modulators.

[0053] Reference Figure 3 As shown, the operating timing of the passive second-order noise-shaping SAR ADC includes the sampling phase CLKS, the conversion phase CLKC, the first integration phase Φ1, and the second integration phase Φ2. Therefore, the signal processing steps for implementing a continuous-time third-order Sigma-delta ADC modulator are as follows:

[0054] During the sampling phase CLKS, the first sampling switch S0p and the second sampling switch S0n are closed to sample the input voltage onto the upper plates of the first capacitor array CDACP and the second capacitor array CDACN, respectively.

[0055] During the CLKC phase transition, the first sampling switch S0p and the second sampling switch S0n are disconnected. The first input terminal of the comparator 400 successively acquires the upper plate voltages of the first capacitor array CDACP and the second capacitor array CDACN, and performs successive approximation comparisons. Based on the digital signal of the output comparison result, the residual voltage of the upper plate is obtained after the CLKC phase transition ends.

[0056] After the transition phase CLKC, the first-order and second-order integrals of passive noise shaping are performed on phases Φ1 and Φ2, respectively.

[0057] During the integration of phase Φ1, the first first-order integrating capacitor switch S1p and the second first-order integrating capacitor switch S1n are closed, while the first second-order integrating capacitor switches S2p ​​and S2n are opened. The upper plate of the first capacitor array CDACP and the upper plate of the first first-order passive integrating capacitor Cint1p are connected to the positive input terminal of the second input pair of comparator 400. The upper plate of the second capacitor array CDACN and the upper plate of the second first-order passive integrating capacitor Cint1n are connected to the negative input terminal of the second input pair of comparator 400. The residual voltage V of the first-order integration is obtained on the upper plates of the first first-order passive integrating capacitor Cint1p and the second first-order passive integrating capacitor Cint1n. Φ1 ;

[0058] During the integration of phase Φ2, the first first-order integrating capacitor switch S1p and the second first-order integrating capacitor switch S1n are disconnected, and the first second-order integrating capacitor switches S2p ​​and S2n are closed. The upper plate of the first capacitor array CDACP, the upper plate of the first second-order passive integrating capacitor Cint2p, and the positive input terminal of the third input pair of comparator 400 are connected. The upper plate of the second capacitor array CDACN, the upper plate of the second second-order passive integrating capacitor Cint2n, and the negative input terminal of the third input pair of comparator 400 are connected. The residual voltage V of the second-order integration is obtained on the upper plates of the first second-order passive integrating capacitor Cint2p and the second second-order passive integrating capacitor Cint2n. Φ2 ;

[0059] When the next conversion phase arrives, the comparator 400 dynamically adds the residual voltage of the first and second order integrals to the voltage to be converted through the three input pairs of the comparator 400 to complete the second-order noise shaping.

[0060] By combining staged switching operations with a multi-input comparator structure, a second-order passive noise shaping effect is introduced into a passive second-order noise-shaping SAR ADC, thus avoiding the stability problems caused by increasing the order of the loop filter, while significantly improving the noise shaping capability. Specifically, this method captures the input signal through sampling, generates quantization residuals through phase conversion, and performs first-order and second-order integration on the residuals in the integration phases Φ1 and Φ2 respectively. Finally, the integration effect is applied to the new signal through dynamic addition of the three inputs of the comparator, forming a continuous second-order noise shaping loop. This design effectively solves the problem of limited improvement effect of single-order noise shaping and meets the application requirements of low power consumption and high bandwidth. Furthermore, by combining the collaborative work of the loop filter 100 and the quantizer 200, the loop filter 100 uses a first-order differential active integrator to achieve initial integration, and the passive second-order noise-shaping SAR ADC in the quantizer 200 performs subsequent second-order and third-order integration, thus constructing a third-order noise transfer function as a whole. Not only does it avoid the stability risks of high-order loop filters, but it also utilizes the low-bit quantization capability of the passive second-order noise-shaping SAR ADC to passively extend the integration order, overcoming the limitation of quantizer bit depth on signal quality, thereby significantly improving noise suppression capability without increasing system complexity.

[0061] The residual voltage refers to the error signal remaining after the ADC quantization process. After N-bit conversion, the residual voltage of the upper plate of the capacitor array CDACP or CDACN in the above-mentioned SAR ADC is V. CDAC The residual voltage after first-order integration: V Φ1 =V CDAC *C / [C+b / (1-b)*C)]=(1-b)*V CDAC The residual voltage after second-order integration: V Φ2 =V Φ1 *C / [C+b / (1-b)*C)]=(1-b) 2 *V CDAC .

[0062] Specifically, in a continuous-time third-order Sigma-delta ADC modulator, the mathematical relationship of the residual voltage is precisely quantized, tightly binding the circuit's physical parameters with the theoretical parameters of noise shaping. For the first-order integral, the residual voltage expression V... Φ1 = (1-b)*V CDACBased on the correlation between the total capacitance C of the capacitor array and the noise shaping zero-point coefficient b, the input voltage VCDAC is attenuated to a factor of (1-b) after charge sharing, which directly corresponds to the formation of a first-order zero in the noise transfer function. This attenuation mechanism relies on the setting of the capacitance ratio b / (1-b) to avoid zero-point shift caused by deviations in capacitor parameters due to process, voltage, and temperature variations. For the residual voltage expression V of the second-order integral... Φ2 =(1-b) 2 *V CDAC It is based on the first-order residual voltage V Φ1 By using the same capacitance ratio to achieve secondary attenuation, a square-zero characteristic of second-order noise shaping is formed. This cascaded attenuation structure ensures that the noise transfer function possesses an ideal (1-b*z)2 -1 ) 2 This design enhances high-frequency noise suppression capabilities and, in conjunction with the first-order integral characteristics of the loop filter 100, constructs a complete third-order noise shaping effect, ensuring the stability and accuracy of the noise shaping process.

[0063] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A continuous-time third-order Sigma-delta ADC modulator, characterized in that, include: A loop filter and a quantizer, wherein the loop filter is used to sample the input signal and the quantizer is used to quantize the sampled signal; The loop filter uses a first-order differential active integrator. The input terminal of the first-order differential active integrator is connected to the input signal u(t), and the input signal u(t) is integrated in the continuous time domain by the first-order differential active integrator to generate the output signal x(t). The quantizer includes a passive second-order noise-shaping SAR ADC and a feedback DAC. The output signal x(t) is sampled to obtain y[n], which serves as the input signal of the quantizer. The passive second-order noise-shaping SAR ADC performs second-order passive noise shaping and quantization on y[n] to realize the second-order integration and third-order integration of the modulator, and outputs an N-bit analog-to-digital conversion digital signal v[n]. The feedback DAC converts the digital signal v[n] into a continuous-time analog signal and feeds it back to the input of the loop filter. The input signal u(t) is subtracted from the output of the feedback DAC and then enters the loop filter for accumulation and filtering.

2. The continuous-time third-order Sigma-delta ADC modulator according to claim 1, characterized in that: The first-order differential active integrator includes a first input resistor R1, a second input resistor R2, a first integrating capacitor C1, a second integrating capacitor C2, and an operational amplifier. One end of the first input resistor R1 and the second input resistor R2 are respectively connected to the differential input signal, and the other end of the first input resistor R1 and the second input resistor R2 are respectively connected to the differential input terminal of the operational amplifier. The differential input terminal of the operational amplifier is connected in series with the first integrating capacitor C1 and the second integrating capacitor C2 and then connected to the differential output terminal of the operational amplifier. A first resistor Re1 is connected in series in the branch containing the first integrating capacitor C1 for excessive loop delay compensation, and a second resistor Re2 is connected in series in the branch containing the second integrating capacitor C2 for excessive loop delay compensation, thereby reducing the loop delay of the modulator.

3. The continuous-time third-order Sigma-delta ADC modulator according to claim 1 or 2, characterized in that: The noise transfer function of the first-order loop of the first-order differential active integrator is: NTF1(z) = (1-z) -1 ).

4. The continuous-time third-order Sigma-delta ADC modulator according to claim 1, characterized in that: The passive second-order noise-shaping SAR ADC includes a first sampling switch S0p, a second sampling switch S0n, a first capacitor array CDACP, a second capacitor array CDACN, a first first-order passive integrating capacitor Cint1p, a second first-order passive integrating capacitor Cint1n, a first second-order passive integrating capacitor Cint2p, a second second-order passive integrating capacitor Cint2n, a first first-order integrating capacitor switch S1p, a second first-order integrating capacitor switch S1n, a first second-order integrating capacitor switch S2p, a second second-order integrating capacitor switch S2n, a comparator, and SAR logic circuitry. The first sampling switch S0p is connected to the upper plate of the first capacitor array CDACP, and the second sampling switch S0n is connected to the upper plate of the second capacitor array CDACN. The lower plates of the first capacitor array CDACP and the second capacitor array CDACN are respectively connected to a reference voltage Vref via switches. Simultaneously, the first sampling switch S0p and the second sampling switch S0n are connected to the first input terminal of the comparator. The first sampling switch S0p is also connected to the first first-order integrating capacitor switch S1p. p and the first second-order integrator capacitor switch S2p, the second sampling switch S0n is connected to the second first-order integrator capacitor switch S1n and the second second-order integrator capacitor switch S2n, the other end of the first first-order integrator capacitor switch S1p is connected to the upper plate of the first first-order passive integrator capacitor Cint1p, the other end of the first second-order integrator capacitor switch S2p is connected to the upper plate of the first second-order passive integrator capacitor Cint2p, the other end of the second first-order integrator capacitor switch S1n is connected to the upper plate of the second first-order passive integrator capacitor Cint1n, the other end of the second second-order integrator capacitor switch S2n is connected to the upper plate of the second second-order passive integrator capacitor Cint2n, and the first first-order passive integrator capacitor Cint1p and the second first-order passive integrator capacitor Cint1n are connected to the upper plate of the second second-order passive integrator capacitor Cint2n. n is connected to the second input terminal of the comparator, the first second-order passive integrating capacitor Cint2p and the second second-order passive integrating capacitor Cint2n are connected to the third input terminal of the comparator, the output of the comparator is connected to the input terminal of the SAR logic circuit, the output of the SAR logic circuit is used to control the lower plate switching of the first capacitor array CDACP and the second capacitor array CDACN, and the SAR logic circuit outputs an N-bit analog-to-digital conversion signal.

5. The continuous-time third-order Sigma-delta ADC modulator according to claim 4, characterized in that: The comparator has three pairs of differential inputs, and the gain ratio of the first input pair, the second input pair, and the third input pair is 1:g1:g2.

6. The continuous-time third-order Sigma-delta ADC modulator according to claim 5, characterized in that: The capacitance values ​​of the first first-order passive integrating capacitor Cint1p, the second first-order passive integrating capacitor Cint1n, the first second-order passive integrating capacitor Cint2p, and the second second-order passive integrating capacitor Cint2n are equal, and the capacitance value of the first first-order passive integrating capacitor Cint1p, the second first-order passive integrating capacitor Cint1n, the first second-order passive integrating capacitor Cint2p, and the second second-order passive integrating capacitor Cint2n is b / (1-b) times the total capacitance value of the first capacitor array CDACP and the second capacitor array CDACN, where b is the noise shaping zero-point coefficient.

7. The continuous-time third-order Sigma-delta ADC modulator according to claim 3, characterized in that: The noise transfer function of the passive second-order noise-shaping SAR ADC is: NTF2=(1–b*z) -1 ) 2 / {1+(1-b)*[(1-b)*g2+g1–2*b / (1-b)]*z -1 +b 2 *[1-g1*(1-b) / b]*z -2 } 8. The continuous-time third-order Sigma-delta ADC modulator according to claim 7, characterized in that: The values ​​of the first input pair g1 and the second input pair g2 of the comparator make the denominator of NTF2 equal to 1, i.e.: g1 = b / (1-b); g2 = b / (1-b). 2 The final noise transfer function of the modulator is: NTF = NTF1 * NTF2 = (1 - z) -1 )*(1-b*z -1 ) 2 .

9. A method for implementing a continuous-time third-order Sigma-delta ADC modulator, characterized in that: Includes the following steps: During the sampling phase CLKS, the first sampling switch S0p and the second sampling switch S0n are closed to sample the input voltage onto the upper plates of the first capacitor array CDACP and the second capacitor array CDACN, respectively. During the CLKC phase transition, the first sampling switch S0p and the second sampling switch S0n are disconnected. The first input terminal of the comparator successively acquires the upper plate voltages of the first capacitor array CDACP and the second capacitor array CDACN, and performs successive approximation comparisons. Based on the digital signal of the output comparison result, the residual voltage of the upper plate is obtained after the CLKC phase transition ends. After the transition phase CLKC, the first-order and second-order integrals of passive noise shaping are performed on phases Φ1 and Φ2, respectively. During the integration of phase Φ1, the first first-order integrating capacitor switch S1p and the second first-order integrating capacitor switch S1n are closed, while the first second-order integrating capacitor switches S2p ​​and S2n are opened. The upper plate of the first capacitor array CDACP and the upper plate of the first first-order passive integrating capacitor Cint1p are connected to the positive input terminal of the second input pair of the comparator. The upper plate of the second capacitor array CDACN and the upper plate of the second first-order passive integrating capacitor Cint1n are connected to the negative input terminal of the second input pair of the comparator. The residual voltage V of the first-order integration is obtained on the upper plates of the first first-order passive integrating capacitor Cint1p and the second first-order passive integrating capacitor Cint1n. Φ1 ; During the integration of phase Φ2, the first first-order integrating capacitor switch S1p and the second first-order integrating capacitor switch S1n are disconnected, and the first second-order integrating capacitor switches S2p ​​and S2n are closed. The upper plate of the first capacitor array CDACP, the upper plate of the first second-order passive integrating capacitor Cint2p, and the positive input terminal of the third input pair of the comparator are connected. The upper plate of the second capacitor array CDACN, the upper plate of the second second-order passive integrating capacitor Cint2n, and the negative input terminal of the third input pair of the comparator are connected. The residual voltage V of the second-order integration is obtained on the upper plates of the first second-order passive integrating capacitor Cint2p and the second second-order passive integrating capacitor Cint2n. Φ2 ; When the next conversion phase arrives, the comparator dynamically adds the residual voltage of the first and second order integrals to the voltage to be converted through the three input pairs of the comparator to complete the second-order noise shaping.

10. The method for implementing a continuous-time third-order Sigma-delta ADC modulator according to claim 9, characterized in that: The residual voltage of the first-order integral: V Φ1 =V CDAC *C / [C+b / (1-b)*C)]=(1-b)*V CDAC The residual voltage of the second-order integral: V Φ2 =V Φ1 *C / [C+b / (1-b)*C)]=(1-b) 2 *V CDAC .

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