CSI image transmission system applied between two FPGAs

Abstract

The invention discloses a CSI (Channel State Information) image transmission system applied between two FPGAs (Field Programmable Gate Array). The CSI image transmission system comprises an FPGA sending module and an FPGA receiving module, the FPGA sending module comprises an LCD (Liquid Crystal Display) time sequence generation module, a CSI (Channel State Information) data calculation and transmission module, a superposed image transmission module and an ODDR (Optical Double Data Rate) clock double-edge sending module; the ODDR clock double-edge sending module outputs an image data signal to the FPGA receiving module through a signal output end in a serialization and clock double-edge sending mode, wherein the image data signal is received by a data signal input end; the FPGA receiving module comprises an IDDR clock double-edge receiving module, a superposed image transmission module and a CSI data calculation and display module; and the CSI data calculation and display module outputs the aligned image time sequence signal and image data signal to the LCD screen for displaying. According to the invention, high real-time performance and high transmission efficiency of the image are maintained.

Description

Technical Field

[0001] This invention relates to the field of CSI image transmission technology, specifically a CSI image transmission system applied between two FPGAs. Background Technology

[0002] FPGA (Field-Programmable Gate Array) is a user-programmable semi-custom circuit with a large number of internal memory modules and abundant I / O resources. FPGA is used in the field of imaging and has the advantages of high real-time performance and high transmission efficiency. For large-scale projects, multiple FPGAs can be cascaded or connected in parallel to realize large-scale projects.

[0003] CSI (Camera Serial Interface) is short for MIPI CSI. It is an interface standard specified by the Camera Working Group under the MIPI Alliance. CSI is usually used for outputting images and videos from cameras or other video devices. It defines the interface between camera peripherals and the receiver (usually the CPU or other main control unit), and is specifically used for the transmission of high-definition, high-frame-rate camera data.

[0004] When using FPGA as the hardware foundation for transmitting CSI images, the invention patent with application number CN202410680848.7, "A Video Transmission System and Method Based on FPGA", provides a solution: the interface processing layer extracts the CSI enable signal and high-pass signal from the video stream obtained from the MIPI interface, and then the CSI processing layer adaptively counts the number of channels based on the CSI stream, and splices the CSI stream to extract valid data based on the number of channels, so as to use the video processing layer to convert and output the AXIS data stream.

[0005] However, when transmitting CSI images between FPGAs, the transmission efficiency needs to be considered. Currently, this is generally achieved by data stitching. This method requires high stitching accuracy and increases the amount of computation, resulting in low transmission efficiency. Existing technologies can no longer meet people's current needs, and based on the current situation, there is an urgent need to improve existing technologies. Summary of the Invention

[0006] The purpose of this invention is to provide a CSI image transmission system for use between two FPGAs, in order to solve the problems mentioned in the background art.

[0007] This invention provides a CSI image transmission system applied between two FPGAs, comprising: an FPGA transmitting module and an FPGA receiving module; characterized in that: the FPGA transmitting module includes: an LCD timing generation module, a CSI data calculation and transmission module, an overlay image transmission module, and an ODDR clock dual-edge transmission module; the LCD timing generation module is coupled to the CSI data calculation and transmission module, and the LCD timing generation module generates VSYNC, HSYNC, DE, and CLK signals by counting according to the image frame rate, row and column size, and image clock rate required by the LCD display screen to communicate with the CSI data calculation and transmission module; the overlay image transmission module is coupled to the CSI data calculation and transmission module, and transmits the overlay image data signal VIDEO_DATA1 to the CSI data calculation and transmission module, and the CSI data calculation and transmission module also loads the main image data signal VIDEO_DATA0.

[0008] The CSI data calculation and transmission module output is coupled to the ODDR clock double-edge transmission module. The CSI data calculation and transmission module combines and superimposes the image data signal VIDEO_DATA1 and the main image data signal VIDEO_DATA0, and performs pipelined processing on the VSYNC, HSYNC, DE, and CLK signals, outputting aligned image timing signals and image data signal VIDEO_DATA2 to the ODDR clock double-edge transmission module. The ODDR clock double-edge transmission module has one signal output terminal and five input signal terminals, including: two data signal input terminals, one chip select signal terminal, one clock signal terminal, and one reset signal terminal. The CSI data calculation and transmission module outputs the image data signal VIDEO_DATA2 to the data signal input terminal. The CSI data calculation and transmission module outputs the clock signal to the clock signal terminal. The ODDR clock double-edge transmission module serializes the image data received at the data signal input terminal and transmits it via the clock double-edge through the signal output terminal, outputting the image data signal VIDEO_DATA3 to the FPGA receiving module.

[0009] The specific steps for the CSI data calculation and transmission module to process data include: The S101 and CSI data calculation and transmission modules calculate the number of rows (ROW) and columns (COLUMN) of the image based on the generated VSYNC, HSYNC, DE, and CLK signals. S102. Based on the number of rows (ROW) and columns (COLUMN), generate the RAM read address for reading the overlay image and the RAM read address for reading the main image according to the size of the overlay image and the main image. S103, Read the image data signal VIDEO_DATA0 from the main image RAM or read the image data signal VIDEO_DATA1 from the overlay image RAM; S104. Based on the number of rows (ROW) and columns (COLUMN), determine whether the main image or the overlay image should be output at this time, and generate a control signal. According to the requirements, use the control signal to make the overlay image cover the main image in the specified area. S105. Pipeline the VSYNC, HSYNC, DE, and CLK signals to output aligned image timing signals and image data signals VIDEO_DATA2 to the ODDR clock double-edge transmission module.

[0010] The FPGA receiving module includes: an IDDR clock double-edge receiving module, an overlay image transmission module, and a CSI data calculation and display module; the IDDR clock double-edge receiving module has two signal output terminals and four input signal terminals, including: one data signal input terminal, one chip select signal terminal, one clock signal terminal, and one reset signal terminal; The ODDR clock double-edge transmitting module sends the image data signal VIDEO_DATA3 to the data signal input terminal. The IDDR clock double-edge receiving module receives the image data in a deserialized and clock double-edge receiving manner, and outputs the image data signal VIDEO_DATA4 to the CSI data calculation and display module through the signal output terminal. The CSI data calculation and display module receives the image data signal VIDEO_DATA4, combines it with the superimposed image VIDEO_DATA5, and performs pipelined processing on the VSYNC, HSYNC, DE, and CLK signals to output aligned image timing signals and image data signal VIDEO_DATA6 for display on the LCD screen.

[0011] The specific steps for the CSI data calculation and display module to process data include: S201. Based on the generated VSYNC, HSYNC, DE, and CLK signals, calculate the number of rows (ROW) and columns (COLUMN) of the image. S202. Based on the ROW and COLUMN counts, generate the RAM read address for reading the overlay image according to the size of the overlay image and the main image, and read the image data in the RAM of the overlay image. S204. The main image data is the image received by the FPGA, which needs to be pipelined. The number of pipeline stages is the number of clock cycles required to calculate row count, column count, and image selection control. S204. Based on the ROW and COLUMN counts, determine whether to output the main image or the overlay image, generate a control signal, and make the overlay image cover the main image in the specified area. S205. Pipeline the VSYNC, HSYNC, DE, and CLK signals. The number of pipeline stages is consistent with the clock tree that needs to be calculated for the image data output. Finally, the output image data is aligned with VSYNC, HSYNC, DE, and CLK. S206 outputs aligned image timing signals and image data signals VIDEO_DATA6, which are then transmitted to the LCD screen for display.

[0012] The present invention has the following beneficial effects: This invention simulates one FPGA as a camera and another FPGA as a receiver, realizing real-time image transmission between FPGAs. Throughout the transmission process, the same VSYNC, HSYNC, and DE signal timings for the same image are maintained. Image transmission, reception, and processing are performed under the control of the timing signals, ensuring high real-time performance and high transmission efficiency throughout the entire project. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the structure of the present invention; Figure 2 This is a timing diagram of the HV mode and DE mode of the present invention; Figure 3 This is a schematic diagram of the CSI data calculation and transmission process of the present invention; Figure 4 This is a schematic diagram of the specific pin connection structure of the ODDR clock double-edge transmitting module of the present invention; Figure 5 This is a schematic diagram of the specific pin connection structure of the IDDR clock double-edge receiving module of the present invention; Figure 6 This is a schematic diagram of the CSI data calculation and display process of the present invention. Detailed Implementation

[0014] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the present invention without creative effort are within the scope of protection of the present invention.

[0015] This invention provides a CSI image transmission system applied between two FPGAs, comprising: an FPGA transmitting module and an FPGA receiving module; wherein, The FPGA transmission module includes: an LCD timing generation module, a CSI data calculation and transmission module, an overlay image transmission module, and an ODDR clock dual-edge transmission module; The LCD timing generation module is coupled to the CSI data calculation and transmission module. The LCD timing generation module generates timing signals by counting according to the image frame rate, row and column size and image clock rate required by the LCD display screen: VSYNC (field synchronization signal), HSYNC (row synchronization signal), DE (data enable signal) and CLK (clock signal) and communicates with the CSI data calculation and transmission module. For example, for a 1080P LCD screen, the image clock is generally 150MHz, the image frame rate is about 60Hz and the image size is 1920 columns * 1080 rows.

[0016] refer to Figure 2 The LCD timing generation module has two working modes: HV (horizontal and vertical synchronization) mode and DE (data enable) mode; In HV mode, the LCD screen display is controlled by using VSYNC, HSYNC, CLK, and image data signals. When using HV mode, the DE signal is ignored. In DE mode, the LCD screen display is controlled by using DE, CLK, and image data signals. When using DE mode, the VSYNC and HSYNC signals are ignored. In this embodiment, considering the need for compatibility with different hardware and to facilitate the implementation of FPGA logic, the present invention retains the VSYNC, HSYNC, and DE signals.

[0017] The overlay image transmission module is coupled to the CSI data calculation and transmission module, transmitting the overlay image data signal VIDEO_DATA1 to the CSI data calculation and transmission module. The CSI data calculation and transmission module also loads the main image data signal VIDEO_DATA0. The output of the CSI data calculation and transmission module is coupled to the ODDR clock double-edge transmission module. The CSI data calculation and transmission module combines the overlay image data signal VIDEO_DATA1 and the main image data signal VIDEO_DATA0, and performs pipelined processing on the VSYNC, HSYNC, DE, and CLK signals, outputting aligned image timing signals and image data signal VIDEO_DATA2 to the ODDR clock double-edge transmission module.

[0018] refer to Figure 3 The CSI data calculation and transmission module processes data as follows: The S101 and CSI data calculation and transmission modules calculate the number of rows (ROW) and columns (COLUMN) of the image based on the generated VSYNC, HSYNC, DE, and CLK signals.

[0019] S102. Based on the number of rows (ROW) and columns (COLUMN), generate the RAM read address for reading the overlay image and the RAM read address for reading the main image according to the size of the overlay image and the main image.

[0020] S103. Read the image data signal VIDEO_DATA0 from the main image RAM or read the image data signal VIDEO_DATA1 from the overlay image RAM.

[0021] S104. Based on the number of rows (ROW) and columns (COLUMN), determine whether the main image or the overlay image should be output at this time, and generate a control signal. According to the requirements, use the control signal to make the overlay image cover the main image in the specified area.

[0022] S105. Pipeline the VSYNC, HSYNC, DE, and CLK signals to output aligned image timing signals and image data signals VIDEO_DATA2 to the ODDR clock double-edge transmission module.

[0023] In this embodiment, the pipeline stage is consistent with the clock tree that needs to be calculated for the image data output, ensuring that the final output image data VIDEO_DATA2 is aligned with VSYNC, HSYNC, DE, and CLK.

[0024] refer to Figure 4 The ODDR clock double-edge transmission module has one signal output terminal Q and five input signal terminals, including: two data signal input terminals D1 and D2, one chip select signal terminal CE, one clock signal terminal C, and one reset signal terminal S / R; the CSI data calculation and transmission module outputs the image data signal VIDEO_DATA2 to the data signal input terminals D1 and D2; the CSI data calculation and transmission module outputs the CLK signal to the clock signal terminal C.

[0025] In this embodiment, the ODDR clock double-edge transmitting module serializes the image data received from data signal input terminals D1 and D2 and transmits it via clock double-edge transmission through signal output terminal Q to output the image data signal VIDEO_DATA3 to the FPGA receiving module; the above transmission method is specifically as follows: The input data is converted into half of the output data. On the rising edge of the clock, the level signal on the data signal input pin D1 is transmitted to the signal output pin Q; on the falling edge of the clock, the level signal on the data signal input pin D2 is transmitted to the signal output pin Q. For image data VIDEO_DATA2 and the timing control signals VSYNC, HSYNC, DE, and CLK, they can be directly output through logic combination. However, 32-bit wide image data requires ODDR conversion for output. This is mainly because FPGA pin resources are relatively limited. Using ODDR transmission saves half the pins; therefore, 32-bit image data can be transmitted to the next-level FPGA using only 16 bits. (Reference) Figure 4The chip select signal CE of the ODDR clock dual-edge transmission module is set to high level; the reset signal S / R is always set to low level to ensure that the ODDR clock dual-edge transmission module is always working normally. The 32-bit image data is divided into 16 groups, with each group consisting of 2 bits, and connected to two data signal input terminals D1 and D2. The image clock CLK is connected to the clock signal C pin of the ODDR clock dual-edge transmission module. With this architecture, the 32-bit image data can be transmitted to the next FPGA in a dual-clock edge manner. This method of image transmission simplifies the logic design and reduces the use of FPGA pin resources.

[0026] The FPGA receiving module includes: an IDDR clock dual-edge receiving module, an overlay image transmission module, and a CSI data calculation and display module.

[0027] refer to Figure 5 The IDDR clock double-edge receiving module has two signal output terminals Q1 and Q2, and four input signal terminals, including: one data signal input terminal D, one chip select signal terminal CE, one clock signal terminal C, and one reset signal terminal S / R. The IDDR clock double-edge transmitting module sends the image data signal VIDEO_DATA3 to the data signal input terminal D. The IDDR clock double-edge receiving module receives the image data in a deserialized and clock double-edge receiving manner, and outputs the image data signal VIDEO_DATA4 to the CSI data calculation and display module through the output terminals Q1 and Q2.

[0028] The IDDR clock double-edge receiving module converts the received dual-clock-edge data into single-clock-edge data. The IDDR clock double-edge receiving module is paired with the ODDR clock double-edge transmitting module to finally restore the image data to 32 bits.

[0029] In this embodiment, the IDDR clock double-edge receiving module receives data in the following way: the image data converted by the ODDR clock double-edge transmitting module is restored, so that the input data is converted into twice the output data; the image data VIDEO_DATA3 and VSYNC, HSYNC, DE, CLK are matched with the corresponding FPGA transmitting module, and the timing control signals are directly used after pipeline processing; the 16-bit received data is received and converted by the IDDR clock double-edge receiving module before being used.

[0030] refer to Figure 5The chip select signal CE of the IDDR clock double-edge receiving module is set to high level, and the reset signal S / R is always set to low level, so that the IDDR always works normally. The clock signal C of the IDDR clock double-edge receiving module is the same clock as that of the ODDR clock double-edge transmitting module. As can be seen in the figure, 16 groups of IDDR receive 16 clock double-edge data lines to restore the image data and restore the 32-bit image data input from ODDR.

[0031] The CSI data calculation and display module receives the image data signal VIDEO_DATA4, combines it with the superimposed image VIDEO_DATA5, and performs pipeline processing on the VSYNC, HSYNC, DE, and CLK signals to output aligned image timing signals and image data signals VIDEO_DATA6 for display on the LCD screen.

[0032] refer to Figure 6 The CSI data calculation and display module processes data as follows: S201. Based on the generated VSYNC, HSYNC, DE, and CLK signals, calculate the number of rows (ROW) and columns (COLUMN) of the image.

[0033] S202. Based on the ROW and COLUMN counts, generate a RAM read address for reading the overlay image according to the size of the overlay image and the main image, and read the image data in the overlay image RAM.

[0034] S204. The main image data is the image received by the FPGA, which needs to be pipelined. The number of pipeline stages is the number of clock cycles required to calculate row counts, column counts, and image selection control.

[0035] S204. Based on the ROW and COLUMN counts, determine whether to output the main image or the overlay image, generate a control signal, and make the overlay image cover the main image in the specified area.

[0036] S205. Pipeline the VSYNC, HSYNC, DE, and CLK signals. The number of pipeline stages is consistent with the clock tree that needs to be calculated for the image data output. Finally, the output image data is aligned with VSYNC, HSYNC, DE, and CLK.

[0037] S206 outputs aligned image timing signals and image data signals VIDEO_DATA6, which are then transmitted to the LCD screen for display.

[0038] In this embodiment, when transmitting image data between two FPGAs, the VSYNC / HSYNC / DE / CLK signals used are always the image timing signals generated in the FPGA transmitting module. Subsequent pipeline processing is simply performed to ensure that they are consistent with the transmitted image data.

[0039] As another optional embodiment of the present invention, in large-scale projects, when multiple FPGA architectures are used to receive and process images separately, this approach has more obvious advantages: multiple FPGAs are connected in series or in parallel, using the same CSI timing, and simultaneously superimposed and transmitted image data acquired by multiple FPGAs for display.

[0040] Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A CSI image transmission system applied between two FPGAs, comprising: FPGA transmitting module and FPGA receiving module; characterized in that: The FPGA transmission module includes: an LCD timing generation module, a CSI data calculation and transmission module, an overlay image transmission module, and an ODDR clock dual-edge transmission module; The LCD timing generation module is coupled to the CSI data calculation and transmission module. The LCD timing generation module generates timing signals (VSYNC, HSYNC, DE, CLK signals) by counting according to the image frame rate, row and column size and image clock rate required by the LCD display screen. These signals communicate with the CSI data calculation and transmission module. The overlay image transmission module is coupled to the CSI data calculation and transmission module, and transmits the overlay image data signal VIDEO_DATA1 to the CSI data calculation and transmission module. The CSI data calculation and transmission module also loads the main image data signal VIDEO_DATA0. The output of the CSI data calculation and transmission module is coupled to the ODDR clock double-edge transmission module. The CSI data calculation and transmission module combines the superimposed image data signal VIDEO_DATA1 and the main image data signal VIDEO_DATA0, and performs pipelined processing on the VSYNC, HSYNC, DE, and CLK signals, outputting aligned image timing signals and image data signal VIDEO_DATA2 to the ODDR clock double-edge transmission module. The ODDR clock double-edge transmission module has one signal output terminal and five input signal terminals, including: two data signal input terminals, one chip select signal terminal, one clock signal terminal, and one reset signal terminal; the CSI data calculation and transmission module outputs the image data signal VIDEO_DATA2 to the data signal input terminal; the CSI data calculation and transmission module outputs the clock signal to the clock signal terminal. The ODDR clock double-edge transmission module serializes the image data received at the data signal input terminal and transmits it via clock double-edge transmission through the signal output terminal to output the image data signal VIDEO_DATA3 to the FPGA receiving module. The FPGA receiving module includes: an IDDR clock dual-edge receiving module, an overlay image transmission module, and a CSI data calculation and display module; The IDDR clock dual-edge receiving module has two signal output terminals and four input signal terminals, including: one data signal input terminal, one chip select signal terminal, one clock signal terminal, and one reset signal terminal. The ODDR clock double-edge transmitting module sends the image data signal VIDEO_DATA3 to the data signal input terminal. The IDDR clock double-edge receiving module receives image data in a deserialized, clock double-edge receiving manner, and outputs the image data signal VIDEO_DATA4 to the CSI data calculation and display module through the signal output terminal. The CSI data calculation and display module receives the image data signal VIDEO_DATA4, combines it with the superimposed image VIDEO_DATA5, and performs pipeline processing on the VSYNC, HSYNC, DE, and CLK signals to output aligned image timing signals and image data signals VIDEO_DATA6 for display on the LCD screen.

2. The CSI image transmission system applied between two FPGAs according to claim 1, characterized in that: The LCD timing generation module has two working modes: HV mode and DE mode; The HV mode controls the LCD screen display by using VSYNC, HSYNC, CLK and image data signals, and the DE signal is ignored when using HV mode; The DE mode uses DE, CLK, and image data signals to control the LCD screen display, and ignores the VSYNC and HSYNC signals when using DE mode.

3. A CSI image transmission system applied between two FPGAs according to claim 1, characterized in that: The specific steps involved in data processing by the CSI data calculation and transmission module include: The S101 and CSI data calculation and transmission modules calculate the number of rows (ROW) and columns (COLUMN) of the image based on the generated VSYNC, HSYNC, DE, and CLK signals. S102. Based on the number of rows (ROW) and columns (COLUMN), generate the RAM read address for reading the overlay image and the RAM read address for reading the main image according to the size of the overlay image and the main image. S103, Read the image data signal VIDEO_DATA0 from the main image RAM or read the image data signal VIDEO_DATA1 from the overlay image RAM; S104. Based on the number of rows (ROW) and columns (COLUMN), determine whether the main image or the overlay image should be output at this time, and generate a control signal. According to the requirements, use the control signal to make the overlay image cover the main image in the specified area. S105. Pipeline the VSYNC, HSYNC, DE, and CLK signals to output aligned image timing signals and image data signals VIDEO_DATA2 to the ODDR clock double-edge transmission module.

4. A CSI image transmission system applied between two FPGAs according to claim 3, characterized in that: The number of pipeline stages in step S105 is consistent with the clock tree that needs to be calculated for the image data output, so that the output image data VIDEO_DATA2 is aligned with the timing signals VSYNC, HSYNC, DE, and CLK.

5. A CSI image transmission system applied between two FPGAs according to claim 1, characterized in that: The IDDR clock dual-edge receiving module converts the received dual-clock-edge data into single-clock-edge data.

6. A CSI image transmission system applied between two FPGAs according to claim 1, characterized in that: The parameters for the IDDR clock double-edge receiving module are set as follows: the chip select signal is set to high level, the reset signal is always set to low level, and the clock signal is the same as that of the IDDR clock double-edge transmitting module; so that the IDDR in the IDDR clock double-edge receiving module always works normally.

7. A CSI image transmission system applied between two FPGAs according to claim 1, characterized in that: The ODDR clock double-edge transmitting module uses a transmitting method that can convert the input data into half of the output data; The specific operation is as follows: when the clock is rising, the level signal on one of the data signal input pins is transmitted to the signal output pin; when the clock is falling, the level signal on the other data signal input pin is transmitted to the signal output pin. The image data VIDEO_DATA2 and the timing control signals VSYNC, HSYNC, DE, and CLK are directly output through logic combination.

8. A CSI image transmission system applied between two FPGAs according to claim 1, characterized in that: The IDDR clock double-edge receiving module can restore the image data converted by the ODDR clock double-edge sending module, thus converting the input data into twice the output data. The specific operation is as follows: the image data VIDEO_DATA3 and VSYNC, HSYNC, DE, CLK are matched with the corresponding FPGA transmission module, the timing control signals are processed in a pipeline and used directly, and the received data is received and converted by the IDDR clock dual-edge receiving module before use.

9. A CSI image transmission system applied between two FPGAs according to claim 1, characterized in that: The specific steps for the CSI data calculation and display module to process data include: S201. Based on the generated VSYNC, HSYNC, DE, and CLK signals, calculate the number of rows (ROW) and columns (COLUMN) of the image. S202. Based on the ROW and COLUMN counts, generate the RAM read address for reading the overlay image according to the size of the overlay image and the main image, and read the image data in the RAM of the overlay image. S204. The main image data is the image received by the FPGA, which needs to be pipelined. The number of pipeline stages is the number of clock cycles required to calculate row count, column count, and image selection control. S204. Based on the ROW and COLUMN counts, determine whether to output the main image or the overlay image, generate a control signal, and make the overlay image cover the main image in the specified area. S205. Pipeline the VSYNC, HSYNC, DE, and CLK signals. The number of pipeline stages is consistent with the clock tree that needs to be calculated for the image data output. Finally, the output image data is aligned with VSYNC, HSYNC, DE, and CLK. S206 outputs aligned image timing signals and image data signals VIDEO_DATA6, which are then transmitted to the LCD screen for display.

10. A CSI image transmission system applied between two FPGAs according to claim 1, characterized in that: When transmitting image data between the FPGA transmitting module and the FPGA receiving module, VSYNC, HSYNC, DE, and CLK are always the image timing signals generated by the FPGA transmitting module. Subsequent processing is simply pipelined to ensure they are consistent with the transmitted image data.

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