Method of manufacturing semiconductor device, semiconductor device, and printed circuit board

Abstract

Embodiments described herein generally relate to a method of manufacturing a semiconductor device, a semiconductor device, and a printed circuit board. According to one embodiment, a method of manufacturing a semiconductor device includes providing a printed circuit board having a first surface on which a first solder resist is formed and a second surface opposite the first surface and on which a second solder resist is formed, the second solder resist having a first region and a second region, wherein in a first direction perpendicular to the second surface, the thickness of the second solder resist in the first region is greater than that of the second solder resist in the second region; placing a semiconductor chip on the first solder resist of the printed circuit board; sealing the semiconductor chip on the printed circuit board; and removing a portion of the second solder resist in the first region.

Description

[0001] Cross-referencing related applications

[0002] This application is based on and claims priority to Japanese Patent Application No. 2024-181888, filed October 17, 2024, and U.S. Patent Application No. 19 / 063,206, filed February 25, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments described herein generally relate to a method of manufacturing a semiconductor device, a semiconductor device, and a printed circuit board. Background Technology

[0004] A semiconductor device is known having a semiconductor chip disposed on a printed circuit board, wherein solder resist is interposed between the semiconductor chip and the printed circuit board. In recent years, there has been a demand for thinner semiconductor devices, but thinner devices are more susceptible to warping. Summary of the Invention

[0005] The embodiments provide a method for manufacturing a semiconductor device, a semiconductor device, and a printed circuit board that can reduce the warpage of a printed circuit board.

[0006] Examples are provided.

[0007] A method for manufacturing a semiconductor device, comprising:

[0008] (a) A printed circuit board is provided having a first surface on which a first solder resist is formed and a second surface opposite to the first surface on which a second solder resist is formed, the second solder resist having a first region and a second region, wherein in a first direction perpendicular to the second surface, the thickness of the second solder resist in the first region is greater than the thickness of the second solder resist in the second region.

[0009] (b) Placing the semiconductor chip on the first solder resist of the printed circuit board;

[0010] (c) Sealing the semiconductor chip onto the printed circuit board; and

[0011] (d) Remove a portion of the second solder resist in the first region.

[0012] Furthermore, the embodiments provide,

[0013] A semiconductor device comprising:

[0014] A core component having a first surface and a second surface opposite to the first surface;

[0015] A first prepreg is formed on the first surface;

[0016] A second prepreg is formed on the second surface and has a third region and a fourth region;

[0017] A first solder resist is formed on the first prepreg;

[0018] A second solder resist is formed on the second prepreg and has a first region and a second region;

[0019] A semiconductor chip disposed on the first solder resist; and

[0020] Sealing resin, which seals the semiconductor chip.

[0021] The third region is disposed at a position where it overlaps with the first region in a first direction perpendicular to the second surface, and the fourth region is disposed at a position where it overlaps with the second region in the first direction.

[0022] The second solder resist in the first region is formed to be thicker than the second solder resist in the second region in the first direction, and a portion of the second solder resist will be removed.

[0023] Furthermore, the embodiments provide,

[0024] A printed circuit board comprising:

[0025] A core material having a first surface and a second surface opposite to the first surface;

[0026] A first prepreg is formed on the first surface;

[0027] A second prepreg is formed on the second surface and has a third region and a fourth region;

[0028] A first solder resist is formed on the surface of the first prepreg opposite to the first surface; and

[0029] A second solder resist is formed on the surface of the second prepreg opposite to the second surface and has a first region and a second region.

[0030] The third region is disposed at a position where it overlaps with the first region in a first direction perpendicular to the second surface, and the fourth region is disposed at a position where it overlaps with the second region in the first direction.

[0031] In the first direction, the thickness of the second solder resist in the first region is greater than the thickness of the second solder resist in the second region. Attached Figure Description

[0032] Figure 1 This is a cross-sectional view illustrating the configuration of a semiconductor device according to an embodiment (an intermediate state before a portion of the solder resist is removed).

[0033] Figure 2 This is a cross-sectional view illustrating the configuration of a semiconductor device according to an embodiment (in a completed state after a portion of the solder resist has been removed).

[0034] Figure 3 This is a bottom view illustrating the configuration of a semiconductor device according to an embodiment.

[0035] Figure 4 This is a bottom view illustrating the configuration of a plurality of printed circuit boards framed into a single printed circuit board according to an embodiment.

[0036] Figure 5 This is a cross-sectional view illustrating the configuration of a region of a printed circuit board according to an embodiment.

[0037] Figure 6 This is a cross-sectional view illustrating the configuration of another region of a printed circuit board according to an embodiment.

[0038] Figure 7 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0039] Figures 8 to 13 These are cross-sectional views illustrating the steps of manufacturing a semiconductor device according to an embodiment.

[0040] Figure 14 This is a flowchart illustrating a method for manufacturing a semiconductor device according to another embodiment. Detailed Implementation

[0041] The embodiments provide a method for manufacturing a semiconductor device, a semiconductor device, and a printed circuit board that can reduce the warpage of a printed circuit board.

[0042] Generally, according to one embodiment, a method of manufacturing a semiconductor device includes: providing a printed circuit board having a first surface on which a first solder resist is formed and a second surface opposite to the first surface on which a second solder resist is formed, the second solder resist having a first region and a second region, wherein in a first direction perpendicular to the second surface, the thickness of the second solder resist in the first region is greater than the thickness of the second solder resist in the second region; placing a semiconductor chip on the first solder resist of the printed circuit board; sealing the semiconductor chip on the printed circuit board; and removing a portion of the second solder resist in the first region.

[0043] According to another embodiment, a semiconductor device includes: a die having a first surface and a second surface opposite to the first surface; a first prepreg formed on the first surface; a second prepreg formed on the second surface and having a third region and a fourth region; a first solder resist formed on the first prepreg; a second solder resist formed on the second prepreg and having a first region and a second region; a semiconductor chip disposed on the first solder resist; and a sealing resin sealing the semiconductor chip, wherein the third region is disposed at a position where the third region overlaps with the first region in a first direction perpendicular to the second surface, and the fourth region is disposed at a position where the fourth region overlaps with the second region in the first direction, and wherein the second solder resist in the first region is formed to be thicker than the second solder resist in the second region in the first direction, and a portion of the second solder resist is to be removed.

[0044] According to another embodiment, a printed circuit board includes: a core material having a first surface and a second surface opposite to the first surface; a first prepreg formed on the first surface; a second prepreg formed on the second surface and having a third region and a fourth region; a first solder resist formed on the surface of the first prepreg opposite to the first surface; and a second solder resist formed on the surface of the second prepreg opposite to the second surface and having a first region and a second region, wherein the third region is disposed at a position where the third region overlaps with the first region in a first direction perpendicular to the second surface, and the fourth region is disposed at a position where the fourth region overlaps with the second region in the first direction, and wherein in the first direction, the thickness of the second solder resist in the first region is greater than the thickness of the second solder resist in the second region.

[0045] In the following description, embodiments will be illustrated with reference to the figures.

[0046] The diagrams provided below are schematic and may differ from actual measurements in terms of thickness-to-planar dimensions, layer thickness ratios, etc. Furthermore, some parts may have different dimensional relationships and ratios between diagrams. In the following description, elements with substantially the same function and configuration are represented by the same reference numerals and symbols. The letter characters following the letters in the reference numerals and symbols are used to distinguish elements with similar configurations from reference numerals containing the same letters. In this specification, a step includes not only a single step but also combinations of said step with other steps and other processes.

[0047] First, define a first direction, a second direction, and a third direction. The first direction is perpendicular to the first surface 1a of the printed circuit board 1, which will be described later. The second and third directions are directions that intersect (for example, are perpendicular to) the first direction. In other words, the second and third directions are directions parallel to the first surface 1a of the printed circuit board 1.

[0048] 1. Structure (Configuration)

[0049] 1.1. Semiconductor Devices

[0050] Figure 1 This is a cross-sectional view illustrating the configuration (in an intermediate state) of the semiconductor device 100 according to an embodiment. Figure 2 This is a cross-sectional view illustrating the configuration (in a completed state) of the semiconductor device 100 according to an embodiment. Figure 3 The basis for observation from the lower side Figure 1 and 2 The diagram shows a bottom view of the configuration of the semiconductor device 100 in the embodiment shown. Figure 1 The image shows the intermediate state before a portion of the second solder resist 15b is removed. Figure 2 This demonstrates the "finished state after a portion of the second solder resist 15b has been removed following the intermediate state." For details regarding the method of manufacturing the semiconductor device 100, please refer to "2. Manufacturing Method," which will be described later. Figure 1 As shown, the semiconductor device 100 includes a printed circuit board 1, an adhesive 2, a stack of semiconductor chips 3, connecting components 4, a sealing resin 5, and metal bumps 6.

[0051] The printed circuit board 1 includes a core component 11, a first prepreg 12a, a second prepreg 12b, interconnect layers 13a and 13b, through-holes 14, a first solder resist 15a, a second solder resist 15b and 15c, a pad 16, and an electrode 17. The printed circuit board 1 has a first surface 1a and a second surface 1b opposite to the first surface 1a. Furthermore, the printed circuit board 1 may have a multilayer wiring structure formed by stacking multiple interconnect layers and multiple insulating layers.

[0052] The core component 11 has a third surface 11a and a fourth surface 11b opposite to the third surface 11a. For example, an insulating material such as glass epoxy resin is used for the core component.

[0053] Interconnect layer 13a is disposed on the third surface 11a of the core component 11. Interconnect layer 13b is disposed on the fourth surface 11b of the core component 11. Interconnect layers 13a and 13b are electrically connected through via 14. When it is not necessary to distinguish between interconnect layers 13a and 13b, interconnect layers 13a and 13b are described as interconnect layer 13.

[0054] A first prepreg 12a is disposed on a third surface 11a of the core component 11. A second prepreg 12b is disposed on a fourth surface 11b of the core component 11. The second prepreg 12b has a third region 12b3 and a fourth region 12b4. The third region 12b3 is an example of a third region. The fourth region 12b4 is an example of a fourth region. In a first direction, the thickness of the third region 12b3 may be equal to or less than the thickness of the fourth region 12b4. In one embodiment, for example, the thickness ratio of the fourth region 12b4 to the third region 12b3 of the prepreg is 1.25 or greater.

[0055] A first solder resist 15a is disposed on a first prepreg 12a. The first solder resist 15a covers the first prepreg 12a except for the portion corresponding to the pad 16. A second solder resist 15b is disposed on a second prepreg 12b. The second solder resist 15b covers the second prepreg 12b except for the portion corresponding to the electrode 17. The second solder resist 15b has a first region 15b1 corresponding to a third region 12b3 of the second prepreg 12b and a second region 15b2 corresponding to a fourth region 12b4 of the second prepreg 12b. In a first direction, the thickness of the second solder resist 15b in the first region 15b1 is equal to or greater than the thickness of the second solder resist 15b in the second region 15b2. In one embodiment, for example, the thickness ratio of the first region 15b1 to the second region 15b2 of the solder resist is 1.25 or greater. The first solder resist 15a electrically insulates the first prepreg 12a to protect the first prepreg 12a.

[0056] A pad 16 is disposed on the first prepreg 12a. The pad 16 may be part of the interconnect layer 13a. The pad 16 contains a conductive material such as copper (Cu). An electrode 17 is disposed on the second prepreg 12b. The electrode 17 may be part of the interconnect layer 13b. The electrode 17 contains a conductive material such as copper (Cu). A metal bump 6 is disposed on the electrode 17. The metal bump 6 is electrically connected to the interconnect layer 13b through the electrode 17. The metal bump 6 may be disposed on the electrode 17 after “step S6 (step of removing a portion of the second solder resist)”, which will be described later. A conductive material such as solder is used for the metal bump 6.

[0057] Adhesive 2 is a thermosetting resin. For example, adhesive 2 is epoxy resin, polyimide resin, acrylic resin, or a mixture of these resins. For example, adhesive 2 may be a bare film attachment film (DAF).

[0058] Semiconductor chips 3 are stacked on a first surface 1a of a printed circuit board 1, and an adhesive 2 is inserted between the stack of semiconductor chips and the first surface. Additionally, the adhesive 2 is disposed between the semiconductor chips 3 in the stack. Each semiconductor chip 3 has a pad 21 on the periphery of its surface. Pads 16 and 21 are electrically connected by conductive connection components 4, such as bonding wires. Pads 16 and 21 are connected one-to-one.

[0059] Semiconductor chip 3 can be, for example, a NAND flash memory chip, but is not limited to NAND flash memory. For example, any semiconductor chip can be used, such as a memory element like dynamic random access memory (DRAM), a computing element like a microprocessor, a signal processing element, and so on. It should be noted that semiconductor chip 3 can be configured as a single chip rather than multiple stacked chips.

[0060] The sealing resin 5 seals the first surface 1a of the printed circuit board 1, the adhesive 2, the semiconductor chip 3, and the connecting components 4. For example, a thermosetting resin such as epoxy resin is used as the sealing resin 5.

[0061] The metal bump 6 is electrically connected to the interconnect layer 13 via electrode 17. Conductive materials such as solder are used for the metal bump 6. Figure 2 As shown in the figure, Figure 1 In the intermediate state of the semiconductor device 100 shown, a portion of the solder resist 15b is removed under predetermined conditions to form solder resist 15c. Thus, the manufacturing of the semiconductor device 100 is completed. The predetermined conditions mentioned above (e.g., the location and amount of the portion to be removed) are selected as follows: Individual diced samples of the semiconductor device are provided separately, and measurement tests are performed using multiple samples with different conditions, such as the location and amount of the portion to be removed, and conditions for reducing warpage of the printed circuit board are selected from these conditions. For details, please refer to "2. Manufacturing Method" described later. Solder resist 15c refers to the solder resist obtained after removing a portion of the solder resist 15b from the first region 15b1. Solder resist 15c electrically insulates the second prepreg 12b to protect the second prepreg 12b. Figure 3 As shown, the first region 15b1 of the solder resist 15c surrounds the periphery of the second region 15b2 of the solder resist 15c. Generally, a problem with semiconductor devices having printed circuit boards is that the warpage of the printed circuit board increases as its thickness decreases. Return to Figure 1 As described, in the semiconductor device 100 according to an embodiment, the thickness of the second solder resist 15b in the first region 15b1 is thicker than the thickness of the second solder resist 15b in the second region 15b2. Furthermore, under conditions for reducing printed circuit board warpage, a portion of the solder resist 15b is removed from the first region 15b1. This may reduce printed circuit board warpage. In other words, the semiconductor device 100 has a solder resist 15b of sufficient thickness to reduce printed circuit board warpage. Therefore, it may reduce printed circuit board warpage.

[0062] 1.2. Printed Circuit Board

[0063] Here, the printed circuit board 1 that forms the semiconductor device 100 will be described. Figure 4 This is a bottom view illustrating the configuration of a semiconductor device 100 according to this embodiment, in which multiple printed circuit boards 1 are jointly framed into a single printed circuit board. Prepreg 12b3 is an example of a third region. Prepreg 12b4 is an example of a fourth region. It should be noted that in... Figure 4 Interconnect layer 13, via 14, solder resist 15, and electrode 17 are omitted. For details on the method of manufacturing the semiconductor device 100 having the printed circuit board 1, please refer to "2. Manufacturing Method" which will be described later.

[0064] By printing circuit boards (e.g.) Figure 4 The printed circuit board shown is divided into individual components to obtain a chip-shaped semiconductor device 100. In the printed circuit board before division, multiple semiconductor devices 100 are arranged, for example, in a matrix shape. Scribing lines 12s for dividing the semiconductor device 100 into individual components are provided between the individual semiconductor devices 100. Figure 5 It is observed from a second or third direction. Figure 4 An example of a cross-sectional view of a magnified view of part A in the diagram. Figure 5 This is a simplified illustration. Figure 1 A partial view. It should be noted that in... Figure 5Interconnect layer 13, via 14, and electrode 17 are omitted. In the printed circuit board according to the embodiment, the thickness of the second solder resist 15b in the first region 15b1 is greater than the thickness of the second solder resist 15b in the second region 15b2. Therefore, a portion of the second solder resist 15b in the first region 15b1 can be removed under a wide range of conditions. Therefore, by removing a portion of the second solder resist 15b under conditions that reduce the warpage of the printed circuit board, the warpage of the printed circuit board may be reduced (effect 1). Furthermore, in the printed circuit board according to the embodiment, in the first direction, the thickness of the second solder resist 15b in the first region 15b1 is greater than the thickness of the first solder resist 15a. In related art, the thicknesses of the first solder resist 15a and the second solder resist 15b disposed on both sides of the printed circuit board 1 are substantially the same. Meanwhile, in the method of manufacturing a semiconductor device according to the embodiment, the thicknesses are made different, making the thicknesses unbalanced, and then a portion of the thicker portion is removed to balance the thicknesses. Therefore, the warpage of the printed circuit board is reduced. Therefore, it is possible to reduce the warpage of the printed circuit board with higher accuracy (Effect 2). Furthermore, in the printed circuit board according to the embodiment, the thickness of the second prepreg 12b in the third region 12b3 is less than the thickness of the second prepreg 12b in the fourth region 12b4. In this state, when the second solder resist 15b is formed on the second prepreg 12b, the thickness of the first region 15b1 of the second solder resist 15b becomes greater than the thickness of the second region 15b2. Therefore, to increase the thickness of the first region 15b1 of the second solder resist 15b, it is not necessary to add a solder resist coating step. Therefore, it is possible to easily reduce the warpage of the printed circuit board (Effect 3). Furthermore, in the printed circuit board according to the embodiment, in a state where multiple printed circuit boards 1 are framed into one printed circuit board, semiconductor chips disposed on the respective printed circuit boards 1 are sealed with resin. Then, in a state where the printed circuit boards 1 are still framed, a portion of the thicker portion of the second solder resist is removed. Thus, it is possible to easily perform the process of reducing the warpage of the printed circuit board (Effect 4).

[0065] Figure 6 It is observed from a second or third direction. Figure 4 An example of a cross-sectional view of a magnified view of part A in the diagram. It should be noted that... Figure 6 Interconnect layer 13, via 14, and electrode 17 are omitted. Regarding the uniform thickness of the second prepreg 12b and the shape of the second solder resist 15bb disposed on the second prepreg 12b, Figure 6 and Figure 5 They are different. In the first direction, the thickness of the first region 15b1 of the solder resist 15bb is greater than the thickness of the second region 15b2 of the solder resist 15bb.

[0066] 2. Manufacturing method

[0067] 2.1. Method for manufacturing semiconductor devices

[0068] The method of manufacturing a semiconductor device according to this embodiment will be described below. Figure 7 This is a flowchart illustrating a method for manufacturing a semiconductor device according to this embodiment. Figure 4 As shown in the illustration, in this embodiment, the following steps are performed sequentially: providing a printed circuit board (step S1); placing a semiconductor chip on the printed circuit board (step S2); performing a baking process (step S3); electrically connecting the semiconductor chip to the printed circuit board (step S4); sealing (step S5); and removing a portion of the second solder resist (step S6). These steps will be described below.

[0069] 2.1.1. Step S1 (Providing the printed circuit board)

[0070] First, provide such Figure 8 The printed circuit board 1 shown in the figure. The printed circuit board 1 has a first surface 1a on which a first solder resist 15a is formed and a second surface 1b facing the first surface 1a and on which a second solder resist 15b is formed, the second solder resist having a first region 15b1 and a second region 15b2. Furthermore, in a first direction perpendicular to the second surface 1b, the thickness of the second solder resist 15b in the first region 15b1 is greater than the thickness of the second solder resist 15b in the second region 15b2. A plurality of printed circuit boards described above are framed to form a single printed circuit board. The plurality of printed circuit boards used in steps S2 to S6 described later are framed to form a single printed circuit board. The framed printed circuit board 1 can be formed by a semiconductor device manufacturer, but is typically formed by a printed circuit board manufacturer. When the printed circuit board manufacturer forms the framed printed circuit board 1, the semiconductor device manufacturer obtains the framed printed circuit board 1 from the printed circuit board manufacturer and manufactures the semiconductor device 100 by using the framed printed circuit board 1.

[0071] 2.1.2. Step S2 (the step of placing the semiconductor chip on the printed circuit board)

[0072] Next, as Figure 9As shown, a stack of semiconductor chips 3 (with adhesive 2 attached to the back surface of the stack) is placed on a first surface 1a of a printed circuit board 1. Through holes are formed in the core component 11 using a drill bit or the like. Through-holes 14 are then formed by filling the interior of each through hole with copper or the like. Note that through-holes 14 can be formed by electroplating the side surfaces of the through holes with copper or the like. An interconnect layer 13 is then formed on the core component 11 using known methods. A first prepreg 12a is then applied to a third surface 11a of the core component. Solder resist 15a is then applied to the first prepreg 12a, and solder resist 15b is applied to a second prepreg 12b.

[0073] 2.1.3. Step S3 (Baking Process)

[0074] Next, as Figure 10 As shown, a baking process is performed to remove moisture and volatile organic compounds attached to the printed circuit board 1.

[0075] 2.1.4. Step S4 (The step of electrically connecting the semiconductor chip to the printed circuit board)

[0076] Next, as Figure 11 As shown, the pad 16 formed on the prepreg 12a is electrically connected to the pad 21 formed on the periphery of the surface of the semiconductor chip 3 via the connecting component 4.

[0077] 2.1.5. Step S5 (Sealing Step)

[0078] Next, as Figure 12 As shown, the entire surface of the first surface 1a of the printed circuit board 1 is covered with sealing resin 5, so that the adhesive 2, semiconductor chip 3, and connecting components 4 are completely covered. The sealing resin 5 is cured through drying, heat curing, UV curing, and other processes. The circuit is manufactured according to the steps mentioned above. Figure 1 The semiconductor device 100 (intermediate state) of the embodiment shown in the figure.

[0079] 2.1.6. Step S6 (Step of removing a portion of the second solder resist)

[0080] Next, as Figure 13 As shown, a portion of the first region 15b1 of the solder resist 15b is removed according to the conditions used for removing a portion of the solder resist (for details, please refer to "2.2. Method for Determining the Conditions for Removing a Portion of the Second Solder Resist" which will be described later). At this time, the first region 15b1 of the second solder resist 15b is removed through a polishing step, etc. The process described above (steps S1 to S6) is then used to manufacture the product according to... Figure 2 The semiconductor device 100 (complete state) of the embodiment shown in the figure.

[0081] 2.1.7. Step S7 (Step of dividing the frame-type semiconductor device into individual components)

[0082] Finally, the frame-type semiconductor device 100 formed on each printed circuit board is divided into individual components to form each semiconductor device 100.

[0083] 2.2. Method for determining the conditions used to remove a portion of the second solder resist

[0084] Figure 14 This is a flowchart illustrating a method for determining conditions for removing a portion of the second solder resist (step S6) in a manufacturing method according to an embodiment. The method includes: providing a printed circuit board (step S'1); placing a semiconductor chip on the printed circuit board (step S'2); performing a baking process (step S'3); electrically connecting the semiconductor chip to the printed circuit board (step S'4); a sealing step (step S'5); forming multiple samples by dividing them into individual parts (step S'6); removing the solder resist from each of the multiple samples under different conditions (step S'7); measuring the warpage of the multiple samples (step S'8); and determining conditions based on the measurement results (step S'9). The method for determining the conditions for removing a portion of the solder resist differs from the method for manufacturing a semiconductor device according to an embodiment in the step of forming multiple samples by dividing the printed circuit board on which the semiconductor chip is sealed into individual parts (step S'6) and subsequent steps. Therefore, steps up to the sealing step (steps S'1 to S'5) will not be described further.

[0085] 2.2.1. Step S'6 (The step of dividing the semiconductor device into individual components to form multiple samples)

[0086] In this step, the frame-type semiconductor device manufactured up to step S'5 is divided into individual pieces by a cutting step, thereby forming multiple samples.

[0087] 2.2.2. Step S'7 (The step of removing solder resist from each of the multiple samples under different conditions)

[0088] In this step, a portion of the first region 15b1 of the solder resist 15b is removed from each of the multiple samples under different conditions (such as the location and amount of the portion to be removed). By modifying the location of the portion to be removed and the amount (thickness) of the portion to be removed in the first region 15b1, the amount of warpage of the printed circuit board 1 in each sample becomes different.

[0089] 2.2.3. Step S'8 (Step for measuring the warp of multiple samples)

[0090] In this step, after the first region 15b1 of the solder resist 15b is removed under its conditions, the amount of warpage for each sample is measured. After the resin sealing step for the semiconductor device 100 is completed, a temperature cycling test (TCT) is performed to measure the amount of warpage caused by heat.

[0091] 2.2.4. Step S'9 (Step for determining conditions based on measurement results)

[0092] In this step, a sample with the minimum warpage is specified based on the measurement results of the warpage amount of the corresponding sample. In the step of removing a portion of the second solder resist (step S6), the conditions for forming the sample (e.g., the location and amount of the portion to be removed) are referred to as "removal conditions." The "removal conditions" in the step of removing a portion of the solder resist (step S5) are determined through the steps (S'1 to S'9) mentioned above. In the method of manufacturing a semiconductor device according to the embodiment, the thickness of the second solder resist 15b in the first region 15b1 is greater than the thickness of the second solder resist 15b in the second region 15b2. Therefore, a portion of the second solder resist 15b in the first region 15b1 can be removed under a wide range of conditions. Therefore, by removing a portion of the second solder resist 15b under conditions for reducing the warpage of the printed circuit board, the warpage of the printed circuit board may be reduced. Furthermore, in the method of manufacturing a semiconductor device according to the embodiment, in the first direction, the thickness of the second solder resist 15b in the first region 15b1 is greater than the thickness of the first solder resist 15a. In related technologies, the thicknesses of the second solder resists 15a and 15b disposed on both sides of the printed circuit board 1 are substantially the same. However, in the method for manufacturing a semiconductor device according to the embodiment, the thicknesses are made different, resulting in an unbalanced thickness, and then a portion of the thicker portion is removed to balance the thickness. Therefore, the warpage of the printed circuit board is reduced. Thus, it is possible to reduce the warpage of the printed circuit board with higher accuracy. Furthermore, in the method for manufacturing a semiconductor device according to the embodiment, in the sealing step (step S5), the semiconductor chip 3 on the printed circuit board 1 is protected using a sealing resin 5, and then a step of removing a portion of the solder resist 15b is performed (step S6). Therefore, the amount of warpage of the printed circuit board 1 can be easily changed without redesigning the internal structure of the semiconductor device 100 or the printed circuit board 1. Furthermore, in the method for manufacturing a semiconductor device according to the embodiment, in the sealing step (step S5), the semiconductor chip 3 on the printed circuit board 1 is protected using a sealing resin 5, and then a step of removing a portion of the solder resist 15b is performed (step S6). Therefore, when solder resist 15b fragments are generated in step S6, the semiconductor chip 3 is protected by the sealing resin 5. Otherwise, solder resist 15b fragments generated in the removal step may adhere to the semiconductor chip 3, leading to defects in the semiconductor device 100. Additionally, in the method of manufacturing the semiconductor device according to the embodiment, the thickness of the second prepreg 12b in the third region 12b3 is less than the thickness of the second prepreg 12b in the fourth region 12b4. In this state, when the second solder resist 15b is formed on the second prepreg 12b, the thickness of the first region 15b1 of the second solder resist 15b becomes greater than the thickness of the second region 15b2. Therefore, to increase the thickness of the first region 15b1 of the second solder resist 15b, it is not necessary to add a solder resist coating process.Therefore, it is possible to easily reduce the warpage of printed circuit boards. Furthermore, in the method of manufacturing a semiconductor device according to the embodiment, while a plurality of printed circuit boards 1 are framed into a single printed circuit board, semiconductor chips disposed on respective printed circuit boards 1 are sealed with resin. Then, while the printed circuit boards 1 are still framed, a portion of the thicker portion of the second solder resist is removed. Thus, it is possible to easily perform a process that reduces the warpage of the printed circuit board.

[0093] 3. Effects

[0094] In at least one of the embodiments mentioned above regarding the semiconductor device, printed circuit board, and method of manufacturing the semiconductor device, the thickness of the second solder resist in the first region is greater than the thickness of the second solder resist in the second region. Therefore, by removing a portion of the second solder resist in the first region, warpage of the printed circuit board may be reduced.

[0095] Although specific embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of this disclosure. In fact, the novel embodiments described herein may be embodied in many other forms; furthermore, various omissions, substitutions, and changes may be made to the form of the embodiments described herein without departing from the spirit of this disclosure. The appended claims and their equivalents are intended to cover such forms or modifications that fall within the scope and spirit of this disclosure.

Claims

1. A method for manufacturing a semiconductor device, comprising: (a) A printed circuit board is provided having a first surface on which a first solder resist is formed and a second surface opposite to the first surface on which a second solder resist is formed, the second solder resist having a first region and a second region, wherein in a first direction perpendicular to the second surface, the thickness of the second solder resist in the first region is greater than the thickness of the second solder resist in the second region. (b) Placing the semiconductor chip on the first solder resist of the printed circuit board; (c) Sealing the semiconductor chip onto the printed circuit board; as well as (d) Remove a portion of the second solder resist in the first region.

2. The method for manufacturing a semiconductor device according to claim 1, The conditions for removing the portion of the second solder resist in the first region are determined by the following operations: Multiple samples are generated by performing steps (a), (b), and (c). Under different conditions, a portion of the second solder resist in the first region is removed from each of the plurality of samples. After the removal, the warpage of the printed circuit board in each of the plurality of samples was measured under the different conditions, and The conditions for performing (d) are determined based on the measured warpage of the printed circuit board of each of the plurality of samples.

3. The method for manufacturing a semiconductor device according to claim 2, The conditions specify the location of the portion of the second solder resist to be removed and the amount of the portion to be removed.

4. The method for manufacturing a semiconductor device according to claim 1, further comprising: After the portion of the second solder resist is removed, a metal bump is formed on the second surface.

5. The method for manufacturing a semiconductor device according to claim 1, The printed circuit board mentioned therein is one of a plurality of printed circuit boards that are framed together to form a single printed circuit board.

6. The method for manufacturing a semiconductor device according to claim 1, In the first direction, the thickness of the second solder resist in the first region is greater than the thickness of the first solder resist.

7. The method for manufacturing a semiconductor device according to claim 1, The printed circuit board includes A core component having a third surface and a fourth surface opposite to the third surface. The first prepreg, which is formed on the third surface, and A second prepreg, formed on the fourth surface and having a third region and a fourth region. Wherein the first surface is the surface of the first prepreg, and the second surface is the surface of the second prepreg. The third region is disposed at a position where it overlaps with the first region in the first direction, and the fourth region is disposed at a position where it overlaps with the second region in the first direction. In the first direction, the thickness of the second prepreg in the third region is less than the thickness of the second prepreg in the fourth region.

8. A semiconductor device comprising: A core component having a first surface and a second surface opposite to the first surface; A first prepreg is formed on the first surface; A second prepreg is formed on the second surface and has a third region and a fourth region; A first solder resist is formed on the first prepreg; A second solder resist is formed on the second prepreg and has a first region and a second region; A semiconductor chip disposed on the first solder resist; and Sealing resin, which seals the semiconductor chip. The third region is disposed at a position where it overlaps with the first region in a first direction perpendicular to the second surface, and the fourth region is disposed at a position where it overlaps with the second region in the first direction. The second solder resist in the first region is formed to be thicker than the second solder resist in the second region in the first direction, and a portion of the second solder resist will be removed.

9. The semiconductor device according to claim 8, In the first direction, the thickness of the second prepreg in the third region is less than the thickness of the second prepreg in the fourth region.

10. The semiconductor device according to claim 8, The core component, the first prepreg, and the second prepreg form a printed circuit board.

11. A printed circuit board comprising: A core material having a first surface and a second surface opposite to the first surface; A first prepreg is formed on the first surface; A second prepreg is formed on the second surface and has a third region and a fourth region; A first solder resist is formed on the surface of the first prepreg opposite to the first surface; as well as A second solder resist is formed on the surface of the second prepreg opposite to the second surface and has a first region and a second region. The third region is disposed at a position where it overlaps with the first region in a first direction perpendicular to the second surface, and the fourth region is disposed at a position where it overlaps with the second region in the first direction. In the first direction, the thickness of the second solder resist in the first region is greater than the thickness of the second solder resist in the second region.

12. The printed circuit board according to claim 11, The second solder resist is removable in a portion of the first region.

13. The printed circuit board according to claim 11, In a first direction perpendicular to the second surface, the thickness of the second prepreg in the third region is less than the thickness of the second prepreg in the fourth region.

14. A printed circuit board frame, comprising: Multiple printed circuit boards according to claim 11 are arranged in a matrix.

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