Memory and preparation method thereof

Abstract

The invention provides a memory and a preparation method of the memory, and relates to the technical field of semiconductors. The memory comprises a substrate which comprises a first central region and a second central region which are distributed adjacently, and an edge region located between the first central region and the second central region; the first storage array is located in the first central area; the second storage array is located in the second central area; the first selection transistor is located in the edge region, and a first source electrode / drain electrode of the first selection transistor is coupled with a first word line of the first storage array; the second selection transistor is located in the edge region, and a second source electrode / drain electrode of the second selection transistor is coupled with a second word line of the second storage array; and the contact plug is located in the edge region, and the contact plug is coupled with the first drain electrode / source electrode of the first selection transistor and the second drain electrode / source electrode of the second selection transistor. The number of contact plugs in the device can be reduced, the process difficulty of the device is reduced, and the storage density is improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a memory and a method for fabricating the memory. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a type of volatile semiconductor memory that is commonly used for storing high-density data.

[0003] DRAM typically consists of multiple memory cells, each electrically connected to the others via signal lines. These signal lines can be connected to metal interconnect structures via contact plugs to achieve electrical connection between the DRAM and control circuits. However, the connection method between signal lines and memory cells in existing dynamic random access memory remains one of the factors affecting the device's storage density.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] In view of this, a memory is provided that can improve the storage density of a device.

[0006] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0007] According to one aspect of this disclosure, a memory is provided, the memory comprising: The substrate includes a first central region and a second central region that are adjacent to each other, and an edge region located between the first central region and the second central region; The first storage array is located in the first central area; The second storage array is located in the second central area; A first selection transistor is located in the edge region, and the first source / drain of the first selection transistor is coupled to a first word line of the first memory array, the first word line extending along a first horizontal direction; A second selection transistor is located in the edge region, and the second source / drain of the second selection transistor is coupled to the second word line of the second memory array, the second word line extending along the first horizontal direction; A contact plug, located in the edge region, is coupled to the first drain / source of the first selection transistor and the second drain / source of the second selection transistor.

[0008] In one exemplary embodiment of this disclosure, the first drain / source of the first selection transistor and the second drain / source of the second selection transistor are the same drain / source.

[0009] In one exemplary embodiment of this disclosure, both the first storage array and the second storage array include: Multiple storage cells arranged at intervals along the first horizontal direction; Bit lines extend along a second horizontal direction, the bit lines are coupled to the memory cells, and the bit lines and the contact plugs are located on the same side of the substrate.

[0010] In one exemplary embodiment of this disclosure, the first selection transistor includes: A first active region is located in the substrate of the edge region; the first active region includes a first source / drain, a first channel region, and a first drain / source; A first gate structure is located on the first channel region; The second selection transistor includes: The second active region is located in the substrate of the edge region; the second active region includes the second source / drain, the second channel region, and the second drain / source; A second gate structure is located on the second channel region; The first gate structure, the second gate structure, and the bit line are located on the same side of the substrate and are parallel to each other.

[0011] In one exemplary embodiment of this disclosure, the memory cell includes a semiconductor pillar located in a region where the first word line and the second word line intersect with a plurality of bit lines; a first end of the semiconductor pillar is coupled to the bit lines; The storage unit also includes a plurality of capacitors coupled to the second end of the semiconductor pillar, wherein the first end of the semiconductor pillar is opposite to the second end.

[0012] According to another aspect of this disclosure, a method for fabricating a memory is provided, the method comprising: A substrate is provided, the substrate including a first central region and a second central region distributed adjacent to each other, and an edge region located between the first central region and the second central region; A first character line extending along a first horizontal direction to the edge of the edge area is formed in the first central area, and a second character line extending along the first horizontal direction to the edge of the edge area is formed in the second central area; A selector is formed in the edge region. The selector includes a first selector transistor and a second selector transistor arranged side by side in the edge region along the first horizontal direction. The first source / drain of the first selector transistor is coupled to the first word line, and the second source / drain of the second selector transistor is coupled to the second word line. A contact plug is formed, which is simultaneously coupled to the first drain / source of the first selection transistor and the second drain / source of the second selection transistor.

[0013] In one exemplary embodiment of this disclosure, forming the first word line and the second word line includes: Bit line isolation trenches extending along the second horizontal direction are formed in the first central region and the second central region; Word line isolation trenches extending along the first horizontal direction are formed in the first central region and the second central region, and the word line isolation trenches intersect with the bit line isolation trenches to form exposed semiconductor pillars in the first central region and the second central region; While forming the word line isolation groove, an isolation structure is formed in the edge area, the bottom of the isolation structure being flush with the bottom of the word line isolation groove, and the isolation structure dividing the edge area into multiple active areas of the selector distributed at intervals along the second horizontal direction.

[0014] In one exemplary embodiment of this disclosure, it further includes: A first word line and a second word line are formed that at least cover a portion of the outer sidewall of the semiconductor pillar. The first word line is coupled to one end of the active region, and the second word line is coupled to the other end of the active region.

[0015] In one exemplary embodiment of this disclosure, it further includes: A capacitor is formed on the substrate, and the capacitor is coupled to one end of the semiconductor pillar; The substrate is flipped and thinned to expose the other end of the semiconductor pillar; A first gate structure and a second gate structure are formed in the edge region, the first gate structure and the second gate structure respectively covering a portion of the surface of the active region; meanwhile, bit lines are formed in the first center region and the second center region, the bit lines being coupled to the other end of the semiconductor pillar.

[0016] According to another aspect of this disclosure, a memory is provided, the memory comprising: A stacked structure, the stacked structure comprising at least a first substrate and a second substrate stacked vertically; The first substrate includes a first central region and a second central region that are adjacent to each other, and a first edge region located between the first central region and the second central region; The first storage array is located in the first central area; The second storage array is located in the second central area; The first selector includes four first select transistors arranged side-by-side along the first horizontal direction in the first edge region, the first word line of the first memory array is coupled to the first select transistor adjacent to it, and the second word line of the second memory array is coupled to the first select transistor adjacent to it. A first contact plug is simultaneously coupled to four first selection transistors, and the first contact plug is configured to selectively control any one of the four first selection transistors to be turned on. The second substrate includes a third central region and a fourth central region that are distributed adjacently, and a second edge region located between the third central region and the fourth central region; The third storage array is located in the third central area; The fourth storage array is located in the fourth central area; The second selector includes four second select transistors arranged side-by-side along the first horizontal direction in the second edge region. The third word line of the third memory array is coupled to its adjacent second select transistors, and the fourth word line of the fourth memory array is coupled to its adjacent second select transistors. The second contact plug is simultaneously coupled to four second selection transistors, and the second contact plug is configured to selectively control the conduction of any one of the four second selection transistors; The first contact plug is coupled to the second selector, and the second contact plug and the first contact plug are located on both sides of the second substrate and are staggered.

[0017] In one exemplary embodiment of this disclosure, a third substrate is further included, the third substrate including control circuitry coupled to the second selector.

[0018] The memory provided in this disclosure has a first selection transistor and a second selection transistor disposed in the edge region. The first selection transistor is coupled to a first word line of a first memory array located in a first central region, and the second selection transistor is coupled to a second word line of a second memory array located in a second central region. Contact plugs are disposed in the edge region and are coupled to both the first and second selection transistors. This reduces the total number of contact plugs in the device, which increases the storage density of the device structurally. In terms of manufacturing process, since the contact plugs are located in the edge region, the fabrication difficulty of the contact plugs is reduced, the connection reliability between the word line and the contact plugs is improved, and thus the overall performance of the device is improved.

[0019] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0021] Figure 1 This is a top view schematic diagram of the structure of a memory according to an exemplary embodiment of the present disclosure.

[0022] Figure 2 In exemplary embodiments of this disclosure Figure 1 The diagram shows a cross-sectional view of the memory structure.

[0023] Figure 3 In exemplary embodiments of this disclosure Figure 1 A schematic diagram of a partial structure within the memory is shown.

[0024] Figure 4 This is a flowchart illustrating a method for fabricating a memory according to an exemplary embodiment of this disclosure.

[0025] Figure 5 This is a schematic diagram of the structure of a bitline isolation trench in an exemplary embodiment of the present disclosure.

[0026] Figure 6 In exemplary embodiments of this disclosure Figure 5 The cross-sectional view corresponding to the structure shown.

[0027] Figure 7 This is a schematic diagram of the structure of a first isolation layer in an exemplary embodiment of the present disclosure.

[0028] Figure 8In exemplary embodiments of this disclosure Figure 7 The cross-sectional view corresponding to the structure shown.

[0029] Figure 9 This is a schematic diagram of the structure of a word line isolation groove in an exemplary embodiment of the present disclosure.

[0030] Figure 10 In exemplary embodiments of this disclosure Figure 9 The cross-sectional view corresponding to the structure shown.

[0031] Figure 11 This is a schematic diagram of an isolation structure in an exemplary embodiment of the present disclosure.

[0032] Figure 12 In exemplary embodiments of this disclosure Figure 11 The cross-sectional view corresponding to the structure shown.

[0033] Figure 13 This is a schematic diagram of the structure after removing part of the first isolation layer in an exemplary embodiment of the present disclosure.

[0034] Figure 14 In exemplary embodiments of this disclosure Figure 13 The cross-sectional view corresponding to the structure shown.

[0035] Figure 15 This is a schematic diagram of the structure of a first character line and a second character line in an exemplary embodiment of this disclosure.

[0036] Figure 16 In exemplary embodiments of this disclosure Figure 15 The cross-sectional view corresponding to the structure shown.

[0037] Figure 17 This is a schematic diagram of the structure of a third isolation layer in an exemplary embodiment of this disclosure.

[0038] Figure 18 In exemplary embodiments of this disclosure Figure 17 The cross-sectional view corresponding to the structure shown.

[0039] Figure 19 This is a schematic diagram of the structure of a capacitor according to an exemplary embodiment of the present disclosure.

[0040] Figure 20 In exemplary embodiments of this disclosure Figure 19 The cross-sectional view corresponding to the structure shown.

[0041] Figure 21 This is a schematic diagram of the structure of a substrate after thinning in an exemplary embodiment of the present disclosure.

[0042] Figure 22 In exemplary embodiments of this disclosure Figure 21 The cross-sectional view corresponding to the structure shown.

[0043] Figure 23 This is a schematic diagram of the structure of an isolation trench according to an exemplary embodiment of the present disclosure.

[0044] Figure 24 In exemplary embodiments of this disclosure Figure 23 The cross-sectional view corresponding to the structure shown.

[0045] Figure 25 This is a schematic diagram of the structure of an active region in an exemplary embodiment of this disclosure.

[0046] Figure 26 In exemplary embodiments of this disclosure Figure 25 The cross-sectional view corresponding to the structure shown.

[0047] Figure 27 This is a schematic diagram of a gate structure according to an exemplary embodiment of the present disclosure.

[0048] Figure 28 In exemplary embodiments of this disclosure Figure 27 The cross-sectional view corresponding to the structure shown.

[0049] Figure 29 This is a partial structural diagram of a memory according to an exemplary embodiment of the present disclosure.

[0050] Figure 30 This is a schematic diagram illustrating the connection relationship between a first selector and a second selector within a memory in an exemplary embodiment of this disclosure.

[0051] Figure 31 This is a schematic diagram illustrating the connection relationship between a first selector and a second selector within a memory in an exemplary embodiment of this disclosure.

[0052] The reference numerals in the attached figures are explained as follows: 100. Substrate; 101. First central region; 102. Second central region; 103. Edge region; 211. First word line; 212. Second word line; 311. First source / drain; 312. First drain / source; 313. First channel region; 314. First gate structure; 321. Second source / drain; 322. Second drain / source; 323. Second channel region; 324. Second gate structure; 400. Contact plug; 500. Bit line; 501. Bit line plug; 600. Capacitor; 601. Capacitor contact; 701. Bit line isolation trench; 702. Word line isolation trench; 703. Isolation structure; 704. Isolation trench; 901. First isolation layer ; 902, Second isolation layer; 903, Third isolation layer; 904, Fourth isolation layer; 1000, Semiconductor pillar; 1030, Active region; 100A, First substrate; 100B, Second substrate; 100C, Third substrate; 300A, First selector; 300B, Second selector; 400A, First contact plug; 400B, Second contact plug; 213, Third word line; 214, Fourth word line; ARRAY1, First memory array; ARRAY2, Second memory array; ARRAY3, Third memory array; ARRAY4, Fourth memory array; CT, Control circuit; X, First horizontal direction; Y, Second horizontal direction; Z, Vertical direction. Detailed Implementation

[0053] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0054] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0055] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0056] This disclosure provides a memory, such as Figures 1 to 3 As shown, the memory includes: a substrate 100, a first memory array, a second memory array, a first selection transistor, a second selection transistor, and a contact plug 400.

[0057] The substrate 100 includes a first central region 101 and a second central region 102 distributed adjacently, and an edge region 103 located between the first central region 101 and the second central region 102; a first memory array is located in the first central region 101; a second memory array is located in the second central region 102; a first select transistor is located in the edge region 103, and the first source / drain 311 of the first select transistor is coupled to the first word line 211 of the first memory array, the first word line 211 extending along the first horizontal direction X; a second select transistor is located in the edge region 103, and the second source / drain 321 of the second select transistor is coupled to the second word line 212 of the second memory array, the second word line 212 extending along the first horizontal direction X; a contact plug 400 is located in the edge region 103, and the contact plug 400 is coupled to the first drain / source 312 of the first select transistor and the second drain / source 322 of the second select transistor.

[0058] The memory provided in this disclosure has a first selection transistor and a second selection transistor disposed in the edge region 103. The first selection transistor is coupled to a first word line 211 of a first memory array located in the first central region 101, and the second selection transistor is coupled to a second word line 212 of a second memory array located in the second central region 102. A contact plug 400 is disposed in the edge region 103 and is coupled to both the first and second selection transistors. This reduces the total number of contact plugs in the device, which increases the storage density of the device structurally. In terms of manufacturing process, since the contact plug is located in the edge region 103, the manufacturing process of the contact plug 400 is simplified, and the connection reliability between the word line and the contact plug 400 is improved, thereby improving the overall performance of the device.

[0059] It should be noted that, in the embodiments provided in this disclosure, such as Figure 1As shown, the first horizontal direction X is the extension direction of the first word line 211 and the second word line 212 in this embodiment of the present disclosure, that is, the first horizontal direction X can be a direction parallel to the surface of the substrate 100; the second horizontal direction Y is the extension direction of the bit line 500 in this embodiment of the present disclosure, the second horizontal direction Y can be a direction parallel to the surface of the substrate 100 and intersect with the first horizontal direction X. Further, in the memory, the extension direction of the bit line 500 and the extension direction of the word lines (first word line 211 and second word line 212) can be perpendicular to each other, that is, the first horizontal direction X and the second horizontal direction Y can be perpendicular to each other. In this disclosure, a vertical direction Z is also involved, the vertical direction Z can be a direction perpendicular to the surface of the substrate 100, that is, the vertical direction Z can be perpendicular to both the first horizontal direction X and the second horizontal direction Y.

[0060] It should be noted that, in order to clearly show the structure within the memory, the embodiments provided in this disclosure... Figure 2 Figure (2-A-A1) in the middle is Figure 1 The cross-sectional view along the A-A1 direction in the figure. Figure 2 Figure (2-B-B1) in the middle is Figure 1 The cross-sectional view along the B-B1 direction in the figure. Figure 2 Figure (2-C-C1) is Figure 1 The cross-sectional view along the C-C1 direction.

[0061] The various parts of the memory provided in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings: In the embodiments provided in this disclosure, the memory includes a substrate 100, a first memory array, and a second memory array.

[0062] The substrate 100 can be a semiconductor substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (GeSi) substrate, SOI (Silicon on Insulator), or GOI (Germanium on Insulator). In some embodiments, the semiconductor substrate can also be a substrate including other elemental semiconductors or compound semiconductors, such as silicon carbide (SiC), indium phosphide (InP), or gallium arsenide (GaAs). The substrate 100 can be selected according to the actual design requirements of the memory. In this embodiment, a silicon wafer is used as an example for illustration, but the material of the substrate 100 is not limited thereto.

[0063] The substrate 100 includes a first central region 101 and a second central region 102 that are adjacent to each other, and an edge region 103 located between the first central region 101 and the second central region 102.

[0064] The first central region 101 and the second central region 102 can be the main areas forming the memory, used to realize functions such as data storage and calculation. In some specific embodiments, the first central region 101 may include a first memory array composed of multiple memory cell arrays, and the second central region 102 may include a second memory array composed of multiple memory cell arrays; wherein, the memory cell can be 1T1C (1 transistor and 1 capacitor).

[0065] The first central region 101 includes a plurality of first word lines 211 spaced apart along the second horizontal direction Y. The first word lines 211 extend along the first horizontal direction X and connect to a plurality of memory cells, and the ends of the first word lines 211 are located in the edge region 103. The second central region 102 includes a plurality of second word lines 212 spaced apart along the second horizontal direction Y. The second word lines 212 extend along the first horizontal direction X and connect to a plurality of memory cells, and the ends of the second word lines 212 are located in the edge region 103.

[0066] In some embodiments, the first character line 211 and the second character line 212 may be manufactured using a synchronous process.

[0067] In some embodiments, the first word line 211 and the second word line 212 may be made of the same material. For example, the first word line 211 and the second word line 212 may be made of a conductive material, such as polycrystalline silicon, metal, or metal nitride, etc. The metal may be tungsten (W), cobalt (Co), or molybdenum (Mo); the metal nitride may be titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or titanium aluminum nitride (TiAlN), etc.

[0068] The first central region 101 and the second central region 102 each include multiple bit lines 500 distributed at intervals along the first horizontal direction X. The bit lines 500 extend along the second horizontal direction Y and are coupled to multiple memory cells. The bit lines 500 are coupled to the source of the transistors in the memory cells, so as to realize the functions of data control and transmission through the synergistic effect between the bit lines 500 and the first word line 211 and the second word line 212.

[0069] In some embodiments, bit line 500 may be made of a conductive material, such as one or more combinations of polycrystalline silicon, metal or metal nitride, wherein the metal may be tungsten (W), cobalt (Co) or molybdenum (Mo); and the metal nitride may be titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN) or titanium aluminum nitride (TiAlN).

[0070] In some embodiments, such as Figure 1As shown, the first central region 101 and the second central region 102 may also include bit line plugs 501, which are connected to bit lines 500. Bit line plugs 501 can serve as a bridge between bit lines 500 and the metal interconnect structure to realize the electrical connection of the device.

[0071] In some embodiments, such as Figure 2 As shown, combined with Figure 1 Each memory cell includes a semiconductor pillar 1000 located in the region where the first word line 211 and the second word line 212 intersect with multiple bit lines 500. The first end of the semiconductor pillar 1000 is coupled to the bit line 500, and the second end of the semiconductor pillar 1000 is coupled to the capacitor 600. The first end and the second end of the semiconductor pillar 1000 are opposite to each other.

[0072] It should be noted that the semiconductor pillar 1000 in the above embodiments can refer to an active pillar, that is, an active layer of a transistor in the first central region 101 and the second central region 102 is formed by doping the substrate 100. The active pillar can include the source, channel and drain of the transistor. After the active pillar forms an electrical connection with other devices through the source and drain, it can realize functions such as data reading and writing through control signals.

[0073] The second end of the semiconductor pillar 1000 is coupled to the capacitor 600. The coupling between the capacitor 600 and the transistor can form a 1T1C memory cell to realize data storage.

[0074] In some embodiments, such as Figure 2 As shown, combined with Figure 1 The capacitor 600 may be a cylindrical capacitor, and may include a first electrode, a second electrode, and a dielectric layer located between the first electrode and the second electrode. The first electrodes are independent of each other. The dielectric layer may be integrally formed and continuously cover the surfaces of multiple independent first electrodes. The second electrode may be integrally formed and continuously cover the surface of the dielectric layer. The second electrode may be connected to a capacitor contact plug, through which the capacitor 600 is led out.

[0075] Both the first and second electrodes can comprise metals, noble metals, metal nitrides, conductive metal oxides, conductive noble metal oxides, metal carbides, metal silicides, or combinations thereof. For example, they can comprise one or more combinations of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, and tungsten nitride. The dielectric layer can comprise one or more of silicon oxide, silicon nitride, high dielectric constant materials, ferroelectric materials, and antiferroelectric materials. The specific materials and fabrication process of capacitor 600 can be selected and adjusted according to the actual design requirements of the device, and will not be detailed here. It should be understood that the capacitor 600 provided in this disclosure can be fabricated using capacitor fabrication methods available in the art.

[0076] In some embodiments, a capacitor 600 may be formed in the first central region 101, and further, a capacitor 600 may be formed in the edge region 103 to increase storage capacity.

[0077] In some embodiments, such as Figure 2 and Figure 3 As shown, combined with Figure 1 The capacitor 600 and the semiconductor pillar 1000 may also include a capacitor contact 601, which can be used to connect the capacitor 600 and the semiconductor pillar 1000 to reduce the contact resistance between the capacitor 600 and the semiconductor pillar 1000.

[0078] In the embodiments provided in this disclosure, the memory includes a first selection transistor and a second selection transistor located in the edge region 103, the first selection transistor being coupled to a first word line 211 and the second selection transistor being coupled to a second word line 212.

[0079] The first selection transistor includes a first active region located in the edge region 103 and a first gate structure 314. The first active region includes a first channel region 313, a first source / drain 311, and a first drain / source 312. The first gate structure 314 is located on the first channel region 313. The first word line 211 is coupled to the first source / drain 311 of the first selection transistor, and the conduction state of the first word line 211 is controlled by the first selection transistor.

[0080] In some embodiments, the first gate structure 314 is located within the edge region 103 and extends along the second horizontal direction Y. The first gate structure 314 can control the opening and closing of the first selection transistor, thereby controlling the conduction state of the first word line 211.

[0081] The second selection transistor includes a second active region and a second gate structure 324 located in the edge region 103. The second active region includes a second channel region 323, a second source / drain 321, and a second drain / source 322. The second gate structure 324 is located on the second channel region 323. The second word line 212 is coupled to the second source / drain 321 of the second selection transistor, and the conduction state of the second word line 212 is controlled by the second selection transistor.

[0082] In some embodiments, the second gate structure 324 is located within the edge region 103 and extends along the second horizontal direction Y. The second gate structure 324 can control the turning on and off of the second selection transistor, thereby controlling the conduction state of the second word line 212.

[0083] In some embodiments, the first gate structure 314, the second gate structure 324 and the bit line 500 are located on the same side of the substrate 100 and are parallel to each other. That is, the bit line 500 can be fabricated in the same process as the first gate structure 314 and the second gate structure 324, which can reduce the number of photomasks and simplify the process flow.

[0084] In the embodiments provided in this disclosure, the memory includes a contact plug 400 located in the edge region 103. The first drain / source 312 of the first selection transistor and the second drain / source 322 of the second selection transistor are simultaneously coupled to the contact plug 400. By simultaneously coupling the first selection transistor and the second selection transistor to the same contact plug 400, the conduction state of the first selection transistor and the second selection transistor can be controlled by the contact plug 400, thereby controlling the conduction of the first word line 211 and the second word line 212. In the first central region 101 and the second central region 102 of the memory, it is not necessary to set a separate word line contact plug for each first word line 211 and each second word line 212. Under the premise of controlling the conduction state of the word lines, the total number of word line contact plugs in the memory can be reduced, thereby increasing the storage density. In addition, since the contact plug 400 is located in the edge region 103, the manufacturing difficulty of the contact plug 400 can be reduced, and the connection reliability between the word line and the contact plug 400 can be improved.

[0085] In some embodiments, the first drain / source 312 of the first selection transistor and the first drain / source 312 of the second selection transistor are the same drain / source. By sharing the same drain / source, the space occupied by the selection transistor can be further saved, the area occupied by the edge region 103 can be reduced, thereby providing more fabrication space for the memory cells in the central region and improving the storage density.

[0086] In some embodiments, the contact plug 400 and the bit line 500 are located on the same side of the substrate 100. The contact plug 400 can be obtained by exposing the same photomask as the bit line plug 501 in the first central region 101 and the second central region 102 to reduce the number of photomasks.

[0087] It should be noted that the contact plug 400, bit line plug 501, and capacitor contact plug provided in this embodiment can be made of conductive materials such as metal or metal nitride. For example, the metal can be tungsten (W), cobalt (Co), or molybdenum (Mo); the metal nitride can be titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or titanium aluminum nitride (TiAlN).

[0088] This disclosure provides a method for fabricating a memory, used to fabricate the memory provided in any of the above embodiments, such as... Figure 4As shown, the preparation method includes steps S10 to S40.

[0089] Wherein, step S10: providing a substrate, the substrate including a first central region and a second central region distributed adjacently, and an edge region located between the first central region and the second central region; Step S20: A first character line extending along the first horizontal direction to the edge of the edge area is formed in the first central area, and a second character line extending along the first horizontal direction to the edge of the edge area is formed in the second central area. Step S30: A selector is formed in the edge region. The selector includes a first selector transistor and a second selector transistor arranged side by side in the edge region along the first horizontal direction. The first source / drain of the first selector transistor is coupled to the first word line, and the second source / drain of the second selector transistor is coupled to the second word line. Step S40: Form a contact plug, which is simultaneously coupled to the first drain / source of the first select transistor and the second drain / source of the second select transistor.

[0090] The memory fabrication method disclosed herein involves forming a first selection transistor coupled to a first word line and a second selection transistor coupled to a second word line in an edge region, and then forming contact plugs simultaneously coupled to the first and second selection transistors in the edge region. The conduction states of the first and second selection transistors can be controlled by the contact plugs, thereby achieving the purpose of controlling the first and second word lines. This fabrication method can reduce the total number of contact plugs in the device, and fabricating the contact plugs in the edge region can reduce the process difficulty of the contact plugs, ensure the connection reliability of the contact plugs, and improve the electrical performance of the device.

[0091] It should be noted that the information provided in this disclosure... Figures 5 to 28 This is a schematic diagram of the structure corresponding to each step in a method for fabricating a memory according to an exemplary embodiment of the present disclosure, wherein, Figure 5 , Figure 7 , Figure 9 , Figure 11 , Figure 13 , Figure 15 , Figure 17 , Figure 19 , Figure 21 , Figure 23 , Figure 25 as well as Figure 27 This is a top view schematic diagram of the structure corresponding to each step of the memory fabrication method. Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 , Figure 16 , Figure 18 , Figure 20 , Figure 22 , Figure 24 , Figure 26 as well as Figure 28 These are structural cross-sectional views corresponding to each step of the memory fabrication method, where... Figure 6 The internal figures are Figure 5 Cross-sectional views of the corresponding structure from different directions. Figure 8 The internal figures are Figure 7 The corresponding cross-sectional views of the structure in different directions, and so on, combined with Figures 5 to 28 The steps of the method for fabricating the memory provided in the embodiments of this disclosure will be described in detail with structural diagrams from various directions.

[0092] In the embodiments provided in this disclosure, such as Figure 5 and Figure 6 As shown, the substrate 100 includes a first central region 101 and a second central region 102 distributed adjacent to each other, and an edge region 103 located between the first central region 101 and the second central region 102. Since the first central region 101 and the second central region 102 are the main regions forming the storage region, the area of ​​the first central region 101 and the second central region 102 can be larger than or much larger than the area of ​​the edge region 103. In addition, in order to improve the structural symmetry of the storage region, the area of ​​the first central region 101 and the area of ​​the second central region 102 can be equal to or approximately equal to each other, but this is not a limitation. The division of the first central region 101, the second central region 102 and the edge region 103 can be adjusted according to the structural design requirements of the device to meet the process requirements of device fabrication.

[0093] The process of forming a first word line 211 in a first central region 101 and a second word line 212 in a second central region 102 includes: S101, forming a bit line isolation trench 701 extending along a second horizontal direction Y in the first central region 101 and the second central region 102; S102, forming a word line isolation trench 702 extending along a first horizontal direction X in the first central region 101 and the second central region 102, the word line isolation trench 702 intersecting the bit line isolation trench 701 to form exposed semiconductor pillars 1000 in the first central region 101 and the second central region 102; S103, forming an isolation structure 703 in the edge region 103 while forming the word line isolation trench 702, the bottom of the isolation structure 703 being flush with the bottom of the word line isolation trench 702, the isolation structure 703 dividing the edge region 103 into multiple active regions 1030 of selectors spaced apart along the second horizontal direction Y.

[0094] Among them, such as Figure 7 and Figure 8As shown, in S101, forming the bit line isolation trench 701 may include: simultaneously patterning the first central region 101 and the second central region 102 to form a bit line isolation trench 701 extending along the second horizontal direction Y in the first central region 101 and the second central region 102; filling the bit line isolation trench 701 with a first isolation layer 901 to provide a structural basis for the subsequent fabrication of the bit line 500.

[0095] The first isolation layer 901 can be made of insulating materials such as silicon oxide or silicon nitride. Furthermore, in order to facilitate the large-area deposition and etching of the first isolation layer 901, the first isolation layer 901 can be made of silicon oxide.

[0096] The semiconductor pillars 1000 located in the first central region 101 and the second central region 102 can be subsequently formed into active pillars through a doping process to form transistors. The active pillars can include a source, a channel, and a drain connected sequentially along the vertical direction Z. After the active pillars are electrically connected to other devices through the source and drain, data can be read and written by control signals.

[0097] In some embodiments, the semiconductor pillar 1000 can be doped with group III or group V elements to form the source and drain. For example, group III elements can be boron (B), gallium (Ga), etc., and group V elements can be phosphorus (P), arsenic (As), etc. Different elements can be selected to dope the semiconductor pillar 1000 according to the specific type of transistor to be formed, so as to meet the structural design requirements of the device.

[0098] The doping of the semiconductor pillar 1000 can be performed before or after the fabrication of the first word line 211 and the second word line 212. It should be noted that the order of doping of the semiconductor pillar 1000 and the fabrication of the first word line 211 and the second word line 212 can be determined according to the actual requirements of the device structure, and this disclosure does not impose specific limitations.

[0099] Among them, such as Figure 9 and Figure 10 As shown, in S102, forming the word line isolation trench 702 may include: simultaneously patterning the first central region 101, the second central region 102, and the edge region 103 to form a word line isolation trench 702 extending along the first horizontal direction X in the first central region 101 and the second central region 102; filling the word line isolation trench 702 with a second isolation layer 902 to provide a structural basis for the subsequent fabrication of the first word line 211 and the second word line 212.

[0100] The second isolation layer 902 can be made of insulating materials such as silicon oxide and silicon nitride. Furthermore, in order to distinguish the first isolation layer 901 and the second isolation layer 902 in subsequent processes, the first isolation layer 901 and the second isolation layer 902 can be made of different materials. For example, the first isolation layer 901 can be made of silicon oxide and the second isolation layer 902 can be made of silicon nitride.

[0101] Among them, such as Figure 11 and Figure 12 As shown, in S103, while forming the word line isolation trench 702, an isolation structure 703 is formed in the edge region 103. That is, the isolation structure 703 and the word line isolation trench 702 can be formed using the same process step. When forming the word line isolation trench 702, the word line isolation trench 702 can be extended to the edge region 103. The word line isolation trench 702 and the isolation structure 703 can be prepared simultaneously through a one-step etching process.

[0102] It should be noted that the removal or etching method in the embodiments of this disclosure may be one or a combination of wet etching, dry etching, etc. The etching method may be adaptively selected and adjusted according to the specific material and other parameters of the film layer, which will not be repeated in the following embodiments.

[0103] In some embodiments, the bottom of the isolation structure 703 is flush with the bottom of the word line isolation trench 702. The isolation structure 703 divides the edge region 103 into multiple active regions 1030 of selectors that are spaced apart along the second horizontal direction Y. The active regions 1030 of the selectors can provide a structural basis for the subsequent formation of the first selector transistor 310 and the second selector transistor 320. Furthermore, the isolation structure 703 can electrically isolate the active regions 1030 of adjacent selectors, avoiding short circuits between adjacent selectors and ensuring the reliability of the selectors.

[0104] Following S103, the method further includes: Figure 13 and Figure 14 As shown, the first isolation layer 901 between the semiconductor pillars 1000 is etched away to expose part of the outer wall of the semiconductor pillars 1000. Simultaneously, the first isolation layer 901 between the semiconductor pillars 1000 located at the edge of the first central region 101 and one end of the selector active region 1030 is removed, and the first isolation layer 901 between the semiconductor pillars 1000 located at the edge of the second central region 102 and the other end of the selector active region 1030 is removed to expose both ends of the active region 1030; as shown... Figure 15 and Figure 16As shown, a first word line 211 and a second word line 212 are formed to at least cover a portion of the outer sidewall of the semiconductor pillar 1000. The first word line 211 is coupled to one end of the active region 1030, and the second word line 212 is coupled to the other end of the active region 1030.

[0105] The first character line 211 and the second character line 212 can be formed in the same process step to simplify the manufacturing process. Of course, the first character line 211 and the second character line 212 can also be manufactured separately according to actual process requirements. For example, to meet the special structural requirements of some devices, when the first character line 211 and the second character line 212 are made of different materials, the first character line 211 and the second character line 212 can be manufactured separately in different processes.

[0106] like Figure 17 and Figure 18 As shown, after forming the first word line 211 and the second word line 212, the method further includes filling the remaining gaps between the semiconductor pillars 1000 with a third isolation layer 903, the surface of which may be flush with the exposed surface of the semiconductor pillars 1000.

[0107] like Figure 19 and Figure 20 As shown, after forming the third isolation layer 903, the method further includes forming a capacitor 600 on the substrate 100, the capacitor 600 being coupled to one exposed end of the semiconductor pillar 1000.

[0108] In this process, a capacitive contact 601 can be formed between the capacitor 600 and the semiconductor pillar 1000 to reduce the contact resistance between the capacitor 600 and the semiconductor pillar 1000.

[0109] In some embodiments, capacitor 600 may be a cylindrical capacitor. The capacitor 600 provided in this disclosure may be manufactured according to capacitor manufacturing methods available in the art, which will not be described in detail in this disclosure.

[0110] In the embodiments provided in this disclosure, the materials with insulating and insulating properties, such as the first isolation layer 901, the second isolation layer 902, and the third isolation layer 903, can be formed by one or more combinations of methods such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), thermal oxidation, and sol-gel. The formation process can be selected according to the specific material of the film layer, and this disclosure does not make specific limitations.

[0111] After forming capacitor 600, the method further includes: Figure 21 and Figure 22 As shown, the substrate 100 is flipped and thinned to expose the other end of the semiconductor pillar 1000; as Figure 25 and Figure 26 As shown, a first gate structure 314 and a second gate structure 324 are formed in the edge region 103, and the first gate structure 314 and the second gate structure 324 respectively cover a portion of the surface of the active region 1030; at the same time, bit lines 500 are formed in the first central region 101 and the second central region 102, and the bit lines 500 are coupled to the other end of the semiconductor pillar 1000.

[0112] Before the first gate structure 314 and the second gate structure 324 are formed in the edge region 103, the method further includes: Figure 23 and Figure 24 As shown, a portion of the substrate 100 located in the edge region 103 after being flipped is removed to form an isolation trench 704, which exposes a portion of the outer wall of the semiconductor pillar material; as Figure 25 and Figure 26 As shown, a portion of the semiconductor pillar material is removed from the isolation trench 704, causing the remaining semiconductor pillar material to break in the second horizontal direction Y, forming multiple active regions 1030. Specifically, semiconductor pillar material along the first horizontal direction X can be removed along the isolation trench 704, exposing the first isolation layer 901. Then, a fourth isolation layer 904 is formed between the isolation trenches 704 to electrically isolate the multiple active regions 1030 in the second horizontal direction. Figure 27 and Figure 28 As shown, gate material is filled in the isolation trench 704 to form the gate structure of the transistor in the selector. Specifically, in the first horizontal direction X, the same active region 1030 has at least two isolation trenches 704, one of which is used to subsequently form the first gate structure 314 of the first select transistor 310, and the other isolation trench 704 is used to subsequently form the second gate structure 324 of the second select transistor 320.

[0113] After forming the first gate structure and the second gate structure, the method further includes: doping the active region 1030 of the selector to form the first source / drain 311 and the first drain / source 312 of the first select transistor, and the second source / drain 321 and the second drain / source 322 of the second select transistor. Of course, the order of doping and the formation of the first gate structure 314 and the second gate structure 324 can be adjusted according to the actual design requirements of the process.

[0114] In some embodiments, refer again Figure 4The first selection transistor and the second selection transistor share the same drain / source, that is, the first drain / source 312 of the first selection transistor and the second drain / source 322 of the second selection transistor are the same drain / source. When doping the active region 1030 of the selector, doping can be performed at the middle position of the active region 1030 to form the first selection transistor and the second selection transistor that share the same drain / source.

[0115] In the embodiments provided in this disclosure, reference is made again. Figure 1 and Figure 2 After forming the first selection transistor and the second selection transistor in the edge region 103, the method includes forming a contact plug 400 that simultaneously couples the first drain / source 312 of the first selection transistor and the second drain / source 322 of the second selection transistor. The contact plug 400 allows the first selection transistor and the second selection transistor to be simultaneously brought out. By controlling the conduction states of the first selection transistor and the second selection transistor, control of the first word line 211 and the second word line 212 is achieved, reducing the total number of contact plugs 400 in the memory and increasing storage density. Furthermore, the contact plug 400 is fabricated in the edge region 103, reducing the manufacturing complexity of the contact plug 400.

[0116] In some embodiments, when a contact plug 400 is formed in the edge region 103, the method may further include forming a bit line plug 501 in the first central region 101 and the second central region 102. The bit line 500 can be led out through the bit line plug 501 to realize the connection between the bit line 500 and the metal interconnect structure.

[0117] It should be noted that although the steps of the memory fabrication method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0118] This disclosure provides a method for controlling a memory, used to control the memory provided in any of the above embodiments, wherein the memory structure is as follows: Figure 1 and Figure 2 As shown.

[0119] In some embodiments, the control method includes: when performing read / write operations on the first memory array, turning on the first gate structure 314 and turning off the second gate structure 324 to turn on the first selection transistor, thereby transmitting a signal from the first selection transistor to the first word line 211, and controlling the reading and writing of data in the first memory array through the first word line 211.

[0120] In some embodiments, the control method includes: when performing read / write operations on the second memory array, turning on the second gate structure 324 and turning off the first gate structure 314 to turn on the second selection transistor, thereby allowing a signal to be transmitted from the second selection transistor to the second word line 212, and controlling the reading and writing of data in the second memory array through the second word line 212.

[0121] This disclosure also provides a memory, such as... Figure 29 As shown, combined with Figures 1 to 3 , Figure 30 and Figure 31 The memory includes: a first substrate 100A, a first selector 300A, a first contact plug 400A, a second substrate 100B, a second selector 300B, and a second contact plug 400B.

[0122] The stacked structure includes at least a first substrate 100A and a second substrate 100B stacked vertically.

[0123] The first substrate 100A includes a first central region and a second central region distributed adjacent to each other, and a first edge region located between the first central region and the second central region; the first memory array ARRAY1 is located in the first central region 101; the second memory array ARRAY2 is located in the second central region; the first selector 300A includes four first select transistors distributed side by side along the first horizontal direction X in the first edge region, the first word line 211 of the first memory array ARRAY1 is coupled to its adjacent first select transistor, and the second word line 212 of the second memory array ARRAY2 is coupled to its adjacent first select transistor; the first contact plug 400A is coupled to the four first select transistors simultaneously, and the first contact plug 400A is configured to selectively control any one of the four first select transistors to be turned on.

[0124] The second substrate 100B includes a third central region and a fourth central region distributed adjacent to each other, and a second edge region located between the third central region and the fourth central region; the third memory array ARRAY3 is located in the third central region; the fourth memory array ARRAY4 is located in the fourth central region; the second selector 300B includes four second select transistors distributed side by side along the first horizontal direction X in the second edge region, the third word line 213 of the third memory array ARRAY3 is coupled to its adjacent second select transistor, and the fourth word line 214 of the fourth memory array ARRAY4 is coupled to its adjacent second select transistor; the second contact plug 400B is simultaneously coupled to the four second select transistors, and the second contact plug 400B is configured to selectively control any one of the four second select transistors to be turned on.

[0125] The first contact plug 400A is coupled to the second selector 300B, and the second contact plug 400B and the first contact plug 400A are located on both sides of the second substrate 100B and are staggered.

[0126] The memory disclosed herein includes a first substrate 100A and a second substrate 100B stacked vertically. By controlling the conduction states of four first selection transistors in the first selector 300A and four second selection transistors in the second selector 300B, data reading and writing to different memory arrays can be controlled, and different memory arrays can be flexibly selected. At the same time, since the device has a first contact plug 400A in the first edge region and a second contact plug 400B in the second edge region, it avoids fabricating contact plugs in the memory array, reduces the total number of contact plugs in the device, and can improve the storage density of the device. In addition, fabricating contact plugs in the edge region can reduce the process difficulty of contact plugs.

[0127] It should be noted that the device structure in the first substrate 100A and the device structure in the second substrate 100B can be fabricated separately and then vertically stacked and connected. The fabrication method of the device in each substrate can refer to the fabrication process shown in the embodiment of the memory fabrication method. That is, the memory structure provided in the above embodiment can be formed in the first substrate 100A and the second substrate 100B respectively.

[0128] In some embodiments, the first contact plug 400A may be positioned in the middle of the four first select transistors to ensure structural symmetry within the first substrate 100A.

[0129] In some embodiments, the second contact plug 400B may be positioned in the middle of the four second selection transistors to ensure structural symmetry within the first substrate 100A.

[0130] In some embodiments, the first contact plug 400A is also coupled to the second selector 300B to control the first selector 300A via the second selector 300B. To ensure that the second selector 300B controls the data read and write operations of the third memory array ARRAY3 and the fourth memory array ARRAY4, the second contact plug 400B and the first contact plug 400A are located on opposite sides of the second substrate 100B and are staggered.

[0131] In some specific embodiments, the connection position between the first contact plug 400A and the second selector 300B can be close to the two second select transistors of the third memory array ARRAY3.

[0132] In some specific embodiments, the connection position of the first contact plug 400A and the second selector 300B can be close to the two second select transistors of the fourth memory array ARRAY4.

[0133] In some embodiments, the memory further includes a third substrate 100C, which includes a control circuit CT coupled to a second selector 300B.

[0134] The control circuit CT located on the third substrate 100C includes at least a word line driving circuit, which drives the second selection word lines W21, W22, W23, and W24 in the second selector 300B to control the conduction state of the first selection transistor in the first selector 300A. In addition, the control circuit CT may also include an SA (Sense Amplifier), a read / write control circuit CT, a power management circuit, etc., which are not listed here.

[0135] The embodiments provided in this disclosure fabricate the second selector 300B and the control circuit CT on different substrates, and then couple the control circuit CT to the second selector 300B. This avoids damage to the control circuit CT caused by the high-temperature process of the capacitors in the storage array, and improves the overall performance of the device.

[0136] This disclosure provides a method for controlling a memory, used to control the memory provided in any of the above embodiments, the structure of which is as follows: Figure 30 and Figure 31 As shown, the first edge region includes four first select word lines, which are connected to the first select transistors respectively. The first select word lines are W11, W12, W13, and W14. The second edge region includes four second select word lines, which are connected to the second select transistors respectively. The second select word lines are W21, W22, W23, and W24.

[0137] In some embodiments, the control method includes: when performing read / write operations on the third memory array ARRAY3, simultaneously turning on the second select word lines W21 and W22, turning off the second select word lines W23 and W24, and turning off the first select word lines W11, W12, W13, and W14, so that two second select transistors close to the third memory array ARRAY3 are turned on, thereby allowing signals to be transmitted from the two second select transistors to the third word line 213, and controlling the read / write of data in the third memory array ARRAY3 through the third word line 213.

[0138] In some embodiments, the control method includes: when performing read / write operations on the fourth memory array ARRAY4, simultaneously turning on the second select word lines W23 and W24, turning off the second select word lines W21 and W22, and turning off the first select word lines W11, W12, W13, and W14, so that two second select transistors close to the fourth memory array ARRAY4 are turned on, thereby allowing signals to be transmitted from the two second select transistors to the fourth word line 214, and controlling the read / write of data in the fourth memory array ARRAY4 through the fourth word line 214.

[0139] In some embodiments, when the first contact plug 400A is located between the second select word lines W21 and W22, the control method includes: when performing read / write operations on the first memory array ARRAY1, opening the second select word line W22 and simultaneously closing the second select word lines W21, W23, and W24, opening the first select word lines W11 and W12 and closing the first select word lines W13 and W14, so as to turn on the first select transistor, thereby allowing a signal to be transmitted from the first select transistor to the first word line 211, and controlling the reading and writing of data in the first memory array ARRAY1 through the first word line 211.

[0140] In some embodiments, when the first contact plug 400A is located between the second select word lines W21 and W22, the control method includes: when performing read / write operations on the second memory array ARRAY2, opening the second select word line W22 while closing the second select word lines W21, W23, and W24, opening the first select word lines W13 and W14, and closing the first select word lines W11 and W12, so as to turn on the first select transistor 310, thereby allowing a signal to be transmitted from the first select transistor to the second word line 212, and controlling the reading and writing of data in the second memory array ARRAY2 through the second word line 212.

[0141] In some embodiments, when the first contact plug 400A is located between the second select word lines W23 and W24, the control method includes: when performing read / write operations on the first memory array ARRAY1, opening the second select word line W23 and simultaneously closing the second select word lines W21, W22, and W24, opening the first select word lines W11 and W12 and closing the first select word lines W13 and W14, so as to turn on the first select transistor, thereby allowing a signal to be transmitted from the first select transistor to the first word line 211, and controlling the reading and writing of data in the first memory array ARRAY1 through the first word line 211.

[0142] In some embodiments, when the first contact plug 400A is located between the second select word lines W23 and W24, the control method includes: when performing read / write operations on the second memory array ARRAY2, turning on the second select word line W23 and simultaneously turning off the second select word lines W21, W22 and W24, turning on the first select word lines W13 and W14 and turning off the first select word lines W11 and W12, so as to turn on the first select transistor, thereby allowing a signal to be transmitted from the first select transistor to the second word line 212, and controlling the reading and writing of data in the second memory array ARRAY2 through the second word line 212.

[0143] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A memory, characterized in that, include: The substrate includes a first central region and a second central region that are adjacent to each other, and an edge region located between the first central region and the second central region; The first storage array is located in the first central area; The second storage array is located in the second central area; A first selection transistor is located in the edge region, and the first source / drain of the first selection transistor is coupled to a first word line of the first memory array, the first word line extending along a first horizontal direction; A second selection transistor is located in the edge region, and the second source / drain of the second selection transistor is coupled to the second word line of the second memory array, the second word line extending along the first horizontal direction; A contact plug, located in the edge region, is coupled to the first drain / source of the first selection transistor and the second drain / source of the second selection transistor.

2. The memory according to claim 1, characterized in that, The first drain / source of the first selection transistor and the second drain / source of the second selection transistor are the same drain / source.

3. The memory according to claim 1 or 2, characterized in that, Both the first storage array and the second storage array include: Multiple storage cells arranged at intervals along the first horizontal direction; Bit lines extend along a second horizontal direction, the bit lines are coupled to the memory cells, and the bit lines and the contact plugs are located on the same side of the substrate.

4. The memory according to claim 3, characterized in that, The first selection transistor includes: A first active region is located in the substrate of the edge region; the first active region includes a first source / drain, a first channel region, and a first drain / source; A first gate structure is located on the first channel region; The second selection transistor includes: The second active region is located in the substrate of the edge region; the second active region includes the second source / drain, the second channel region, and the second drain / source; A second gate structure is located on the second channel region; The first gate structure, the second gate structure, and the bit line are located on the same side of the substrate and are parallel to each other.

5. The memory according to claim 3, characterized in that, The memory cell includes a semiconductor pillar located in the region where the first word line and the second word line intersect with the plurality of bit lines; a first end of the semiconductor pillar is coupled to the bit line. The storage unit also includes a plurality of capacitors coupled to the second end of the semiconductor pillar, wherein the first end of the semiconductor pillar is opposite to the second end.

6. A method for fabricating a memory, characterized in that, include: A substrate is provided, the substrate including a first central region and a second central region distributed adjacent to each other, and an edge region located between the first central region and the second central region; A first character line extending along a first horizontal direction to the edge of the edge area is formed in the first central area, and a second character line extending along the first horizontal direction to the edge of the edge area is formed in the second central area; A selector is formed in the edge region, the selector including a first selector transistor and a second selector transistor arranged side by side in the edge region along the first horizontal direction; The first source / drain of the first selection transistor is coupled to the first word line, and the second source / drain of the second selection transistor is coupled to the second word line; A contact plug is formed, which is simultaneously coupled to the first drain / source of the first selection transistor and the second drain / source of the second selection transistor.

7. The method for fabricating a memory according to claim 6, characterized in that, Forming the first character line and the second character line includes: Bit line isolation trenches extending along the second horizontal direction are formed in the first central region and the second central region; Word line isolation trenches extending along the first horizontal direction are formed in the first central region and the second central region, and the word line isolation trenches intersect with the bit line isolation trenches to form exposed semiconductor pillars in the first central region and the second central region; While forming the word line isolation groove, an isolation structure is formed in the edge area, the bottom of the isolation structure being flush with the bottom of the word line isolation groove, the isolation structure dividing the edge area into a plurality of active areas of the selector spaced apart along the second horizontal direction.

8. The method for fabricating a memory according to claim 7, characterized in that, Also includes: A first word line and a second word line are formed that at least cover a portion of the outer sidewall of the semiconductor pillar. The first word line is coupled to one end of the active region, and the second word line is coupled to the other end of the active region.

9. The method for fabricating a memory according to claim 8, characterized in that, Also includes: A capacitor is formed on the substrate, and the capacitor is coupled to one end of the semiconductor pillar; The substrate is flipped and thinned to expose the other end of the semiconductor pillar; A first gate structure and a second gate structure are formed in the edge region, the first gate structure and the second gate structure respectively covering a portion of the surface of the active region; meanwhile, bit lines are formed in the first center region and the second center region, the bit lines being coupled to the other end of the semiconductor pillar.

10. A memory, characterized in that, include: A stacked structure, the stacked structure comprising at least a first substrate and a second substrate stacked vertically; The first substrate includes a first central region and a second central region that are adjacent to each other, and a first edge region located between the first central region and the second central region; The first storage array is located in the first central area; The second storage array is located in the second central area; The first selector includes four first select transistors arranged side-by-side along the first horizontal direction in the first edge region, the first word line of the first memory array is coupled to the first select transistor adjacent to it, and the second word line of the second memory array is coupled to the first select transistor adjacent to it. A first contact plug is simultaneously coupled to four first selection transistors, and the first contact plug is configured to selectively control any one of the four first selection transistors to be turned on. The second substrate includes a third central region and a fourth central region that are distributed adjacently, and a second edge region located between the third central region and the fourth central region; The third storage array is located in the third central area; The fourth storage array is located in the fourth central area; The second selector includes four second select transistors arranged side-by-side along the first horizontal direction in the second edge region. The third word line of the third memory array is coupled to its adjacent second select transistors, and the fourth word line of the fourth memory array is coupled to its adjacent second select transistors. The second contact plug is simultaneously coupled to four second selection transistors, and the second contact plug is configured to selectively control the conduction of any one of the four second selection transistors; The first contact plug is coupled to the second selector, and the second contact plug and the first contact plug are located on both sides of the second substrate and are staggered.

11. The memory according to claim 10, characterized in that, It also includes a third substrate, which includes control circuitry coupled to the second selector.

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