Memory device and manufacturing method of the memory device

Abstract

The invention relates to a memory device and a manufacturing method of the memory device. A method of manufacturing a memory device includes forming a first stack including first interlayer insulating layers and first sacrificial layers alternately stacked, the first sacrificial layers having a first etch rate; forming a second stack over the first stack, the second stack including alternately stacked second interlayer insulating layers and second sacrificial layers, the second sacrificial layers having a second etch rate lower than the first etch rate; forming a first sacrificial pillar penetrating through the second stack; forming a preliminary opening by removing the first sacrificial pillar; forming first openings penetrating the first number of first sacrificial layers, respectively, by etching a portion of the first stack via the preliminary openings; forming second openings penetrating the first number of second sacrificial layers, respectively, by etching a portion of the second stack spaced apart from the preliminary openings; and forming contacts in the first opening and the second opening.

Description

Technical Field

[0001] This disclosure relates to a memory device and a method of manufacturing the memory device, and more specifically, to a memory device comprising a memory block having a three-dimensional structure and a method of manufacturing the memory device having a three-dimensional structure. Background Technology

[0002] Memory devices can include non-volatile memory devices that retain stored data even without power. Based on the arrangement of memory cells within the memory device, non-volatile memory devices can be classified as two-dimensional or three-dimensional memory devices. Memory cells of a two-dimensional non-volatile memory device can be arranged in a single layer on a substrate. Memory cells of a three-dimensional non-volatile memory device can be stacked in the vertical direction of the substrate. Because the integration density of three-dimensional non-volatile memory devices is greater than that of two-dimensional non-volatile memory devices, electronic devices incorporating three-dimensional non-volatile memory devices are increasingly common. Summary of the Invention

[0003] According to embodiments of the present disclosure, a method of manufacturing a memory device may include the following steps: forming a lower stack comprising a first interlayer insulating layer and a first sacrificial layer alternately stacked in a first direction; forming an upper stack above the lower stack in a first direction, wherein the upper stack comprises a second interlayer insulating layer and a second sacrificial layer alternately stacked in the first direction, the second sacrificial layer having an etch rate lower than that of the first sacrificial layer; forming a preliminary opening penetrating the upper stack and exposing an upper surface of the lower stack; and forming a first opening extending from one of the first sacrificial layers in the first direction and a second opening extending from one of the second sacrificial layers in the first direction by simultaneously etching a portion of the lower stack exposed through the preliminary opening and a portion of the upper stack spaced apart from the preliminary opening.

[0004] According to embodiments of the present disclosure, a method of manufacturing a memory device may include the following steps: forming a first stack comprising a first interlayer insulating layer and a first sacrificial layer alternately stacked on top of each other, the first sacrificial layer having a first etch rate; forming a second stack over the first stack, wherein the second stack comprises a second interlayer insulating layer and a second sacrificial layer alternately stacked on top of each other, the second sacrificial layer having a second etch rate lower than the first etch rate; forming a first sacrificial pillar penetrating the second stack; forming an initial opening by removing the first sacrificial pillar; forming a first opening penetrating a first number of first sacrificial layers by etching a portion of the first stack through the initial opening; forming a second opening penetrating a first number of second sacrificial layers by etching a portion of the second stack spaced apart from the initial opening; and forming contacts in the first and second openings.

[0005] According to embodiments of this disclosure, a memory device may include: a first cell stack including a first conductive layer and a first interlayer insulating layer alternately stacked on top of each other; a second cell stack including a second conductive layer and a second interlayer insulating layer alternately stacked on top of each other in the first cell stack; a cell plug penetrating each of the first cell stack and the second cell stack; a first contact extending vertically from one of the first conductive layers; a second contact extending vertically from one of the second conductive layers; a first dummy stack in the horizontal direction of the first cell stack, including a first interlayer insulating layer and a first sacrificial layer alternately stacked on top of each other; and a second dummy stack in the horizontal direction of the second cell stack, including a second interlayer insulating layer and a second sacrificial layer alternately stacked on top of each other. Furthermore, the etch rate of the second sacrificial layer may be lower than the etch rate of the first sacrificial layer. Attached Figure Description

[0006] Figure 1 This is a diagram illustrating a memory device according to an embodiment of the present disclosure;

[0007] Figure 2 This is an isometric view showing a memory device according to an embodiment of the present disclosure;

[0008] Figures 3A to 3C This is a diagram illustrating a memory device including formed contacts according to an embodiment of the present disclosure;

[0009] Figures 4A to 4H This is a diagram illustrating a method for fabricating contacts in two laminates comprising different sacrificial layers with different etch rates;

[0010] Figures 5A to 5H This is a diagram used to describe a method for fabricating contacts in four stacks comprising different sacrificial layers with different etch rates;

[0011] Figure 6A and Figure 6B This is a diagram illustrating a method of manufacturing contacts in a laminate according to another embodiment of the present disclosure;

[0012] Figures 7A to 7D This is a diagram illustrating a method of manufacturing contacts in a laminate according to another embodiment of the present disclosure;

[0013] Figure 8 A diagram illustrating a memory card system using a memory device according to an embodiment of the present disclosure; and

[0014] Figure 9 This is a diagram illustrating a solid-state drive (SSD) system for a memory device applied according to an embodiment of the present disclosure. Detailed Implementation

[0015] The specific structural or functional descriptions of examples of embodiments based on the concepts disclosed in this specification are shown only as examples of embodiments based on these concepts, which may be implemented in various forms, but the description is not limited to the examples of embodiments described in this specification.

[0016] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, so that those skilled in the art can implement the technical spirit of the present disclosure. According to an embodiment, for example, a memory device with improved contact quality can be manufactured.

[0017] Figure 1 This is a diagram illustrating a memory device 100 according to an embodiment of the present disclosure.

[0018] Reference Figure 1 The memory device 100 may include a memory cell array 110, peripheral circuitry 170, and control circuitry 180.

[0019] The memory cell array 110 may include first memory blocks BLK1 to the i-th memory block BLKi. Each of the first memory blocks BLK1 to the i-th memory block BLKi may include a memory cell for storing data. Drain select line DSL, word line WL, source select line SSL, and source line SL may be connected to each of the first memory blocks BLK1 to the i-th memory block BLKi, and bit line BL may be collectively connected to the first memory blocks BLK1 to the i-th memory block BLKi.

[0020] The first memory block BLK1 to the i-th memory block BLKi may have a three-dimensional structure. The three-dimensional memory block may include memory cells stacked in a direction perpendicular to the substrate.

[0021] Depending on the programming method, a memory cell may include one bit of data or two or more bits of data. For example, storing one bit of data in a single memory cell is called the single-level cell method, storing two bits of data is called the multi-level cell method, storing three bits of data in a single memory cell is called the three-level cell method, and storing four bits of data is called the four-level cell method. Furthermore, five bits or more of data can be stored in a single memory cell.

[0022] The peripheral circuitry 170 may include programming operations for storing data in the memory cell array 110, reading operations for outputting data stored in the memory cell array 110, and erasing operations for erasing data stored in the memory cell array 110. For example, the peripheral circuitry 170 may include a voltage generator 120, a row decoder 130, a page buffer group 140, a column decoder 150, and input / output circuitry 160.

[0023] Voltage generator 120 can generate various operating voltages Vop in response to the opcode OPCD to perform programming, reading, or erasing operations. For example, voltage generator 120 can be configured to generate programming voltage, turn-on voltage, turn-off voltage, negative voltage, pre-charge voltage, verification voltage, read voltage, pass voltage, or erase voltage in response to the opcode OPCD. The operating voltage Vop generated by voltage generator 120 can be applied to the drain select line DSL, word line WL, source select line SSL, and source line SL of the memory block selected by line decoder 130.

[0024] A programming voltage can be applied to a selected word line (WL) during a programming operation and is used to increase the threshold voltage of the memory cell connected to the selected word line. A turn-on voltage can be applied to the drain select line (DSL) or the source select line (SSL) and is used to turn on the drain select transistor or the source select transistor. A turn-off voltage can be applied to the drain select line (DSL) or the source select line (SSL) and is used to turn on the drain select transistor or the source select transistor. For example, the turn-off voltage can be set to 0V. A precharge voltage can be greater than 0V and is applied to the bit line during a read operation. A verification voltage can be used during a verification operation to determine whether the threshold voltage of the selected memory cell has increased to a target level. The verification voltage can be set to various levels depending on the target level and is applied to the selected word line.

[0025] A read voltage can be applied to a selected word line during a read operation of a selected memory cell. For example, the read voltage can be set to various levels depending on the programming method of the selected memory cell. A voltage can be applied to unselected word lines within the word line WL during a read or erase operation, and can be used to turn on memory cells connected to unselected word lines. An erase voltage can be used to erase memory cells included in a selected memory block during an erase operation, and can be applied to the source line SL.

[0026] The row decoder 130 can be configured to apply an operating voltage Vop to a drain select line DSL, a word line WL, a source select line SSL, and a source line SL connected to a memory block selected according to the row address RADD. For example, the row decoder 130 can be connected to the voltage generator 120 via a global line and to the first memory block BLK1 through the i-th memory block BLKi via the drain select line DSL, the word line WL, the source select line SSL, and the source line SL.

[0027] Page buffer group 140 may include page buffers (not shown) respectively connected to first memory blocks BLK1 through i-th memory blocks BLKi. Each page buffer is connected to the first memory blocks BLK1 through i-th memory blocks BLKi via bit lines BL. During a read operation, each page buffer can sense the current or voltage in the bit line that varies according to the threshold voltage of the selected memory cell in response to the page buffer control signal PBSIG, and can temporarily store the sensed data.

[0028] The column decoder 150 can be configured to transfer data between the page buffer group 140 and the input / output circuitry 160 in response to a column address CADD. For example, the column decoder 150 can be coupled to the page buffer group 140 via column line CL and transmit an enable signal via column line CL. The page buffer (not shown) included in the page buffer group 140 can receive or output data via data line DL in response to the enable signal.

[0029] Input / output circuit 160 can receive or output commands (CMD), addresses (ADD), and data via input / output lines I / O. For example, input / output circuit 160 can transmit commands (CMD) and addresses (ADD) received from an external controller to control circuit 180 via input / output lines I / O, and can transmit data received from an external controller to page buffer group 140 via input / output lines I / O. Alternatively, input / output circuit 160 can output data received from page buffer group 140 to an external controller via input / output lines I / O.

[0030] Control circuit 180 can output at least one of the following in response to command CMD and address ADD: opcode OPCD, row address RADD, page buffer control signal PBSIG, and column address CADD. For example, when command CMD input to control circuit 180 corresponds to a programming operation, control circuit 180 can control peripheral circuit 170 to perform a programming operation on the memory block selected by address ADD. When control circuit 180 corresponds to a read operation, control circuit 180 can control peripheral circuit 170 to perform a read operation on the memory block selected by address and output the read data. When command CMD input to control circuit 180 corresponds to an erase operation, control circuit 180 can control peripheral circuit 170 to perform an erase operation on the selected memory block.

[0031] Figure 2 This is an isometric view showing a memory device 100 according to an embodiment of the present disclosure.

[0032] Reference Figure 2 The memory device 100 may include a peripheral circuit structure PC and first memory blocks BLK1 to BLKi disposed above the substrate SUB. The first memory blocks BLK1 to BLKi may overlap with the peripheral circuit structure PC.

[0033] The substrate SUB can be a single-crystal semiconductor layer. For example, the substrate SUB can be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial thin film formed using selective epitaxial growth technology.

[0034] The peripheral circuit structure PC may include a row decoder 130, a column decoder 150, a page buffer group 140, and control circuitry 180, which constitute circuitry for controlling the operation of the first memory blocks BLK1 through the i-th memory blocks BLKi. For example, the peripheral circuit structure PC may include one or more NMOS transistors, PMOS transistors, resistors, and capacitors electrically connected to the first memory blocks BLK1 through the i-th memory blocks BLKi. The peripheral circuit structure PC may be arranged between the substrate SUB and the first memory blocks BLK1 through the i-th memory blocks BLKi.

[0035] Each of the first memory block BLK1 to the i-th memory block BLKi may include a source structure, a bit line, a cell string electrically connected between the source structure and the bit line, a word line electrically connected to the cell string, and a select line electrically connected to the cell string. Each cell string may include memory cells and select transistors connected in series via cell plugs. Each select line may serve as the gate electrode of a corresponding select transistor. Each word line may serve as the gate electrode of a corresponding memory cell.

[0036] As the length of the first storage block BLK1 to the i-th storage block BLKi increases in the Z direction, a double-layer stacking method or a multi-layer stacking method can be used, which involves stacking two or more layers. For example, each of the first storage blocks BLK1 to the i-th storage block BLKi may include a first layer and a second layer located above the first layer, and the respective cell plugs included in the first storage blocks BLK1 to the i-th storage blocks BLKi may include a first portion located in the first layer and a second portion located in the second layer.

[0037] In another embodiment, the substrate SUB, the peripheral circuit structure PC, and the first memory blocks BLK1 to the i-th memory blocks BLKi can be configured according to... Figure 2The stacking order is the reverse of the given order. For example, the peripheral circuitry PC can be arranged above the first memory block BLK1 to the i-th memory block BLKi.

[0038] In another embodiment, with Figure 2 Conversely, the peripheral circuit structure PC can be arranged above some areas of the substrate SUB that do not overlap with the first memory blocks BLK1 to the i-th memory blocks BLKi. For example, the peripheral circuit structure PC and the first memory blocks BLK1 to the i-th memory blocks BLKi can be arranged in areas of the substrate SUB that do not overlap with each other.

[0039] Figures 3A to 3C This is a diagram illustrating a memory device including formed contacts according to an embodiment of the present disclosure. Figure 3A This is a plan view of the layout of a memory device according to an embodiment of the present disclosure. Figure 3B It is shown Figure 3A Cross-sectional view of cross section A-A'. Figure 3C It is shown Figure 3A A cross-sectional view of cross section A'-A.

[0040] Reference Figure 3A Memory device 100 (e.g., Figure 2 The first memory block (BLK1 to any one of the i-th memory blocks BLKi) may include a cell region CR and a contact region CTR. The contact region CTR may be located in the X direction of the cell region CR. The contact region CTR may extend from the cell region CR in the X direction. Figure 3A Conversely, the contact region CTR can extend from the element region CR in the Y direction, or it can extend in both the X and Y directions. Furthermore, the element region CR and the contact region CTR can be arranged in various ways.

[0041] Cell plugs (CPLs) can be located within cell regions (CRs). Cell plugs (CPLs) can be arranged in both the X and Y directions. Cell plugs (CPLs) can be spaced apart from each other in both the X and Y directions. Each cell plug (CPL) can extend in the Z direction. Each cell plug (CPL) can be electrically connected to a bitline (e.g., via a wiring structure) through a wiring configuration. Figure 1 Bit lines (BL) and source lines (e.g., Figure 1 The source line (SL).

[0042] Each cell plug CPL may include a memory layer ML, a channel layer CH, and a core CO. In an embodiment, the memory layer ML may have a cylindrical shape. The memory layer ML may include a circular cross-section in the XY plane. The memory layer ML may surround the channel layer CH. Although Figure 3A As not shown in the diagram, the memory layer ML may include a blocking layer, a charge trapping layer, and a tunneling layer.

[0043] In another embodiment, with Figure 3A Conversely, the memory layer ML comprises an elliptical or cloverleaf-shaped cross-section in the XY plane. The memory layer ML may be formed on at least a portion of the inner surface of an aperture having an elliptical or cloverleaf-shaped cross-section. For example, the memory layer ML may cover the entire inner surface of the aperture. In another example, the memory layer ML may cover only a portion of the inner surface of the aperture. That is, two or more cell strings separated from each other may be formed in one aperture. However, for ease of illustration, it is assumed that the cell plug CPL has a circular cross-section in the XY plane.

[0044] The blocking and tunneling layers included in the memory layer ML may comprise oxide layers (e.g., silicon oxide layers) or oxynitride layers (e.g., silicon oxynitride layers) or combinations thereof. The charge trapping layer included in the memory layer ML may comprise a nitride layer or a variable resistance material.

[0045] A channel layer CH may be formed on the inner wall of the memory layer ML. A die CO may fill the interior of the channel layer CH. The die CO may have a cylindrical shape surrounded by the channel layer CH. The channel layer CH may include an undoped silicon layer or a doped silicon layer. The die CO may include an insulating layer (e.g., an oxide layer) or a conductive layer.

[0046] Contact points (CTs) can be located within the contact area (CTR). Multiple contacts can be arranged within the contact area (CTR). Figure 3A Only some contact points (CTs) are shown. Contact points (CTs) may be spaced apart from each other in the X direction. Contact points (CTs) may be arranged in the X direction. Additionally, contact points (CTs) may be arranged differently within the contact area (CTR). Individual contact points (CTs) may extend in the Z direction. Contact points (CTs) may include conductive material. Contact points (CTs) may be referred to as word line contacts or contact plugs.

[0047] Spacers SP may surround contacts CT. Spacers SP may contact the sides of contacts CT. Contacts CT may fill the interior of spacers SP. Spacers SP may include an insulating layer. For example, spacers SP may include an oxide layer.

[0048] The memory device 100 may further include a peripheral contact region PCTR. The peripheral contact region PCTR may be within a contact region CTR. For example, the peripheral contact region PCTR may correspond to a portion of the contact region CTR. The peripheral contact region PCTR may be surrounded by an isolation structure IS. The isolation structure IS may separate the peripheral contact region PCTR from the remainder of the contact region CTR.

[0049] The peripheral circuit contact PCT can be arranged within the peripheral contact area PCTR. The peripheral circuit contact PCT can penetrate the peripheral contact area PCTR. The peripheral circuit contact PCT can extend in the Z direction. The peripheral circuit contact PCT can be electrically connected to... Figure 2 The peripheral circuit structure PC.

[0050] Reference Figure 3B The memory device 100 may include a first stack STK1 and a second stack STK2. The second stack STK2 may be disposed on the first stack STK1. The second stack STK2 may be located in the Z-direction of the first stack STK1. The upper surface of the first stack STK1 may contact the lower surface of the second stack STK2. The first stack STK1 and the second stack STK2 may be referred to as a first cell stack and a second cell stack, respectively. The first stack STK1 and the second stack STK2 may extend from a cell region CR to a contact region CTR. The first stack STK1 and the second stack STK2 may be located within the cell region CR and the contact region CTR.

[0051] The first stack STK1 may include a first conductive layer CD1 and a first interlayer insulating layer IL1. The first conductive layer CD1 and the first interlayer insulating layer IL1 may be stacked alternately with each other in the Z direction. The second stack STK2 may include a second conductive layer CD2 and a second interlayer insulating layer IL2. The second conductive layer CD2 and the second interlayer insulating layer IL2 may be stacked alternately with each other in the Z direction. The first conductive layer CD1 and the second conductive layer CD2 may include at least one of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si), or polysilicon (poly-Si). The first conductive layer CD1 and the second conductive layer CD2 may include the same material. The first conductive layer CD1 and the second conductive layer CD2 may correspond to a gate line (e.g., Figure 1 The drain select line (DSL), word line (WL), and source select line (SSL) are included. The first interlayer insulating layer IL1 and the second interlayer insulating layer IL2 may include oxide layers (e.g., silicon oxide layers). The first interlayer insulating layer IL1 and the second interlayer insulating layer IL2 may include the same material.

[0052] The memory device 100 may include a first dummy stack DSTK1 and a second dummy stack DSTK2. The second dummy stack DSTK2 may be disposed on the first dummy stack DSTK1. The second dummy stack DSTK2 may be located in the Z-direction of the first dummy stack DSTK1. The upper surface of the first dummy stack DSTK1 may contact the lower surface of the second dummy stack DSTK2. The first dummy stack DSTK1 may be located in the horizontal direction (e.g., the X-direction) of the first stack DSTK1. The first dummy stack DSTK1 may be at the same height as the first stack DSTK1. The second dummy stack DSTK2 may be located in the horizontal direction (e.g., the X-direction) of the second stack DSTK2. The second dummy stack DSTK2 may be at the same height as the second stack DSTK2. The first dummy stack DSTK1 and the second dummy stack DSTK2 may be located within a peripheral contact region PCTR. The isolation structure IS can be located between the first dummy laminate DSTK1 and the first laminate STK1. The isolation structure IS can also be located between the second dummy laminate DSTK2 and the second laminate STK2.

[0053] The first dummy laminate DSTK1 may include a first sacrificial layer SF1 and a first interlayer insulating layer IL1. The first interlayer insulating layer IL1 included in the first dummy laminate DSTK1 may have the same height as the first interlayer insulating layer IL1 included in the first laminate STK1. The first interlayer insulating layer IL1 included in the first dummy laminate DSTK1 may include the same material as the first interlayer insulating layer IL1 included in the first laminate STK1. The first sacrificial layer SF1 may have the same height as the first conductive layer CD1. The isolation structure IS may allow the first sacrificial layer SF1 to be retained without being replaced by the first conductive layer CD1.

[0054] The second dummy laminate DSTK2 may include a second sacrificial layer SF2 and a second interlayer insulating layer IL2. The second interlayer insulating layer IL2 included in the second dummy laminate DSTK2 may have the same height as the second interlayer insulating layer IL2 included in the second laminate STK2. The second interlayer insulating layer IL2 included in the second dummy laminate DSTK2 may include the same material as the second interlayer insulating layer IL2 included in the second laminate STK2. The second sacrificial layer SF2 may have the same height as the second conductive layer CD2. The isolation structure IS allows the second sacrificial layer SF2 to be retained without being replaced by the second conductive layer CD2.

[0055] The first sacrificial layer SF1 and the second sacrificial layer SF2 may comprise materials that are etch-selective relative to the first interlayer insulating layer IL1 and the second interlayer insulating layer IL2. The first sacrificial layer SF1 and the second sacrificial layer SF2 may comprise nitride materials. For example, the first sacrificial layer SF1 and the second sacrificial layer SF2 may comprise silicon nitride.

[0056] In this disclosure, the first sacrificial layer SF1 and the second sacrificial layer SF2 may have different etch rates. The first sacrificial layer SF1 may have a first etch rate, and the second sacrificial layer SF2 may have a second etch rate. The second etch rate may be lower than the first etch rate. The etch rate of the second sacrificial layer SF2 may be slower than the etch rate of the first sacrificial layer SF1. That is, the etch rate of the sacrificial layer may increase towards the lower part of the stack, and the etch rate of the sacrificial layer may decrease towards the upper part of the stack.

[0057] In this embodiment, the etching rate may vary depending on the concentration of impurities contained in the first sacrificial layer SF1 and the second sacrificial layer SF2. The concentration of impurities contained in the second sacrificial layer SF2 may be greater than the concentration of impurities contained in the first sacrificial layer SF1. Impurities may include carbon. Impurities may be included in the first sacrificial layer SF1 and the second sacrificial layer SF2 by a doping process or an implantation process.

[0058] In another embodiment, the contents of the materials included in the first sacrificial layer SF1 and the second sacrificial layer SF2 may be different from each other. The first sacrificial layer SF1 and the second sacrificial layer SF2 may respectively include nitrogen (N) and silicon (Si). The proportion of silicon (Si) included in the second sacrificial layer SF2 may be higher than the proportion of silicon (Si) included in the first sacrificial layer SF1.

[0059] In another embodiment, the etching rates of the first sacrificial layer SF1 and the second sacrificial layer SF2 can be set differently by varying various conditions (e.g., heat treatment time, number of treatments, temperature, etc.) applied to each of the lower stack (e.g., STK1 or DSTK1) and the upper stack (e.g., STK2 or DSTK2).

[0060] Reference Figure 3B The cell plugs (CPLs) can penetrate the cell regions (CRs) of the first stack (STK1) and the second stack (STK2). Each cell plug (CPL) may include a memory layer (ML), a channel layer (CH), and a core (CO). Memory cells and select transistors may be formed at the respective intersections of the cell plug (CPL) with the first conductive layer (CD1) and the second conductive layer (CD2). The cell plugs (CPLs) can serve as channel regions for cell strings. The width of each cell plug (CPL) may vary at the interface between the first stack (STK1) and the second stack (STK2). For example, the width of the cell plug (CPL) in the X direction at the bottom of the second stack (STK2) may be smaller than the width of the cell plug (CPL) in the X direction at the top of the first stack (STK1).

[0061] The contact CT can extend in the Z-direction within the contact area CTR. The contact CT can extend in the Z-direction from either the first conductive layer CD1 or the second conductive layer CD2. For example, a first contact contacting one of the first conductive layers CD1 can penetrate the second laminate STK2. The first contact can penetrate the second conductive layer CD2 and the second interlayer insulating layer IL2. The first contact can be surrounded by the second conductive layer CD2 and the second interlayer insulating layer IL2. The first contact can penetrate at least one of the first interlayer insulating layers IL1. Additionally, a second contact contacting one of the second conductive layers CD2 can penetrate at least one of the second interlayer insulating layers IL2. The lower surface of each contact CT can contact the upper surface of either the first conductive layer CD1 or the second conductive layer CD2. The contact CT can be electrically connected to the first conductive layer CD1 and the second conductive layer CD2, respectively. (Refer to...) Figure 3B The contact region CTR is formed as a stepless structure. For example, the length of each first conductive layer CD1 in the X direction is the same as the length of each second conductive layer CD2 in the X direction.

[0062] Spacers SP may surround the sides of each contact CT. Spacers SP may insulate the contact CT from other conductive layers (e.g., CD1 and CD2) besides the conductive layer to which each contact is connected.

[0063] The peripheral circuit contact PCT can penetrate the first dummy stack DSTK1 and the second dummy stack DSTK2. Because the first dummy stack DSTK1 and the second dummy stack DSTK2 do not contain conductive layers, no spacers need to be arranged on the side surface of the peripheral circuit contact PCT.

[0064] Although not shown, in one embodiment, a support post may be formed in the contact region CTR. The support post may extend in the Z-direction within the contact region CTR. The support post may penetrate at least some of the first conductive layers CD1 and CD2, and at least some of the first interlayer insulating layers IL1 and IL2. For example, the support post may penetrate the first laminate STK1 and second laminate STK2 in the contact region CTR. In another example, the support post may pass through the first laminate STK1 from the bottom of the second laminate STK2. The support post may support the first interlayer insulating layers IL1 and IL2 during the process of forming the first conductive layers CD1 and CD2. The support post may have various shapes, such as cylindrical or elliptical. The support post may include an insulating material.

[0065] Additionally, in this embodiment, a dummy post may be further formed in the contact region CTR. The dummy post may extend in the Z-direction within the contact region CTR. The dummy post may penetrate at least some of the first conductive layer CD1 and the second conductive layer CD2, as well as at least some of the first interlayer insulating layer IL1 and the second interlayer insulating layer IL2. The dummy post may have various shapes, such as cylindrical or elliptical. The dummy post may include insulating material.

[0066] Reference Figure 3C A first stack STK1, a second stack STK2, a first dummy stack DSTK1, and a second dummy stack DSTK2 can be stacked above the lower structure LSTR. For example, the upper insulating layer UIL can be disposed in the Z direction of the second stack STK2 and the second dummy stack DSTK2. The first upper contact UCT1, the bit line BL, the upper line ULN, the second upper contact UCT2, and the upper bonding pad UPD can be disposed within the upper insulating layer UIL. The first upper contact UCT1 can contact the cell plug CPL, the contact CT, and the peripheral circuit contact PCT. The bit line BL can be connected to the cell plug CPL through the first upper contact UCT1. The upper line ULN can be connected to the contact CT or the peripheral circuit contact PCT through the first upper contact UCT1. The upper bonding pad UPD can be connected to the bit line BL or the upper line ULN through the second upper contact UCT2. The lower structure LSTR may include a lower substrate LSUB, a lower insulating layer LIL, at least one transistor TR, a lower contact LCT, a lower line LLN, and a lower bonding pad LPD. The upper bonding pad UPD may contact the lower bonding pad LPD. A source layer (not shown) may be disposed on the first laminate STK1.

[0067] Figures 4A to 4H This is a diagram used to describe a method for manufacturing contacts in two laminates comprising different sacrificial layers with different etch rates. Figures 4A to 4H Is with Figure 3A The cross-sectional view corresponding to cross section B-B'.

[0068] Reference Figure 4A A first preliminary stack pSTK1 can be formed, wherein a first interlayer insulating layer IL1 and a first sacrificial layer SF1 are alternately stacked on top of each other. The first interlayer insulating layer IL1 and the first sacrificial layer SF1 may be stacked on top of each other in the Z direction. The first interlayer insulating layer IL1 may include an insulating material. For example, the first interlayer insulating layer IL1 may include an oxide layer (e.g., a silicon oxide layer). The first sacrificial layer SF1 may include a material that is selectively removed in subsequent processes. The first sacrificial layer SF1 may include a material having an etch selectivity different from that of the first interlayer insulating layer IL1. For example, the first sacrificial layer SF1 may include a nitride layer.

[0069] Subsequently, first unit sacrificial pillars CSP1 can be formed through the first preliminary stack pSTK1. The first unit sacrificial pillars CSP1 can be formed in the unit region CR. Each first unit sacrificial pillar CSP1 can extend in the Z direction. The XY cross-section of the first unit sacrificial pillar CSP1 can have a cylindrical, elliptical, or columnar shape, filling a tapered hole in the Z direction. The first unit sacrificial pillar CSP1 may include a carbon layer. For example, the first unit sacrificial pillar CSP1 may include a carbon layer, a carbon layer and polysilicon, or a carbon layer and a metal nitride (e.g., TiN).

[0070] Subsequently, a second preliminary laminate pSTK2 may be formed on the first preliminary laminate pSTK1. The second preliminary laminate pSTK2 may include a second interlayer insulating layer IL2 and a second sacrificial layer SF2 that are alternately stacked on top of each other. The second interlayer insulating layer IL2 and the second sacrificial layer SF2 may be stacked on top of each other in the Z direction. The lowermost second sacrificial layer of the second sacrificial layer SF2 may be in contact with the uppermost first interlayer insulating layer of the first interlayer insulating layer IL1.

[0071] The second interlayer insulating layer IL2 may include an insulating material. For example, the second interlayer insulating layer IL2 may include an oxide layer (e.g., a silicon oxide layer). The second interlayer insulating layer IL2 may include the same material as the first interlayer insulating layer IL1. The second sacrificial layer SF2 may include a material that is selectively removed in subsequent processes. The second sacrificial layer SF2 may include a material having an etch selectivity different from that of the second interlayer insulating layer IL2. For example, the second sacrificial layer SF2 may include a nitride layer.

[0072] The first sacrificial layer SF1 may have a first etch rate. The second sacrificial layer SF2 may have a second etch rate. The second etch rate may be lower than the first etch rate. That is, the etch rate of the second sacrificial layer SF2 may be slower than the etch rate of the first sacrificial layer SF1.

[0073] In an embodiment, the second sacrificial layer SF2 may be formed to contain more impurities than the first sacrificial layer SF1. For example, the first sacrificial layer SF1 and the second sacrificial layer SF2 may each contain impurities such as carbon, and the second sacrificial layer SF2 may contain more impurities than the first sacrificial layer SF1. Therefore, the etching rate of the second sacrificial layer SF2 may be slower than the etching rate of the first sacrificial layer SF1.

[0074] In another embodiment, the first sacrificial layer SF1 and the second sacrificial layer SF2 may each comprise silicon (Si) and nitrogen (N), and the proportion of Si contained in the second sacrificial layer SF2 may be higher than the proportion of Si contained in the first sacrificial layer SF1. For example, the first sacrificial layer SF1 may comprise Si a N b The second sacrificial layer SF2 may include Si xN y Where x / y can have a value greater than a / b. Therefore, the etching rate of the second sacrificial layer SF2 can be slower than the etching rate of the first sacrificial layer SF1.

[0075] Furthermore, various methods can be used to allow the first sacrificial layer SF1 and the second sacrificial layer SF2 to have different etching rates. For example, the etching rates of the first sacrificial layer SF1 and the second sacrificial layer SF2 can be controlled by adjusting the time, quantity, temperature, etc., of the heat treatment process during the formation of each of the first preliminary stack pSTK1 and the second preliminary stack pSTK2. In another example, different types of impurities can be implanted into the first sacrificial layer SF1 and the second sacrificial layer SF2 to control their relative etching rates.

[0076] Subsequently, second unit sacrificial pillars CSP2 can be formed through the second preliminary laminate pSTK2. The second unit sacrificial pillars CSP2 can be formed in the unit region CR. Each second unit sacrificial pillar CSP2 can extend in the Z direction. The second unit sacrificial pillars CSP2 can overlap with a first unit sacrificial pillar CSP1. The lower surface of each second unit sacrificial pillar CSP2 can contact the upper surface of its corresponding lower first unit sacrificial pillar CSP1. The XY cross-section of the second unit sacrificial pillar CSP2 can have a cylindrical, elliptical, or columnar shape, filling a tapered hole in the Z direction. Because the second unit sacrificial pillars CSP2 are formed on the already formed first unit sacrificial pillars CSP1, irregularities can be formed on the side surfaces of the first unit sacrificial pillars CSP1 and CSP2 at the interface between the first preliminary laminate pSTK1 and the second preliminary laminate pSTK2. For example, the width of the upper end of each first unit sacrificial pillar CSP1 can be greater than the width of the lower end of each second unit sacrificial pillar CSP2.

[0077] Additionally, a first sacrificial pillar SFP1 can be formed through the second preliminary laminate pSTK2. The first sacrificial pillar SFP1 can be formed in the contact region CTR. For example, the first sacrificial pillar SFP1 can be formed by etching a portion of the second preliminary laminate pSTK2 in the contact region CTR and filling it with sacrificial material. Each first sacrificial pillar SFP1 can extend in the Z direction. The lower surface of the first sacrificial pillar SFP1 can contact the upper surface of the first preliminary laminate pSTK1. The XY cross-section of the first sacrificial pillar SFP1 can have a cylindrical, elliptical, or columnar shape, filling a tapered hole in the Z direction.

[0078] The second sacrificial pillar CSP2 and the first sacrificial pillar SFP1 may include a carbon layer. For example, the second sacrificial pillar CSP2 and the first sacrificial pillar SFP1 may include a carbon layer, a carbon layer and polysilicon, or a carbon layer and a metal nitride (e.g., TiN).

[0079] Reference Figure 4B The first cell sacrificial pillar CSP1 and the second cell sacrificial pillar CSP2 can be removed. The space where the first cell sacrificial pillar CSP1 and the second cell sacrificial pillar CSP2 are removed can be referred to as a cell opening. For example, each cell opening can correspond to the space where one of the first cell sacrificial pillars CSP1 and one of the second cell sacrificial pillars CSP2 are removed. A cell plug CPL can be formed in the space where the first cell sacrificial pillars CSP1 and the second cell sacrificial pillars CSP2 are removed (e.g., the cell opening). For example, as the first cell sacrificial pillars CSP1 and the second cell sacrificial pillars CSP2 are removed, the side surfaces of the first preliminary stack pSTK1 and the second preliminary stack pSTK2 can be exposed. The memory layer ML, the channel layer CH, and the die pillar CO can be sequentially formed on the side surfaces of the first preliminary stack pSTK1 and the second preliminary stack pSTK2 within the cell opening.

[0080] Reference Figure 4C A hard mask HM and a thinning mask SM can be formed on the second preliminary laminate pSTK2. The hard mask HM can contact the upper surface of the second preliminary laminate pSTK2. The hard mask HM may include a mask opening MOP. The mask opening MOP may correspond to the surface to be formed. Figure 3A and Figure 3B The location of the contact point CT. The mask opening MOP can expose... Figure 4B The first sacrificial column SFP1. Additionally, a portion of the upper surface of the second preliminary laminate pSTK2 can be exposed through a mask opening MOP. The hard mask HM may comprise a nitride material. The thinning mask SM may contact the upper surface of the hard mask HM. The thinning mask SM may comprise an opening in the mask opening MOP that exposes the hard mask HM. The thinning mask SM may comprise a material whose volume is reduced due to heat treatment.

[0081] Subsequently, the first sacrificial pillar SFP1 can be removed to form an initial opening POP. The first sacrificial pillar SFP1 can be etched through a mask opening MOP. The initial opening POP corresponds to the space where the first sacrificial pillar SFP1 has been removed. The initial opening POP can penetrate the second preliminary stack pSTK2 and expose the upper surface of the first preliminary stack pSTK1.

[0082] Reference Figure 4DThe portions of the first preliminary stack pSTK1 and the second preliminary stack pSTK2 exposed by the thinning mask SM and the hard mask HM can be etched. The portion of the first preliminary stack pSTK1 exposed by the mask opening MOP and the initial opening POP can be removed to form a first opening OP1. Each first opening OP1 may include a space corresponding to the initial opening POP. Additionally, the portion of the second preliminary stack pSTK2 exposed by the mask opening MOP can be removed to form a second opening OP2. The second opening OP2 may be horizontally spaced from the first opening OP1.

[0083] The first opening OP1 can extend in the Z direction from either of the first sacrificial layers SF1. The first opening OP1 can expose the upper surface of either of the first sacrificial layers SF1. In addition, the second opening OP2 can extend in the Z direction from either of the second sacrificial layers SF2. The second opening OP2 can expose the upper surface of either of the second sacrificial layers SF2.

[0084] The height of the area of ​​the first opening OP1, excluding the area corresponding to the initial opening POP, may correspond to the height of the second opening OP2. For example, the first opening OP1 may have a depth corresponding to the depth of the second first sacrificial layer SF1 from the top of the first sacrificial layer SF1. Similarly, the second opening OP2 may have a depth corresponding to the depth of the second second sacrificial layer SF2 from the top of the second second sacrificial layer SF2.

[0085] A process for forming a first opening OP1 and a second opening OP2 can be performed to alternately remove an interlayer insulating layer (e.g., IL1 and IL2) and a sacrificial layer (e.g., SF1 and SF2). A process for sequentially etching an oxide layer and a nitride layer can be performed to give the first opening OP1 and the second opening OP2 a specific depth.

[0086] The etching processes of the first preliminary stack pSTK1 and the second preliminary stack pSTK2 can be performed simultaneously. The lower portions of the second opening OP2 and the first opening OP1 are formed by a single etching process. For example, when performing an etching process using etching gas, the second preliminary stack pSTK2 can be etched by etching gas passing through the mask opening MOP to form the second opening OP2. Alternatively, the first preliminary stack pSTK1 can be etched by etching gas passing through the mask opening MOP and the preliminary opening POP to form the first opening OP1. The time for the etching gas to reach the first preliminary stack pSTK1 can be longer than the time for the etching gas to reach the second preliminary stack pSTK2. Therefore, when the first sacrificial layer SF1 and the second sacrificial layer SF2 have the same etching rate, the degree to which the first preliminary stack pSTK1 is etched can be less than the degree to which the second preliminary stack pSTK2 is etched. However, according to the embodiments of this disclosure, since the etching rate of the first sacrificial layer SF1 is faster than that of the second sacrificial layer SF2, even if the time it takes for the etching gas to reach the first preliminary stack pSTK1 is longer than the time it takes for the etching gas to reach the second preliminary stack pSTK2, the etching depth of the first preliminary stack pSTK1 can be the same as that of the second preliminary stack pSTK2.

[0087] Reference Figure 4E The thinned mask SM can be modified to further cover a portion of the hard mask HM. For example, it can be done in... Figure 4D After the thinning mask SM is removed, a new thinning mask SM is formed, or it can be... Figure 4D On the thinned mask SM, a material corresponding to the thinned mask is further formed to fill some mask openings MOP.

[0088] Some of the first opening OP1 and some of the second opening OP2 can be exposed by modifying the thinning mask SM. The remaining first opening OP1 and second opening OP2 can be covered by the thinning mask SM.

[0089] Subsequently, a portion of the first preliminary laminate pSTK1 exposed through the first opening OP1 can be etched to form the third opening OP3. For example, the left side of the first opening OP1 can extend downward to form the third opening OP3. Additionally, a portion of the second preliminary laminate pSTK2 exposed through the second opening OP2 can be etched to form the fourth opening OP4. For example, the right side of the second opening OP2 can extend downward to form the fourth opening OP4.

[0090] The third opening OP3 can be formed with a depth greater than the first opening OP1 and a length corresponding to the sum of the thickness of the first sacrificial layer SF1 and the thickness of the first interlayer insulating layer IL1. The third opening OP3 can extend from any one of the first sacrificial layers SF1 in the Z direction. Furthermore, the fourth opening OP4 can be formed with a depth greater than the second opening OP2 and a length corresponding to the sum of the thickness of the second sacrificial layer SF2 and the thickness of the second interlayer insulating layer IL2. The fourth opening OP4 can extend from any one of the second sacrificial layers SF2 in the Z direction.

[0091] The height of the area of ​​the third opening OP3, excluding the area corresponding to the initial opening POP, can correspond to the height of the fourth opening OP4. For example, the third opening OP3 can have a depth corresponding to the depth of the third first sacrificial layer SF1 from the top of the first sacrificial layer SF1. Similarly, the fourth opening OP4 can have a depth corresponding to the depth of the third second sacrificial layer SF2 from the top of the second sacrificial layer SF2.

[0092] For example, regarding Figure 4D As described, the etching processes of the first preliminary stack pSTK1 and the second preliminary stack pSTK2 can be performed simultaneously. The lower portion of the third opening OP3 and the lower portion of the fourth opening OP4 are formed by a single etching process. For example, when performing an etching process using an etching gas, the first preliminary stack pSTK1 can be etched by the etching gas passing through the first opening OP1 to form the third opening OP3. Similarly, the second preliminary stack pSTK2 can be etched by the etching gas passing through the second opening OP2 to form the fourth opening OP4. The time it takes for the etching gas to reach the first preliminary stack pSTK1 can be longer than the time it takes for the etching gas to reach the second preliminary stack pSTK2. According to embodiments of this disclosure, because the etching rate of the first sacrificial layer SF1 is faster than the etching rate of the second sacrificial layer SF2, even if the time it takes for the etching gas to reach the first preliminary stack pSTK1 is longer than the time it takes for the etching gas to reach the second preliminary stack pSTK2, the depth to which the first preliminary stack pSTK1 is etched can be the same as the depth to which the second preliminary stack pSTK2 is etched.

[0093] exist Figure 4D and Figure 4E For ease of description, only the method of forming the first opening OP1 to the fourth opening OP4 is shown, but the present disclosure is not limited thereto. For example, openings connected to each of the first sacrificial layers SF1 and openings connected to each of the second sacrificial layers SF2 can be formed.

[0094] Reference Figure 4FThe thinning mask SM and the hard mask HM can be removed. Subsequently, a spacer layer SPL can be formed on the inner surfaces of the first opening OP1 to the fourth opening OP4. The spacer layer SPL can extend on the side and bottom surfaces of the first opening OP1 to the fourth opening OP4, respectively. The spacer layer SPL can be formed on the side and top surfaces of the first preliminary laminate pSTK1 and the second preliminary laminate pSTK2 exposed through the first opening OP1 to the fourth opening OP4. The spacer layer SPL can be conformally formed on the inner surfaces of the first opening OP1 to the fourth opening OP4. The spacer layer SPL may include an insulating material. For example, the spacer layer SPL may be an oxide layer.

[0095] Subsequently, second sacrificial pillars SFP2 can be formed in the first opening OP1 to the fourth opening OP4. The second sacrificial pillars SFP2 can respectively fill the first opening OP1 to the fourth opening OP4. The second sacrificial pillars SFP2 can be surrounded by spacer layers SPL. The second sacrificial pillars SFP2 can be separated from the first preliminary laminate pSTK1 and the second preliminary laminate pSTK2 through the spacer layers SPL. The second sacrificial pillars SFP2 may include a carbon layer or a conductive layer (e.g., tungsten).

[0096] Reference Figure 4G The first conductive layer CD1 can replace the first sacrificial layer SF1, and the second conductive layer CD2 can replace the second sacrificial layer SF2. For example, the first sacrificial layer SF1 and the second sacrificial layer SF2 can be removed, and the space between the first interlayer insulating layer IL1 and the second interlayer insulating layer IL2 can be filled with a conductive material. The first conductive layer CD1 and the second conductive layer CD2 can be formed simultaneously. The first conductive layer CD1 and the second conductive layer CD2 can comprise materials equivalent to each other. The first conductive layer CD1 and the first interlayer insulating layer IL1 can form a first laminate STK1. The second conductive layer CD2 and the second interlayer insulating layer IL2 can form a second laminate STK2.

[0097] Although not shown here, such as Figure 3A The peripheral contact region PCTR shown may be surrounded by an isolation structure IS. Therefore, in an embodiment, the first sacrificial layer SF1 and the second sacrificial layer SF2 may not be removed within the peripheral contact region PCTR. Thus, within the isolation structure IS, the first sacrificial layer SF1 and the second sacrificial layer SF2 may be retained without being replaced by the first conductive layer CD1 and the second conductive layer CD2.

[0098] Subsequently, the second sacrificial post SFP2 can be removed from the first opening OP1 to the fourth opening OP4. The second sacrificial post SFP2 can be removed to form the contact opening CTOP.

[0099] The bottom of each spacer layer SPL can then be removed. Spacers SP can be formed by removing the lower surface of the spacer layer SPL through the contact opening CTOP. The spacers SP can extend on the inner surface of the contact opening CTOP. As the lower surface of the spacer layer SPL is removed, the upper surfaces of the first conductive layer CD1 and the second conductive layer CD2 can be exposed through the contact opening CTOP. Each contact opening CTOP can expose one of the first conductive layer CD1 and the second conductive layer CD2.

[0100] Reference Figure 4H Each contact CT can fill the contact opening CTOP. The contact CT can be disposed within the contact opening CTOP. Each contact CT can contact the first conductive layer CD1 and the second conductive layer CD2. Each contact CT can be electrically connected to the first conductive layer CD1 and the second conductive layer CD2. Each contact CT can be surrounded by a spacer SP. Therefore, each contact CT can be connected to one of the conductive layers, but not to the other conductive layers.

[0101] According to embodiments of this disclosure, as referred to Figure 4D and Figure 4E As described, by forming a first sacrificial layer SF1 having an etch rate different from that of the second sacrificial layer SF2, an opening for the contact (CT) can be formed (e.g., OP1 to OP4). Therefore, by controlling the etch rates of the first sacrificial layer SF1 and the second sacrificial layer SF2, which are alternately stacked with the first interlayer insulating layer IL1 and the second interlayer insulating layer IL2, the quality of the contact CT can be improved, and the manufacturing process of the contact CT can be perfected.

[0102] Figures 5A to 5H This is a diagram used to describe a method for fabricating contacts in four stacks comprising different sacrificial layers with different etch rates.

[0103] Figures 5A to 5H It is used to describe when a memory device comprises a four-layer stack, in relation to a reference. Figures 4A to 4H The diagrams illustrate different methods for forming contact points (CT) in the contact area (CTR). (Already referenced...) Figures 4A to 4H The described configuration will be omitted or combined. Figures 5A to 5H Brief description.

[0104] Reference Figure 5AA first preliminary laminate pSTK1 can be formed, wherein a first interlayer insulating layer IL1 and a first sacrificial layer SF1 are alternately laminated. Subsequently, a first unit sacrificial pillar CSP1 can be formed through the first preliminary laminate pSTK1 in the unit region CR. Then, a second preliminary laminate pSTK2 can be formed, wherein a second interlayer insulating layer IL2 and a second sacrificial layer SF2 are alternately laminated. Subsequently, a second unit sacrificial pillar CSP2 can be formed through the second preliminary laminate pSTK2 in the unit region CR. The second unit sacrificial pillar CSP2 can overlap with the first unit sacrificial pillar CSP1. Additionally, a (1-1)th sacrificial pillar SFP1-1 can be formed through the second preliminary laminate pSTK2 in the contact region CTR.

[0105] Subsequently, a third preliminary laminate pSTK3 can be formed, wherein a third interlayer insulating layer IL3 and a third sacrificial layer SF3 are alternately laminated. Then, a third unit sacrificial pillar CSP3 can be formed through the third preliminary laminate pSTK3 in the unit region CR. The third unit sacrificial pillar CSP3 can overlap with the second unit sacrificial pillar CSP2 and the first unit sacrificial pillar CSP1, respectively. Furthermore, a (1-2) sacrificial pillar SFP1-2 can be formed through the third preliminary laminate pSTK3 in the contact region CTR. Some of the (1-2) sacrificial pillars SFP1-2 can overlap with the (1-1) sacrificial pillar SFP1-1, while the remaining (1-2) sacrificial pillars SFP1-2 may not overlap with the (1-1) sacrificial pillar SFP1-1.

[0106] Next, a fourth preliminary laminate pSTK4 can be formed, wherein the fourth interlayer insulating layer IL4 and the fourth sacrificial layer SF4 are alternately laminated. Subsequently, a fourth unit sacrificial pillar CSP4 can be formed in the unit region CR, passing through the fourth preliminary laminate pSTK4. The fourth unit sacrificial pillar CSP4 can overlap with the third unit sacrificial pillar CSP3, the second unit sacrificial pillar CSP2, and the first unit sacrificial pillar CSP1, respectively. In addition, (1-3) sacrificial pillars SFP1-3 passing through the fourth preliminary laminate pSTK4 can be formed in the contact region CTR. Some (1-3) sacrificial pillars SFP1-3 can overlap with (1-2) sacrificial pillars SFP1-2, and the remaining (1-3) sacrificial pillars SFP1-3 may not overlap with (1-2) sacrificial pillars SFP1-2.

[0107] The first sacrificial layer SF1 may have a first etch rate, the second sacrificial layer SF2 may have a second etch rate, the third sacrificial layer SF3 may have a third etch rate, and the fourth sacrificial layer SF4 may have a fourth etch rate. The first etch rate may be higher than the second etch rate. The second etch rate may be higher than the third etch rate. The third etch rate may be higher than the fourth etch rate. That is, the etch rate of the sacrificial layers may increase towards the bottom of the stack, and the etch rate of the sacrificial layers may decrease towards the top of the stack. For example, the etch rates of the first sacrificial layer SF1 to the fourth sacrificial layer SF4 may be formed as shown in Equation 1 below.

[0108] [Formula 1]

[0109] The etching rate of the first sacrificial layer SF1 is greater than that of the second sacrificial layer SF2, which is greater than that of the third sacrificial layer SF3, which is greater than that of the fourth sacrificial layer SF4.

[0110] This can be done by referring to... Figure 4A The etch rate of the first sacrificial layer SF1 to the fourth sacrificial layer SF4 is controlled by making various changes to conditions such as the concentration or type of impurities contained in each sacrificial layer, the silicon to nitrogen ratio, or the number of heat treatments, temperature, and duration.

[0111] Reference Figure 5B The sacrificial pillars CSP1 to CSP4 of the first cell can be removed. The space where the sacrificial pillars CSP1 to CSP4 of the first cell can be removed can be referred to as cell openings. Cell plugs CPL can then be formed in the cell openings. For example, the memory layer ML, the channel layer CH, and the die pillar CO can be sequentially formed on the side surfaces of the first preliminary stack pSTK1 to the fourth preliminary stack pSTK4 exposed through the cell openings.

[0112] Reference Figure 5C A hard mask HM and a thinning mask SM can be formed on the fourth preliminary stack pSTK4. The hard mask HM may include a mask opening MOP. For example... Figure 5B The (1-1) sacrificial pillars SFP1-1 to (1-3) sacrificial pillars SFP1-3 shown can be exposed through the mask opening MOP. Additionally, a portion of the upper surface of the fourth preliminary stack pSTK4 can be exposed through the mask opening MOP. The thinning mask SM can contact the upper surface of the hard mask HM. The thinning mask SM may include openings that expose the mask opening MOP of the hard mask HM.

[0113] Subsequently, sacrificial pillar SFP1-1 (1-1), sacrificial pillar SFP1-2 (1-2), and sacrificial pillar SFP1-3 (1-3) can be removed. Through the mask opening MOP, sacrificial pillar SFP1-3 (1-3), sacrificial pillar SFP1-2 (1-2), and sacrificial pillar SFP1-1 (1-1) can be etched sequentially. For example, sacrificial pillar SFP1-3 (1-3) can be removed to expose the upper surface of sacrificial pillar SFP1-2 (1-2) and the upper surface of the third preliminary stack pSTK3. Subsequently, sacrificial pillar SFP1-2 (1-2) can be removed.

[0114] The first preliminary opening POP1 corresponds to the space where sacrificial pillars SFP1-1 (1-1), SFP1-2 (1-2), and SFP1-3 (1-3) are removed. The first preliminary opening POP1 penetrates from the second preliminary laminate pSTK2 to the fourth preliminary laminate pSTK4. The first preliminary opening POP1 exposes the upper surface of the first preliminary laminate pSTK1. The second preliminary opening POP2 corresponds to the space where sacrificial pillars SFP1-2 (1-2) and SFP1-3 (1-3) are removed. The second preliminary opening POP2 penetrates the third preliminary laminate pSTK3 and the fourth preliminary laminate pSTK4. The second preliminary opening POP2 exposes the upper surface of the second preliminary laminate pSTK2. The third preliminary opening POP3 corresponds to the space where sacrificial pillar SFP1-3 (1-3) is removed. The third preliminary opening POP3 penetrates the fourth preliminary laminate pSTK4. The third preliminary opening POP3 can expose the upper surface of the third preliminary stack pSTK3.

[0115] Reference Figure 5D A portion of the first preliminary stack pSTK1 to the fourth preliminary stack pSTK4 exposed through the thinning mask SM and the hard mask HM can be etched. The portion of the first preliminary stack pSTK1 exposed through the mask opening MOP and the first preliminary opening POP1 can be removed to form the first opening OP1. Additionally, the portion of the second preliminary stack pSTK2 exposed through the mask opening MOP and the second preliminary opening POP2 can be removed to form the second opening OP2. Additionally, the portion of the third preliminary stack pSTK3 exposed through the mask opening MOP and the third preliminary opening POP3 can be removed to form the third opening OP3. Additionally, the portion of the fourth preliminary stack pSTK4 exposed through the mask opening MOP can be removed to form the fourth opening OP4. The first opening OP1 to the fourth opening OP4 may be spaced apart from each other in the X direction.

[0116] A first opening OP1 can extend in the Z direction from any one of the first sacrificial layers SF1. The first opening OP1 can expose the upper surface of any one of the first sacrificial layers SF1. Additionally, a second opening OP2 can extend in the Z direction from any one of the second sacrificial layers SF2. The second opening OP2 can expose the upper surface of any one of the second sacrificial layers SF2. Furthermore, a third opening OP3 can extend in the Z direction from any one of the third sacrificial layers SF3. The third opening OP3 can expose the upper surface of any one of the third sacrificial layers SF3. Finally, a fourth opening OP4 can extend in the Z direction from any one of the fourth sacrificial layers SF4. The fourth opening OP4 can expose the upper surface of any one of the fourth sacrificial layers SF4.

[0117] and Figure 5C In comparison, the first opening OP1 to the fourth opening OP4 can be etched to the same depth. For example, the first opening OP1 may have a depth corresponding to the depth of the second first sacrificial layer SF1 from the top of the first sacrificial layer SF1. Additionally, the second opening OP2 may have a depth corresponding to the depth of the second second sacrificial layer SF2 from the top of the second second sacrificial layer SF2. Furthermore, the third opening OP3 may have a depth corresponding to the depth of the second third sacrificial layer SF3 from the top of the third sacrificial layer SF3. Additionally, the fourth opening OP4 may have a depth corresponding to the depth of the second fourth sacrificial layer SF4 from the top of the fourth sacrificial layer SF4. That is, each of the first opening OP1 to the fourth opening OP4 can penetrate one of the first sacrificial layers SF1 to the fourth sacrificial layer SF4.

[0118] The etching processes of the first preliminary stack pSTK1 to the fourth preliminary stack pSTK4 can be performed simultaneously. For example, when performing an etching process using etching gas, each of the first preliminary stack pSTK1 to the fourth preliminary stack pSTK4 can be etched by etching gas passing through mask opening MOP and the first preliminary openings POP1 to the third preliminary openings POP3 to form the first opening OP1 to the fourth opening OP4. For the lower preliminary stacks, the time it takes for the etching gas to reach the target to be etched (e.g., the interlayer insulating layer and the sacrificial layer) can be longer. For example, the time it takes for the etching gas to reach the first preliminary stack pSTK1 can be longer than the time it takes for the etching gas to reach the fourth preliminary stack pSTK4. Therefore, when the first sacrificial layers SF1 to the fourth sacrificial layers SF4 have the same etching rate, the degree of etching in the lower preliminary stacks can be smaller. However, in this disclosure, because the etching rate of the sacrificial layers is faster towards the bottom, the preliminary stacks can be etched to the same depth even when the etching gas reaches the target to be etched at different times.

[0119] Reference Figure 5EThe thinning mask SM can be modified to further cover a portion of the hard mask HM. The modified thinning mask SM can expose some first openings OP1, some second openings OP2, some third openings OP3, and some fourth openings OP4. The remaining first openings OP1, remaining second openings OP2, remaining third openings OP3, and remaining fourth openings OP4 can be covered by the thinning mask SM.

[0120] Subsequently, a portion of the first preliminary laminate pSTK1 exposed through the first opening OP1 can be etched to form an extension of the first opening OP1′. Additionally, a portion of the second preliminary laminate pSTK2 exposed through the second opening OP2 can be etched to form an extension of the second opening OP2′. Furthermore, a portion of the third preliminary laminate pSTK3 exposed through the third opening OP3 can be etched to form an extension of the third opening OP3′. Finally, a portion of the fourth preliminary laminate pSTK4 exposed through the fourth opening OP4 can be etched to form an extension of the fourth opening OP4′.

[0121] The extensions from the first opening OP1' to the fourth opening OP4' can be formed with a depth greater than the length corresponding to a single sacrificial layer and a single interlayer insulation layer. For example, the extensions from the first opening OP1' to the fourth opening OP4' can have a depth corresponding to the depth of the third sacrificial layer from the top of the first sacrificial layer SF1 to the fourth sacrificial layer SF4. That is, each of the extensions from the first opening OP1' to the fourth opening OP4' can penetrate two layers of each of the first sacrificial layer SF1 to the fourth sacrificial layer SF4.

[0122] For example, regarding Figure 5D As described, the etching processes for the first preliminary stack pSTK1 to the fourth preliminary stack pSTK4 can be performed simultaneously. For example, when performing an etching process using etching gas, the time it takes for the etching gas to reach the first preliminary stack pSTK1 can be longer than the time it takes for the etching gas to reach the second preliminary stack pSTK2 to the fourth preliminary stack pSTK4. In this disclosure, because the etching rate of the sacrificial layer is faster towards the bottom, the preliminary stacks can be etched to the same amount or depth even when the arrival times of the etching gases are different.

[0123] Reference Figure 5F The thinning mask SM and the hard mask HM can be removed. Subsequently, a spacer layer SPL can be formed on the inner surfaces of the first opening OP1 to the fourth opening OP4 and extending from the first opening OP1′ to the fourth opening OP4′. Subsequently, a second sacrificial pillar SFP2 can be formed in the first opening OP1 to the fourth opening OP4 and extending from the first opening OP1′ to the fourth opening OP4′.

[0124] Reference Figure 5GThe first to fourth sacrificial layers SF1 to SF4 can be replaced by the first conductive layer CD1 to the fourth conductive layer CD4, respectively. The first conductive layer CD1 and the first interlayer insulating layer IL1 can form a first laminate STK1. The second conductive layer CD2 and the second interlayer insulating layer IL2 can form a second laminate STK2. The third conductive layer CD3 and the third interlayer insulating layer IL3 can form a third laminate STK3. The fourth conductive layer CD4 and the fourth interlayer insulating layer IL4 can form a fourth laminate STK4.

[0125] Subsequently, the second sacrificial pillar SFP2, extending from the first opening OP1' to the fourth opening OP4', and the first opening OP1 to the fourth opening OP4 can be removed. The second sacrificial pillar SFP2 can be removed to form the contact opening CTOP. Subsequently, the lower surface of the spacer layer SPL can be removed through the contact opening CTOP to form the spacer SP.

[0126] Reference Figure 5H This allows for the formation of contact points CT to fill contact openings CTOP. Each contact point CT can contact the first conductive layer CD1 through the fourth conductive layer CD4. Each contact point CT can be electrically connected to the first conductive layer CD1 through the fourth conductive layer CD4. Each contact point CT can be surrounded by a spacer SP. Therefore, each contact point CT is electrically connected to one conductive layer and electrically insulated from the other conductive layers.

[0127] According to this disclosure, as referenced Figure 5D and Figure 5E As described, openings (e.g., OP1 to OP4) for contacts (CTs) can be formed by forming first sacrificial layers SF1 to fourth sacrificial layers SF4 with different etch rates. Therefore, by controlling the etch rates of the first sacrificial layers SF1 to fourth sacrificial layers SF4, the quality of the contact CT can be improved, and the manufacturing process of the contact CT can be perfected.

[0128] Figures 4A to 4H This illustrates an embodiment of a memory device comprising two stacked layers (STK1 and STK2). Figures 5A to 5H An embodiment of a memory device comprising four stacks (STK1 to STK4) is shown. However, this disclosure is not limited thereto. For example, in some embodiments, the memory device may include three stacks or five or more stacks. These embodiments may also be included within the scope of this disclosure when the depth of the contact opening is adjusted by controlling the relative etch rate of the sacrificial layers included in the different stacks.

[0129] In addition, although Figures 4A to 4H and Figures 5A to 5HAn embodiment in which the etch rate of the sacrificial layer increases towards the bottom has been described, but this disclosure is not limited thereto. For example, when the memory device includes four stacks, the top two stacks may include sacrificial layers with different etch rates, and the bottom two stacks may include sacrificial layers with different etch rates. (Refer to below...) Figure 6A and Figure 6B as well as Figures 7A to 7D To describe the corresponding implementation method.

[0130] Figure 6A and Figure 6B This is a diagram illustrating a method for manufacturing contacts in a laminate according to another embodiment of this disclosure. Regarding... Figure 6A and Figure 6B Only describe with Figures 5A to 5H For differences, and for configurations not described in this article, please refer to the relevant documentation. Figure 5A and Figure 5H The description is as follows.

[0131] The first sacrificial layer SF1 may have a first etch rate, and the second sacrificial layer SF2 may have a second etch rate. Additionally, the third sacrificial layer SF3 may have a first etch rate, and the fourth sacrificial layer SF4 may have a second etch rate. The second etch rate may be lower than the first etch rate. That is, the first sacrificial layer SF1 and the third sacrificial layer SF3 may have faster etch rates, while the second sacrificial layer SF2 and the fourth sacrificial layer SF4 may have slower etch rates. For example, the etch rates of the first sacrificial layer SF1 to the fourth sacrificial layer SF4 can be defined as shown in Equation 2 below.

[0132] [Equation 2]

[0133] The etch rate of the first sacrificial layer (SF1) = the etch rate of the third sacrificial layer (SF3) > the etch rate of the second sacrificial layer (SF2) = the etch rate of the fourth sacrificial layer (SF4).

[0134] In another embodiment, the first sacrificial layer SF1 and the third sacrificial layer SF3 may have different etch rates, and the second sacrificial layer SF2 and the fourth sacrificial layer SF4 may have different etch rates. In other words, embodiments of this disclosure may include a first sacrificial layer SF1 with an etch rate faster than the second sacrificial layer SF2 and a third sacrificial layer SF3 with an etch rate faster than the fourth sacrificial layer SF4.

[0135] Reference Figure 6AOpenings can be formed in the third preliminary stack pSTK3 and the fourth preliminary stack pSTK4. When the (1-1) sacrificial column SFP1-1, the (1-2) sacrificial column SFP1-2 and the (1-3) sacrificial column SFP1-3 are retained, a fourth opening OP4 and an extended fourth opening OP4′ connected to the fourth sacrificial layer SF4, and a third opening OP3 and an extended third opening OP3′ connected to the third sacrificial layer SF3 can be formed.

[0136] Reference Figure 6B The (1-1) sacrificial pillar SFP1-1, the (1-2) sacrificial pillar SFP1-2, and the (1-3) sacrificial pillar SFP1-3 can be removed, and a second opening OP2 and an extended second opening OP2′ connected to the second sacrificial layer SF2, and a first opening OP1 and an extended first opening OP1′ connected to the first sacrificial layer SF1 can then be executed. Figures 5F to 5H The process described.

[0137] That is, as referred to above Figure 6A and Figure 6B As described, openings corresponding to the two upper stacks (e.g., OP3, OP3′, OP4 and OP4′) can be formed first, and then openings corresponding to the two lower stacks (e.g., OP1, OP1′, OP2 and OP2′) can be formed.

[0138] Figures 7A to 7D This is a diagram illustrating a method of manufacturing contacts in a laminate according to another embodiment of this disclosure. Figures 7A to 7D In the text, only descriptions of... Figures 5A to 5H as well as Figure 6A and Figure 6B The differences are as follows. Additionally, for configurations not described, please refer to... Figures 5A to 5H as well as Figure 6A and Figure 6B .

[0139] For reference Figure 6A and Figure 6B As described, the first sacrificial layer SF1 can have a faster etch rate than the second sacrificial layer SF2. Figures 7A to 7D In this process, openings can be formed in the first preliminary laminate pSTK1 and the second preliminary laminate pSTK2 before the third preliminary laminate pSTK3 is formed.

[0140] Reference Figure 7A This can form a preliminary opening POP that penetrates the second preliminary laminate pSTK2. The preliminary opening POP can expose a portion of the upper surface of the first preliminary laminate pSTK1.

[0141] Reference Figure 7BA first lower opening LOP1 and an extended first lower opening LOP1′ can be formed, each connected to the first sacrificial layer SF1. Additionally, a second lower opening LOP2 and an extended second lower opening LOP2′ can be formed, each connected to the second sacrificial layer SF2. That is, an etching process can be performed such that the openings are connected to the first sacrificial layer SF1 and the second sacrificial layer SF2 before the formation of the third preliminary stack pSTK3.

[0142] Reference Figure 7C The (1-1) sacrificial column SFP1-1′ can be formed in the first lower opening LOP1, the extended first lower opening LOP1′, the second lower opening LOP2, and the extended second lower opening LOP2′.

[0143] Subsequently, a third preliminary stack pSTK3 and (1-2) sacrificial pillars SFP1-2 can be formed. Then, a fourth preliminary stack pSTK4 and (1-3) sacrificial pillars SFP1-3 can be formed. Subsequently, the element sacrificial pillars (e.g., CSP1 and CSP2) can be removed and element plugs (CPLs) can be formed.

[0144] Reference Figure 7D It can form a fourth opening OP4 and an extended fourth opening OP4′ connected to the fourth sacrificial layer SF4, and a third opening OP3 and an extended third opening OP3′ connected to the third sacrificial layer SF3.

[0145] Subsequently, the (1-1) sacrificial column SFP1-1′, the (1-2) sacrificial column SFP1-2 and the (1-3) sacrificial column SFP1-3 can be removed to form the first opening OP1, the extended first opening OP1′, the second opening OP2 and the extended second opening OP2′.

[0146] In other words, refer to Figures 7A to 7D It is possible to first form openings corresponding to the two lower stacks (e.g., OP1, OP1′, OP2 and OP2′), and then form openings corresponding to the two upper stacks (e.g., OP3, OP3′, OP4 and OP4′).

[0147] Figure 8 This is a diagram illustrating a memory card system 3000 using a memory device according to an embodiment of the present disclosure.

[0148] Reference Figure 8 The memory card system 3000 may include a controller 3100, a memory device 3200, and a connector 3300.

[0149] Controller 3100 may be coupled to memory device 3200. Controller 3100 may be configured to access memory device 3200. For example, controller 3100 may control programming operations, read operations, erase operations, or background operations of memory device 3200. Controller 3100 may be configured to provide an interface between memory device 3200 and a host. Controller 3100 may be configured to drive firmware for controlling memory device 3200. For example, controller 3100 may include components such as random access memory (RAM), processing unit, host interface, memory interface, and error corrector.

[0150] Controller 3100 can communicate with external devices via connector 3300. Controller 3100 can communicate with external devices (e.g., a host) according to a specific communication protocol. For example, controller 3100 can be configured to communicate with external devices via at least one of various communication protocols such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe. For example, connector 3300 can be defined by at least one of the aforementioned communication protocols.

[0151] The memory device 3200 may include a plurality of memory cells and can be configured according to... Figure 1 The memory device 100 shown is configured in the same manner.

[0152] The controller 3100 and memory device 3200 can be integrated into a single semiconductor device to form a memory card. For example, the controller 3100 and memory device 3200 can form memory cards such as personal computer (PC) cards (PCMCIA International Association) cards, compact flash memory (CF) cards, smart media cards (SM and SMC), memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro or eMMC), SD cards (SD, miniSD, microSD or SDHC) and universal flash memory (UFS).

[0153] Figure 9 This is a diagram illustrating a solid-state drive (SSD) system 4000 to which an embodiment of the memory device according to the present disclosure is applied.

[0154] Reference Figure 9The SSD system 4000 may include a host 4100 and an SSD 4200. The SSD 4200 may exchange signals with the host 4100 via a signal connector 4001 and may receive power via a power connector 4002. The SSD 4200 may include a controller 4210, a plurality of memory devices 4221 to 422n, an auxiliary power supply 4230, and a cache memory 4240.

[0155] Controller 4210 may control a plurality of memory devices 4221 to 422n in response to signals received from host 4100. For example, the signals may be based on the interface between host 4100 and SSD 4200. For example, the signals may be defined by at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe.

[0156] The plurality of memory devices 4221 to 422n may include a plurality of memory cells configured to store data. Each of the plurality of memory devices 4221 to 422n may be configured in accordance with... Figure 1 The memory device 100 shown is configured in the same manner. Multiple memory devices 4221 to 422n can communicate with the controller 4210 via channels CH1 to CHn.

[0157] Auxiliary power supply 4230 can be connected to host 4100 via power connector 4002. Auxiliary power supply 4230 can receive and charge power from host 4100. When the power supply from host 4100 is unreliable, auxiliary power supply 4230 can provide power to SSD 4200. For example, auxiliary power supply 4230 can be inside or outside SSD 4200. For example, auxiliary power supply 4230 can be on the motherboard and provide auxiliary power to SSD 4200.

[0158] Buffer memory 4240 can be used as a buffer memory for SSD 4200. For example, buffer memory 4240 can temporarily store data received from host 4100 or data received from multiple memory devices 4221 to 422n, or it can temporarily store metadata (e.g., mapping tables) of memory devices 4221 to 422n. Buffer memory 4240 can include volatile memory such as DRAM, SDRAM, DDR SDRAM and LPDDR SDRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM and PRAM.

[0159] According to embodiments of this disclosure, by controlling the etching rate of the sacrificial layer that is alternately stacked with the interlayer insulating layer, the quality of the contact can be improved, and the manufacturing process of the contact can be perfected.

[0160] It will be apparent to those skilled in the art that various modifications may be made to the above embodiments of this teaching without departing from the spirit or scope of this disclosure. Therefore, this teaching is intended to cover all such modifications, provided they fall within the scope of the appended claims and their equivalents.

[0161] Cross-references to related applications

[0162] This application claims priority to Korean Patent Application No. 10-2024-0142985, filed with the Korean Intellectual Property Office on October 18, 2024, the full disclosure of which is incorporated herein by reference.

Claims

1. A method for manufacturing a memory device, the method comprising the following steps: A lower laminate is formed, the lower laminate comprising a first interlayer insulating layer and a first sacrificial layer alternately stacked on top of each other in a first direction; An upper stack is formed over the lower stack in the first direction, wherein the upper stack includes a second interlayer insulating layer and a second sacrificial layer that are alternately stacked with each other in the first direction, the etch rate of the second sacrificial layer being lower than the etch rate of the first sacrificial layer; A preliminary opening is formed that penetrates the upper stack and exposes the upper surface of the lower stack; as well as A first opening extending in the first direction from one of the first sacrificial layers and a second opening extending in the first direction from one of the second sacrificial layers are formed by simultaneously etching a portion of the lower stack exposed through the initial opening and a portion of the upper stack spaced apart from the initial opening.

2. The method according to claim 1, wherein, During the formation of the lower stack and the formation of the upper stack The second sacrificial layer has a higher concentration of impurities than the first sacrificial layer.

3. The method according to claim 2, wherein, The impurities include carbon.

4. The method according to claim 1, wherein, During the formation of the lower stack and the formation of the upper stack The first sacrificial layer and the second sacrificial layer each comprise nitrogen (N) and silicon (Si), and The proportion of Si included in the second sacrificial layer is higher than the proportion of Si included in the first sacrificial layer.

5. The method according to claim 1, further comprising the following steps: After the upper stack is formed, a first sacrificial column is formed through the upper stack.

6. The method according to claim 5, wherein, The step of forming the initial opening includes the following steps: removing the first sacrificial column.

7. The method according to claim 1, wherein, When forming the first opening and the second opening The height of the area of ​​the first opening other than the initial opening corresponds to the height of the second opening.

8. The method according to claim 1, further comprising the following steps: After the first opening and the second opening are formed A third opening extending beyond the first opening to a first length is formed by simultaneously etching a portion of the lower stack exposed through the first opening and a portion of the upper stack exposed through the second opening, and a fourth opening extending beyond the second opening to the first length is also formed.

9. The method according to claim 1, further comprising the following steps: After forming the first opening and the second opening A spacer layer is formed on the inner surface of the first opening and the inner surface of the second opening; A second sacrificial pillar is formed, each surrounded by the spacer layer; The first sacrificial layer and the second sacrificial layer are replaced with a conductive layer; Remove the second sacrificial column; Spacers are formed by etching the lower ends of the spacer layer to expose portions of the conductive layer. as well as Contacts are formed that are respectively in contact with the conductive layer and are respectively surrounded by the spacers.

10. The method according to claim 1, further comprising the step of: After the lower stack is formed, a first unit sacrificial column is formed that penetrates the lower stack.

11. The method of claim 10, further comprising the step of: After the upper layer is formed A second unit sacrificial column is formed that penetrates the upper stack and overlaps with the first unit sacrificial column; A cell opening penetrating each of the lower and upper stacks is formed by removing the first and second unit sacrificial pillars. as well as A unit plug is formed in the unit opening.

12. A method of manufacturing a memory device, the method comprising the following steps: A first stack is formed comprising a first interlayer insulating layer and a first sacrificial layer that are alternately stacked on top of each other, the first sacrificial layer having a first etch rate; A second stack is formed on top of the first stack, wherein the second stack includes a second interlayer insulating layer and a second sacrificial layer that are alternately stacked on top of each other, the second sacrificial layer having a second etch rate lower than the first etch rate; Forming a first sacrificial column that penetrates the second layer; An initial opening is formed by removing the first sacrificial column; First openings are formed by etching a portion of the first stack through the initial opening to penetrate a first number of the first sacrificial layers; Second openings penetrating the first number of second sacrificial layers are formed by etching a portion of the second stack spaced apart from the initial opening; and Contacts are formed in the first opening and the second opening.

13. The method of claim 12, further comprising the step of: After the first sacrificial column is formed A third stack is formed above the second stack, wherein the third stack includes a third interlayer insulating layer and a third sacrificial layer alternately stacked on top of each other, the third sacrificial layer having a third etch rate; and A second sacrificial column is formed through the third stack. Wherein, the third etching rate is lower than the first etching rate and the second etching rate; and In this case, one or more of the second sacrificial pillars overlap with the first sacrificial pillar.

14. The method according to claim 13, wherein, The step of forming the initial opening by removing the first sacrificial column includes the following steps: Remove the second sacrificial post to expose a portion of the upper surface of the first sacrificial post and the second laminate; and Remove the first sacrificial column that was exposed. The initial opening includes the space left after the first and second sacrificial pillars are removed.

15. The method according to claim 14, wherein, When the second opening is formed The second opening is formed by etching a portion of the second laminate through the initial opening.

16. The method of claim 13, further comprising the step of: A third opening penetrating the first number of third sacrificial layers is formed by etching a portion of the third stack that is spaced apart from the initial opening.

17. The method according to claim 12, wherein, The steps of forming the first opening and forming the second opening are performed simultaneously.

18. The method of claim 12, further comprising the step of: After forming the first opening and the second opening An extended first opening penetrating a second number of the first sacrificial layers is formed by simultaneously etching the portion of the first stack exposed through the first opening and the portion of the second stack exposed through the second opening, wherein the second number is greater than the first number.

19. A memory device comprising: A first unit stack includes a first conductive layer and a first interlayer insulating layer that are alternately stacked on top of each other; The second unit stack includes a second conductive layer and a second interlayer insulating layer that are alternately stacked on top of the first unit stack. A unit plug extending through the first unit stack and the second unit stack; A first contact point extends vertically from one of the first conductive layers, wherein the first contact point is surrounded by the second conductive layer; A second contact point extends from one of the second conductive layers in the vertical direction; A first dummy stack, the first dummy stack being horizontal in the first unit stack and comprising alternating layers of a first interlayer insulating layer and a first sacrificial layer; and The second dummy stack, which is horizontal in the second unit stack and includes a second interlayer insulating layer and a second sacrificial layer alternately stacked on top of each other, The etching rate of the second sacrificial layer is lower than that of the first sacrificial layer.

20. The memory device of claim 19, further comprising peripheral circuit contacts extending through the first dummy stack and the second dummy stack.

21. The memory device according to claim 19, wherein, The first contact penetrates the second conductive layer and the second interlayer insulating layer.

22. The memory device of claim 19, further comprising a first spacer disposed between the first contact and the second cell stack.

23. The memory device according to claim 19, wherein, The length of each of the first conductive layers in the horizontal direction is substantially the same as the length of each of the second conductive layers in the horizontal direction.

24. The memory device of claim 19, wherein, The concentration of impurities in the second sacrificial layer is greater than the concentration of impurities in the first sacrificial layer.

25. The memory device according to claim 24, wherein, The impurities include carbon.

26. The memory device according to claim 19, wherein, Each of the first sacrificial layer and the second sacrificial layer comprises nitrogen and silicon, and the silicon content in the second sacrificial layer is higher than the silicon content in the first sacrificial layer.

27. The memory device according to claim 19, wherein, The first contact is disposed in the first opening, and the second contact is disposed in the second opening. The lower part of the first opening and the lower part of the second opening are formed by a single etching process.

28. A memory device comprising: A first unit stack includes a first conductive layer and a first interlayer insulating layer that are alternately stacked on top of each other; The second unit stack includes a second conductive layer and a second interlayer insulating layer that are alternately stacked on top of the first unit stack. A unit plug extending through the first unit stack and the second unit stack; A first contact point extends vertically from one of the first conductive layers; A second contact point extends from one of the second conductive layers in the vertical direction; A first dummy stack, which is in the horizontal direction of the first unit stack and includes a first interlayer insulating layer and a first sacrificial layer that are alternately stacked on top of each other; as well as The second dummy stack, which is horizontal in the second unit stack and includes a second interlayer insulating layer and a second sacrificial layer alternately stacked on top of each other, The concentration of impurities in the second sacrificial layer is greater than the concentration of impurities in the first sacrificial layer.

29. The memory device according to claim 28, wherein, The impurities include carbon.

30. The memory device according to claim 28, wherein, The etch rate of the second sacrificial layer is lower than that of the first sacrificial layer.

31. The memory device according to claim 28, wherein, The first contact is surrounded by the second conductive layer.

32. The memory device according to claim 28, wherein, The first contact is disposed in the first opening, and the second contact is disposed in the second opening. The lower part of the first opening and the lower part of the second opening are formed by a single etching process.

33. A memory device comprising: A first unit stack includes a first conductive layer and a first interlayer insulating layer that are alternately stacked on top of each other; The second unit stack includes a second conductive layer and a second interlayer insulating layer that are alternately stacked on top of the first unit stack. A unit plug extending through the first unit stack and the second unit stack; A first contact point extends vertically from one of the first conductive layers; A second contact point extends from one of the second conductive layers in the vertical direction; A first dummy stack, which is in the horizontal direction of the first unit stack and includes a first interlayer insulating layer and a first sacrificial layer that are alternately stacked on top of each other; as well as The second dummy stack, which is horizontal in the second unit stack and includes a second interlayer insulating layer and a second sacrificial layer alternately stacked on top of each other, Each of the first sacrificial layer and the second sacrificial layer comprises nitrogen and silicon, and The silicon content in the second sacrificial layer is higher than that in the first sacrificial layer.

34. The memory device according to claim 33, wherein, The etch rate of the second sacrificial layer is lower than that of the first sacrificial layer.

35. The memory device according to claim 33, wherein, The first contact is surrounded by the second conductive layer.

36. The memory device according to claim 33, wherein, The first contact is disposed in the first opening, and the second contact is disposed in the second opening. The lower part of the first opening and the lower part of the second opening are formed by a single etching process.

37. A memory device comprising: A first unit stack includes a first conductive layer and a first interlayer insulating layer that are alternately stacked on top of each other; The second unit stack includes a second conductive layer and a second interlayer insulating layer that are alternately stacked on top of the first unit stack. A unit plug extending through the first unit stack and the second unit stack; A first contact is disposed in a first opening and extends vertically from one of the first conductive layers; as well as A second contact is disposed in the second opening and extends from one of the second conductive layers in the vertical direction. The lower part of the first opening and the lower part of the second opening are formed by a single etching process.

38. The memory device according to claim 37, wherein, The first contact is surrounded by the second conductive layer.

39. The memory device of claim 37, further comprising a first spacer disposed between the first contact and the second cell stack.

40. The memory device of claim 37, wherein, The length of each of the first conductive layers in the horizontal direction is substantially the same as the length of each of the second conductive layers in the horizontal direction.

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