Heterojunction-integrated super-junction groove type 4H-SiC MOSFET (Metal Oxide Semiconductor Field Effect Transistor)

Abstract

The invention discloses a super-junction groove type 4H-SiC MOSFET integrated with a heterojunction, and belongs to the technical field of semiconductor power chips. The device is composed of drain metal, an N + substrate region, an N-drift region, a P-super junction region, a P + polysilicon gate, an N-polysilicon region, an N-body region, an N + polysilicon source region, an N + body source region, source metal, a source trench, a gate trench and a P + separation gate. A heterojunction structure with a low potential barrier is introduced into the device, current does not flow through the body diode when the device works reversely, and the bipolar degradation effect existing when the device works in a third quadrant is effectively eliminated. In order to optimize the performance of the device, an accumulation type conducting channel is further designed, the accumulation type conducting channel conducts electricity by means of majority carriers, scattering of the carriers is little, the mobility is increased, the switching speed of the device is effectively improved, and the on-resistance of the device is reduced. In addition, the device is excellent in reliability and breakdown characteristic.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power chip technology, specifically relating to a superjunction trench 4H-SiC MOSFET with integrated heterojunction. Background Technology

[0002] As a wide bandgap semiconductor material, 4H-SiC exhibits higher thermal conductivity, critical breakdown field strength, and electron saturation velocity compared to traditional Si materials. Therefore, 4H-SiC MOSFETs (metal-oxide-semiconductor field-effect transistors) possess advantages such as good thermal stability, low on-resistance, and fast switching speed, making them a rapidly developing power semiconductor device. For example... Figure 2 As shown, traditional trench-gate MOSFETs (UMOSFETs) suffer from bipolar degradation when operating in the third quadrant, leading to performance degradation and increased reverse power dissipation. To suppress this bipolar degradation effect, researchers have proposed a 4H-SiC MOSFET structure integrating a Schottky diode (SBD). However, integrating the SBD causes metallization contamination of the gate oxide layer, resulting in a series of reliability issues such as unstable threshold voltage and gate oxide layer breakdown. Furthermore, integrated SBDs are prone to tunneling, resulting in relatively large reverse leakage current in blocking mode. These problems severely limit the application of power SiC MOSFETs in manufacturing. Summary of the Invention

[0003] The purpose of this invention is to provide a superjunction trench 4H-SiC MOSFET with integrated heterojunction to solve the bipolar degradation problem of trench 4H-SiC MOSFET.

[0004] This invention introduces a heterojunction structure with a low potential barrier into a 4H-SiC MOSFET. Since the heterojunction barrier is significantly lower than the body diode barrier, current no longer flows through the body diode during reverse operation, effectively eliminating the bipolar degradation effect. To optimize device performance, this invention also designs an accumulation-type conductive channel. Compared to traditional inversion layer channels, the accumulation-type conductive channel relies on majority carriers for conduction, resulting in less carrier scattering and increased mobility, effectively improving the switching speed and reducing the on-resistance. Furthermore, this device also exhibits excellent reliability and breakdown characteristics.

[0005] like Figure 1 As shown, the present invention discloses an integrated heterojunction superjunction trench 4H-SiC MOSFET, which integrates a heterojunction with a low potential barrier in a superjunction trench 4H-SiC MOSFET. The device consists of a drain metal (1), N... + Substrate region (2), N - Drift zone (3), P - Superjunction region (4), P+ Polysilicon gate (5), N - Polycrystalline silicon region (6), N - body area (7), N + Polycrystalline silicon source region (8), N + Body source region (9), source metal (10), source trench (11-1), gate trench (11-2) and P + The separation gate (12) is composed of N + The substrate region (2) is located above the drain metal (1), N - The drift region (3) is located in N + Above the substrate region (2), P - The superjunction region (4) is located in N - N is located to the upper left of the drift area (3). - Polycrystalline silicon region (6) and N - The body region (7) is located in N - Above the drift region (3), the source trench (11-1) is located at P - The gate trench (11-2) is located to the upper left of the superjunction region (4) and is situated in the N region. - P is located to the upper right of the drift zone (3). + The polysilicon gate (5) is located to the upper right of the gate trench (11-2); N + The polycrystalline silicon source region (8) is located in N - Above the polycrystalline silicon region (6), N + The body source region (9) is located in N - Above the body region (7); source trench (11-1), P - Superjunction region (4), N + Polycrystalline silicon source region (8) and N + The upper surface of the body source region (9) is flat, and the source metal (10) is located in the source trench (11-1), P - Superjunction region (4), N + Polycrystalline silicon source region (8) and N + Above the body source region (9); gate trench (11-2) and P + The upper surface of the polysilicon gate (5) is flush with the upper surface of the source metal (10); P + The separation gate (12) is located within the gate trench (11-2) and is located at P + The lower right side of the polysilicon gate (5);

[0006] Preferably, the drain metal (1) is Al with a thickness of 50~100 nm;

[0007] Preferably, the N +The substrate region (2) is N-type heavily doped 4H-SiC, with nitrogen or phosphorus as the doping element and a doping concentration of 1×10⁻⁶. 19 cm -3 ~1×10 20 cm -3 ;

[0008] Preferably, the N - The drift region (3) is N-type lightly doped 4H-SiC, with nitrogen or phosphorus as the doping element and a doping concentration of 5 × 10⁻⁶. 15 cm -3 ~7×10 15 cm -3 The thickness is 8~15 μm;

[0009] Preferably, the P - The superjunction region (4) is a lightly doped P-type 4H-SiC, with aluminum or boron as the doping element and a doping concentration of 5 × 10⁻⁶. 16 cm -3 ~5×10 17 cm -3 The thickness is 5.0~6.5 μm;

[0010] Preferably, the N - The polycrystalline silicon region (6) is N-type lightly doped polycrystalline silicon, with phosphorus as the doping element and a doping concentration of 5 × 10⁻⁶. 15 cm -3 ~5×10 16 cm -3 The thickness is 0.5~1.5 μm and the width is 0.3~0.5 μm;

[0011] Preferably, the N - The body region (7) is lightly doped N-type 4H-SiC, with nitrogen or phosphorus as the doping element and a doping concentration of 1×10⁻⁶. 14 cm -3 ~1×10 15 cm -3 The thickness is 0.5~1.5 μm and the width is 0.3~0.5 μm;

[0012] Preferably, the N + The polycrystalline silicon source region (8) is N-type heavily doped polycrystalline silicon, with phosphorus as the doping element and a doping concentration of 1×10⁻⁶. 19 cm -3 ~1×10 20 cm -3 The thickness is 0.15~0.25 μm and the width is 0.3~0.5 μm;

[0013] Preferably, the N +The body source region (9) is N-type heavily doped 4H-SiC, with nitrogen or phosphorus as the doping element and a doping concentration of 1×10⁻⁶. 19 cm -3 ~1×10 20 cm -3 The thickness is 0.15~0.25 μm and the width is 0.3~0.5 μm;

[0014] Preferably, the source metal (10) is Al, and its thickness is 50~100 nm;

[0015] Preferably, the source trench (11-1) is made of SiO2 and has a thickness of 4.8~6.3 μm;

[0016] Preferably, the gate trench (11-2) is made of SiO2 and has a thickness of 2.5~3.0 μm;

[0017] Preferably, the P + The polysilicon gate (5) is a P-type heavily doped polysilicon, with aluminum or boron as the doping element and a doping concentration of 1×10⁻⁶. 19 cm -3 ~1×10 20 cm -3 The thickness is 2~2.5 μm;

[0018] Preferably, the P + The separation gate (12) is a P-type heavily doped polysilicon, with aluminum or boron as the doping element and a doping concentration of 1×10⁻⁶. 19 cm -3 ~1×10 20 cm -3 The thickness is 0.15~0.25 μm.

[0019] The present invention has the following beneficial effects:

[0020] This invention proposes an integrated heterojunction superjunction trench SiC MOSFET. When this SiC MOSFET operates in the first quadrant, due to the presence of the accumulation channel, the conductive channel relies on majority carriers for conduction, resulting in less carrier scattering and increased mobility, effectively improving the device's switching speed and optimizing its on-resistance. The grounded split gate structure reduces the coupling effect between the gate and drain, and also distributes most of the gate-drain capacitance C. GD Converted to gate-source capacitance C GS Significantly reduced C GDThe switching speed is improved; when the device operates in the third quadrant, due to the presence of the heterojunction with a low barrier, the heterojunction barrier is significantly lower than the body diode barrier, and the current no longer flows through the body diode, effectively eliminating the bipolar degradation effect that exists when the device operates in the third quadrant; in addition, the device also performs well in terms of reliability and breakdown characteristics. Attached Figure Description

[0021] Figure 1 This is a schematic cross-sectional view of the integrated heterojunction superjunction trench 4H-SiC MOSFET proposed in this invention.

[0022] Figure 2 This is a schematic diagram of the cross-sectional structure of a traditional superjunction trench 4H-SiC MOSFET;

[0023] Figure 3 The output characteristic curves of the superjunction trench 4H-SiC MOSFET with integrated heterojunction proposed in this invention and the conventional superjunction trench 4H-SiC MOSFET are shown.

[0024] Figure 4 These are the transfer characteristic curves of the superjunction trench 4H-SiC MOSFET with integrated heterojunction proposed in this invention and the conventional superjunction trench 4H-SiC MOSFET;

[0025] Figure 5 This is the current flow path diagram of the integrated heterojunction superjunction trench 4H-SiC MOSFET proposed in this invention;

[0026] Figure 6 This is a current flow path diagram of a traditional superjunction trench 4H-SiC MOSFET.

[0027] Figure 1 and Figure 2 The names of the components are: drain metal (1), N + Substrate region (2), N - Drift zone (3), P - Superjunction region (4), P + Polysilicon gate (5), N - Polycrystalline silicon region (6), N - body area (7), N + Polycrystalline silicon source region (8), N + Body source region (9), source metal (10), source trench (11-1), gate trench (11-2), P + Separation gate (12), P - Body region (13, P-type doped, doping concentration 1×10⁻⁶) 17 cm -3 (thickness 1.0 μm).

[0028] like Figure 2 As shown, a traditional superjunction trench 4H-SiC MOSFET consists of a drain metal (1), an N-type electrode (2), and a core. + Substrate region (2), N - Drift zone (3), P - Superjunction region (4), P + Polysilicon gate (5), N + Body source region (9), source metal (10), source trench (11-1), gate trench (11-2) and P - The body region (13) is composed of N. + The substrate region (2) is located above the drain metal (1), N - The drift region (3) is located in N + Above the substrate region (2), P - The body region (13) is located in N - Above the drift zone (3), P - The superjunction region (4) is located in N - The source trench (11-1) is located to the upper left of the drift region (3) at P. - The gate trench (11-2) is located to the upper left of the superjunction region (4) and is situated in the N region. - P is located to the upper right of the drift zone (3). + The polysilicon gate (5) is located to the upper right of the gate trench (11-2); P - Superjunction (4) and P - The upper surface of the body region (13) is flat, N + The body source region (9) is located in P - Superjunction (4) and P - Above the body region (13); source trench (11-1) and N + The upper surface of the body source region (9) is flat, and the source metal (10) is located between the source trench (11-1) and N. + Above the body source region (9); gate trench (11-2), P + The upper surfaces of the polysilicon gate (5) and the source metal (10) are flat;

[0029] like Figure 3 As shown, this curve represents the gate voltage V. G At 5V, the relationship between drain current and drain voltage was obtained by simulation using TCAD software. The horizontal axis represents drain voltage and the vertical axis represents drain current. The scan step size of drain voltage is 0.2V.

[0030] like Figure 4 As shown, the curve represents the drain voltage V. DAt 10V, the relationship between drain current and gate voltage was simulated using TCAD software. The horizontal axis represents gate voltage, and the vertical axis represents drain current. The scan step size of the gate voltage is 0.2V.

[0031] like Figure 5 As shown in the left figure, the data represents the total current density, with the magnitude indicated by color, from largest to smallest: red → yellow → green → blue → purple. The current mainly passes through N. + Polycrystalline silicon source region (8), N - Polycrystalline silicon region (6), N - Drift zone (3); The right figure is an enlarged view of the lower left corner area;

[0032] like Figure 6 As shown in the left figure, the data represents the total current density, with the magnitude indicated by color, from largest to smallest: red → yellow → green → blue → purple. The current mainly passes through N. + body source region (9), P - body area (13), N - Drift zone (3), and P - Superjunction region (4) and N - The drift region (3) forms a bulk PN junction; the right figure is an enlarged view of the lower left corner of the left figure. Detailed Implementation

[0033] To make the objectives, technical solutions, and effects of this invention clearer, the technical solutions of this invention are described in detail below with reference to specific examples. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this invention.

[0034] Example 1:

[0035] The device consists of drain metal (1) and N + Substrate region (2), N - Drift zone (3), P - Superjunction region (4), P + Polysilicon gate (5), N - Polycrystalline silicon region (6), N - body area (7), N + Polycrystalline silicon source region (8), N + Body source region (9), source metal (10), source trench (11-1), gate trench (11-2) and P + The separation gate (12) is composed of N + The substrate region (2) is located above the drain metal (1), N - The drift region (3) is located in N + Above the substrate region (2), P - The superjunction region (4) is located in N- N is located to the upper left of the drift area (3). - Polycrystalline silicon region (6) and N - The body region (7) is located in N - Above the drift region (3), the source trench (11-1) is located at P - The gate trench (11-2) is located to the upper left of the superjunction region (4) and is situated in the N region. - P is located to the upper right of the drift zone (3). + The polysilicon gate (5) is located to the upper right of the gate trench (11-2); N + The polycrystalline silicon source region (8) is located in N - Above the polycrystalline silicon region (6), N + The body source region (9) is located in N - Above the body region (7); source trench (11-1), P - Superjunction region (4), N + Polycrystalline silicon source region (8) and N + The upper surface of the body source region (9) is flat, and the source metal (10) is located in the source trench (11-1), P - Superjunction region (4), N + Polycrystalline silicon source region (8) and N + Above the body source region (9); gate trench (11-2) and P + The upper surface of the polysilicon gate (5) is flush with the upper surface of the source metal (10); P + The separation gate (12) is located within the gate trench (11-2) and is located at P + The lower right side of the polysilicon gate (5);

[0036] The drain metal (1) is Al with a thickness of 50 nm;

[0037] The N + Substrate region (2) is N-type heavily doped 4H-SiC, with phosphorus as the doping element and a doping concentration of 1×10⁻⁶. 20 cm -3 The thickness is 2 μm;

[0038] The N - The drift region (3) is N-type lightly doped 4H-SiC, with phosphorus as the doping element and a doping concentration of 6.5 × 10⁻⁶. 15 cm -3 The thickness is 12 μm;

[0039] The P - The superjunction region (4) is a lightly doped P-type 4H-SiC with boron as the doping element and a doping concentration of 1×10⁻⁶. 17 cm -3The thickness is 6.0 μm;

[0040] The N - The polycrystalline silicon region (6) is N-type lightly doped polycrystalline silicon, with phosphorus as the doping element and a doping concentration of 1×10⁻⁶. 16 cm -3 It has a thickness of 1.0 μm and a width of 0.4 μm;

[0041] The N - The body region (7) is N-type lightly doped 4H-SiC, with phosphorus as the doping element and a doping concentration of 1×10⁻⁶. 15 cm -3 It has a thickness of 1.0 μm and a width of 0.4 μm;

[0042] The N + The polycrystalline silicon source region (8) is N-type heavily doped polycrystalline silicon, with phosphorus as the doping element and a doping concentration of 1×10⁻⁶. 20 cm -3 It has a thickness of 0.2 μm and a width of 0.4 μm;

[0043] The N + The body source region (9) is N-type heavily doped 4H-SiC, with phosphorus as the dopant element and a doping concentration of 1×10⁻⁶. 20 cm -3 It has a thickness of 0.2 μm and a width of 0.4 μm;

[0044] Preferably, the source metal (10) is Al with a thickness of 100 nm;

[0045] The source trench (11-1) is made of SiO2 and has a thickness of 6.0 μm;

[0046] The gate trench (11-2) is made of SiO2 and has a thickness of 2.5 μm;

[0047] The P + The polysilicon gate (5) is a P-type heavily doped polysilicon, with boron as the doping element and a doping concentration of 1×10⁻⁶. 20 cm -3 The thickness is 2.0 μm;

[0048] The P + The separation gate (12) is a P-type heavily doped polysilicon, with boron as the doping element and a doping concentration of 1×10⁻⁶. 20 cm -3 The thickness is 0.2 μm.

[0049] When a gate voltage V is applied to the device G=5V, when a scanning positive voltage with a step size of 0.2V is applied to the drain metal (1), the device operates in the first quadrant. For conventional superjunction trench type 4H-SiC MOSEFT (such as Figure 2 ), electrons from N + The body source region (9) is emitted, and after passing through P... - The inversion layer channel is adjacent to the gate trench (11-2) on the right side of the body region (13), and then flows through N - Drift zone (3), N + The substrate region (2) eventually enters the drain metal (1), forming a positive current pointing from the drain metal (1) to the source metal (10); for the integrated heterojunction superjunction trench 4H-SiC MOSFET structure described in this invention (such as... Figure 1 ), electrons from N + The polycrystalline silicon source region (8) emits, after passing through N + body source region (9), reaching N - The accumulation layer channel is adjacent to the gate trench (11-2) on the right side of the body region (7), and then flows through N - Drift zone (3), N + The substrate region (2) eventually enters the drain metal (1), forming a forward current from the drain metal (1) to the source metal (10). Figure 3 As can be observed from the output curves, the on-resistance of the present invention, represented by the black curve, is significantly lower than that of the conventional structure, represented by the red curve. This can be explained at the device level by N... - The accumulation layer conductive channel in the body region (7) conducts electricity using majority carriers, resulting in less carrier scattering and increased mobility. This effectively improves the switching speed of the device and reduces its on-resistance by 1.61 mΩ∙cm. 2 (like Figure 3 ).

[0050] When a scanning negative voltage with a step size of 0.2V is applied to the drain metal (1), the device operates in the third quadrant. In the traditional superjunction trench 4H-SiC MOSFET structure, P - Superjunction region (4), P - body region (13) and N - The bulk PN junction formed by the drift region (3) clearly has current flowing through it (e.g. Figure 6 This results in a depolarization effect; while for integrated heterojunction superjunction trench 4H-SiC MOSFETs (such as...), a depolarization effect is generated; Figure 1 Since the turn-on voltage of the body PN junction is around 3V, while that of the heterojunction is around 1V, the current in the device flows through the heterojunction structure and will not pass through the P junction. - Superjunction region (4) and N -The bulk PN junction formed by the drift region (3) mainly passes through N + Polycrystalline silicon source region (8), N - Polycrystalline silicon region (6), N - Drift zone (3), N + Substrate region (2), and finally to drain (e.g.) Figure 5 ),contrast Figure 6 The current path diagram clearly shows that in the traditional structure, the current flows through P. - body region (13) and N - The drift region (3) forms a bulk PN junction, and the structure of the present invention solves this problem well and suppresses the depolarization effect.

[0051] When a 10V positive voltage is applied to the drain, and a scan voltage with a step size of 0.2V is applied to the gate, the following can be obtained: Figure 4 This refers to the transfer characteristic curve of the device. When a drain voltage is applied and the gate voltage reaches the threshold voltage at which the device turns on, the device is activated, and the threshold voltage can be obtained. From the data in the figure, it can be seen that the threshold voltage of the device is reduced from 4.11V in the conventional structure to 2.21V in this invention (e.g., ...). Figure 4 This reduces power loss during reverse operation and provides excellent switching characteristics (such as...). Figure 4 ), reverse recovery characteristics and blocking characteristics.

[0052] The above description is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the protection scope of the present invention.

Claims

1. A superjunction trench 4H-SiC MOSFET with integrated heterojunction, characterized in that: It integrates a heterojunction with a low barrier in a superjunction trench 4H-SiC MOSFET. The device consists of a drain metal (1) and an N-type junction. + Substrate region (2), N - Drift zone (3), P - Superjunction region (4), P + Polysilicon gate (5), N - Polycrystalline silicon region (6), N - body area (7), N + Polycrystalline silicon source region (8), N + Body source region (9), source metal (10), source trench (11-1), gate trench (11-2) and P + The separation gate (12) is composed of N + The substrate region (2) is located above the drain metal (1), N - The drift region (3) is located in N + Above the substrate region (2), P - The superjunction region (4) is located in N - N is located to the upper left of the drift area (3). - Polycrystalline silicon region (6) and N - The body region (7) is located in N - Above the drift region (3), the source trench (11-1) is located at P - The gate trench (11-2) is located to the upper left of the superjunction region (4) and is situated in the N region. - P is located to the upper right of the drift zone (3). + The polysilicon gate (5) is located to the upper right of the gate trench (11-2); N + The polycrystalline silicon source region (8) is located in N - Above the polycrystalline silicon region (6), N + The body source region (9) is located in N - Above the body region (7); source trench (11-1), P - Superjunction region (4), N + Polycrystalline silicon source region (8) and N + The upper surface of the body source region (9) is flat, and the source metal (10) is located in the source trench (11-1), P - Superjunction region (4), N + Polycrystalline silicon source region (8) and N + Above the body source region (9); gate trench (11-2) and P + The upper surface of the polysilicon gate (5) is flush with the upper surface of the source metal (10); P + The separation gate (12) is located within the gate trench (11-2) and is located at P + The lower right side of the polysilicon gate (5).

2. The superjunction trench 4H-SiC MOSFET with integrated heterojunction as described in claim 1, characterized in that: The drain metal (1) is Al with a thickness of 50~100 nm; the source metal (10) is Al with a thickness of 50~100 nm; the source trench (11-1) is SiO2 with a thickness of 4.8~6.3 μm; and the gate trench (11-2) is SiO2 with a thickness of 2.5~3.0 μm.

3. The superjunction trench 4H-SiC MOSFET with integrated heterojunction as described in claim 1, characterized in that: N + The substrate region (2) is N-type heavily doped 4H-SiC, with nitrogen or phosphorus as the doping element and a doping concentration of 1×10⁻⁶. 19 cm -3 ~1×10 20 cm -3 .

4. The superjunction trench 4H-SiC MOSFET with integrated heterojunction as described in claim 1, characterized in that: N - The drift region (3) is N-type lightly doped 4H-SiC, with nitrogen or phosphorus as the doping element and a doping concentration of 5 × 10⁻⁶. 15 cm -3 ~7×10 15 cm -3 The thickness is 8~15 μm.

5. The superjunction trench 4H-SiC MOSFET with integrated heterojunction as described in claim 1, characterized in that: P - The superjunction region (4) is a lightly doped P-type 4H-SiC, with aluminum or boron as the doping element and a doping concentration of 5 × 10⁻⁶. 16 cm -3 ~5×10 17 cm -3 The thickness is 5.0~6.5 μm.

6. The superjunction trench 4H-SiC MOSFET with integrated heterojunction as described in claim 1, characterized in that: N - The polycrystalline silicon region (6) is N-type lightly doped polycrystalline silicon, with phosphorus as the doping element and a doping concentration of 5 × 10⁻⁶. 15 cm -3 ~5×10 16 cm -3 The thickness is 0.5~1.5 μm and the width is 0.3~0.5 μm.

7. The superjunction trench 4H-SiC MOSFET with integrated heterojunction as described in claim 1, characterized in that: N - The body region (7) is lightly doped N-type 4H-SiC, with nitrogen or phosphorus as the doping element and a doping concentration of 1×10⁻⁶. 14 cm -3 ~1×10 15 cm -3 The thickness is 0.5~1.5 μm and the width is 0.3~0.5 μm.

8. The superjunction trench 4H-SiC MOSFET with integrated heterojunction as described in claim 1, characterized in that: N + The polycrystalline silicon source region (8) is N-type heavily doped polycrystalline silicon, with phosphorus as the doping element and a doping concentration of 1×10⁻⁶. 19 cm -3 ~1×10 20 cm -3 The thickness is 0.15~0.25 μm and the width is 0.3~0.5 μm.

9. The superjunction trench 4H-SiC MOSFET with integrated heterojunction as described in claim 1, characterized in that: N + The body source region (9) is N-type heavily doped 4H-SiC, with nitrogen or phosphorus as the doping element and a doping concentration of 1×10⁻⁶. 19 cm -3 ~1×10 20 cm -3 The thickness is 0.15~0.25 μm and the width is 0.3~0.5 μm.

10. A superjunction trench 4H-SiC MOSFET with integrated heterojunction as described in claim 1, characterized in that: P + The polysilicon gate (5) is a P-type heavily doped polysilicon, with aluminum or boron as the doping element and a doping concentration of 1×10⁻⁶. 19 cm -3 ~1×10 20 cm -3 Thickness is 2~2.5 μm; P + The separation gate (12) is a P-type heavily doped polysilicon, with aluminum or boron as the doping element and a doping concentration of 1×10⁻⁶. 19 cm -3 ~1×10 20 cm -3 The thickness is 0.15~0.25 μm.

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