Two-dimensional semiconductor field effect transistor and preparation method thereof

Abstract

The invention discloses a two-dimensional semiconductor field effect transistor and a preparation method thereof, and belongs to the technical field of microelectronic devices. The two-dimensional semiconductor field effect transistor is formed by constructing a substrate, a buffer layer, a two-dimensional conductive shielding layer, a dielectric spacer layer, a two-dimensional semiconductor channel, a top gate dielectric layer, a top gate metal layer and a cap sealing layer which are stacked from bottom to top and arranging a drain electrode and a source electrode at the two ends of the two-dimensional semiconductor channel respectively. Coulomb impurity scattering and remote polarized phonon scattering of the field effect transistor can be shielded through the two-dimensional conductive shielding layer, and the grid control capability of the field effect transistor and the shielding capability of the two-dimensional conductive shielding layer can be coupled through the dielectric spacing layer; according to the field effect transistor, coulomb impurity scattering and remote polarization phonon scattering of the field effect transistor can be shielded while the grid control capability of the field effect transistor is considered, and the mobility and the performance of the field effect transistor are improved.

Description

Technical Field

[0001] This invention belongs to the field of microelectronic device technology, and particularly relates to a two-dimensional semiconductor field-effect transistor and its fabrication method. Background Technology

[0002] Two-dimensional semiconductors (such as MoS2, WS2, WSe2, and InSe) are widely used in the fabrication of channel materials for field-effect transistors (FETs) due to their atomic-level thickness, high on / off current ratio, and excellent subthreshold characteristics. Compared with traditional silicon channels, two-dimensional semiconductors exhibit unique advantages in ultra-short channels and flexible electronics due to their weak surface dangling bonds and stackability. However, insufficient mobility at room temperature remains a bottleneck problem for two-dimensional semiconductor FETs, limited by scattering mechanisms such as Coulomb impurity scattering (CI), remote interfacial / optical phonon scattering (RIP / ROP), phonon scattering within two-dimensional semiconductors, and interface roughness effects.

[0003] To address the insufficient mobility of two-dimensional semiconductor field-effect transistors (FETs) at room temperature, current methods typically involve coupling the two-dimensional semiconductor with hexagonal boron nitride (h-BN) to reduce interface defects and impurity scattering. Alternatively, a dielectric layer can be introduced during fabrication for optimization. However, while high-dielectric-constant dielectrics can reduce Coulomb impurity scattering, they enhance long-range polarized phonon scattering. Conversely, low-dielectric-constant dielectrics reduce long-range polarized phonon scattering but increase the equivalent oxide thickness (EOT), weakening the gate control capability of the FET. Furthermore, current optimization methods for FETs primarily rely on material selection or thickness adjustment, making it difficult for FETs to effectively suppress potential fluctuations across different frequency bands. Summary of the Invention

[0004] The present invention aims to provide a two-dimensional semiconductor field-effect transistor and its fabrication method to solve the above-mentioned technical problems. By using a dielectric spacer layer and a two-dimensional conductive shielding layer made of two-dimensional semiconductor material, the field-effect transistor can be shielded from Coulomb impurity scattering and long-range polarized phonon scattering while taking into account the gate control capability of the field-effect transistor, thereby improving the mobility of the field-effect transistor.

[0005] To address the aforementioned technical problems, this invention provides a two-dimensional semiconductor field-effect transistor, comprising a substrate, a buffer layer, a two-dimensional conductive shielding layer, a dielectric spacer layer, a two-dimensional semiconductor channel, a top gate dielectric layer, a top gate metal layer, and a capping layer stacked from bottom to top. A drain and a source are respectively disposed at both ends of the two-dimensional semiconductor channel; Both the two-dimensional conductive shielding layer and the two-dimensional semiconductor channel are made of two-dimensional semiconductor materials; The two-dimensional conductive shielding layer is used to shield the field-effect transistor from Coulomb impurity scattering and long-range polarized phonon scattering.

[0006] It is understood that the present invention forms a two-dimensional semiconductor field-effect transistor by constructing a substrate, a buffer layer, a two-dimensional conductive shielding layer, a dielectric spacer layer, a two-dimensional semiconductor channel, a top gate dielectric layer, a top gate metal layer, and a capping layer stacked from bottom to top, and by setting drain and source electrodes at both ends of the two-dimensional semiconductor channel, respectively. The two-dimensional conductive shielding layer and the two-dimensional semiconductor channel are fabricated using two-dimensional semiconductor materials. Then, the two-dimensional conductive shielding layer is placed between the substrate and the two-dimensional semiconductor channel, and a dielectric spacer layer is placed between the two-dimensional conductive shielding layer and the two-dimensional semiconductor channel. This ensures that the two-dimensional conductive shielding layer and the two-dimensional semiconductor channel are always isolated and not directly conductive. This allows the two-dimensional conductive shielding layer to shield the field-effect transistor from Coulomb impurity scattering and long-range polarized phonon scattering, and the dielectric spacer layer couples the gate control capability of the field-effect transistor with the shielding capability of the two-dimensional conductive shielding layer, thereby improving the mobility and performance of the field-effect transistor.

[0007] The two-dimensional conductive shielding layer attenuates external electric field disturbances. Specifically, due to the presence of charged defects or trapped charges between the two-dimensional semiconductor channel and the substrate, or between the two-dimensional semiconductor channel and the buffer layer, these charges generate a long-range Coulomb potential field in the two-dimensional semiconductor channel. However, due to the thinness of the two-dimensional semiconductor material, the charge carriers in the two-dimensional semiconductor channel cannot effectively shield the long-range Coulomb potential field, resulting in electron scattering. The two-dimensional conductive shielding layer beneath the two-dimensional semiconductor channel utilizes the free electrons in the shielding layer to respond to the long-range Coulomb potential field, forming mirror charges, thereby partially canceling the long-range Coulomb potential field. When the long-range Coulomb potential field is transmitted... When the polarized phonons reach the two-dimensional semiconductor channel, their intensity has been weakened, thus achieving Coulomb impurity scattering shielding of the field-effect transistor by the two-dimensional conductive shielding layer. At room temperature, polarized optical phonons excite a high-frequency electric dipole field in the top gate dielectric layer, which forms a polarized phonon electric field. Through the two-dimensional conductive shielding layer, the high-frequency electric dipole field first acts on the two-dimensional conductive shielding layer. The electrons in the two-dimensional conductive shielding layer can quickly generate a response and form a counteracting electric field, thereby canceling out part of the polarized phonon electric field. As a result, when the polarized phonon electric field reaches the two-dimensional semiconductor channel, its intensity has been weakened, thus achieving long-range polarized phonon scattering shielding of the field-effect transistor by the two-dimensional conductive shielding layer. In the dielectric spacer layer between the two-dimensional conductive shielding layer and the two-dimensional semiconductor channel, a thinner dielectric spacer layer can improve the shielding capability of the two-dimensional conductive shielding layer but weaken the gate control capability of the field-effect transistor (FET). Conversely, a thicker dielectric spacer layer results in stronger gate control capability for the FET and weaker shielding capability of the two-dimensional conductive shielding layer. By controlling the thickness of the dielectric spacer layer, the gate control capability of the FET and the shielding capability of the two-dimensional conductive shielding layer can be coupled. This allows the FET to not only possess strong gate control capability but also enable the two-dimensional conductive shielding layer to scatter Coulomb impurities and long-range polarized phonons, thereby improving the performance of the FET.

[0008] As a preferred embodiment, the two-dimensional semiconductor material of the two-dimensional conductive shielding layer includes any one or more combinations of graphene, graphite, and metallic transition metal chalcogenides. The thickness of the two-dimensional conductive shielding layer is set to 3 nanometers to 5 nanometers.

[0009] This preferred embodiment limits the two-dimensional semiconductor materials to include any one or more combinations of graphene, graphite, and metallic transition metal chalcogenides. The selection of highly conductive two-dimensional semiconductor materials such as graphene, graphite, and metallic transition metal chalcogenides ensures that the two-dimensional conductive shielding layer possesses excellent shielding capabilities and suitable application environments. It effectively shields against Coulomb impurity scattering and long-range polarized phonon scattering in field-effect transistors. Graphene can be fabricated over large areas, effectively shielding against interference. Two-dimensional conductive shielding layers prepared from graphite have stronger shielding capabilities against Coulomb impurity scattering and long-range polarized phonon scattering. Metallic transition metal chalcogenides provide stable metallicity to the two-dimensional conductive shielding layer, making it suitable for various environments. By setting the thickness of the two-dimensional conductive shielding layer to 3 to 5 nanometers, it ensures that the two-dimensional conductive shielding layer does not significantly shunt the signal of the top gate dielectric layer, thus ensuring the gate control capability of the field-effect transistor.

[0010] As a preferred embodiment, the two-dimensional semiconductor material of the two-dimensional semiconductor channel includes molybdenum disulfide or indium selenide; When the two-dimensional semiconductor material of the two-dimensional semiconductor channel is molybdenum disulfide, the number of molybdenum disulfide layers in the two-dimensional semiconductor channel is set to 3 to 8 layers. When the two-dimensional semiconductor material of the two-dimensional semiconductor channel is indium selenide, the thickness of the two-dimensional semiconductor channel is set to 5 nanometers to 10 nanometers.

[0011] This preferred embodiment defines the two-dimensional semiconductor material of the two-dimensional semiconductor channel as molybdenum disulfide or indium selenide. When the two-dimensional semiconductor material is molybdenum disulfide, the number of molybdenum disulfide layers is set to 3 to 8 layers, ensuring sufficient carrier density and high mobility, and providing sufficient band gap. When the two-dimensional semiconductor material is indium selenide, the thickness is set to 5 nanometers to 10 nanometers. Indium selenide can improve the mobility of the field-effect transistor and suppress short-channel effects, thereby improving the performance of the field-effect transistor.

[0012] As a preferred embodiment, the two-dimensional semiconductor material of the dielectric spacer layer is hexagonal boron nitride; The thickness of the dielectric spacer layer is set to 3 nanometers to 5 nanometers.

[0013] This preferred embodiment uses hexagonal boron nitride as the two-dimensional semiconductor material for the dielectric spacer layer, with a thickness of 3 to 5 nanometers. Hexagonal boron nitride, with its atomically flat surface, low defect density, and high chemical stability, effectively isolates the two-dimensional conductive shielding layer and the two-dimensional semiconductor channel, preventing electrical crosstalk. While a thinner dielectric spacer layer improves the shielding capability of the two-dimensional conductive shielding layer, it weakens the gate control capability of the field-effect transistor (FET). Conversely, a thicker dielectric spacer layer results in stronger gate control capability for the FET and weaker shielding capability for the two-dimensional conductive shielding layer. Therefore, by controlling the thickness to 3 to 5 nanometers, the gate control capability of the FET and the shielding capability of the two-dimensional conductive shielding layer can be coupled. This allows the FET to not only possess strong gate control capability but also enable the two-dimensional conductive shielding layer to scatter Coulomb impurities and long-range polarized phonons, thereby improving the performance of the FET.

[0014] As a preferred embodiment, the top gate dielectric layer is an iridium dioxide film; The thickness of the top gate dielectric layer is set to 5 nanometers to 8 nanometers.

[0015] This preferred embodiment defines the top gate dielectric layer as an iridium dioxide film with a thickness of 5 to 8 nanometers. Iridium dioxide, as a high dielectric constant material, can provide a higher gate capacitance, thereby enhancing the control capability of the two-dimensional semiconductor channel and reducing the operating voltage and power consumption. At the same time, setting the thickness to 5 to 8 nanometers can reduce the equivalent oxide thickness (EOT) of the field-effect transistor.

[0016] As a preferred embodiment, the substrate adopts Or quartz insulating substrate material.

[0017] This preferred solution limits the substrate used. Or quartz insulating substrate material, It possesses good thermal stability, electrical isolation, and cost-effectiveness, effectively reducing parasitic capacitance and substrate coupling interference; quartz offers high transparency, chemical inertness, and mechanical rigidity; [The text abruptly ends here, likely due to an incomplete sentence or missing information.] The insulating substrate material, such as quartz, can provide stable mechanical support for the upper structure.

[0018] As a preferred embodiment, the top gate metal layer adopts Metal materials or Metallic materials.

[0019] This preferred embodiment defines the top gate metal layer as... Metal materials or Metallic materials can ensure low work function difference and process stability in field-effect transistors.

[0020] As a preferred embodiment, the buffer layer is made of hexagonal boron nitride, and the thickness of the buffer layer is set to 5 nanometers to 20 nanometers.

[0021] This preferred embodiment defines the buffer layer as hexagonal boron nitride (BON) with a thickness of 5 to 20 nanometers. Using BON as the buffer layer provides an atomically flat surface and low defect density, effectively isolating impurities, phonon scattering, and stress in the substrate, reducing the impact on the performance of upper-layer devices. The high thermal conductivity of BON aids in heat dissipation and improves device stability, while its chemical inertness protects the two-dimensional material from environmental corrosion. Simultaneously, BON provides an atomically flat surface, reducing interface traps and roughness scattering between the two-dimensional semiconductor channel and the substrate. Furthermore, the thickness of 5 to 20 nanometers can shield substrate charge traps while maintaining mechanical stability.

[0022] As a preferred embodiment, the two-dimensional conductive shielding layer is externally connected to the first end of a preset capacitor; the two-dimensional conductive shielding layer is externally connected to the first end of a preset resistor. The capacitor and resistor are connected in parallel; the second terminal of the capacitor and the second terminal of the resistor are both grounded. The capacitor is set to 10~100nF; the resistor is set to 10~100MΩ. ; Both the capacitor and the resistor are used to adjust the scattering shielding range of the two-dimensional conductive shielding layer.

[0023] This preferred solution sets the capacitor to 10~100nF and the resistor to 10~100MΩ. By using external capacitors and resistors, dynamic control of the two-dimensional conductive shielding layer is achieved, thereby optimizing the coordinated control of Coulomb impurity scattering and long-range polarized phonon scattering. Specifically, although the two-dimensional conductive shielding layer can effectively shield Coulomb impurity scattering and long-range polarized phonon scattering, directly grounding the two-dimensional conductive shielding layer will cause a DC grounding problem, that is, it will introduce a fixed potential near the two-dimensional semiconductor channel, change the threshold voltage, and even form parasitic capacitance, weakening the gate control capability of the effect transistor. Furthermore, coupling the two-dimensional conductive shielding layer with the top gate dielectric layer will cause a complete floating problem, that is, it will weaken the shielding effect of the two-dimensional conductive shielding layer on high-frequency long-range polarized phonon scattering. Therefore, this preferred solution uses a capacitor and resistor connected in parallel for connection. By setting the parameters of the capacitor and resistor, the cutoff frequency of the field-effect transistor can be set. When the external interference frequency is higher than the cutoff frequency, i.e., under AC or mid-to-high frequency conditions, the two-dimensional conductive shielding layer is coupled to ground through the capacitor path, which is approximately grounded, effectively dissipating potential fluctuations and effectively absorbing high-frequency potential disturbances (long-range polarized phonon scattering and high-frequency noise). When the external interference frequency is lower than the cutoff frequency, i.e., under DC operating conditions, the two-dimensional conductive shielding layer remains suspended and does not affect DC and low-frequency gate control characteristics. Therefore, by adjusting the capacitor and resistor, the cutoff frequency of the field-effect transistor can be adjusted, thereby enabling the two-dimensional conductive shielding layer to operate in different frequency bands of DC, AC, or mid-to-high frequency, thus achieving adjustment of the scattering shielding range.

[0024] Accordingly, this invention provides a method for fabricating a two-dimensional semiconductor field-effect transistor, applicable to the two-dimensional semiconductor field-effect transistor described above, comprising: A substrate is generated, and a buffer layer is deposited on the upper surface of the substrate; Based on a preset dry transfer method, a two-dimensional conductive shielding layer is generated on the upper surface of the buffer layer; A dielectric spacer layer is deposited on the upper surface of the two-dimensional conductive shielding layer; A two-dimensional semiconductor channel is generated on the upper surface of the dielectric spacer layer based on a preset etching method. Fabricate a drain and a source, and place the drain and the source at opposite ends of the two-dimensional semiconductor channel, respectively. A top gate dielectric layer is deposited on the upper surface of the two-dimensional semiconductor channel based on a preset atomic layer deposition method. A top gate metal layer and a capping layer are fabricated, and the top gate metal layer and the capping layer are stacked sequentially on the upper surface of the top gate dielectric layer to complete the fabrication of the field-effect transistor.

[0025] It is understood that the present invention completes the fabrication of the field-effect transistor by generating a substrate and depositing a buffer layer on the upper surface of the substrate; generating a two-dimensional conductive shielding layer on the upper surface of the buffer layer based on a preset dry transfer method; depositing a dielectric spacer layer on the upper surface of the two-dimensional conductive shielding layer; generating a two-dimensional semiconductor channel on the upper surface of the dielectric spacer layer based on a preset etching method; fabricating a drain and a source electrode, and placing the drain and source electrode at opposite ends of the two-dimensional semiconductor channel; depositing a top gate dielectric layer on the upper surface of the two-dimensional semiconductor channel based on a preset atomic layer deposition method; fabricating a top gate metal layer and a capping layer, and stacking the top gate metal layer and the capping layer sequentially on the upper surface of the top gate dielectric layer; thereby enabling the construction of a substrate, buffer layer, two-dimensional conductive shielding layer, and dielectric spacer layer stacked from bottom to top. A two-dimensional semiconductor field-effect transistor (FET) is formed by comprising a separator, a two-dimensional semiconductor channel, a top-gate dielectric layer, a top-gate metal layer, and a capping layer, with a drain and a source respectively disposed at both ends of the two-dimensional semiconductor channel. A two-dimensional conductive shielding layer and the two-dimensional semiconductor channel are fabricated using two-dimensional semiconductor material. Then, a two-dimensional conductive shielding layer is disposed between the substrate and the two-dimensional semiconductor channel, and a dielectric spacer layer is disposed between the two-dimensional conductive shielding layer and the two-dimensional semiconductor channel. This ensures that the two-dimensional conductive shielding layer and the two-dimensional semiconductor channel are always isolated and do not directly conduct. This allows the two-dimensional conductive shielding layer to shield the field-effect transistor from Coulomb impurity scattering and long-range polarized phonon scattering, and the dielectric spacer layer can couple the gate control capability of the field-effect transistor with the shielding capability of the two-dimensional conductive shielding layer, thereby improving the mobility and performance of the field-effect transistor. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the structure of a two-dimensional semiconductor field-effect transistor provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of an external two-dimensional conductive shielding layer provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of another two-dimensional semiconductor field-effect transistor provided in an embodiment of the present invention; Figure 4 This is a flowchart illustrating the steps of a method for fabricating a two-dimensional semiconductor field-effect transistor, as provided in an embodiment of the present invention. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] Example 1 Please refer to Figure 1 , Figure 1 This is a schematic diagram of a two-dimensional semiconductor field-effect transistor provided in an embodiment of the present invention, including a substrate 101, a buffer layer 102, a two-dimensional conductive shielding layer 103, a dielectric spacer layer 104, a two-dimensional semiconductor channel 105, a top gate dielectric layer 106, a top gate metal layer 107, and a capping layer 108 stacked from bottom to top. At both ends of the two-dimensional semiconductor channel 105, a drain 109 and a source 110 are respectively provided; Both the two-dimensional conductive shielding layer 103 and the two-dimensional semiconductor channel 105 are made of two-dimensional semiconductor materials; The two-dimensional conductive shielding layer 103 is used to shield the field-effect transistor from Coulomb impurity scattering and long-range polarized phonon scattering.

[0029] It is understood that the present invention forms a two-dimensional semiconductor field-effect transistor by constructing a substrate, a buffer layer, a two-dimensional conductive shielding layer, a dielectric spacer layer, a two-dimensional semiconductor channel, a top gate dielectric layer, a top gate metal layer, and a capping layer stacked from bottom to top, and by setting drain and source electrodes at both ends of the two-dimensional semiconductor channel, respectively. The two-dimensional conductive shielding layer and the two-dimensional semiconductor channel are fabricated using two-dimensional semiconductor materials. Then, the two-dimensional conductive shielding layer is placed between the substrate and the two-dimensional semiconductor channel, and a dielectric spacer layer is placed between the two-dimensional conductive shielding layer and the two-dimensional semiconductor channel. This ensures that the two-dimensional conductive shielding layer and the two-dimensional semiconductor channel are always isolated and not directly conductive. This allows the two-dimensional conductive shielding layer to shield the field-effect transistor from Coulomb impurity scattering and long-range polarized phonon scattering, and the dielectric spacer layer couples the gate control capability of the field-effect transistor with the shielding capability of the two-dimensional conductive shielding layer, thereby improving the mobility and performance of the field-effect transistor.

[0030] Furthermore, the two-dimensional conductive shielding layer can attenuate external electric field disturbances. Specifically, due to the presence of charged defects or trapped charges between the two-dimensional semiconductor channel and the substrate, or between the two-dimensional semiconductor channel and the buffer layer, these charges generate a long-range Coulomb potential field in the two-dimensional semiconductor channel. However, due to the thinness of the two-dimensional semiconductor material, the charge carriers in the two-dimensional semiconductor channel cannot effectively shield the long-range Coulomb potential field, resulting in electron scattering. Through the two-dimensional conductive shielding layer below the two-dimensional semiconductor channel, the free electrons in the two-dimensional conductive shielding layer respond to the long-range Coulomb potential field, forming mirror charges, thereby canceling out part of the long-range Coulomb potential field. When the long-range Coulomb potential field is transmitted to the two-dimensional semiconductor channel, its intensity has been weakened, thus achieving the shielding of Coulomb impurity scattering of the field-effect transistor by the two-dimensional conductive shielding layer. Among them, the propagation of the electric field in the layered structure and the wave vector and the thickness of dielectric spacer layer 104 Regarding this, after setting the two-dimensional conductive shielding layer 103, the effective potential of the field-effect transistor can be expressed as: ; This represents the effective potential of the field-effect transistor. This represents the original defect potential of the field-effect transistor. This indicates the thickness of the dielectric spacer layer 104. The resulting exponential decay; This indicates that the conductivity / polarization of the two-dimensional conductive shielding layer 103 further weakens the electric field; As the primordial defect potential is weakened, the Coulomb scattering probability decreases, the electron mean free path increases, and the mobility dominated by Coulomb impurity scattering... The corresponding increase.

[0031] Furthermore, polarized optical phonons at room temperature will excite a high-frequency electric dipole field in the top gate dielectric layer. The electric dipole field will form a polarized phonon electric field. Through the two-dimensional conductive shielding layer, the high-frequency electric dipole field will first act on the two-dimensional conductive shielding layer. The electrons in the two-dimensional conductive shielding layer can quickly generate a response and form a counteracting electric field, thereby canceling out part of the polarized phonon electric field. When the polarized phonon electric field is transmitted to the two-dimensional semiconductor channel, its intensity has been weakened, thus realizing the long-range polarized phonon scattering shielding of the field-effect transistor by the two-dimensional conductive shielding layer. After the two-dimensional conductive shielding layer 103 is provided, the effective dielectric environment experienced by the two-dimensional semiconductor channel 105 is jointly determined by the dielectric spacer layer 104 and the two-dimensional conductive shielding layer 103, which can be expressed as: ; in, The frequency-dependent dielectric constant of the dielectric in the dielectric spacer layer 104; Represents the angular frequency of the electric field excitation (unit: rad / s); In-plane wave vector (unit: ); Represents the vacuum permittivity ( F / m); This represents the wave vector-dependent conductivity of the two-dimensional conductive shielding layer 103. This indicates the attenuation effect of the thickness of the dielectric spacer layer 104 on the electric field coupling; The imaginary unit; The higher the conductivity of the two-dimensional conductive shielding layer 103, the faster the response and the more significant the attenuation effect; the thinner the dielectric spacer layer 104, the stronger the electric field coupling and the better the shielding effect; the effect is manifested in a decrease in the long-range polarized phonon scattering rate and a mobility dominated by long-range polarized phonon scattering. improve.

[0032] Therefore, as described above, the mobility is dominated by Coulomb impurity scattering. Correspondingly, the mobility dominated by long-range polarized phonon scattering is increased. The overall mobility of the two-dimensional semiconductor channel 105 is improved, while the overall mobility is determined by multiple scattering mechanisms, which can be superimposed using the Matthiessen rule: ; This indicates a limit on the total mobility. This indicates the limitation of mobility imposed by Coulomb impurity scattering; This indicates the limitation of mobility imposed by long-range polarized phonon scattering; This indicates the limitation of mobility imposed by polar optical phonon scattering. This indicates the limitation of mobility imposed by acoustic phonon scattering. By improving the mobility dominated by Coulomb impurity scattering mobility dominated by long-range polarized phonon scattering , reduced and This reduces the constraint on the total mobility, thus increasing the total mobility.

[0033] In the dielectric spacer layer between the two-dimensional conductive shielding layer and the two-dimensional semiconductor channel, a thinner dielectric spacer layer can improve the shielding capability of the two-dimensional conductive shielding layer but weaken the gate control capability of the field-effect transistor (FET). Conversely, a thicker dielectric spacer layer results in stronger gate control capability for the FET and weaker shielding capability of the two-dimensional conductive shielding layer. By controlling the thickness of the dielectric spacer layer, the gate control capability of the FET and the shielding capability of the two-dimensional conductive shielding layer can be coupled. This allows the FET to not only possess strong gate control capability but also enable the two-dimensional conductive shielding layer to scatter Coulomb impurities and long-range polarized phonons, thereby improving the performance of the FET.

[0034] In this embodiment, the two-dimensional semiconductor material of the two-dimensional conductive shielding layer 103 includes any one or more combinations of graphene, graphite, and metallic transition metal chalcogenides. The thickness of the two-dimensional conductive shielding layer 103 is set to 3 nanometers to 5 nanometers.

[0035] Furthermore, graphene can be single-layer graphene or double-layer graphene.

[0036] This embodiment limits the two-dimensional semiconductor materials to include any one or more combinations of graphene, graphite, and metallic transition metal chalcogenides. The selection of highly conductive two-dimensional semiconductor materials such as graphene, graphite, and metallic transition metal chalcogenides ensures that the two-dimensional conductive shielding layer possesses excellent shielding capabilities and suitable application environments. It can effectively shield against Coulomb impurity scattering and long-range polarized phonon scattering in field-effect transistors. Graphene can be fabricated over large areas, effectively shielding against interference. The two-dimensional conductive shielding layer prepared from graphite has stronger shielding capabilities against Coulomb impurity scattering and long-range polarized phonon scattering. Metallic transition metal chalcogenides provide stable metallicity to the two-dimensional conductive shielding layer, making it suitable for various environments. By setting the thickness of the two-dimensional conductive shielding layer to 3 to 5 nanometers, it is ensured that the two-dimensional conductive shielding layer does not significantly shunt the signal of the top gate dielectric layer, thus ensuring the gate control capability of the field-effect transistor.

[0037] In this embodiment, the two-dimensional semiconductor material of the two-dimensional semiconductor channel 105 includes molybdenum disulfide. or indium selenide ; When the two-dimensional semiconductor material of the two-dimensional semiconductor channel 105 is molybdenum disulfide In this case, the number of molybdenum disulfide layers in the two-dimensional semiconductor channel is set to 3 to 8 layers; When the two-dimensional semiconductor material of the two-dimensional semiconductor channel 105 is indium selenide At that time, the thickness of the two-dimensional semiconductor channel was set to 5 nanometers to 10 nanometers.

[0038] This embodiment defines the two-dimensional semiconductor material of the two-dimensional semiconductor channel as molybdenum disulfide or indium selenide. When the two-dimensional semiconductor material is molybdenum disulfide, the number of molybdenum disulfide layers is set to 3 to 8 layers, which ensures sufficient carrier density and high mobility, and also provides a sufficient band gap. When the two-dimensional semiconductor material is indium selenide, the thickness is set to 5 nanometers to 10 nanometers. Indium selenide can improve the mobility of the field-effect transistor and suppress the short-channel effect, thereby improving the performance of the field-effect transistor.

[0039] In this embodiment, the two-dimensional semiconductor material of the dielectric spacer layer 104 is hexagonal boron nitride. The thickness of the dielectric spacer layer 104 is set to 3 nanometers to 5 nanometers.

[0040] Furthermore, when the dielectric spacer layer 104 is thin (e.g., 2 nm), the shielding capability of the two-dimensional conductive shielding layer is the strongest, but the electric field of the top gate dielectric layer 106 is shunted by the two-dimensional conductive shielding layer, resulting in a weakening of the gate control capability of the field-effect transistor. When the dielectric spacer layer 104 is thick (greater than 8 nm), the two-dimensional conductive shielding layer is too far away from the two-dimensional semiconductor channel 105, and the potential disturbance attenuation is insufficient, resulting in a weaker shielding capability of the two-dimensional conductive shielding layer. Therefore, limiting the thickness of the dielectric spacer layer 104 to 3 nm to 5 nm can simultaneously ensure both shielding effect and gate control performance.

[0041] In this embodiment, the two-dimensional semiconductor material of the dielectric spacer layer is set to hexagonal boron nitride, and the thickness is set to 3 to 5 nanometers. Hexagonal boron nitride, with its atomically flat surface, low defect density, and high chemical stability, can effectively isolate the two-dimensional conductive shielding layer and the two-dimensional semiconductor channel, preventing electrical crosstalk. When the dielectric spacer layer is thinner, the shielding capability of the two-dimensional conductive shielding layer is improved, but the gate control capability of the field-effect transistor (FET) is weakened. Conversely, when the dielectric spacer layer is thicker, the gate control capability of the FET is stronger, while the shielding capability of the two-dimensional conductive shielding layer is weaker. Therefore, by controlling the thickness to 3 to 5 nanometers, the gate control capability of the FET and the shielding capability of the two-dimensional conductive shielding layer can be coupled. This allows the FET to not only have strong gate control capability but also enable the two-dimensional conductive shielding layer to scatter Coulomb impurities and long-range polarized phonons, thereby improving the performance of the FET.

[0042] In this embodiment, the top gate dielectric layer 106 is an iridium dioxide film. ; The thickness of the top gate dielectric layer 106 is set to 5 nanometers to 8 nanometers.

[0043] Furthermore, the thickness of the top gate dielectric layer 106 is greater than that of the two-dimensional conductive shielding layer 103, which can prevent the gate control capability from being weakened; in an iridium dioxide film of 5 nm to 8 nm... Under these conditions, the equivalent oxide thickness (EOT) remains in the sub-1 nm range, providing strong coupling.

[0044] In this embodiment, the top gate dielectric layer is defined as an iridium dioxide film with a thickness of 5 to 8 nanometers. Iridium dioxide, as a high dielectric constant material, can provide a higher gate capacitance, thereby enhancing the control capability of the two-dimensional semiconductor channel and reducing the operating voltage and power consumption. At the same time, setting the thickness to 5 to 8 nanometers can reduce the equivalent oxide thickness (EOT) of the field-effect transistor.

[0045] In this embodiment, the substrate 101 adopts Or quartz insulating substrate material.

[0046] Furthermore, Use high-resistivity silicon It is silicon dioxide.

[0047] This embodiment limits the substrate used. Or quartz insulating substrate material, It possesses good thermal stability, electrical isolation, and cost-effectiveness, effectively reducing parasitic capacitance and substrate coupling interference; quartz offers high transparency, chemical inertness, and mechanical rigidity; [The text abruptly ends here, likely due to an incomplete sentence or missing information.] The insulating substrate material, such as quartz, can provide stable mechanical support for the upper structure.

[0048] In this embodiment, the top gate metal layer 107 adopts... Metal materials or Metallic materials.

[0049] This embodiment defines the top gate metal layer as... Metal materials or Metallic materials can ensure low work function difference and process stability in field-effect transistors.

[0050] In this embodiment, the buffer layer 102 is made of hexagonal boron nitride. The buffer layer 102 is prepared with a thickness of 5 nanometers to 20 nanometers.

[0051] This embodiment defines the buffer layer as hexagonal boron nitride (BON) with a thickness of 5 to 20 nanometers. Using BON as the buffer layer provides an atomically flat surface and low defect density, effectively isolating impurities, phonon scattering, and stress in the substrate, reducing the impact on the performance of upper-layer devices. The high thermal conductivity of BON aids in heat dissipation and improves device stability, while its chemical inertness protects the two-dimensional material from environmental corrosion. At the same time, BON provides an atomically flat surface, reducing interface traps and roughness scattering between the two-dimensional semiconductor channel and the substrate. Furthermore, the thickness of 5 to 20 nanometers can shield substrate charge traps while maintaining mechanical stability.

[0052] In this embodiment, the capping layer 108 is made of hexagonal boron nitride. The capping layer 108 is prepared with a thickness of 3 nanometers to 10 nanometers.

[0053] In this embodiment, the capping layer is defined as hexagonal boron nitride, and the thickness is set to 3 nanometers to 10 nanometers. The capping layer acts as a protective layer to prevent water and oxygen adsorption and environmental pollution, and to suppress threshold voltage drift and performance degradation.

[0054] In this embodiment, the positions of the drain 109 and the source 110 can be interchanged, and the contact between the drain 109 and the source 110 and the two-dimensional semiconductor channel 105 is a side contact. Phase engineering can also be used to reduce the contact resistance between the drain 109 and the two-dimensional semiconductor channel 105, as well as to reduce the contact resistance between the source 110 and the two-dimensional semiconductor channel 105.

[0055] In this embodiment, as Figure 2 As shown, Figure 2 This is a schematic diagram of an external two-dimensional conductive shielding layer provided in an embodiment of the present invention. The two-dimensional conductive shielding layer 103 is externally connected to a preset capacitor. The first end; the two-dimensional conductive shielding layer is externally connected to a preset resistor. The first end; The capacitor and resistance Parallel connection; the capacitor The second end is connected to the resistor The second end of each is grounded; The capacitor The resistor is set to 10~100nF; Set to 10~100M ; The capacitor and resistance Both are used to adjust the scattering shielding range of the two-dimensional conductive shielding layer 103.

[0056] Furthermore, the cutoff frequency of a field-effect transistor is expressed as: ; in, The cutoff frequency, For resistors The resistance value; For capacitor The capacitance value; In this embodiment, the capacitor is set to 10~100nF and the resistor to 10~100MΩ. By using an external capacitor and resistor, dynamic control of the two-dimensional conductive shielding layer is achieved, thereby optimizing the coordinated control of Coulomb impurity scattering and long-range polarized phonon scattering. Specifically, although the two-dimensional conductive shielding layer can effectively shield Coulomb impurity scattering and long-range polarized phonon scattering, directly grounding the two-dimensional conductive shielding layer will cause a DC grounding problem, that is, it will introduce a fixed potential near the two-dimensional semiconductor channel, change the threshold voltage, and even form parasitic capacitance, weakening the gate control capability of the field-effect transistor. Furthermore, coupling the two-dimensional conductive shielding layer with the top gate dielectric layer will cause a complete floating problem, that is, it will weaken the shielding effect of the two-dimensional conductive shielding layer on high-frequency long-range polarized phonon scattering. Therefore, this preferred solution uses a parallel capacitor and resistor for grounding. By setting the parameters of the capacitor and resistor, the cutoff frequency of the field-effect transistor can be set. When the external interference frequency is higher than the cutoff frequency... At this time, i.e., under AC or mid-to-high frequency conditions (DC-ground mode, two-dimensional conductive shielding layer DC grounded), the two-dimensional conductive shielding layer is coupled to ground through a capacitive path, approximating ground. The capacitive impedance decreases as the frequency increases, and the high-frequency potential is quickly discharged to ground through the capacitor, which can effectively absorb high-frequency potential disturbances (long-range polarized phonon scattering and high-frequency noise); when the external interference frequency is lower than the cutoff frequency... At this point, i.e., at the DC operating point, the capacitor impedance is relatively high, and the resistance is high. This design keeps the two-dimensional conductive shielding layer suspended (AC-ground mode, capacitor grounded, DC suspended), with an approximate open circuit between the two-dimensional conductive shielding layer and ground. The two-dimensional conductive shielding layer does not absorb DC electric fields, the channel potential is completely controlled by the top gate, the threshold voltage is stable, and parasitic bias is avoided in the two-dimensional semiconductor channel, without affecting DC and low-frequency gate control characteristics. Therefore, by adjusting the capacitor and resistor, and thus the cutoff frequency of the field-effect transistor, the two-dimensional conductive shielding layer can operate in different frequency bands (DC, AC, or mid-to-high frequencies), thereby adjusting the scattering shielding range.

[0057] In one alternative embodiment, please refer to Figure 3 , Figure 3 A schematic diagram of another two-dimensional semiconductor field-effect transistor provided in an embodiment of the present invention includes: a substrate 101, a buffer layer 102, a two-dimensional conductive shielding layer 103, a dielectric spacer layer 104, a two-dimensional semiconductor channel 105, a first dielectric spacer layer 111, a first two-dimensional conductive shielding layer 112, a top gate dielectric layer 106, a top gate metal layer 107, and a capping layer 108, stacked from bottom to top. Figure 1 Based on this embodiment Figure 3 A first dielectric spacer layer 111 and a first two-dimensional conductive shielding layer 112 are added. The first dielectric spacer layer 111 and the dielectric spacer layer 104 are configured the same; the first two-dimensional conductive shielding layer 112 and the two-dimensional conductive shielding layer 103 are configured the same.

[0058] The two-dimensional semiconductor field-effect transistor provided in this embodiment has a 1.5 to 3 times higher room temperature mobility compared to conventional field-effect transistors. The device can stably reach 300~800 cm² / V·s; it has excellent gate control capability, that is, the subthreshold slope is controlled within 70–85 mV / dec, the transconductance remains unchanged, and the switching speed is guaranteed; in terms of stability, the noise level is reduced by 30–50%, and the threshold voltage drift and hysteresis are significantly reduced; in terms of process compatibility, the whole process temperature is ≤350℃, and it is compatible with existing ALD and BEOL processes; using standard dry transfer, edge contact and ALD methods, it can be applied on a large scale.

[0059] Example 3 Please refer to Figure 4 , Figure 4 The flowchart of a method for fabricating a two-dimensional semiconductor field-effect transistor provided in this embodiment of the invention is applicable to a two-dimensional semiconductor field-effect transistor as described in Embodiment 1 above, and includes steps S1 to S7.

[0060] Step S1: Generate a substrate and deposit a buffer layer on the upper surface of the substrate.

[0061] Step S2: Based on a preset dry transfer method, a two-dimensional conductive shielding layer is generated on the upper surface of the buffer layer.

[0062] Step S3: Deposit a dielectric spacer layer on the upper surface of the two-dimensional conductive shielding layer.

[0063] Step S4: Based on a preset etching method, a two-dimensional semiconductor channel is generated on the upper surface of the dielectric spacer layer.

[0064] Step S5: Fabricate the drain and source electrodes, and place the drain and source electrodes at both ends of the two-dimensional semiconductor channel, respectively.

[0065] Step S6: Based on a preset atomic layer deposition method, deposit a top gate dielectric layer on the upper surface of the two-dimensional semiconductor channel.

[0066] Step S7: Fabricate the top gate metal layer and the capping layer, and stack the top gate metal layer and the capping layer sequentially on the upper surface of the top gate dielectric layer to complete the fabrication of the field-effect transistor.

[0067] In an optional embodiment, select Using a quartz insulating substrate as the base, a 5-20 nm thick buffer layer of hexagonal boron nitride is deposited on the upper surface of the substrate using a dry pick-up transfer method. A two-dimensional conductive shielding layer is then prepared by mechanical lift-off, and this layer is stacked on top of the buffer layer using a dry pick-up transfer method. A dielectric spacer layer is then deposited on the upper surface of the two-dimensional conductive shielding layer using the same dry transfer method. A two-dimensional semiconductor channel is then prepared by mechanical lift-off, and the pattern of the two-dimensional semiconductor channel is etched using electron beam lithography (i.e., a pre-defined etching method), thereby generating a two-dimensional semiconductor channel on the upper surface of the dielectric spacer layer. Drain and source electrodes are then prepared (since many mature technologies already exist, this embodiment will not describe them in detail again), and the drain and source electrodes are respectively placed at both ends of the two-dimensional semiconductor channel. Finally, an atomic layer deposition (ALD) process is used to deposit a seed layer (e.g., 1 nm) on the surface of the two-dimensional semiconductor channel. Al light oxidation) ensures uniform nucleation, followed by deposition of an iridium dioxide film to form the top gate dielectric layer; then, a top gate metal layer and a capping layer are prepared, and the top gate metal layer and capping layer are sequentially stacked on the upper surface of the top gate dielectric layer by dry transfer to complete the fabrication of the field-effect transistor.

[0068] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A two-dimensional semiconductor field-effect transistor, characterized in that, It includes a substrate, a buffer layer, a two-dimensional conductive shielding layer, a dielectric spacer layer, a two-dimensional semiconductor channel, a top gate dielectric layer, a top gate metal layer, and a capping layer stacked from bottom to top; A drain and a source are respectively disposed at both ends of the two-dimensional semiconductor channel; Both the two-dimensional conductive shielding layer and the two-dimensional semiconductor channel are made of two-dimensional semiconductor materials; The two-dimensional conductive shielding layer is used to shield the field-effect transistor from Coulomb impurity scattering and long-range polarized phonon scattering.

2. The two-dimensional semiconductor field-effect transistor as described in claim 1, characterized in that, The two-dimensional semiconductor material of the two-dimensional conductive shielding layer includes any one or more combinations of graphene, graphite, and metallic transition metal chalcogenides. The thickness of the two-dimensional conductive shielding layer is set to 3 nanometers to 5 nanometers.

3. A two-dimensional semiconductor field-effect transistor as described in claim 1, characterized in that, The two-dimensional semiconductor material of the two-dimensional semiconductor channel includes molybdenum disulfide or indium selenide; When the two-dimensional semiconductor material of the two-dimensional semiconductor channel is molybdenum disulfide, the number of molybdenum disulfide layers in the two-dimensional semiconductor channel is set to 3 to 8 layers. When the two-dimensional semiconductor material of the two-dimensional semiconductor channel is indium selenide, the thickness of the two-dimensional semiconductor channel is set to 5 nanometers to 10 nanometers.

4. A two-dimensional semiconductor field-effect transistor as described in claim 1, characterized in that, The two-dimensional semiconductor material of the dielectric spacer layer is hexagonal boron nitride; The thickness of the dielectric spacer layer is set to 3 nanometers to 5 nanometers.

5. A two-dimensional semiconductor field-effect transistor as described in claim 1, characterized in that, The top gate dielectric layer is an iridium dioxide film; The thickness of the top gate dielectric layer is set to 5 nanometers to 8 nanometers.

6. A two-dimensional semiconductor field-effect transistor as described in claim 1, characterized in that, The substrate is adopted Or quartz insulating substrate material.

7. A two-dimensional semiconductor field-effect transistor as described in claim 1, characterized in that, The top gate metal layer adopts Metal materials or Metallic materials.

8. A two-dimensional semiconductor field-effect transistor as described in claim 1, characterized in that, The buffer layer is made of hexagonal boron nitride, and the thickness of the buffer layer is set to 5 nanometers to 20 nanometers.

9. A two-dimensional semiconductor field-effect transistor as described in any one of claims 1 to 8, characterized in that, The first terminal of the two-dimensional conductive shielding layer is connected to a preset capacitor; the first terminal of the two-dimensional conductive shielding layer is connected to a preset resistor. The capacitor and resistor are connected in parallel; the second terminal of the capacitor and the second terminal of the resistor are both grounded. The capacitor is set to 10~100nF; the resistor is set to 10~100MΩ. ; Both the capacitor and the resistor are used to adjust the scattering shielding range of the two-dimensional conductive shielding layer.

10. A method for fabricating a two-dimensional semiconductor field-effect transistor, characterized in that, A two-dimensional semiconductor field-effect transistor as described in any one of claims 1 to 9, comprising: A substrate is generated, and a buffer layer is deposited on the upper surface of the substrate; Based on a preset dry transfer method, a two-dimensional conductive shielding layer is generated on the upper surface of the buffer layer; A dielectric spacer layer is deposited on the upper surface of the two-dimensional conductive shielding layer; A two-dimensional semiconductor channel is generated on the upper surface of the dielectric spacer layer based on a preset etching method. Fabricate a drain and a source, and place the drain and the source at opposite ends of the two-dimensional semiconductor channel, respectively. A top gate dielectric layer is deposited on the upper surface of the two-dimensional semiconductor channel based on a preset atomic layer deposition method. A top gate metal layer and a capping layer are fabricated, and the top gate metal layer and the capping layer are stacked sequentially on the upper surface of the top gate dielectric layer to complete the fabrication of the field-effect transistor.

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