Super junction semiconductor power device and manufacturing method thereof

Abstract

The invention provides a super junction semiconductor power device which comprises a heavily doped first conductive type substrate, and a first conductive type epitaxial layer is arranged on the heavily doped first conductive type substrate; a groove is formed in the first conductive type epitaxial layer; second conductive type doped monocrystalline silicon is filled in the groove to form a second conductive type columnar epitaxy; first conductive type columnar epitaxy and second conductive type columnar epitaxy which are alternately distributed are formed in the first conductive type epitaxial layer; the doping concentration of the second conductive type columnar epitaxy is greater than that of the first conductive type columnar epitaxy; a plurality of heavily doped first conductive type impurity injection regions extending into the first conductive type columnar epitaxy are distributed on the side walls of the two sides of the second conductive type columnar epitaxy; according to the invention, the soft reverse recovery characteristic can be obtained, the electromagnetic radiation in the reverse recovery process of the device is reduced, and meanwhile, the voltage-resistant stability of the device is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor power device technology, and in particular to a superjunction semiconductor power device and its manufacturing method. Background Technology

[0002] Superjunction semiconductor power devices can achieve their N / P doped alternating superjunction columnar structure through multiple epitaxial growths accompanied by multiple impurity implantations, or by etching deep trenches and filling them with P-type doped single-crystal silicon. The second method has better cost control and lower requirements for epitaxial capacity, and its efficiency will be higher after stable mass production is achieved. However, since the P-type doping is achieved through epitaxial filling, and to achieve dynamic performance, the N / P doped alternating superjunction columnar structure generally adopts a slightly higher P-type doping concentration (i.e., the P-type columnar epitaxial doping concentration is greater than the N-type columnar epitaxial doping concentration). This ensures a stronger electric field at the bottom of the trench, so that the breakdown point occurs at the bottom of the trench during reverse breakdown, thus ensuring its avalanche breakdown characteristics and surge performance.

[0003] However, a slightly higher concentration of P-type doping can lead to faster depletion of the N-pillar epitaxial layer at the P / N columnar epitaxial junction. During reverse recovery, this results in a harder recovery characteristic, stronger electromagnetic radiation, lower application compatibility, and a greater susceptibility to device damage. Summary of the Invention

[0004] To address at least one technical problem in the prior art, embodiments of the present invention provide a superjunction semiconductor power device and its manufacturing method, thereby achieving softer reverse recovery characteristics, reducing electromagnetic radiation during the reverse recovery process, and simultaneously improving the device's breakdown voltage stability. To achieve the above technical objectives, the technical solution adopted by embodiments of the present invention is as follows: In a first aspect, embodiments of the present invention provide a superjunction semiconductor power device, including a heavily doped first conductivity type substrate, a first conductivity type epitaxial layer disposed on the heavily doped first conductivity type substrate; the surface of the first conductivity type epitaxial layer facing away from the heavily doped first conductivity type substrate is a first main surface, and the surface of the heavily doped first conductivity type substrate facing away from the first conductivity type epitaxial layer is a second main surface; a drain metal is disposed on the second main surface. Trenches are provided in the epitaxial layer of the first conductivity type; the trenches are located in the active region of the device and are arranged in parallel at intervals; A second type of conductive doped single-crystal silicon is filled in the trench to form a second type of conductive columnar epitaxial layer; thereby, alternating first type of conductive columnar epitaxial layer and second type of conductive columnar epitaxial layer are formed in the first type of conductive epitaxial layer; the doping concentration of the second type of conductive columnar epitaxial layer is greater than the doping concentration of the first type of conductive columnar epitaxial layer. Multiple heavily doped first-conductivity-type impurity implantation regions extending into the first-conductivity-type columnar epitaxial layer are distributed on both sidewalls of the second-conductivity-type columnar epitaxial layer. A second conductivity type well region is provided at the top of the second conductivity type columnar epitaxial layer; the width of the second conductivity type well region is greater than the width of the second conductivity type columnar epitaxial layer; two heavily doped first conductivity type implantation regions are provided at the top of the second conductivity type well region; and heavily doped second conductivity type implantation regions are provided between and below the two heavily doped first conductivity type implantation regions. A gate oxide layer is provided on the first main surface; a gate polysilicon layer is provided on the gate oxide layer; between two adjacent second conductivity type well regions, the gate polysilicon extends from above a first conductivity type injection region in one of the second conductivity type well regions toward the other second conductivity type well region to above a first conductivity type injection region in the other second conductivity type well region toward the first conductivity type injection region. A second type of insulating dielectric layer is provided above the first main surface, and the second type of insulating dielectric layer covers the gate polysilicon; A source metal and a gate metal are provided on a second type of insulating dielectric layer; the source metal is connected through a source contact hole to two heavily doped first conductivity type implanted regions spaced apart in the second conductivity type well region at the top of the second conductivity type columnar epitaxial layer, and to a heavily doped second conductivity type implanted region between the two spaced heavily doped first conductivity type implanted regions; the gate metal is connected to the gate polysilicon through a gate contact hole.

[0005] Furthermore, the length of the heavily doped first conductivity type impurity implantation region in the height direction ranges from 0.5 μm to 2 μm.

[0006] Furthermore, the length of the heavily doped first conductivity type impurity implantation region in the height direction ranges from 1 μm to 1.5 μm.

[0007] Furthermore, the doping concentration of the heavily doped first conductivity type impurity implantation region is 1.5 to 2.5 times that of the doping concentration of the second conductivity type columnar epitaxy.

[0008] Furthermore, the number of heavily doped first conductivity type impurity implantation regions on each sidewall of the second conductivity type columnar epitaxial layer is 3 to 6.

[0009] Secondly, embodiments of the present invention provide a method for manufacturing a superjunction semiconductor power device, for manufacturing the superjunction semiconductor power device as described above, comprising the following steps: Step S1: Provide a heavily doped first conductivity type substrate, and grow a first conductivity type epitaxial layer on the heavily doped first conductivity type substrate; the surface of the first conductivity type epitaxial layer facing away from the heavily doped first conductivity type substrate is a first main surface, and the surface of the heavily doped first conductivity type substrate facing away from the first conductivity type epitaxial layer is a second main surface. Step S2: Trenches are etched in the epitaxial layer of the first conductivity type; the trenches are located in the active region of the device and are spaced parallel to each other; By selectively injecting heavily doped first conductivity type impurities into trenches, a heavily doped first conductivity type impurity injection region is formed below the bottom of the trench and on the lower part of the sidewalls on both sides of the trench. Step S3: Continue etching the trench to increase its depth, remove the heavily doped first conductivity type impurity implantation region below the bottom of the previous trench, and retain the heavily doped first conductivity type impurity implantation regions on both sides of the trench; then selectively implant heavily doped first conductivity type impurities again to form heavily doped first conductivity type impurity implantation regions below the bottom of the current trench and on the lower part of both sides of the current trench. Step S4: Repeat step S3 until the trench depth reaches the target depth and the number of heavily doped first conductivity type impurity implantation regions on both sides of the trench reaches the target number. Step S5: Deposit second conductivity type doped single crystal silicon in the first main surface and trench and perform CMP treatment; form second conductivity type columnar epitaxial layer in the trench; thereby forming alternating first conductivity type columnar epitaxial layer and second conductivity type columnar epitaxial layer in the first conductivity type epitaxial layer; the doping concentration of the second conductivity type columnar epitaxial layer is greater than the doping concentration of the first conductivity type columnar epitaxial layer. Step S6: Selectively inject a second type of conductivity impurity into the first main surface and push it into a well, forming a second type of conductivity well region on the top of the second type of conductivity columnar epitaxial layer; the width of the second type of conductivity well region is greater than the width of the second type of conductivity columnar epitaxial layer. Step S7: Deposit a gate oxide layer on the first main surface; Step S8: Deposit conductive polysilicon on the first main surface and selectively etch it to form gate polysilicon; Step S9: Selectively implant first conductivity type impurities into the first main surface and anneal it to form two heavily doped first conductivity type implantation regions spaced apart on the top of the second conductivity type well region. Step S10: Deposit an insulating dielectric layer on the first main surface, and then selectively etch the hole structure to form source contact holes and gate contact holes; Step S11: Inject a second conductivity type impurity through the source contact hole and anneal it to form a heavily doped second conductivity type injection region; the second conductivity type injection region is distributed between two spaced heavily doped first conductivity type injection regions in the second conductivity type well region and extends below the two spaced heavily doped first conductivity type injection regions. Step S12: Deposit a metal layer on the insulating dielectric layer and selectively etch it to form the source metal and the gate metal; The source metal is connected through a source contact hole to two spaced-apart heavily doped first conductivity type implantation regions in the second conductivity type well region at the top of the second conductivity type columnar epitaxial layer, and to the heavily doped second conductivity type implantation region between the two spaced-apart heavily doped first conductivity type implantation regions. The gate metal is connected to the gate polysilicon through a gate contact hole; Step S13: Deposit drain metal on the second main surface.

[0010] Furthermore, the length of the heavily doped first conductivity type impurity implantation region in the height direction ranges from 0.5 μm to 2 μm.

[0011] Furthermore, the length of the heavily doped first conductivity type impurity implantation region in the height direction ranges from 1 μm to 1.5 μm.

[0012] Furthermore, the doping concentration of the heavily doped first conductivity type impurity implantation region is 1.5 to 2.5 times that of the doping concentration of the second conductivity type columnar epitaxy.

[0013] Furthermore, the number of heavily doped first conductivity type impurity implantation regions on each sidewall of the trench is 3 to 6.

[0014] The beneficial effects of the technical solution provided by the embodiments of the present invention are as follows: the present application enables the device to obtain softer reverse recovery characteristics, reduces electromagnetic radiation during the reverse recovery process of the device, and improves DV / DT performance and application stability; it can not only ensure the device's avalanche resistance, but also balance the distribution of the electric field in the body and the electric field at the bottom of the trench, thereby improving the device's withstand voltage stability and withstand voltage value. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the growth of an epitaxial layer of the first conductivity type in an embodiment of the present invention.

[0016] Figure 2 This is a schematic diagram of the etching process forming trenches in an embodiment of the present invention.

[0017] Figure 3This is a schematic diagram of a first conductivity type impurity injection region formed by injecting impurities into the lower part of the bottom of the trench and the lower part of the sidewalls on both sides of the trench in an embodiment of the present invention.

[0018] Figure 4 This is a schematic diagram of a heavily doped first conductivity type impurity injection region formed by injecting impurities into the lower part of the bottom of the trench and the lower part of the sidewalls on both sides of the current trench in a re-etched trench embodiment of the present invention.

[0019] Figure 5 This is a schematic diagram of the deposition of doped single-crystal silicon of the second conductivity type and CMP treatment in an embodiment of the present invention.

[0020] Figure 6 This is a schematic diagram illustrating the formation of a second conductivity type well region in an embodiment of the present invention.

[0021] Figure 7 This is a schematic diagram of the deposited gate oxide layer in an embodiment of the present invention.

[0022] Figure 8 This is a schematic diagram illustrating the formation of a gate polysilicon in an embodiment of the present invention.

[0023] Figure 9 This is a schematic diagram of two heavily doped first conductivity type doped regions with spaced distribution in an embodiment of the present invention.

[0024] Figure 10 This is a schematic diagram of the deposition of an insulating dielectric layer and the etching to form source contact holes and gate contact holes in an embodiment of the present invention.

[0025] Figure 11 This is a schematic diagram of the formation of a heavily doped second conductivity type implantation region in an embodiment of the present invention.

[0026] Figure 12 This is a schematic diagram of depositing a metal layer and selectively etching it to form the source metal and gate metal in an embodiment of the present invention. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0028] In the description of the embodiments of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention. In addition, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0029] In the description of the embodiments of the present invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can also refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in the present invention based on the specific circumstances.

[0030] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0031] Example 1: Taking an N-type superjunction MOSFET power device as an example, the first conductivity type is N-type and the second conductivity type is P-type. like Figure 12 As shown, Embodiment 1 of the present invention proposes a superjunction semiconductor power device, including a heavily doped first conductivity type substrate 1, and a first conductivity type epitaxial layer 2 disposed on the heavily doped first conductivity type substrate 1; the surface of the first conductivity type epitaxial layer 2 facing away from the heavily doped first conductivity type substrate 1 is a first main surface, and the surface of the heavily doped first conductivity type substrate 1 facing away from the first conductivity type epitaxial layer 2 is a second main surface; a drain metal is disposed on the second main surface; A trench 3 is provided in the first conductivity type epitaxial layer 2; the trench 3 is located in the active region of the device and is arranged in parallel at intervals; The trench 3 is filled with doped single-crystal silicon 5 of the second conductivity type to form a columnar epitaxial layer 501 of the second conductivity type; thereby forming an alternating distribution of columnar epitaxial layer 501 of the first conductivity type and columnar epitaxial layer 2 of the first conductivity type; the doping concentration of the columnar epitaxial layer 501 of the second conductivity type is greater than the doping concentration of the columnar epitaxial layer of the first conductivity type. Multiple heavily doped first-conductivity type impurity implantation regions 4 extending into the first-conductivity type columnar epitaxial layer are distributed on both sides of the second-conductivity type columnar epitaxial layer 501. A second conductivity type well region 6 is provided at the top of the second conductivity type columnar epitaxial layer 501; the width of the second conductivity type well region 6 is greater than the width of the second conductivity type columnar epitaxial layer 501; two heavily doped first conductivity type implantation regions 9 are provided at the top of the second conductivity type well region 6; and heavily doped second conductivity type implantation regions 12 are provided between and below the two heavily doped first conductivity type implantation regions 9. A gate oxide layer 7 is provided on the first main surface; a gate polysilicon 8 is provided on the gate oxide layer 7; between two adjacent second conductivity type well regions 6, the gate polysilicon 8 extends from one of the second conductivity type well regions 6 over a first conductivity type implantation region 9 toward the other second conductivity type well region 6 to the other second conductivity type well region 6 over the first conductivity type implantation region 9 toward the first conductivity type well region 6. A second type of insulating dielectric layer 10 is provided above the first main surface, and the second type of insulating dielectric layer 10 covers the gate polysilicon 8; A source metal 13 and a gate metal are provided on the second type of insulating dielectric layer 10; the source metal 13 is connected through a source contact hole 11 to two heavily doped first conductivity type implantation regions 9 spaced apart in the second conductivity type well region 6 at the top of the second conductivity type columnar epitaxial layer 501, and to a heavily doped second conductivity type implantation region 12 between the two spaced heavily doped first conductivity type implantation regions 9; the gate metal is connected to the gate polysilicon 8 through a gate contact hole.

[0032] This application introduces a high-concentration, small-area first conductivity type impurity implantation region 4 at the P / N columnar epitaxial junction. During the reverse recovery process of the device, the addition of an undepleted first conductivity type region at the P / N columnar epitaxial junction provides additional and continuous first conductivity type carriers, slowing down the depletion rate of the PN superjunction at the P / N junction. This results in softer reverse recovery characteristics, reduces electromagnetic radiation during the reverse recovery process, and improves DV / DT performance and application stability. Simultaneously, by combining the concentration and area of ​​the first conductivity type impurity implantation region 4, a secondary electric field with a lower electric field strength than the bottom of the trench can be formed at the P / N junction of the first conductivity type impurity implantation region 4 when the device is in reverse cutoff state. This ensures that the highest electric field is always maintained at the bottom of the trench, guaranteeing the avalanche capability of the device. At the same time, it balances the distribution of the electric field in the bulk and at the bottom of the trench, improving the breakdown voltage stability and breakdown voltage of the device.

[0033] More preferably, the length of the heavily doped first conductivity type impurity implantation region 4 in the height direction ranges from 0.5 μm to 2 μm; the optimal length range is from 1 μm to 1.5 μm, so as to ensure that the area of ​​the first conductivity type impurity implantation region 4 is small.

[0034] Furthermore, the doping concentration of the heavily doped first conductivity type impurity implantation region 4 is 1.5 to 2.5 times that of the doping concentration of the second conductivity type columnar epitaxial layer 501; this is the optimal range for the doping concentration of the first conductivity type impurity implantation region 4. More preferably, the number of heavily doped first conductivity type impurity implantation regions 4 on each sidewall of the second conductivity type columnar epitaxial layer 501 is 3 to 6; this can balance the distribution of the electric field in the bulk and the electric field at the bottom of the trench.

[0035] Example 2: Taking an N-type superjunction MOSFET power device as an example, the first conductivity type is N-type and the second conductivity type is P-type; Embodiment 2 of the present invention provides a method for manufacturing a superjunction semiconductor power device, comprising the following steps: Step S1, as follows Figure 1 As shown, a heavily doped first conductivity type substrate 1 is provided, and a first conductivity type epitaxial layer 2 is grown on the heavily doped first conductivity type substrate 1; the surface of the first conductivity type epitaxial layer 2 facing away from the heavily doped first conductivity type substrate 1 is a first main surface, and the surface of the heavily doped first conductivity type substrate 1 facing away from the first conductivity type epitaxial layer 2 is a second main surface. Step S2, as follows Figure 2 As shown, trenches 3 are etched in the epitaxial layer 2 of the first conductivity type; the trenches 3 are located in the active region of the device and are arranged in parallel at intervals. By selectively injecting heavily doped first conductivity type impurities into trench 3, a heavily doped first conductivity type impurity injection region 4 is formed below the bottom of trench 3 and at the lower part of the sidewalls on both sides of trench 3. Step S3, as follows Figure 3 As shown, the trench 3 is etched again to increase the depth of the trench 3, and the heavily doped first conductivity type impurity implantation region 4 below the bottom of the trench 3 in the previous step is removed, while the heavily doped first conductivity type impurity implantation regions 4 on both sides of the trench 3 are retained; then, the heavily doped first conductivity type impurities are selectively implanted again to form the heavily doped first conductivity type impurity implantation region 4 below the bottom of the current trench 3 and at the lower part of the side walls on both sides of the current trench 3. Step S4, as follows Figure 4 As shown, repeat step S3 until the depth of trench 3 reaches the target depth and the number of heavily doped first conductivity type impurity implantation regions 4 on both sides of trench 3 reaches the target number. More preferably, the length of the heavily doped first conductivity type impurity implantation region 4 in the height direction ranges from 0.5 μm to 2 μm; the optimal length range is from 1 μm to 1.5 μm, so as to ensure that the area of ​​the first conductivity type impurity implantation region 4 is small.

[0036] Furthermore, the doping concentration of the heavily doped first conductivity type impurity implantation region 4 is 1.5 to 2.5 times that of the doping concentration of the second conductivity type columnar epitaxial layer 501; this is the optimal range for the doping concentration of the first conductivity type impurity implantation region 4. More preferably, the number of heavily doped first conductivity type impurity implantation regions 4 on each sidewall of trench 3 is 3 to 6; this can balance the distribution of the electric field in the bulk and the electric field at the bottom of the trench. Step S5, as follows Figure 5 As shown, a second conductivity type doped single crystal silicon 5 is deposited in the first main surface and the trench 3 and subjected to CMP treatment; a second conductivity type columnar epitaxial layer 501 is formed in the trench 3; thereby, alternating distributions of the first conductivity type columnar epitaxial layer 2 and the second conductivity type columnar epitaxial layer 501 are formed; the doping concentration of the second conductivity type columnar epitaxial layer 501 is greater than the doping concentration of the first conductivity type columnar epitaxial layer. The epitaxial layer between two adjacent second-conductivity type columnar epitaxial layers 501 is the first-conductivity type columnar epitaxial layer; Step S6, as follows Figure 6 As shown, a second type of conductivity impurity is selectively injected into the first main surface and pushed into a well, forming a second type of conductivity well region 6 on the top of the second type of conductivity columnar epitaxial layer 501; the width of the second type of conductivity well region 6 is greater than the width of the second type of conductivity columnar epitaxial layer 501. Step S7, as follows Figure 7 As shown, a gate oxide layer 7 is deposited on the first main surface; Step S8, as follows Figure 8 As shown, conductive polysilicon is deposited on the first main surface and selectively etched to form gate polysilicon 8; Step S9, as follows Figure 9 As shown, a first conductivity type impurity is selectively implanted into the first main surface and annealed, forming two heavily doped first conductivity type implantation regions 9 spaced apart on the top of the second conductivity type well region 6; Step S10, as follows Figure 10 As shown, an insulating dielectric layer 10 is deposited on the first main surface, and then a hole structure is selectively etched to form a source contact hole 11 and a gate contact hole; The gate contact hole is not shown in the figure; this is hereby noted. Step S11, as follows Figure 11 As shown, a second conductivity type impurity is injected through the source contact hole 11 and annealed to form a heavily doped second conductivity type injection region 12; the second conductivity type injection region 12 is distributed between two spaced heavily doped first conductivity type injection regions 9 in the second conductivity type well region 6, and extends below the two spaced heavily doped first conductivity type injection regions 9. Step S12, as follows Figure 12As shown, a metal layer is deposited on the insulating dielectric layer 10 and selectively etched to form the source metal 13 and the gate metal; The source metal 13 is connected through the source contact hole 11 to two heavily doped first conductive type implantation regions 9 spaced apart in the second conductive type well region 6 at the top of the second conductive type columnar epitaxial layer 501, and to the heavily doped second conductive type implantation region 12 between the two heavily doped first conductive type implantation regions 9 spaced apart. The gate metal is connected to the gate polysilicon 8 through a gate contact hole; A contact hole can be filled during the deposition of a metal layer; Step S13: Deposit drain metal on the second main surface.

[0037] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A superjunction semiconductor power device, comprising a heavily doped first conductivity type substrate (1), wherein a first conductivity type epitaxial layer (2) is disposed on the heavily doped first conductivity type substrate (1); the surface of the first conductivity type epitaxial layer (2) facing away from the heavily doped first conductivity type substrate (1) is a first main surface, and the surface of the heavily doped first conductivity type substrate (1) facing away from the first conductivity type epitaxial layer (2) is a second main surface; a drain metal is disposed on the second main surface; A trench (3) is provided in the epitaxial layer (2) of the first conductivity type; the trench (3) is located in the active region of the device and is arranged in parallel at intervals; characterized in that, The trench (3) is filled with doped single-crystal silicon (5) of the second conductivity type to form a columnar epitaxial layer (501) of the second conductivity type; thereby forming an alternating distribution of columnar epitaxial layer (501) of the first conductivity type and columnar epitaxial layer (2); the doping concentration of the columnar epitaxial layer (501) of the second conductivity type is greater than the doping concentration of the columnar epitaxial layer of the first conductivity type. Multiple heavily doped first-conductivity type impurity implantation regions (4) extending into the first-conductivity type columnar epitaxial layer are distributed on both sides of the second-conductivity type columnar epitaxial layer (501). A second conductivity type well region (6) is provided at the top of the second conductivity type columnar epitaxial layer (501); the width of the second conductivity type well region (6) is greater than the width of the second conductivity type columnar epitaxial layer (501); two heavily doped first conductivity type implantation regions (9) are provided at the top of the second conductivity type well region (6); a heavily doped second conductivity type implantation region (12) is provided between and below the two heavily doped first conductivity type implantation regions (9); A gate oxide layer (7) is provided on the first main surface; a gate polysilicon (8) is provided on the gate oxide layer (7); between two adjacent second conductivity type well regions (6), the gate polysilicon (8) extends from above a first conductivity type implantation region (9) in one of the second conductivity type well regions (6) toward the other second conductivity type well region (6) to above the first conductivity type implantation region (9) in the other second conductivity type well region (6) toward the first conductivity type implantation region (9) in the other second conductivity type well region (6); A second type of insulating dielectric layer (10) is provided above the first main surface, and the second type of insulating dielectric layer (10) covers the gate polysilicon (8); A source metal (13) and a gate metal are provided on the second type insulating dielectric layer (10); the source metal (13) is connected through a source contact hole (11) to two heavily doped first conductivity type implanted regions (9) spaced apart in the second conductivity type well region (6) at the top of the second conductivity type columnar epitaxial layer (501), and to a heavily doped second conductivity type implanted region (12) between the two heavily doped first conductivity type implanted regions (9); the gate metal is connected through a gate contact hole to the gate polysilicon (8).

2. The superjunction semiconductor power device as described in claim 1, characterized in that, The length of the heavily doped first conductivity type impurity implantation region (4) in the height direction ranges from 0.5 μm to 2 μm.

3. The superjunction semiconductor power device as described in claim 2, characterized in that, The length of the heavily doped first conductivity type impurity implantation region (4) in the height direction ranges from 1 μm to 1.5 μm.

4. The superjunction semiconductor power device as described in claim 1, characterized in that, The doping concentration of the heavily doped first conductivity type impurity implantation region (4) is 1.5 to 2.5 times that of the doping concentration of the second conductivity type columnar epitaxial region (501).

5. The superjunction semiconductor power device as described in claim 1, characterized in that, The number of heavily doped first conductivity type impurity implantation regions (4) on each sidewall of the second conductivity type columnar epitaxial layer (501) is 3 to 6.

6. A method for manufacturing a superjunction semiconductor power device, used to manufacture the superjunction semiconductor power device as described in any one of claims 1 to 5, characterized in that, Includes the following steps: Step S1: Provide a heavily doped first conductivity type substrate (1), and grow a first conductivity type epitaxial layer (2) on the heavily doped first conductivity type substrate (1); the surface of the first conductivity type epitaxial layer (2) facing away from the heavily doped first conductivity type substrate (1) is the first main surface, and the surface of the heavily doped first conductivity type substrate (1) facing away from the first conductivity type epitaxial layer (2) is the second main surface. Step S2, trenches (3) are etched in the first conductivity type epitaxial layer (2); the trenches (3) are located in the active region of the device and are arranged in parallel at intervals; By selectively injecting heavily doped first conductivity type impurities into the trench (3), a heavily doped first conductivity type impurity injection region (4) is formed below the bottom of the trench (3) and at the lower part of the sidewalls on both sides of the trench (3); Step S3: Continue etching the trench (3) to increase the depth of the trench (3), remove the heavily doped first conductivity type impurity implantation region (4) below the bottom of the previous trench (3), and retain the heavily doped first conductivity type impurity implantation region (4) on both sides of the trench (3); then selectively implant the heavily doped first conductivity type impurity again to form the heavily doped first conductivity type impurity implantation region (4) below the bottom of the current trench (3) and the lower part of both sides of the current trench (3); Step S4, repeat step S3 until the depth of the trench (3) reaches the target depth and the number of heavily doped first conductivity type impurity implantation regions (4) on both sides of the trench (3) reaches the target number. Step S5: Deposit second conductivity type doped single crystal silicon (5) in the first main surface and trench (3) and perform CMP treatment; form second conductivity type columnar epitaxial layer (501) in the trench (3); thereby forming alternating first conductivity type columnar epitaxial layer and second conductivity type columnar epitaxial layer (501) in the first conductivity type epitaxial layer (2); the doping concentration of the second conductivity type columnar epitaxial layer (501) is greater than the doping concentration of the first conductivity type columnar epitaxial layer; Step S6: Selectively inject a second type of conductivity impurity into the first main surface and push it into a well to form a second type of conductivity well region (6) on the top of the second type of conductivity columnar epitaxial layer (501); the width of the second type of conductivity well region (6) is greater than the width of the second type of conductivity columnar epitaxial layer (501); Step S7, deposit a gate oxide layer (7) on the first main surface; Step S8: Conductive polysilicon is deposited on the first main surface and selectively etched to form gate polysilicon (8); Step S9: Selectively implant first conductivity type impurities into the first main surface and anneal it to form two spaced, heavily doped first conductivity type implantation regions (9) at the top of the second conductivity type well region (6); Step S10: Deposit an insulating dielectric layer (10) on the first main surface, and then selectively etch the hole structure to form the source contact hole (11) and the gate contact hole; Step S11: A second conductivity type impurity is injected through the source contact hole (11) and annealed to form a heavily doped second conductivity type injection region (12); the second conductivity type injection region (12) is distributed between two spaced heavily doped first conductivity type injection regions (9) in the second conductivity type well region (6) and extends below the two spaced heavily doped first conductivity type injection regions (9); Step S12: Deposit a metal layer on the insulating dielectric layer (10) and selectively etch it to form the source metal (13) and the gate metal; The source metal (13) is connected through the source contact hole (11) to two heavily doped first conductive type implanted regions (9) spaced apart in the second conductive type well region (6) at the top of the second conductive type columnar epitaxial layer (501), and to the heavily doped second conductive type implanted region (12) between the two heavily doped first conductive type implanted regions (9). The gate metal is connected to the gate polysilicon (8) through a gate contact hole; Step S13: Deposit drain metal on the second main surface.

7. The method for manufacturing a superjunction semiconductor power device as described in claim 6, characterized in that, The length of the heavily doped first conductivity type impurity implantation region (4) in the height direction ranges from 0.5 μm to 2 μm.

8. The method for manufacturing a superjunction semiconductor power device as described in claim 7, characterized in that, The length of the heavily doped first conductivity type impurity implantation region (4) in the height direction ranges from 1 μm to 1.5 μm.

9. The method for manufacturing a superjunction semiconductor power device as described in claim 6, characterized in that, The doping concentration of the heavily doped first conductivity type impurity implantation region (4) is 1.5 to 2.5 times that of the doping concentration of the second conductivity type columnar epitaxial region (501).

10. The method for manufacturing a superjunction semiconductor power device as described in claim 6, characterized in that, The number of heavily doped first conductivity type impurity implantation regions (4) on each sidewall of the trench (3) is 3 to 6.

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