SiC MOSFET with L-shaped source region structure

Abstract

The invention provides a SiC MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with an L-shaped source region structure, which comprises a substrate and a drift region arranged on the front surface of the substrate, and a first body region and a second body region are respectively arranged in limited regions on two sides of the drift region; a first base region, two first source regions and a second source region are arranged above the first body region; the two first source regions are respectively arranged above the first base region and on two side surfaces of the first body region; the second source region is arranged between and above the two first source regions; the first base region, the first source region and the second source region form an L shape. According to the invention, the L-shaped source region is arranged, so that the hole current diffusion area is increased to suppress source region hot spots, and the single-particle radiation resistance is achieved.

Description

Technical Field

[0001] This application relates to the field of power device technology, specifically to a SiC MOSFET with an L-shaped source region structure. Background Technology

[0002] SiC MOSFETs (Silicon Carbide Metal-Oxide-Semiconductor Field-Effect Transistors) have become one of the best candidates for next-generation high-frequency, high-efficiency, and high-power-density converters due to their low on-resistance and high switching speed. However, in the space environment, SiC MOSFETs face severe single-event failure caused by heavy ions and protons. After heavy ions are incident on the device, the movement of deposited charge carriers causes the device to lose its breakdown voltage in the picosecond range. Deposited electrons and source-injected electrons cause avalanche ionization at the epitaxial layer / substrate interface, resulting in localized material melting of the device, or avalanche ionization hole currents causing parasitic transistors to conduct, ultimately leading to thermal runaway of the device.

[0003] Furthermore, excessive hole current in the early stages can cause hot spots at the contact between the device's source metal and the SiC source region, leading to material degradation at the interface. Currently, traditional SiC MOSFETs suffer single-event burn-out at operating voltages below half their withstand voltage rating, making them unsuitable for direct application in space missions. Summary of the Invention

[0004] In view of this, this application provides a SiC MOSFET with an L-shaped source region structure. By improving the source structure, the source injection electrons during the transient process after single-particle incident are reduced, thereby reducing the electric field concentration formed by excessive non-equilibrium electrons at the epitaxial layer / substrate interface. This suppresses avalanche ionization and single-particle burn-off caused by subsequent parasitic transistor conduction and thermal runaway. At the same time, it suppresses hot spots in the source metal contact area caused by early hole current, thus solving the technical problems of easy thermal runaway and low radiation resistance of existing SiC MOSFETs.

[0005] This application provides a SiC MOSFET with an L-shaped source region structure, including: a substrate and a drift region disposed on the front side of the substrate, wherein a first body region and a second body region are respectively disposed in defined regions on both sides of the drift region; A first base region, two first source regions, and a second source region are disposed above the first body region; the two first source regions are respectively disposed above the first base region and on two sides of the first body region; the second source region is disposed between and above the two first source regions; the first base region, the first source region, and the second source region form an L-shape; A second base region, two third source regions, and a fourth source region are disposed above the second body region; the two third source regions are respectively disposed above the second base region and on two sides of the second body region; the fourth source region is disposed between and above the two third source regions; the second base region, the third source region, and the fourth source region form an L-shape.

[0006] In one possible implementation, the SiC MOSFET further includes a T-shaped insulating layer covering the drift region, the first source region, the second source region, the third source region, and the fourth source region.

[0007] In one possible implementation, the SiC MOSFET further includes: a rectangular first source metal and a rectangular second source metal, wherein the first source metal is in contact with the top of the first body region, the side of the first source region, the side of the second source region, and the side of the insulating layer; and the second source metal is in contact with the top of the second body region, the side of the third source region, the side of the fourth source region, and the side of the insulating layer.

[0008] In one possible implementation, the SiC MOSFET further includes a rectangular insulating layer covering the drift region, the first source region, the second source region, the third source region, and the fourth source region.

[0009] In one possible implementation, the SiC MOSFET further includes: an L-shaped first source metal and an L-shaped second source metal, wherein the first source metal is in contact with the top of the first body region, the side of the first source region, the side and top of the second source region, and the side of the insulating layer, respectively; and the second source metal is in contact with the top of the second body region, the side of the third source region, the side and top of the fourth source region, and the side of the insulating layer, respectively.

[0010] In one possible implementation, a polysilicon gate strip is disposed within the insulating layer, and a thickened arched gate is disposed below the middle of the polysilicon gate strip.

[0011] In one possible implementation, two polysilicon gate strips are disposed within the insulating layer, and oxide is filled between the two polysilicon gate strips.

[0012] In one possible implementation, a drain metal is disposed on the back side of the substrate.

[0013] In one possible implementation, the substrate, drift region, first base region, first source region, second base region, and third source region are all N-type doped; the first body region, second body region, second source region, and fourth source region are all P-type doped. The doping concentration of the first base region is lower than that of the first source region and the first body region; the doping concentration of the second source region is higher than that of the first base region, the first source region and the first body region.

[0014] In one possible implementation, an N-type doped buffer layer is provided between the drift region and the substrate, the doping concentration of the buffer layer being higher than the doping concentration of the drift region but lower than the doping concentration of the substrate.

[0015] This application reduces the injection of electrons into the source during the transient process after single-particle incident by improving the source structure, thereby reducing the electric field concentration formed by excessive non-equilibrium electrons at the epitaxial layer / substrate interface, and thus suppressing avalanche ionization and subsequent single-particle burn-out caused by parasitic transistor conduction and thermal runaway. At the same time, it suppresses hot spots in the source metal contact area caused by early hole current, thus enabling SiC MOSFETs to have radiation resistance and be applied in space missions. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 A schematic diagram of an L-shaped source region structure of a SiC MOSFET provided in this application embodiment; Figure 2 A schematic diagram of another L-shaped source region structure of SiC MOSFET provided in this application embodiment; Figure 3 A schematic diagram of the structure of a SiC MOSFET with an arched gate provided for an embodiment of this application; Figure 4 A schematic diagram of the structure of a SiC MOSFET with oxide as provided in an embodiment of this application; Figure 5 This is a schematic diagram of the structure of a SiC MOSFET with a buffer layer provided in an embodiment of this application.

[0018] Attached image labels: 101: Substrate; 102: Drift region; 103: First body region; 104: First base region; 105: First source region; 106: Second source region; 107: Second body region; 108: Second base region; 109: Third source region; 110: Fourth source region; 111: Insulation layer; 112: Polycrystalline silicon gate bar; 113: First source metal; 114: Second source metal; 115: Drain metal; 116: Arch bridge gate; 117: Oxide; 118: Buffer layer. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0020] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0021] The technical solutions provided in the embodiments of this application will be described below.

[0022] like Figure 1 As shown, this application embodiment provides a SiC MOSFET with an L-shaped source region structure, including: a substrate 101 and a drift region 102 disposed on the front side of the substrate 101, and a first body region 103 and a second body region 107 respectively disposed in the defined regions on both sides of the drift region 102; A first base region 104, two first source regions 105, and a second source region 106 are disposed above the first body region 103; the two first source regions 105 are respectively disposed above the first base region 104 and on two sides of the first body region 103; the second source region 106 is disposed between and above the two first source regions 105; the first base region 104, the first source regions 105, and the second source region 106 form an L-shape; A second base region 108, two third source regions 109, and a fourth source region 110 are disposed above the second body region 107. The two third source regions 109 are respectively disposed above the second base region 108 and on the two sides of the second body region 107. The fourth source region 110 is disposed between and above the two third source regions 109. The second base region 108, the third source regions 109, and the fourth source region 110 form an L-shape.

[0023] This embodiment achieves anti-single-event radiation capability by using the second source region and the first body region to generate a depletion effect on the first base region and the first source region under the source maximum injection condition, thereby suppressing the source electron injection during the single-event transient process, inhibiting the transient current and parasitic transistor conduction, and increasing the hole current diffusion area by making the source region L-shaped as a whole to suppress source region hot spots.

[0024] In some embodiments, such as Figure 1 As shown, the SiC MOSFET also includes a T-shaped insulating layer 111 covering the drift region 102, the first source region 105, the second source region 106, the third source region 109, and the fourth source region 110.

[0025] In some embodiments, such as Figure 1 As shown, the SiC MOSFET also includes: a rectangular first source metal 113 and a rectangular second source metal 114. The first source metal 113 is in contact with the top of the first body region 103, the first source region 105, the second source region 106 and the side of the insulating layer 111; the second source metal 114 is in contact with the top of the second body region 107, the third source region 109, the fourth source region 110 and the side of the insulating layer 111.

[0026] In some embodiments, such as Figure 2 As shown, the SiC MOSFET also includes a rectangular insulating layer 111 covering the drift region 102, the first source region 105, the second source region 106, the third source region 109, and the fourth source region 110.

[0027] In some embodiments, such as Figure 2 As shown, the SiC MOSFET further includes: an L-shaped first source metal 113 and an L-shaped second source metal 114. The first source metal 113 is in contact with the top of the first body region 103, the side of the first source region 105 and the second source region 106, and the side of the insulating layer 111, respectively. The second source metal 114 is in contact with the top of the second body region 107, the side of the third source region 109 and the fourth source region 110, and the side of the insulating layer 111, respectively.

[0028] In this embodiment, by replacing the insulating layer above the second source region with source metal, the area where the single-particle deposited hole current enters the source metal can be further increased, thereby suppressing source region hotspots caused by hole current.

[0029] In some embodiments, such as Figure 3 As shown, a polysilicon gate strip 112 is disposed within the insulating layer 111, and a locally thickened arch bridge gate 116 is disposed in the lower middle part of the polysilicon gate strip 112.

[0030] In some embodiments, such as Figure 4 As shown, two polysilicon gate strips 112 are disposed within the insulating layer 111, and oxide 117 is filled between the two polysilicon gate strips 112.

[0031] The two embodiments described above can reduce the maximum electric field strength experienced on the gate oxide of the device after a single-event incident event, thereby enabling the device to resist single-event gate failure.

[0032] In some embodiments, such as Figure 1 As shown, a drain metal 115 is disposed on the back side of the substrate 101.

[0033] The polysilicon gate bar, source metal, and drain metal respectively form the gate, source, and drain.

[0034] In some embodiments, substrate 101, drift region 102, first base region 104, first source region 105, second base region 108 and third source region 109 are all N-type doped; first body region 103, second body region 107, second source region 106 and fourth source region 110 are all P-type doped. The doping concentration of the first base region 104 is lower than that of the first source region 105 and the first bulk region 103; the doping concentration of the second source region 106 is higher than that of the first base region 104, the first source region 105 and the first bulk region 103; the doping concentration of the second base region 108 is lower than that of the third source region 109 and the second bulk region 107; and the doping concentration of the fourth source region 110 is higher than that of the second base region 108, the third source region 109 and the second bulk region 107.

[0035] In this embodiment, under source maximum implantation conditions, the second source region and the first body region of the P-type doped type deplete the first base region and the first source region of the N-type doped type. The fourth source region and the second body region of the P-type doped type deplete the second base region and the third source region of the N-type doped type.

[0036] In some embodiments, such as Figure 5 As shown, an N-type doped buffer layer 118 is provided between the drift region 102 and the substrate 101. The doping concentration of the buffer layer 118 is higher than that of the drift region 102 but lower than that of the substrate 101.

[0037] This embodiment, by setting an N-type doped buffer layer between the drift region and the substrate, can alleviate the electric field concentration caused by electron accumulation at the epitaxial / substrate interface, suppress avalanche ionization, and achieve single-particle hardening.

[0038] It should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0039] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. Multitasking and parallel processing may be advantageous in certain environments. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this application. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

Claims

1. A SiC MOSFET with an L-shaped source region structure, characterized in that, include: A substrate (101) and a drift region (102) disposed on the front side of the substrate (101), wherein a first body region (103) and a second body region (107) are respectively disposed in the defined regions on both sides of the drift region (102). A first base region (104), two first source regions (105), and a second source region (106) are disposed above the first body region (103); the two first source regions (105) are respectively disposed above the first base region (104) and on two sides of the first body region (103); the second source region (106) is disposed between and above the two first source regions (105); the first base region (104), the first source region (105), and the second source region (106) form an L-shape; A second base region (108), two third source regions (109), and a fourth source region (110) are provided above the second body region (107); the two third source regions (109) are respectively provided above the second base region (108) and on the two sides of the second body region (107); the fourth source region (110) is provided between and above the two third source regions (109); the second base region (108), the third source region (109), and the fourth source region (110) form an L-shape.

2. The SiC MOSFET according to claim 1, characterized in that, The SiC MOSFET further includes a T-shaped insulating layer (111) covering the drift region (102), the first source region (105), the second source region (106), the third source region (109), and the fourth source region (110).

3. The SiC MOSFET according to claim 2, characterized in that, The SiC MOSFET further includes: a rectangular first source metal (113) and a rectangular second source metal (114). The first source metal (113) is in contact with the top of the first body region (103), the side of the first source region (105), the side of the second source region (106), and the side of the insulating layer (111). The second source metal (114) is in contact with the top of the second body region (107), the side of the third source region (109), the side of the fourth source region (110), and the side of the insulating layer (111).

4. The SiC MOSFET according to claim 1, characterized in that, The SiC MOSFET further includes a rectangular insulating layer (111) covering the drift region (102), the first source region (105), the second source region (106), the third source region (109), and the fourth source region (110).

5. The SiC MOSFET according to claim 4, characterized in that, The SiC MOSFET further includes: an L-shaped first source metal (113) and an L-shaped second source metal (114), wherein the first source metal (113) is in contact with the top of the first body region (103), the side of the first source region (105), the side and top of the second source region (106), and the side of the insulating layer (111); wherein the second source metal (114) is in contact with the top of the second body region (107), the side of the third source region (109), the side and top of the fourth source region (110), and the side of the insulating layer (111).

6. The SiC MOSFET according to claim 2 or 4, characterized in that, A polysilicon gate strip (112) is provided in the insulating layer (111), and a thickened arch bridge gate (116) is provided in the middle and lower part of the polysilicon gate strip (112).

7. The SiC MOSFET according to claim 2 or 4, characterized in that, Two polysilicon gate strips (112) are disposed within the insulating layer (111), and oxide (117) is filled between the two polysilicon gate strips (112).

8. The SiC MOSFET according to claim 1, characterized in that, A drain metal (115) is disposed on the back side of the substrate (101).

9. The SiC MOSFET according to claim 1, characterized in that, The substrate (101), drift region (102), first base region (104), first source region (105), second base region (108) and third source region (109) are all N-type doped; the first body region (103), second body region (107), second source region (106) and fourth source region (110) are all P-type doped. The doping concentration of the first base region (104) is lower than that of the first source region (105) and the first body region (103); the doping concentration of the second source region (106) is higher than that of the first base region (104), the first source region (105) and the first body region (103).

10. The SiC MOSFET according to claim 1, characterized in that, An N-type doped buffer layer (118) is provided between the drift region (102) and the substrate (101). The doping concentration of the buffer layer (118) is higher than that of the drift region (102) and lower than that of the substrate (101).

Images