Design method of low-inductance Si / SiC hybrid half-bridge power module structure

Abstract

The invention belongs to the technical field of power electronic power module design and optimization, and relates to a low-inductance Si / SiC hybrid half-bridge power module structure design method. Comprising the following steps: designing a Si / SiC hybrid half-bridge power module, and selecting a high-capacity Si IGB to be matched with a low-capacity SiC MOSFET; differentiated design is carried out on a chip solder layer in the hybrid half-bridge power module, nano-silver with excellent comprehensive performance is sintered at an MOSFET (Metal Oxide Semiconductor Field Effect Transistor) to serve as the solder layer, and 96.5 Sn3. 5Ag solder is selected at an IGBT (Insulated Gate Bipolar Translator); designing a heat dissipation substrate in the hybrid half-bridge power module; power module terminals are designed, DC + and DC-power terminals are adjacently arranged, and the power terminals are connected with the DBC lining plate in a two-point welding mode; and optimizing a commutation loop between module bridge arms and an internal commutation loop. By optimizing the internal structure and layout of the module, the stray inductance is remarkably reduced, and the switching performance and reliability of the hybrid module are improved.

Description

Technical Field

[0001] This invention belongs to the field of power electronic power module design and optimization technology, and relates to a low-inductance Si / SiC hybrid half-bridge power module structure design method. Background Technology

[0002] In the field of power electronics, traditional silicon (Si) devices, while having mature manufacturing processes and low costs, suffer from high switching losses, limiting the potential for increased operating frequencies. Silicon carbide (SiC) devices, on the other hand, offer fast switching speeds and low losses, improving efficiency, but are more expensive. Against this backdrop, hybrid Si / SiC devices, which combine the advantages of both technologies and offer a balance between high performance and low cost, have emerged.

[0003] In high-power applications, the dispersed use of multiple discrete devices presents a series of challenges, including complex circuit design, high parasitic inductance, reduced power density, and more complex thermal management. To further leverage the performance potential of hybrid devices, specialized hybrid module designs are needed. By increasing power density through high integration, a comprehensive optimization of high performance, low cost, and high reliability can be achieved.

[0004] Currently, significant progress has been made in the theoretical construction of single heterogeneous hybrid devices. However, a systematic design method for Si / SiC hybrid power modules is still in the initial exploratory stage, and a complete and reliable design system and standardized process have not yet been formed. Structures such as power terminals, bonding wires, and DBC copper layers in the module introduce stray inductance, leading to a series of problems such as turn-off overvoltage, increased electromagnetic interference, and increased switching losses. The stray inductance in hybrid modules is even more severe, affecting not only the commutation between upper and lower bridge arms but also the commutation within the hybrid device itself. Therefore, optimizing stray inductance in hybrid modules is a major challenge in the design process. This invention proposes a structural design method for constructing a low-inductance Si / SiC hybrid half-bridge power module. By optimizing the internal structure and layout of the module, stray inductance is significantly reduced, improving the switching performance and reliability of the hybrid module. Summary of the Invention

[0005] To achieve the above objectives, the present invention provides a method for designing a low-inductance Si / SiC hybrid half-bridge power module structure, comprising: Design a Si / SiC hybrid half-bridge power module, using a large-capacity Si IGB paired with a small-capacity SiC MOSFET; The chip solder layer in the hybrid half-bridge power module is designed differently. The MOSFET uses nano-silver sintering with excellent comprehensive performance as the solder layer, and the IGBT uses 96.5Sn3.5Ag solder. Design a heat dissipation substrate for the hybrid half-bridge power module; The power module terminals are designed with DC+ and DC- power terminals arranged adjacent to each other. The power terminals are connected to the DBC backing plate by two-point soldering. The converter circuits between module bridge arms and the internal converter circuits are optimized.

[0006] Furthermore, the hybrid half-bridge power module includes four chips. The upper and lower half-bridges each include a high-capacity IGBT and a low-capacity MOSFET. The upper surface of each chip is directly connected to another DBC substrate via bonding wires. The upper and lower half-bridge IGBTs are connected to the DBC board via 96.5Sn3.5Ag solder. The lower half-bridge hybrid device is connected to the DBC board via nano-silver sintered solder. The DC+, DC-, and AC terminals are respectively soldered to the corresponding DBC boards. Electrical conduction is achieved by connecting the chips and the DBC board via bonding wires.

[0007] Furthermore, the heat dissipation substrate is made of copper and has a thickness of 4.5mm.

[0008] Furthermore, the spacing between the DC+ and DC- power terminals is set to 4mm.

[0009] Furthermore, the upper bridge arm MOSFET chip is located on the right side of the DC+ DBC board, and the lower bridge arm MOSFET chip is located on the left side of the AC DBC board. The two connection points of the DC+ power terminal are respectively located on the DC+ DBC board, near the upper and lower sides of the upper bridge arm MOSFET and IGBT chip. The two connection points of the DC- power terminal are located on the DC- DBC board, near the upper and lower sides of the lower bridge arm MOSFET and IGBT chip. The AC power terminal connection point is located on the AC DBC board to the right of the lower bridge arm hybrid device.

[0010] The beneficial effects of this invention are: (1) This invention proposes a low-inductance Si / SiC hybrid half-bridge power module structure design method, which comprehensively considers the electrical, thermal, and mechanical performance of the hybrid module and conducts detailed design for each part of the module. It mainly includes: chip solder difference design, heat dissipation substrate design, power module terminal design, optimization of commutation loop between bridge arms and optimization of commutation loop inside hybrid devices, which effectively reduces the stray inductance of the commutation loop between bridge arms and the stray inductance of the commutation loop inside the upper and lower bridge arm devices.

[0011] (2)For the unique switching process of Si and SiC hybrid devices, the present invention conducts low stray inductance design and structural optimization from two aspects: the commutation loop between arms and the commutation loop inside the hybrid device. Based on the working characteristics of MOSFET turning on first and then turning off and its body diode for freewheeling, the commutation loop between arms is optimized with refined layout; at the same time, for the current transfer path between MOSFET and IGBT during the internal commutation process of the hybrid device, the present invention adds bonding wire interconnection between the upper surfaces of the two chips to shorten the commutation path, reduce the stray inductance of the loop, accelerate the commutation speed, reduce the commutation loss, and ultimately improve the overall efficiency of the module. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0013] Figure 1 is a topological schematic diagram of a Si / SiC hybrid half-bridge power module and the key loop of the module, Figure 1 The red path in (a) is the commutation loop between the upper and lower arms, Figure 1 The red path in (b) is the commutation loop inside the hybrid device; Figure 2 is a diagram showing the influence of the thickness of the heat dissipation substrate on the maximum junction temperature of the chips in the hybrid module; Figure 3 is a schematic diagram of the candidate layout of the chips in the hybrid module, Figure 3 (a) is the traditional "one" - shaped layout 1, Figure 3 (b) is the traditional "one" - shaped layout 2, Figure 3 (c) is the "pin" - shaped layout 1, Figure 3 (d) is the "pin" - shaped layout 2; Figure 4 is a schematic diagram of the final DBC board division and chip layout in the hybrid module; Figure 5 is a schematic diagram of the power terminal arrangement in the hybrid module; Figure 6 is a structural optimization diagram of the commutation loop inside the hybrid device in the hybrid module; Figure 1 The marks shown in the figure: 1 and 2 are the upper - half - bridge IGBT and the upper - half - bridge MOS respectively, and 3 and 4 are the lower - half - bridge IGBT and the lower - half - bridge MOS respectively. DETAILED DESCRIPTION OF THE EMBODIMENTS <00​To facilitate understanding by those skilled in the art, the present invention will be further described below with reference to embodiments and accompanying drawings. The content mentioned in the embodiments is not intended to limit the present invention.

[0015] This invention proposes a low-inductance Si / SiC hybrid half-bridge power module structure design method, including: Step S1: Design a Si / SiC hybrid half-bridge power module, selecting a large-capacity Si IGBT paired with a small-capacity SiC MOSFET. The hybrid half-bridge module uses a hybrid device structure consisting of a high-capacity Si IGBT and a low-capacity SiC MOSFET connected in parallel as the bridge arm. The Si IGBT is rated at 1200V / 120A, and the SiC MOSFET is rated at 1200V / 50A. Its overall structure is similar to that of a traditional power module, including a substrate, a DBC substrate, a solder layer, and power terminals. Due to the use of heterogeneous device combinations and a hybrid switching operating mode, this type of module requires special attention during design to optimize heat dissipation and improve stray inductance in critical circuits, ensuring high efficiency and higher reliability. Figure 4 As shown, the upper and lower half-bridge IGBTs are connected in parallel to form an upper-bridge hybrid device, which is connected to the DBC board via 96.5Sn3.5Ag solder. The lower half-bridge hybrid device is connected to the DBC board via Sinter Ag solder. The DC+, DC-, and AC terminals are soldered to their respective DBC boards. Electrical conduction is achieved by connecting the chips to the DBC board via bonding wires. The upper-bridge MOSFET chip is located on the right side of the DC+ DBC board, while the lower-bridge MOSFET chip is located on the left side of the AC DBC board.

[0016] Step S2: Differentiated design of the chip solder layer within the hybrid half-bridge power module. For the MOSFETs, high-performance nano-silver sintering is used as the solder layer, while for the IGBTs, 96.5Sn3.5Ag solder is selected. In hybrid power modules, MOSFETs, due to bearing most of the switching losses and having a smaller chip area, often have higher junction temperatures and more significant thermal stress than IGBTs. Therefore, they have stricter requirements for heat dissipation and structural reliability. This invention selects high-performance Sinter Ag (nano-silver sintering) as the solder layer for the MOSFETs to meet their higher heat dissipation and thermal stress resistance requirements; while for the IGBTs, cost-effective 96.5Sn3.5Ag solder is selected to control costs while ensuring basic heat dissipation and mechanical performance.

[0017] Step S3: Design the heat dissipation substrate inside the hybrid half-bridge power module; the heat dissipation substrate of the hybrid module is a copper substrate.

[0018] This invention analyzed the effect of different substrate thicknesses on the maximum junction temperature of the chip using ANSYS thermal simulation, and the results are as follows: Figure 2 As shown in the thermal simulation of the hybrid module, when the copper substrate thickness increases from 1 mm to 9 mm, the chip junction temperature exhibits a trend of first decreasing and then stabilizing. In the thin substrate stage (1-3 mm), the increase in substrate thickness significantly improves the lateral heat diffusion capability. This results in a more uniform heat distribution, effectively reducing heat flux density and contact thermal resistance, leading to a significant decrease in junction temperature. When the thickness exceeds a critical value (3-5 mm), the marginal benefit of lateral heat diffusion diminishes. At this point, the thermal resistance is mainly dominated by the heat sink performance and interface material, while the increase in longitudinal conduction distance partially offsets the benefits, causing the junction temperature to tend to stabilize. Based on the above patterns, the thickness of the heat dissipation copper substrate in this invention is 4.5 mm.

[0019] Step S4: Design the power module terminals. The DC+ and DC- power terminals are arranged adjacent to each other. The power terminals are connected to the DBC backing plate by two-point soldering. When two adjacent conductors carry opposite currents, a negative mutual inductance effect is generated, thereby reducing the stray inductance of the circuit. Based on the principle of mutual inductance cancellation, this invention arranges the DC+ and DC- power terminals adjacent to each other. Considering process feasibility and insulation safety, the terminal spacing is set to 4mm to balance leakage protection and electromagnetic performance optimization. Simultaneously, the power terminals are connected to the DBC substrate using a two-point welding method, which not only helps reduce their own parasitic inductance and shorten the commutation path between bridge arms, but also enhances mechanical stability. This terminal design effectively suppresses voltage overshoot during module switching, reduces the impact of stray inductance on the circuit, and thus improves the stability and reliability of the module under high-frequency operating conditions.

[0020] like Figure 5 As shown, the two connection points of the DC+ power terminal are located on the DC+ DBC board, adjacent to the upper and lower sides of the upper bridge arm MOSFET and IGBT chip, respectively; the two connection points of the DC- power terminal are located on the DC- DBC board, near the upper and lower sides of the lower bridge arm MOSFET and IGBT chip. This layout helps to minimize the length of the upper and lower bridge arm commutation loop from DC+ to the upper MOSFET, then to the lower MOSFET, and finally to DC-. Furthermore, the AC power terminal connection point is located on the AC DBC board to the right of the lower bridge arm hybrid device.

[0021] Step S5: Optimize the converter circuits between module bridge arms and the internal converter circuits.

[0022] Figure 1 The diagram shows the topology of a hybrid half-bridge power module of Si and SiC and the key circuits of the module. In (a), the red path is the commutation circuit between the upper and lower bridge arms, and in (c), the red path is the commutation circuit inside the hybrid device.

[0023] like Figure 3 As shown, several candidate layouts of the modules are presented, and the commutation paths between the hybrid module bridge arms in this layout are also marked. As Figure 3 shown in (a), the bonding wire on the upper surface of the Si IGBT is connected to the SiC MOSFET, while the bonding wire on the upper surface of the SiC MOSFET is connected to the DBC substrate of the lower half bridge arm. When both the IGBT and MOSFET in the hybrid device are fully conducting, the currents of both need to flow through the bonding wire between the MOSFET and the DBC of the lower half bridge. Since the hybrid device usually adopts the working mode of turning on the MOSFET first and then turning it off, and uses the body diode of the MOSFET for freewheeling, the path of the commutation loop between the bridge arms during the operation of the module will be the shortest at this time. However, limited by the pad area of the small-capacity SiC MOSFET and the current-carrying capacity of the bonding wire diameter, this connection method is difficult to meet the conduction requirements of all working currents, which may lead to local overcurrent. Therefore, this type of layout should be excluded in the actual design.

[0024] As Figure 3 shown in (b), this is another "one"-shaped layout. Compared with Figure 3 that in (a), it effectively avoids the local overcurrent problem that may occur when both devices are fully conducting. The current all flows through the bonding wire between the upper surface of the large-capacity Si IGBT and the DBC substrate of the lower half bridge. Since the IGBT pad area is large, its bonding wire has sufficient current-carrying capacity. However, this layout also brings new challenges: the commutation loop path between the hybrid module bridge arms will be longer. Compared with Figure 3 that in (a), the current path needs to pass through two additional bonding wires, which will increase the stray inductance and thus affect the switching performance of the module.

[0025] Figure 3 (c) and Figure 3 (d) show two "pin"-shaped layout methods. Different from the "one"-shaped layout, in this type of layout, the upper surface of each chip is directly connected to another DBC substrate through a bonding wire, and there is no interconnection between the chips. This structure can effectively avoid the problem of local current overload whether a single chip is conducting or two chips are conducting simultaneously. By comparing the commutation loops between the bridge arms of the two, it can be found that Figure 3 in (d), the SiC MOSFET chips of the upper and lower bridge arms are both arranged on the same side, and its current path is shorter, which helps to reduce the stray inductance and thus improve the stability of the module under high-frequency working conditions. Therefore, considering the comprehensive electrical performance and reliability, the layout scheme shown in Figure 3(d) can be adopted.

[0026] Optimization of the internal commutation loop in hybrid devices: Hybrid devices employ a SiC MOSFET turn-on-first, turn-off-later operation: the MOSFET turns on first and carries the entire load current. After the IGBT turns on with a delay, the load current needs to be transferred from the MOSFET to the IGBT; this process is the internal commutation process of the hybrid device. During this process, the MOSFET incurs additional conduction losses. To reduce these losses and improve the operational stability of the hybrid device, the stray inductance of the internal commutation loop must be optimized. For example... Figure 6 As shown, this invention effectively shortens the commutation path and reduces stray inductance by adding bonding wires between the MOSFET and the upper surface of the IGBT chip. This optimization can accelerate the commutation speed, reduce commutation losses, and ultimately improve the overall efficiency of the module.

[0027] Validity verification: The effectiveness of the Si / SiC hybrid half-bridge power module designed in this invention was verified. The geometric model was imported into ANSYS EM, material properties were assigned, and corresponding excitation conditions were set. Stray inductance extraction simulation was performed at a frequency of 100 MHz. As shown in Table 1, the simulation results show that the stray inductance value of the inter-arm commutation loop (path: DC+ → upper half-bridge MOSFET → lower half-bridge MOSFET → DC-) is 8.13968 nH; when the internal commutation loop of the hybrid device is not optimized, the stray inductance of the internal commutation loop of the upper half-bridge device is 2.06122 nH, and the stray inductance of the internal commutation loop of the lower half-bridge device is 3.57439 nH; after the internal commutation loop of the device is optimized, the stray inductance of the internal commutation loop of the upper half-bridge device is 0.96927 nH, and the stray inductance of the internal commutation loop of the lower half-bridge device is 1.26978 nH, which are reduced by 53.0% and 64.5% respectively compared with the unoptimized values. The above results verify that the proposed layout and structure optimization measures can effectively reduce stray inductance in critical circuits, which helps to improve the dynamic performance and switching efficiency of the module.

[0028] Table 1 Stray inductance values ​​for each critical circuit ; In summary, the technical solution proposed in this invention can effectively reduce stray inductance in critical circuits, which helps to improve the dynamic performance and switching efficiency of the module.

[0029] The above embodiments are preferred implementations of the present invention. In addition, the present invention can be implemented in other ways. Any obvious substitutions without departing from the concept of the present technical solution are within the protection scope of the present invention.

[0030] To facilitate understanding by those skilled in the art of the improvements of this invention over the prior art, some of the accompanying drawings and descriptions have been simplified, and for clarity, some other elements have been omitted from this application. Those skilled in the art should realize that these omitted elements may also constitute the content of this invention.

Claims

1. A method for designing a low-inductance Si / SiC hybrid half-bridge power module structure, characterized in that, include: Design a Si / SiC hybrid half-bridge power module, using a large-capacity Si IGB paired with a small-capacity SiC MOSFET; The chip solder layer in the hybrid half-bridge power module is designed differently. The MOSFET uses nano-silver sintering with excellent comprehensive performance as the solder layer, and the IGBT uses 96.5Sn3.5Ag solder. Design a heat dissipation substrate for the hybrid half-bridge power module; The power module terminals are designed with DC+ and DC- power terminals arranged adjacent to each other. The power terminals are connected to the DBC backing plate by two-point soldering. The converter circuits between module bridge arms and the internal converter circuits are optimized.

2. The low-inductance Si / SiC hybrid half-bridge power module structure design method as described in claim 1, characterized in that, The hybrid half-bridge power module includes four chips. The upper and lower half-bridges each include a high-capacity IGBT and a low-capacity MOSFET. The upper surface of each chip is directly connected to another DBC substrate via bonding wires. The upper and lower half-bridge IGBTs are connected to the DBC board via 96.5Sn3.5Ag solder. The hybrid device in the lower half-bridge is connected to the DBC board via nano-silver sintered solder. The DC+, DC-, and AC terminals are soldered to their respective DBC boards. Electrical conduction is achieved by connecting the chips to the DBC board via bonding wires.

3. The low-inductance Si / SiC hybrid half-bridge power module structure design method as described in claim 2, characterized in that, The heat dissipation substrate is made of copper and has a thickness of 4.5mm.

4. The low-inductance Si / SiC hybrid half-bridge power module structure design method as described in claim 3, characterized in that, The spacing between the DC+ and DC- power terminals is set to 4mm.

5. The low-inductance Si / SiC hybrid half-bridge power module structure design method as described in claim 4, characterized in that, The upper bridge arm MOSFET chip is located on the right side of the DC+ DBC board, and the lower bridge arm MOSFET chip is located on the left side of the AC DBC board. The two connection points of the DC+ power terminal are respectively located on the DC+ DBC board, near the upper and lower sides of the upper bridge arm MOSFET and IGBT chip. The two connection points of the DC- power terminal are located on the DC- DBC board, near the upper and lower sides of the lower bridge arm MOSFET and IGBT chip. The AC power terminal connection point is located on the AC DBC board to the right of the lower bridge arm hybrid device.

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