Semiconductor structure and forming method thereof

Abstract

A method of forming a semiconductor structure includes forming a semiconductor region, forming a gate spacer over the semiconductor region, forming a source / drain region alongside the semiconductor region, where the source / drain region is p-type; and forming a gate dielectric over the semiconductor region. A gate dielectric is formed in a space between opposing portions of the gate spacer. A ruthenium oxide layer is formed over the gate dielectric and is part of a work function layer of the gate electrode. The method further includes doping silicon into the ruthenium oxide layer. The embodiment of the invention also provides a semiconductor structure.

Description

Technical Field

[0001] Embodiments of this disclosure relate to semiconductor structures and methods of forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor layer on a semiconductor substrate, and then using photolithography to pattern the individual material layers to form circuit components and elements on the semiconductor substrate.

[0003] The semiconductor industry continuously improves the integration density of individual electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum part size, which allows more components to be integrated into a given area. However, as the minimum part size decreases, additional problems arise and need to be addressed. Summary of the Invention

[0004] Some embodiments of this disclosure provide a method for forming a semiconductor structure, the method comprising: forming a semiconductor region; forming a gate spacer over the semiconductor region; forming a source / drain region adjacent to the semiconductor region, wherein the source / drain region is p-type; forming a gate dielectric over the semiconductor region, wherein the gate dielectric is formed in a gap between opposing portions of the gate spacer; forming a first ruthenium oxide layer, wherein the first ruthenium oxide layer is located over the gate dielectric, and wherein the first ruthenium oxide layer serves as part of a work function layer of a gate electrode; and doping silicon into the first ruthenium oxide layer.

[0005] Other embodiments of this disclosure provide a method for forming a semiconductor structure, the method comprising: forming a plurality of semiconductor layers, wherein upper semiconductor layers of the plurality of semiconductor layers overlap with corresponding lower semiconductor layers of the plurality of semiconductor layers; forming a gate dielectric surrounding the plurality of semiconductor layers; depositing a first ruthenium oxide layer comprising a plurality of portions over the gate dielectric; depositing a first silicon oxide layer over the first ruthenium oxide layer; depositing a second ruthenium oxide layer over the first silicon oxide layer; and planarizing the second ruthenium oxide layer, the first silicon oxide layer, and the first ruthenium oxide layer, wherein the remaining portions of the second ruthenium oxide layer, the first silicon oxide layer, and the first ruthenium oxide layer form a portion of a first gate electrode of a transistor.

[0006] Another embodiment of this disclosure provides a semiconductor structure including: a first transistor, the first transistor including: a semiconductor region; a gate spacer located above the semiconductor region; a gate dielectric located above the semiconductor region and between an opposite portion of the gate spacer; a gate electrode including: a first ruthenium oxide layer located above the gate dielectric, wherein the first ruthenium oxide layer includes silicon; and a first source / drain region located adjacent to the gate spacer. Attached Figure Description

[0007] The aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 A perspective view of an exemplary complementary field-effect transistor (CFET) according to some embodiments is shown.

[0009] Figures 2 to 16A and Figure 16B This is a view of an intermediate stage in the manufacturing of a CFET according to some embodiments.

[0010] Figures 17 to 23 This is a view of an intermediate stage in the fabrication of a CFET gate stack according to some embodiments.

[0011] Figures 24 to 25 These are outline diagrams of silicon and ruthenium according to some embodiments.

[0012] Figure 26 and Figure 27 A flowchart illustrating the formation of a CFET according to some embodiments is shown. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or instances of various components for implementing this application. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Additionally, reference numerals and / or characters may be repeated in various instances of this disclosure. This repetition is for clarity and simplicity and does not, in itself, indicate a relationship between the individual embodiments and / or configurations discussed.

[0014] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to encompass different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0015] Complementary field-effect transistor (CFET) structures and methods for forming them are provided. Throughout the description, the terms "FET" and "transistor" are used interchangeably. According to some embodiments, ruthenium oxide is used as the work function layer of the PFET, and silicon (or silicon oxide) is used to trap oxygen in the ruthenium oxide, making it unlikely that the ruthenium oxide will be reduced to elemental ruthenium.

[0016] It should be understood that while gate-all-around (GAA) transistors (such as nanostructure FETs) have been discussed, the concepts of this disclosure can also be applied to the formation of other types of transistors, such as planar transistors, fin field-effect transistors (FiNFETs), etc.

[0017] Figure 1 Examples of CFET 10 (including FET (transistor) 10U and 10L) according to some embodiments are shown. Figure 1 This is a 3D view, in which some components of the CFET have been omitted for ease of explanation.

[0018] A CFET comprises multiple vertically stacked FETs. For example, a CFET may include a lower nanostructure FET 10L of a first device type (e.g., n-type / p-type) and an upper nanostructure FET 10U of a second device type (e.g., p-type / n-type). The nanostructure FETs 10U and 10L include semiconductor nanostructures 26' (including a lower semiconductor nanostructure 26'L and an upper semiconductor nanostructure 26'U), wherein the semiconductor nanostructure 26' serves as the channel region of the nanostructure FET. The lower semiconductor nanostructure 26'L is used for the lower nanostructure FET 10L, and the upper semiconductor nanostructure 26'U is used for the upper nanostructure FET 10U.

[0019] A gate dielectric 78 surrounds the corresponding semiconductor nanostructure 26'. Gate electrodes 80 (including a lower gate electrode 80L and an upper gate electrode 80U) are located above the gate dielectric 78. Source / drain regions 62 (including a lower source / drain region 62L and an upper source / drain region 62U) are disposed on opposite sides of the gate dielectric 78 and the corresponding gate electrode 80. Depending on the context, the source / drain regions may individually or jointly indicate the source or drain. Isolation components (not shown) may be formed to separate the desired source / drain regions 62 and / or the desired gate electrode 80.

[0020] Figure 1 Reference cross sections used in subsequent figures are further illustrated. Cross section A-A' is a vertical cross section parallel to the longitudinal axis of the semiconductor nanostructure 26' of the CFET and in the direction of current flow, for example, between the source / drain regions 62 of the CFET. Cross section B-B' is a vertical cross section perpendicular to cross section A-A' and along the longitudinal axis of the gate electrode 80 of the CFET. For clarity, subsequent figures may refer to these reference cross sections.

[0021] Figures 2 to 23 The formation of a CFET according to some embodiments is shown (e.g.) Figure 1 A schematic cross-sectional view of the intermediate stage. Also... Figure 26 and Figure 27 The process flow shown schematically illustrates the corresponding process. In the following discussion, unless otherwise stated, figures followed by the letter "A" indicate a process along the […]. Figure 1 The diagram shows a vertical section similar to the vertical reference section A-A'. The figure following the number with the letter "B" indicates a section along the vertical reference section A-A'. Figure 1 A cross-sectional view of a section similar to the vertical reference section B-B' in the diagram.

[0022] exist Figure 2 The image shows a wafer 2 including a substrate 20. The substrate 20 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., and can be doped (e.g., with p-type or n-type dopants) or undoped. The SOI substrate can include a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide layer (BOX), a silicon oxide layer, etc. An insulating layer is provided on the substrate, such as a silicon substrate or a glass substrate. Other substrates, such as multilayer substrates or gradient substrates, can also be used. In some embodiments, the semiconductor material of the substrate 20 can include silicon, germanium, carbon-doped silicon, III-V compound semiconductors, etc., or combinations thereof.

[0023] A multilayer stack 22 is formed on top of the substrate 20. Figure 26In the process flow 200 shown, the corresponding process is indicated as process 202. The multilayer stack 22 includes alternating dummy semiconductor layers 24 (including dummy semiconductor layers 24A and 24B) and semiconductor layers 26 (including a lower semiconductor layer 26L and an upper semiconductor layer 26U). The lower semiconductor layer 26L and the upper semiconductor layer 26U are used to form the lower FET and the upper FET, respectively.

[0024] Suitable wells (not shown separately) can be formed in the lower semiconductor layer 26L and the upper semiconductor layer 26U. For example, semiconductor layers 26L and 26U can be in-situ doped (during epitaxial growth) and / or implanted to achieve the desired conductivity type.

[0025] In the example shown, the multilayer stack 22 includes six dummy semiconductor layers 24 and six semiconductor layers 26. It should be understood that the multilayer stack 22 may include any number of dummy semiconductor layers 24 and semiconductor layers 26. Each layer of the multilayer stack 22 may be grown using processes such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), or deposited using processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0026] The dummy semiconductor layer 24A is formed of a first semiconductor material, and the dummy semiconductor layer 24B is formed of a second semiconductor material different from the first semiconductor material. The first and second semiconductor materials can be selected from candidate semiconductor materials of the substrate 20. The first and second semiconductor materials have high etch selectivity relative to each other. Thus, in subsequent processes, the dummy semiconductor layer 24B can be removed at a faster rate than the dummy semiconductor layer 24A.

[0027] Semiconductor layer 26 (including lower semiconductor layer 26L and upper semiconductor layer 26U) is formed of one or more semiconductor materials. The semiconductor material can be selected from candidate semiconductor materials of substrate 20. Lower semiconductor layer 26L and upper semiconductor layer 26U can be formed of the same semiconductor material, or they can be formed of different semiconductor materials.

[0028] In some embodiments, the pseudo-semiconductor layer 24A is formed of or contains silicon germanium, the semiconductor layer 26 is formed of silicon, and the pseudo-semiconductor layer 24B may be formed of germanium or silicon germanium having a higher percentage of germanium atoms than the semiconductor layer 24A.

[0029] exist Figure 3 In this process, a multilayer stack 22 and a substrate 20 are patterned to form a semiconductor strip 28. Figure 26In the process flow 200 shown, the corresponding process is indicated as process 204. Each semiconductor strip 28 includes a semiconductor strip 20' (a portion of the original substrate 20) and a multilayer stack 22', which is the remaining portion of the multilayer stack 22. Hereinafter, the remaining portion 22' of the multilayer stack 22 is referred to as a nanostructure, indicated by a corresponding reference numeral followed by an apostrophe. Accordingly, the multilayer stack 22' includes pseudo-nanostructures 24'A and 24'B, a lower semiconductor nanostructure 26'L, an intermediate semiconductor nanostructure 26'M, and a upper semiconductor nanostructure 26'U.

[0030] Etching can be performed using any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. The etching can be anisotropic. Pseudo-nanostructures 24'A and 24'B can be further collectively referred to as pseudo-nanostructure 24'. The lower semiconductor nanostructure 26'L and the upper semiconductor nanostructure 26'U can be further collectively referred to as semiconductor nanostructure 26'.

[0031] The lower semiconductor nanostructure 26'L will serve as the channel region of the lower nanostructure FET in the CFET. The upper semiconductor nanostructure 26'U will serve as the channel region of the upper nanostructure FET in the CFET. The intermediate semiconductor nanostructure 26'M is a semiconductor nanostructure 26' located directly above / below (e.g., in contact with) the pseudo nanostructure 24'B. The intermediate semiconductor nanostructure 26'M can be used for isolation and can serve as or not serve as the channel region of the CFET. The pseudo nanostructure 24'B will subsequently be replaced with an isolation structure. The isolation structure and the intermediate semiconductor nanostructure 26'M can define the boundaries between the lower and upper nanostructure FETs.

[0032] exist Figure 4 An isolation region 32 is formed above the substrate 20 and between adjacent semiconductor strips 28. Figure 26 In the illustrated process flow 200, the corresponding process is shown as process 205. The isolation region 32 may include a dielectric pad and a dielectric material located above the dielectric pad. The isolation region 32 is then recessed. Some upper portions of the semiconductor strip 28 (including multilayer stack 22') protrude above the remaining isolation region 32 to form protruding fins 34.

[0033] Then a pseudo-dielectric layer 36 is formed on the protruding fin 34. Figure 26In the process flow 200 shown, the corresponding process is shown as process 206. The pseudo dielectric layer 36 may be formed or comprised of, for example, silicon oxide, silicon nitride, combinations thereof, etc., and the pseudo dielectric layer 36 may be deposited or thermally grown according to acceptable techniques.

[0034] A dummy gate layer 38 is formed above the dummy dielectric layer 36. Figure 26 In the illustrated process flow 200, the corresponding process is shown as process 208. The dummy gate layer 38 can be deposited using, for example, physical vapor deposition (PVD), CVD, or other techniques, and then planarized using a process such as CMP. The material of the dummy gate layer 38 can be conductive or non-conductive and can be selected from the group consisting of amorphous silicon, polycrystalline silicon (polycrystalline silicon), polycrystalline silicon germanium (polycrystalline SiGe), etc. A mask layer 40 is formed over the planarized dummy gate layer 38, and the mask layer 40 can include, for example, silicon nitride, silicon oxynitride, etc.

[0035] Next, the mask layer 40 can be patterned using photolithography and etching processes to form a mask. Then, the mask is used to etch and pattern the dummy gate layer 38, and possibly the dummy dielectric layer 36. The resulting structure is as follows: Figure 5 As shown. The remaining portions of the mask layer 40, the dummy gate layer 38, and the dummy dielectric layer 36 form the dummy gate stack 42.

[0036] exist Figure 5 In this configuration, a gate spacer 44 is formed above the multilayer stack 22' and on the exposed sidewalls of the dummy gate stack 42. The gate spacer 44 can be formed by conformally forming one or more dielectric layers and subsequently anisotropically etching the dielectric layers. Suitable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., and can be formed by deposition processes such as CVD, ALD, etc.

[0037] Then, source / drain grooves 46 are formed in semiconductor strip 28. Figure 26 In the process flow 200 shown, the corresponding process is indicated as process 210. Source / drain recesses 46 are formed by etching, and these recesses 46 can extend through the multilayer stack 22' and into the semiconductor strip 20'. The bottom surface of the source / drain recesses 46 can be located in the isolation region 32 ( Figure 4 The horizontal position above the top surface of ) and the horizontal position below it, or the position of the isolation area 32 ( Figure 4The top surface of the semiconductor strip 28 is flush with the horizontal plane. During the etching process, the gate spacer 44 and the dummy gate stack 42 mask portions of the semiconductor strip 28. Etching can include a single etching process or multiple etching processes. A timed etching process can be used to stop etching the source / drain trench 46 when it reaches the desired depth.

[0038] Then, the pseudo-nanostructure 24'A is laterally recessed, and dielectric material is filled into the corresponding grooves to form internal spacers 54, which are dielectric spacers. The resulting structure is as follows: Figure 6 As shown, a dielectric isolation layer 56 was also formed to replace the pseudo-nanostructure 24'B.

[0039] Next, a lower epitaxial source / drain region 62L is formed in the lower portion of the source / drain recess 46. Figure 5 ).exist Figure 26 In the process flow 200 shown, the corresponding process is indicated as process 212. The lower epitaxial source / drain region 62L is in contact with the lower semiconductor nanostructure 26'L, but not with the upper semiconductor nanostructure 26'U. The internal spacer 54 electrically isolates the lower epitaxial source / drain region 62L from the pseudo-nanostructure 24'A, which will be replaced with a replacement gate in a subsequent process.

[0040] The lower epitaxial source / drain region 62L is epitaxially grown, and has a conductivity type suitable for the device type (p-type or n-type) of the lower nanostructure FET. When the lower epitaxial source / drain region 62L is an n-type source / drain region, the corresponding material can include silicon or carbon-doped silicon doped with n-type dopants such as phosphorus or arsenic. When the lower epitaxial source / drain region 62L is a p-type source / drain region, the corresponding material can include silicon or silicon-germanium doped with p-type dopants such as boron or indium. The lower epitaxial source / drain region 62L can be in-situ doped, and may or may not be doped with the corresponding p-type or n-type dopants.

[0041] A first contact etch stop layer (CESL) 66 and a first ILD 68 are formed. The first CESL 66 can be formed from a dielectric material with high etch selectivity relative to the etching of the first ILD 68, such as silicon nitride, silicon oxide, silicon oxynitride, etc., and can be formed by any suitable deposition process, such as CVD, ALD, etc. The first ILD 68 can be formed from a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Suitable dielectric materials for the first ILD 68 may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), silicon oxide, etc.

[0042] The formation process may include depositing a conformal CESL layer, depositing material for ILD 68, followed by a planarization process and then an etch-back process. In some embodiments, the first ILD 68 is first etched, leaving the first CESL 66 unetched. An anisotropic etch process is then performed to remove the portion of the first CESL 66 above the recessed first ILD 68. After recessing, the sidewalls of the upper semiconductor nanostructure 26'U are exposed.

[0043] Next, an upper epitaxial source / drain region 62U is formed in the upper portion of the source / drain recess 46. Figure 26 In the process flow 200 shown, the corresponding process is shown as process 214. Depending on the required conductivity type of the upper epitaxial source / drain region 62U, the material of the upper epitaxial source / drain region 62U can be selected from the same group of candidate materials as those forming the lower source / drain region 62L.

[0044] The conductivity type of the upper epitaxial source / drain region 62U can be opposite to that of the lower epitaxial source / drain region 62L. In other words, the upper epitaxial source / drain region 62U can be doped in the opposite way to the lower epitaxial source / drain region 62L. The upper epitaxial source / drain region 62U can be in-situ doped and / or implanted with n-type or p-type dopants.

[0045] Next, the second CESL 70 and the second ILD 72 are formed. The materials and formation methods can be similar to those of the first CESL 66 and the first ILD 68, respectively, and will not be discussed further here. The formation process may include depositing layers of CESL 70 and ILD 72, and performing a planarization process to remove excess portions of the corresponding layers. After the planarization process, the top surfaces of the second ILD 72, the gate spacer 44, and the dummy gate stack 42 are coplanar (within the range of process variations). The planarization process may remove the mask 40, or leave the hard mask 40 intact.

[0046] Then, the dummy gate stack 42 is removed in one or more etching processes, thereby forming the recess 74 (also called the gap), as... Figure 7A and Figure 7B As shown. Each groove 74 exposes a portion of the multilayer stack 22' and / or rests on top of a portion of the multilayer stack 22'. Figure 6 ).exist Figure 26 In the process flow 200 shown, the corresponding process is shown as process 216.

[0047] Then, the pseudo-nanostructure 24'A was removed by etching. Figure 6 The remaining portion of the space allows the groove 74 to extend between the semiconductor nanostructures 26'. Figure 26 In the process flow 200 shown, the corresponding process is also shown as process 216. In the etching process, the pseudo-nanostructure 24'A is etched at a faster rate than the semiconductor nanostructure 26', the dielectric isolation layer 56, and the internal spacer 54. The etching can be isotropic. For example, when the pseudo-nanostructure 24'A is formed of silicon germanium and the semiconductor nanostructure 26' is formed of silicon, the etching process can include a wet etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc.

[0048] Figure 7B It shows from Figure 7A The structure obtainable by section 7B-7B is shown. Two device regions 300-S and 300-L are illustrated. Device region 300-S is a region adjacent to the multilayer stack with a smaller gap S1, and device region 300-L is a region adjacent to the multilayer stack with a larger gap S2, where gap S2 is larger than gap S1. Each device region is used to form a CFET comprising an upper FET and a lower FET. In the example shown, the upper FET is an NFET, and the lower FET is a PFET. It is understood that this disclosure can be applied to CFETs where the lower FET is an NFET and the upper FET is a PFET. Figure 7A The cross section shown can represent any one or both of the cross sections 7A-7A in device regions 300-S and 300-L.

[0049] exist Figure 8A and Figure 8B In this process, a gate dielectric 78 is formed in the groove 74. Figure 26 In the process flow 200 shown, the corresponding process is illustrated as process 218. A gate dielectric 78 is formed on the exposed surface of the exposed portion, including the semiconductor nanostructure 26' and the gate spacer 44. The gate dielectric 78 surrounds all (e.g., four) sides of the semiconductor nanostructure 26'.

[0050] Each gate dielectric 78 may include an interface layer 78IL, which may include an oxide, such as silicon oxide. The gate dielectric 78 may also include a high-k dielectric layer 78HK surrounding the respective interface layer. The high-k dielectric layer 78HK may be formed of a silicate or metal oxide of a metal selected from hafnium, zirconium, barium, titanium, lead, and combinations thereof, or the high-k dielectric layer 78HK may comprise a silicate or metal oxide of a metal selected from hafnium, zirconium, barium, titanium, lead, and combinations thereof.

[0051] In some embodiments, the interface layer 78IL may be formed on the semiconductor nanostructure 26'M / 26'L / 26'U (e.g. Figure 7A and Figure 7B As shown in the figure, the interface layer 78IL and the high-k dielectric layer 78HK are not formed on dielectric layer 56. In subsequent figures, the interface layer 78IL and the high-k dielectric layer 78HK can be shown together as dielectric layer 78, and the interface layer 78IL and the high-k dielectric layer 78HK are not shown separately. Details of the interface layer 78IL and the high-k dielectric layer 78HK can be found in [reference]. Figure 7A , Figure 7B and Figure 16B turn up.

[0052] The formation of the high-k dielectric layer 78HK can be achieved through methods such as molecular beam deposition (MBD), ALD, and PECVD. For example... Figure 8B As shown, the gate dielectric 78 may surround the nanostructures 26'U, 26'M, and 26'L. The gate dielectric 78 is formed in device regions 300-S and 300-L in a common process.

[0053] Figures 9 to 16A and Figure 16B The formation of gate electrodes 80 (including 80U and 80L) according to some embodiments is shown. Figure 16A and Figure 16B Details of the document. (See reference.) Figure 9 A ruthenium oxide layer 82 is deposited, and the ruthenium oxide layer 82 surrounds the corresponding gate dielectric 78. Figure 26In the process flow 200 shown, the corresponding process is illustrated as process 220. The ruthenium oxide layer 82 comprises multiple portions, each portion surrounding a gate dielectric 78. The multiple portions of the ruthenium oxide layer 82 are also referred to as multiple ruthenium oxide layers 82.

[0054] According to some embodiments, the deposition of the ruthenium oxide layer 82 is performed using a conformal deposition process, such as atomic layer deposition (ALD), which includes multiple ALD cycles. Each ALD cycle may include pulse delivery and purging of a ruthenium-containing precursor, as well as pulse delivery and purging of an oxygen-containing precursor.

[0055] Ruthenium-containing precursors can be selected from bis(cyclopentadienyl)Ru(II)[RuCp2,Ru(C5H5)2](bis(cyclopentadienyl)Ru(II)), bis(ethylcyclopentadienyl)Ru(II)[Ru(EtCp)2,Ru(C2H5C5H4)2](bis(ethylcyclopentadienyl)Ru(II)), tris(tetramethylheptanedioic acid)Ru(III); [Ru(thd)3,Ru(C 11 H 19 [O2)3](tris(tetramethylheptane-dionato)Ru(III)), tri(acetylacetonato)ruthenium(III)[Ru(acac)3,Ru(C5H7O2)3](tris(acetylacetonato)Ru(III)), etc.

[0056] The oxygen-containing precursor may include ozone (O3), water vapor (H2O), oxygen (O2), etc. Hydrogen (H2) may be added to the oxygen-containing precursor. According to some embodiments, the ruthenium oxide layer 82 has a thickness of less than about 1 nm, for example, in the range of about 0.5 nm to about 1 nm.

[0057] refer to Figure 10 A silicon oxide layer 84 is formed. Figure 26 In the process flow 200 shown, the corresponding process is indicated as process 222. A silicon oxide layer 84 can be deposited by immersing the corresponding wafer 2 in a silicon-containing precursor (such as silane, disilane, etc.). The immersion process can be performed in a chamber that would otherwise be filled with air.

[0058] A silicon-containing precursor is introduced into the chamber where wafer 2 is placed. Due to the introduction of the silicon-containing precursor, the pressure inside the chamber can be slightly higher than one atmosphere. Therefore, wafer 2 is immersed in the silicon-containing precursor and air, and an immersion process is performed. Thus, a silicon oxide layer 84 is formed.

[0059] The chamber pressure and immersion time can be controlled to prevent excessive pressure and duration, ensuring that the total silicon atomic percentage of the resulting work function layer is less than approximately 10%. Otherwise, excessive silicon may adversely affect the work function of the resulting work function layer. According to some embodiments, the pressure in the immersion chamber can be in the range of approximately 5 Torr to approximately 30 Torr, and the immersion time can be in the range of approximately 1 minute to approximately 10 minutes. The thickness of the resulting silicon oxide layer 84 can be in the range of approximately 1 angstrom to approximately 10 angstroms.

[0060] Figure 11 The formation of the ruthenium oxide layer 86 is shown. Figure 26 In the illustrated process flow 200, the corresponding process is shown as process 224. The formation process can be substantially the same as that for the formation of ruthenium oxide layer 82, and therefore process details will not be repeated here. According to some embodiments, the thickness of ruthenium oxide layer 86 is greater than that of ruthenium oxide layer 82. For example, the thickness of ruthenium oxide layer 86 can be in the range of about 1.5 nm to about 2.5 nm.

[0061] In some embodiments, the ruthenium oxide layer 86 can completely fill the gaps between the vertically stacked semiconductor nanostructures 26'. In other embodiments, unfilled gaps remain between the vertically stacked semiconductor nanostructures 26'.

[0062] Figure 12 The formation of silicon oxide layer 88 is shown. Figure 26 In the process flow 200 shown, the corresponding process is illustrated as process 226. The formation process can be substantially the same as the formation of silicon oxide layer 84, and therefore process details will not be repeated here. According to some embodiments, the thickness of silicon oxide layer 88 is similar to, greater than, or less than the thickness of silicon oxide layer 84.

[0063] According to some embodiments, a silicon oxide layer 88 is formed outside the spacers between the vertically aligned upper semiconductor nanostructures 26'. In other embodiments, the silicon oxide layer 88 may also include portions located within the spacers between the vertically aligned upper semiconductor nanostructures 26', and thus, in the illustrated cross-section, the silicon oxide layer 88 may form multiple rings.

[0064] Figure 13 The formation of the ruthenium oxide layer 90 is shown. Figure 26 In the illustrated process flow 200, the corresponding process is shown as process 228. The formation process can be substantially the same as the formation of the ruthenium oxide layer 82, and therefore process details will not be repeated here. According to some embodiments, the thickness of the ruthenium oxide layer 90 is greater than the thickness of the ruthenium oxide layer 82. For example, the thickness of the ruthenium oxide layer 90 can be in the range of about 1.5 nm to about 2.5 nm.

[0065] According to some embodiments, the total thickness of the ruthenium oxide layers 82, 86, and 90, and the silicon oxide layers 84 and 88, slightly exceeds the total thickness of the corresponding layers as work functions. Accordingly, the ruthenium oxide layers 82, 86, and 90, and the silicon oxide layers 84 and 88 together form the work function layer of the resulting transistor. The subsequently formed filling region 94 ( Figure 14 It is not a work function layer and does not affect the work function of the resulting gate stack.

[0066] According to some embodiments, in device regions 300-S, the grooves 74 between the horizontally spaced semiconductor nanostructures 26' can be completely filled. On the other hand, in device regions 300-L, the grooves 74 between the horizontally spaced semiconductor nanostructures 26' may still have some portions remaining unfilled.

[0067] In the deposition of ruthenium oxide layers 82, 86 and 90 and the immersion process for forming silicon oxide layers 84 and 88, wafer 2 can be heated, for example to a temperature in the range of about 100°C to about 500°C.

[0068] After forming the ruthenium oxide layer 90, a thermal annealing process 92 is performed. Figure 26 In the process flow 200 shown, the corresponding process is indicated as process 230. The thermal annealing process 92 can be performed by furnace annealing, rapid thermal annealing, etc. When furnace annealing is performed, the annealing duration can be in the range of approximately 10 milliseconds to approximately 300 seconds. The temperature can be in the range of approximately 100°C to approximately 500°C. The annealing process 92 has the function of redistributing oxygen within the deposited thin film stack.

[0069] According to some embodiments, annealing process 92 causes ruthenium, oxygen, and silicon to interdiffusion. Accordingly, each of the ruthenium oxide layers 82, 86, and 90 and the silicon oxide layers 84 and 88 may contain ruthenium, oxygen, and silicon, and is conductive.

[0070] Figure 14 The formation of filled region 94 is shown. Figure 26 In the process flow 200 shown, the corresponding process is illustrated as process 232. According to some embodiments, the filled region 94 contains ruthenium oxide. The formation method may include chemical vapor deposition (CVD), in which both a ruthenium precursor and an oxygen-containing precursor may be introduced. The corresponding ruthenium-containing precursor and oxygen-containing precursor may be selected from candidate precursors of the same group as those forming the ruthenium oxide layers 82, 86, and 90, and will not be repeated here.

[0071] According to an optional embodiment, the filling region 94 contains elemental ruthenium, rather than a compound. Therefore, an oxygen-containing precursor is not used. According to still some optional embodiments, the filling region 94 contains tungsten, cobalt, etc. The deposition of ruthenium, tungsten, cobalt, etc., can be achieved by PVD, CVD, etc.

[0072] In subsequent processes, planarization processes (such as CMP or mechanical polishing) are performed to flatten the top surface of the deposited layer. Then, an etch-back process is performed to etch back the deposited layer until the top surface of the deposited layer is below the bottom of the semiconductor nanostructure 26'U. The resulting ruthenium oxide layers 82, 86, and 90, silicon oxide layers 84 and 88, and filling region 94 form the lower gate electrode 80L, as shown below. Figure 15 As shown. In Figure 26 In the process flow 200 shown, the corresponding process is shown as process 234.

[0073] The lower portions or all of the ruthenium oxide layer 82, silicon oxide layer 84, ruthenium oxide layer 86, silicon oxide layer 88, and ruthenium oxide layer 90 together form a function layer. A CMP process, such as the type of polishing slurry, can be selected to reduce the depressions on the top surface of the polished layer. Furthermore, etching chemicals used in the etch-back process can be selected to make the top surfaces of the ruthenium oxide layer 82, silicon oxide layer 84, ruthenium oxide layer 86, and silicon oxide layer 88 as flat as possible.

[0074] Figure 16A and Figure 16B The formation of the upper gate electrode 80U is shown. Figure 26 In the illustrated process flow 200, the corresponding process is shown as process 236. According to some embodiments, the upper gate electrode 80U may include an n-type work function layer having a relatively low work function, for example, below about 4.6 eV. It should be understood that the upper gate electrode 80U may be electrically connected to the lower gate electrode 80L below, or may be electrically disconnected from the lower gate electrode 80L below, for example, through a dielectric layer 102. The dielectric layers 102 are shown in dashed lines to indicate that they may or may not be formed.

[0075] Therefore, a CFET 10 is formed, which includes a lower FET 10L and an upper FET 10U. The lower FET 10L includes a gate dielectric 78 and a gate electrode 80L, which together form a gate stack 91L. The upper FET 10U includes a gate dielectric 78 and a gate electrode 80U, which together form a gate stack 91U.

[0076] Ruthenium oxide is conductive and has a high work function, for example, in the range of about 5.0 eV to about 5.2 eV, making it a good candidate material for the work function layer of a PFET. However, ruthenium oxide is readily reduced back to elemental ruthenium, and its work function can be undesirably reduced as a result. According to some embodiments of this disclosure, silicon oxide is formed to trap oxygen and block oxygen diffusion through. Therefore, ruthenium oxide is more stable.

[0077] Figure 24 A schematic profile of the distribution of ruthenium and silicon according to some embodiments is shown. The X-axis represents the location and corresponding layer. The Y-axis shows a schematic relative atomic percentage. Figure 16B The curve is obtained from arrow 122. Line 104 is the profile of ruthenium, and line 106 is the profile of silicon. The peaks of ruthenium can correspond to the valleys of silicon, and vice versa, where the peaks of ruthenium are located in ruthenium oxide layers 82, 86, and 90, and the peaks of silicon are located in silicon oxide layers 84 and 86. Line 104A is the profile of ruthenium when the filled region 94 contains ruthenium or ruthenium oxide, and line 104B is the profile of ruthenium when the filled region 94 does not contain ruthenium.

[0078] Along Figure 16A The contour map obtained by the middle arrow 122' and Figure 24 The outlines shown are essentially the same, except that the filled region 94 and its corresponding outline no longer exist, and the regions 90 (and their corresponding outlines) on the opposite side of the filled region 94 are merged and are relatively flat in the merged region.

[0079] Figures 17 to 23 A cross-sectional view is shown of an intermediate stage in the formation of a CFET according to an alternative embodiment of this disclosure. Figure 27 The process flow 300 shown represents the corresponding process. These embodiments are similar to the foregoing embodiments, except that instead of depositing alternating ruthenium oxide and silicon oxide layers, a plating process is performed.

[0080] Unless otherwise stated, the materials, structures, and forming processes of the components in these embodiments are substantially the same as those of the same components indicated by the same reference numerals in the foregoing embodiments. Throughout this specification, the details regarding materials, structures, and forming processes provided in each embodiment may be applied to any other embodiment wherever applicable.

[0081] The initial steps and resulting structures of these embodiments are similar to Figures 1 to 6 , Figure 7A , Figure 7B , Figure 8A and Figure 8B The results are essentially the same. Figure 27 In the illustrated process flow 300, the corresponding process is shown as process 302. Process 302 also includes... Figure 26 Processes 202 to 218 in the process flow 200 shown. Figure 17 A cross-sectional view is shown, which is consistent with... Figure 8B The cross-sectional views shown are the same.

[0082] Next, as Figure 18 As shown, a ruthenium oxide seed layer 112 is formed. Figure 27 In the illustrated process flow 300, the corresponding process is shown as process 304. According to some embodiments, the forming process includes a (wet) plating process in which a chemical solution is used. The chemical solution contains water, a ruthenium-containing precursor, and a reducing agent for reducing the ruthenium-containing precursor to ruthenium.

[0083] According to some embodiments, the ruthenium-containing precursor may comprise RuCl3, (Ru(acac)3), (Ru(NO)(NO3)3), or Ru3(CO). 12 The reducing agent may include hydrazine, NaBH4, ascorbic acid, etc. The deposition rate (which is the increase in thickness of the ruthenium oxide seed layer 112 per unit time) is controlled to be sufficiently small so that the ruthenium oxide seed layer 112 can be formed as a conformal layer with high uniformity. If the deposition rate is too high, there may be sites where the ruthenium oxide seed layer 112 has not formed. For example, the deposition rate can be less than approximately... / minute. The deposition rate can be reduced by controlling the weight percentage of the ruthenium precursor to be small (e.g., less than about 20%). The ruthenium oxide seed layer 112 does not contain doped silicon. Otherwise, doped silicon would adversely affect seed formation.

[0084] refer to Figure 19 A ruthenium oxide layer 114 is formed. Figure 27 In the illustrated process flow 300, the corresponding process is shown as process 306. According to some embodiments, the forming process also includes a plating process, wherein a chemical solution is used. The chemical solution also contains water, a ruthenium-containing precursor, and a reducing agent for reducing the ruthenium-containing precursor to ruthenium. The ruthenium-containing precursor and the reducing agent may be selected from candidate precursors of the same group used for plating the ruthenium oxide seed layer 112.

[0085] Because the ruthenium oxide seed layer 112 is a conformal layer with good uniformity, the ruthenium oxide layer 114 can be deposited more quickly without compromising film quality. The deposition rate of the ruthenium oxide layer 114 is greater than that of the ruthenium oxide seed layer 112; for example, the deposition rate ratio of the ruthenium oxide layer 114 to the ruthenium oxide seed layer 112 is greater than 2. The deposition rate ratio can also be in the range of about 2 to about 10. The deposition rate can be increased by increasing the weight percentage of the ruthenium-containing precursor (e.g., greater than about 100%).

[0086] The ruthenium oxide layer 114 also does not contain doped silicon. Otherwise, since the ruthenium oxide layer 114 is close to the channel, the doped silicon would adversely affect the performance of the resulting transistor.

[0087] refer to Figure 20 A ruthenium silicon oxide layer 116 was deposited. Figure 27In the process flow 300 shown, the corresponding process is illustrated as process 308. According to some embodiments, a ruthenium silicon oxide layer 116 is deposited by plating, wherein a chemical solution is used. The chemical solution contains water, a ruthenium-containing precursor, a silicon-containing precursor, and a reducing agent for reducing the ruthenium-containing precursor to ruthenium.

[0088] The ruthenium-containing precursor and reducing agent can be selected from candidate materials of the same group used for plating the ruthenium oxide seed layer 112 and the ruthenium oxide layer 114 (these can be the same as or different from the candidate materials used for plating the ruthenium oxide seed layer 112 and the ruthenium oxide layer 114). The silicon-containing precursor can include tetraethyl orthosilicate (TEOS), TMOS Si(OCH3)4, trimethylsilane (TMS, (CH3)3SiH), etc., and the silicon-containing precursor can be soluble in water.

[0089] According to these embodiments, at least the lower portion of the ruthenium oxide seed layer 112, the ruthenium oxide layer 114, and the ruthenium oxide silicon layer 116 together form the work function layer of the resulting transistor. The silicon in the ruthenium oxide silicon layer 116 exists in the form of silicon oxide, which has the function of capturing oxygen, thereby preventing the ruthenium oxide in the ruthenium oxide silicon layer 116 from being reduced to elemental ruthenium, which has a lower work function than ruthenium oxide.

[0090] According to some embodiments, in device regions 300-S, the gaps between the horizontally spaced semiconductor nanostructures 26' can be completely filled by the ruthenium silicon oxide layer 116. On the other hand, in device regions 300-L, some portions of the gaps between the horizontally spaced semiconductor nanostructures 26' can still be retained.

[0091] Figure 20 Annealing process 92 is further illustrated, which is used to densify the ruthenium oxide seed layer 112, the ruthenium oxide layer 114, and the ruthenium oxide silicon layer 116. Figure 27 In the process flow 300 shown, the corresponding process is indicated as process 310. The process conditions and references for annealing process 92 are as follows. Figure 13 The process conditions discussed in the previous section are basically the same, and will not be repeated here.

[0092] Figure 21 The deposition in filling region 94 is shown. Figure 27 In the process flow 300 shown, the corresponding process is indicated as process 312. Materials and forming processes are referenced. Figure 14 The materials and fabrication processes discussed earlier are essentially the same, and therefore will not be repeated here. The filled region 94 is farther from the channel of the corresponding transistor than it would be as a work function layer, and therefore is not a work function layer.

[0093] Next, as Figure 21As further shown, annealing process 95 is performed, which can be performed in a synthesis gas (such as a mixture of H2 and N2). Figure 27 In the process flow 300 shown, the corresponding process is indicated as process 314. The annealing duration can be in the range of about 60 seconds to about 600 seconds. The temperature can be in the range of about 150°C to about 500°C. Annealing process 95 also has the function of densifying the deposited layer.

[0094] Figure 22 The planarization and recessing of the deposited material are shown, thereby forming a lower gate electrode 81L, which includes a ruthenium oxide seed layer 112, a ruthenium oxide layer 114, a ruthenium oxide silicon layer 116, and a filled region 94. Figure 27 In the process flow 300 shown, the corresponding process is shown as process 316.

[0095] Figure 23 The formation of the upper gate electrode 81U and possibly the dielectric layer 102 (if present) is shown. Figure 27 In the process flow 300 shown, the corresponding process is indicated as process 318. This results in the formation of CFET 10.

[0096] Figure 25 A schematic profile of the distribution of ruthenium and silicon according to some embodiments is shown. The X-axis represents the location and corresponding layer. The Y-axis shows a schematic relative atomic percentage. Figure 23 The curve is obtained from arrow 124. Line 128 is a profile of ruthenium, and line 126 is a profile of silicon. Line 128 may include 128-A or 128-B, depending on whether the filled region 94 contains ruthenium. Line 128A is a profile of ruthenium when the filled region 94 contains ruthenium or ruthenium oxide, and line 128B is a profile of ruthenium when the filled region 94 does not contain ruthenium.

[0097] Along Figure 23 The contour map obtained by the middle arrow 124' and Figure 25 The outlines shown are basically the same, except that the filled area 94 and its corresponding outline no longer exist, and the area 116 (and its corresponding outline) located opposite the filled area 94 (and its corresponding outline) is merged.

[0098] The embodiments disclosed herein have several advantageous features. By doping silicon (and silicon oxide) into ruthenium oxide, oxygen is better trapped in the ruthenium oxide, and thus the ruthenium oxide becomes more stable. Due to the high work function of ruthenium oxide, the performance of the resulting PFET can be improved, and the stability of the PFET can be maintained.

[0099] According to some embodiments of the present disclosure, a method includes: forming a semiconductor region; forming a gate spacer over the semiconductor region; forming a source / drain region adjacent to the semiconductor region, wherein the source / drain region is p-type; forming a gate dielectric over the semiconductor region, wherein the gate dielectric is formed in a gap between opposing portions of the gate spacer; forming a first ruthenium oxide layer, wherein the first ruthenium oxide layer is located over the gate dielectric and wherein the first ruthenium oxide layer is part of a work function layer of a gate electrode; and doping silicon into the first ruthenium oxide layer.

[0100] In one embodiment, incorporating silicon into the first ruthenium oxide layer includes: depositing a first silicon oxide layer over the first ruthenium oxide layer, wherein the first silicon oxide layer is in contact with the first ruthenium oxide layer; and performing an annealing process. In another embodiment, the method further includes depositing a second ruthenium oxide layer over the first silicon oxide layer. In yet another embodiment, the method further includes depositing a second silicon oxide layer over the second ruthenium oxide layer.

[0101] In one embodiment, depositing the first silicon oxide layer includes immersing a wafer comprising the first ruthenium oxide layer in a silicon-containing gas. In another embodiment, the immersion is performed in a chamber communicating with ambient air. In yet another embodiment, forming the first ruthenium oxide layer includes a plating process, wherein incorporating silicon into the first ruthenium oxide layer includes co-plating silicon during the plating of the first ruthenium oxide layer.

[0102] In one embodiment, the method further includes depositing a conductive gap-filling region over the first ruthenium oxide layer, wherein the conductive gap-filling region comprises elemental ruthenium. In another embodiment, the method further includes depositing a conductive gap-filling region over the first ruthenium oxide layer, wherein the conductive gap-filling region comprises ruthenium oxide. In yet another embodiment, the first ruthenium oxide layer and the source / drain region are included in the lower transistor, and the method further includes forming an upper transistor overlapping the lower transistor.

[0103] According to some embodiments of the present disclosure, a method includes: forming a plurality of semiconductor layers, wherein upper semiconductor layers of the plurality of semiconductor layers overlap with corresponding lower semiconductor layers of the plurality of semiconductor layers; forming a gate dielectric surrounding the plurality of semiconductor layers; depositing a first ruthenium oxide layer comprising a plurality of portions over the gate dielectric; depositing a first silicon oxide layer over the first ruthenium oxide layer; depositing a second ruthenium oxide layer over the first silicon oxide layer; and planarizing the second ruthenium oxide layer, the first silicon oxide layer, and the first ruthenium oxide layer, wherein the remaining portions of the second ruthenium oxide layer, the first silicon oxide layer, and the first ruthenium oxide layer form a portion of a first gate electrode of a transistor.

[0104] In one embodiment, the method further includes performing an annealing process after forming the second ruthenium oxide layer. In another embodiment, the method further includes depositing a second silicon oxide layer over the second ruthenium oxide layer. In yet another embodiment, the method further includes depositing a third ruthenium oxide layer over the second silicon oxide layer. In yet another embodiment, the method further includes depositing a ruthenium layer over the second ruthenium oxide layer. In yet another embodiment, depositing the first silicon oxide layer includes immersing the first ruthenium oxide layer in a process gas comprising silicon and a process gas comprising oxygen.

[0105] According to some embodiments of this disclosure, a structure includes: a first transistor comprising: a semiconductor region; a gate spacer located above the semiconductor region; a gate dielectric located between the semiconductor region and an opposing portion of the gate spacer; a gate electrode comprising: a first ruthenium oxide layer located above the gate dielectric, wherein the first ruthenium oxide layer includes silicon; and a first source / drain region located adjacent to the gate spacer. In embodiments, the structure further includes a silicon oxide layer in contact with the first ruthenium oxide layer.

[0106] In one embodiment, the structure further includes a second ruthenium oxide layer located between the first ruthenium oxide layer and the semiconductor region, wherein the second ruthenium oxide layer has a lower percentage of silicon atoms than the first ruthenium oxide layer. In another embodiment, the structure further includes a second transistor overlapping the first transistor, wherein the first transistor is a p-type transistor and the second transistor is an n-type transistor.

[0107] According to some embodiments of this disclosure, a method for forming a semiconductor structure is provided, the method comprising: forming a semiconductor region; forming a gate spacer over the semiconductor region; forming a source / drain region adjacent to the semiconductor region, wherein the source / drain region is p-type; forming a gate dielectric over the semiconductor region, wherein the gate dielectric is formed in a gap between opposing portions of the gate spacer; forming a first ruthenium oxide layer, wherein the first ruthenium oxide layer is located over the gate dielectric, and wherein the first ruthenium oxide layer is part of a work function layer of a gate electrode; and doping silicon into the first ruthenium oxide layer. In some embodiments, doping silicon into the first ruthenium oxide layer comprises: depositing a first silicon oxide layer over the first ruthenium oxide layer, and the first silicon oxide layer being in contact with the first ruthenium oxide layer; and performing an annealing process. In some embodiments, the method of forming the semiconductor structure further comprises depositing a second ruthenium oxide layer over the first silicon oxide layer. In some embodiments, the method of forming the semiconductor structure further comprises depositing a second silicon oxide layer over the second ruthenium oxide layer. In some embodiments, depositing the first silicon oxide layer comprises immersing a wafer including the first ruthenium oxide layer in a silicon-containing gas. In some embodiments, wafer immersion is performed in a chamber communicating with ambient air. In some embodiments, forming a first ruthenium oxide layer includes a plating process, wherein incorporating silicon into the first ruthenium oxide layer includes co-plating silicon during the plating of the first ruthenium oxide layer. In some embodiments, the method of forming a semiconductor structure further includes depositing a conductive gap-filling region over the first ruthenium oxide layer, wherein the conductive gap-filling region comprises elemental ruthenium. In some embodiments, the method of forming a semiconductor structure further includes depositing a conductive gap-filling region over the first ruthenium oxide layer, wherein the conductive gap-filling region comprises ruthenium oxide. In some embodiments, the first ruthenium oxide layer and source / drain regions are included in a lower transistor, and the method further includes forming an upper transistor overlapping the lower transistor.

[0108] According to other embodiments of this disclosure, a method for forming a semiconductor structure is provided, the method comprising: forming a plurality of semiconductor layers, wherein upper semiconductor layers of the plurality of semiconductor layers overlap with corresponding lower semiconductor layers of the plurality of semiconductor layers; forming a gate dielectric surrounding the plurality of semiconductor layers; depositing a first ruthenium oxide layer comprising a plurality of portions over the gate dielectric; depositing a first silicon oxide layer over the first ruthenium oxide layer; depositing a second ruthenium oxide layer over the first silicon oxide layer; and planarizing the second ruthenium oxide layer, the first silicon oxide layer, and the first ruthenium oxide layer, wherein the remaining portions of the second ruthenium oxide layer, the first silicon oxide layer, and the first ruthenium oxide layer form a portion of a first gate electrode of a transistor. In some embodiments, the method for forming the semiconductor structure further comprises: performing an annealing process after forming the second ruthenium oxide layer. In some embodiments, the method for forming the semiconductor structure further comprises: depositing a second silicon oxide layer over the second ruthenium oxide layer. In some embodiments, the method for forming the semiconductor structure further comprises: depositing a third ruthenium oxide layer over the second silicon oxide layer. In some embodiments, the method for forming the semiconductor structure further comprises depositing a ruthenium layer over the second ruthenium oxide layer. In some embodiments, depositing the first silicon oxide layer includes immersing the first ruthenium oxide layer in a process gas comprising silicon and a process gas comprising oxygen.

[0109] According to further embodiments of this disclosure, a semiconductor structure is provided, the semiconductor structure comprising: a first transistor including: a semiconductor region; a gate spacer located above the semiconductor region; a gate dielectric located between the semiconductor region and an opposing portion of the gate spacer; a gate electrode including: a first ruthenium oxide layer located above the gate dielectric, wherein the first ruthenium oxide layer includes silicon; and a first source / drain region located adjacent to the gate spacer. In some embodiments, the semiconductor structure further includes a silicon oxide layer in contact with the first ruthenium oxide layer. In some embodiments, the semiconductor structure further includes a second ruthenium oxide layer located between the first ruthenium oxide layer and the semiconductor region, wherein the second ruthenium oxide layer has a lower percentage of silicon atoms than the first ruthenium oxide layer. In some embodiments, the semiconductor structure further includes a second transistor overlapping the first transistor, wherein the first transistor is a p-type transistor and the second transistor is an n-type transistor.

[0110] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other operations and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: Forming semiconductor regions; A gate spacer is formed above the semiconductor region; A source / drain region is formed next to the semiconductor region, wherein the source / drain region is p-type; A gate dielectric is formed over the semiconductor region, wherein the gate dielectric is formed in the gap between opposing portions of the gate spacer; A first ruthenium oxide layer is formed, wherein the first ruthenium oxide layer is located above the gate dielectric, and wherein the first ruthenium oxide layer serves as part of the work function layer of the gate electrode; and Silicon is incorporated into the first ruthenium oxide layer.

2. The method according to claim 1, wherein, Incorporating the silicon into the first ruthenium oxide layer includes: A first silicon oxide layer is deposited over the first ruthenium oxide layer, and the first silicon oxide layer is in contact with the first ruthenium oxide layer; and Perform the annealing process.

3. The method of claim 2 further includes depositing a second ruthenium oxide layer over the first silicon oxide layer.

4. The method of claim 3 further comprises depositing a second silicon oxide layer over the second ruthenium oxide layer.

5. The method according to claim 2, wherein, Depositing the first silicon oxide layer includes immersing a wafer containing the first ruthenium oxide layer in a silicon-containing gas.

6. The method according to claim 5, wherein, The immersion of the wafer is performed in a chamber connected to the outside air.

7. The method according to claim 1, wherein, Forming the first ruthenium oxide layer includes a plating process, wherein incorporating silicon into the first ruthenium oxide layer includes: Silicon is co-plated during the deposition of the first ruthenium oxide layer.

8. The method according to claim 1, further comprising: A conductive gap-filling region is deposited above the first ruthenium oxide layer, wherein the conductive gap-filling region comprises elemental ruthenium.

9. A method for forming a semiconductor structure, comprising: Multiple semiconductor layers are formed, wherein the upper semiconductor layer of the multiple semiconductor layers overlaps with the corresponding lower semiconductor layer of the multiple semiconductor layers; Forming a gate dielectric surrounding the plurality of semiconductor layers; A first ruthenium oxide layer comprising multiple portions is deposited over the gate dielectric; A first silicon oxide layer is deposited on top of the first ruthenium oxide layer; A second ruthenium oxide layer is deposited above the first silicon oxide layer; as well as The second ruthenium oxide layer, the first silicon oxide layer, and the first ruthenium oxide layer are planarized, wherein the remaining portions of the second ruthenium oxide layer, the first silicon oxide layer, and the first ruthenium oxide layer form part of the first gate electrode of the transistor.

10. A semiconductor structure, comprising: A first transistor, the first transistor comprising: Semiconductor region; A gate spacer is located above the semiconductor region; A gate dielectric is located above the semiconductor region and between the opposite portion of the gate spacer; Gate electrode, the gate electrode comprising: A first ruthenium oxide layer is located above the gate dielectric, wherein the first ruthenium oxide layer includes silicon; and The first source / drain region is located next to the gate spacer.

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