Silicon terminal diamond and boron nitride integrated CMOS device and method

Abstract

The invention discloses a silicon terminal diamond and boron nitride integrated CMOS device and method, and relates to the technical field of semiconductor devices.The CMOS device comprises an NMOS device and a PMOS device which are integrated on the same diamond substrate layer and arranged at an interval, the NMOS device is located in a first area of the diamond substrate layer, the PMOS device is located in a second area of the diamond substrate layer, and the NMOS device is located in a third area of the diamond substrate layer; the NMOS device comprises a c-BN layer positioned on a part of the diamond substrate layer in the first region; the PMOS device comprises a silicon terminal thin film layer with a C-Si bond and two boron-doped diamond layers, the silicon terminal thin film layer is located on part of the diamond substrate layer in the second area, and the two boron-doped diamond layers are located on part of the diamond substrate layer in the second area and located on the two sides of the silicon terminal thin film layer. The structure of the invention is beneficial for realizing the balance of the driving capability of the complementary device, thereby reducing the size compensation demand and parasitic effect.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and specifically to a CMOS device and method integrating silicon-terminated diamond and boron nitride. Background Technology

[0002] With the rapid development of aerospace, nuclear energy exploration, high-temperature electronics, and electronic systems operating in high-radiation environments, the performance and reliability issues of traditional semiconductor devices under extreme conditions are becoming increasingly prominent. Mainstream complementary metal-oxide-semiconductor (CMOS) technology still relies heavily on silicon materials. Although silicon-based CMOS processes are mature and offer high integration, silicon's intrinsic bandgap is only about 1.12 eV, and its thermal conductivity is about 150 W·m. -1 ·K -1 The breakdown electric field strength is typically below 0.5 MV·cm. -1 Under high temperature or strong radiation (>5000 rads), the intrinsic carrier concentration in silicon increases significantly, leading to more radiation defects. This can cause increased leakage current, higher static power consumption, and device threshold drift and reliability degradation. When the operating temperature exceeds 150°C, silicon-based CMOS devices struggle to maintain stable operation and cannot meet the requirements for long-term reliable operation in extreme environments.

[0003] Diamond, as an ultrawide bandgap semiconductor material, has a bandgap of approximately 5.47 eV and a thermal conductivity exceeding 2000 W·m. -1 ·K -1 The breakdown electric field strength can reach 10 MV·cm -1 The diamond material exhibits excellent high-temperature stability (>400℃) and radiation resistance (>1M rad), making it a promising candidate for applications in extreme environment electronic devices. Therefore, constructing CMOS devices based on diamond materials is considered a crucial research direction for overcoming the limitations of traditional silicon-based CMOS technology.

[0004] However, existing technologies, whether traditional CMOS based on silicon materials or CMOS solutions based on a combination of diamond hydrogen terminals and gallium nitride devices, cannot simultaneously achieve low static power consumption, long-term stability (high reliability), and high integration under extreme environments. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a CMOS device and method for monolithic integration of silicon-terminated diamond and boron nitride.

[0006] The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides a silicon-terminated diamond and boron nitride integrated CMOS device, comprising an NMOS device and a PMOS device integrated on the same diamond substrate and spaced apart, wherein the NMOS device is located in a first region of the diamond substrate and the PMOS device is located in a second region of the diamond substrate, wherein: The NMOS device includes a c-BN layer located on a portion of the diamond substrate layer in the first region. A two-dimensional electron gas is formed between the c-BN layer and the diamond substrate layer, serving as a conductive channel for the NMOS device. The PMOS device includes a silicon-terminated thin film layer with C-Si bonds and two boron-doped diamond layers. The silicon-terminated thin film layer is located on a portion of the diamond substrate layer in the second region. The two boron-doped diamond layers are located on a portion of the diamond substrate layer in the second region and are located on both sides of the silicon-terminated thin film layer. The lower surface of the boron-doped diamond layer is located below the upper surface of the diamond substrate layer, and the upper surface of the boron-doped diamond layer is located above the upper surface of the diamond substrate layer.

[0007] Secondly, the present invention provides a method for fabricating a silicon-terminated diamond and boron nitride integrated CMOS device, the method being used to fabricate the CMOS device described in any of the above embodiments, the method comprising: Step 1: Grow a c-BN layer on a diamond substrate; Step 2: Selectively remove the c-BN layer in the second region; Step 3: Grow a dielectric layer on the exposed diamond substrate and the remaining c-BN layer; Step 4: Selectively remove a portion of the dielectric layer in the second region to expose the diamond substrate layer, thereby defining the location of the active region of the PMOS device; Step 5: In a mixed atmosphere of hydrogen, carbon source gas and boron source gas, two boron-doped diamond layers are formed on both sides of the remaining dielectric layer in the second region using microwave plasma chemical vapor deposition. The lower surface of the boron-doped diamond layer is located below the upper surface of the diamond substrate layer, and the upper surface of the boron-doped diamond layer is located above the upper surface of the diamond substrate layer. Step 6: Selectively remove part of the dielectric layer and part of the c-BN layer in the first region to expose the diamond substrate layer, thereby defining the location of the active region of the NMOS device; Step 7: Remove the remaining dielectric layer in the first region and the second region, and retain a silicon-terminated thin film layer with C-Si bonds on the surface of the diamond substrate layer between the two boron-doped diamond layers.

[0008] Compared with the prior art, the beneficial effects of the present invention are as follows: The diamond substrate of this invention is used by both PMOS and NMOS devices. The NMOS device forms a heterostructure based on c-BN and diamond, while the PMOS device forms a channel structure based on silicon termination and diamond. Electrical isolation between the c-BN and diamond heterostructure NMOS device and the silicon-terminated diamond PMOS device is achieved by disrupting the local c-BN and diamond heterostructure interface to form an isolation region. Therefore, this invention constructs a monolithic integrated CMOS device structure of silicon-terminated diamond and boron nitride by integrating a c-BN and diamond heterostructure NMOS device and a silicon-terminated diamond PMOS device on the same diamond substrate. This CMOS device avoids the limitations of high activation energy and difficulty in effectively activating carriers in n-type doping of diamond materials, while achieving controllable conductivity of the PMOS device through the synergistic regulation of silicon termination and gate dielectric. Since the NMOS and PMOS devices have good matching in terms of channel mobility, it is beneficial to achieve a balance in the driving capabilities of complementary devices, thereby reducing size compensation requirements and parasitic effects. Meanwhile, NMOS and PMOS devices are integrated on the same diamond substrate, making full use of diamond's excellent thermal conductivity and providing a structural basis for the stable operation of CMOS devices in extreme environments such as high temperature and strong radiation.

[0009] The present invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of the structure of a silicon-terminated diamond and boron nitride integrated CMOS device provided by the present invention; Figure 2 This is a band structure diagram comparing the heterostructure of c-BN and diamond provided by the present invention with the conductivity mechanism of traditional n-type doped diamond. Figure 3 This is a comparison diagram of the n / p channel mobility matching in different diamond CMOS technologies provided in this embodiment of the invention; Figures 4a-4l This is a schematic diagram illustrating the fabrication process of a silicon-terminated diamond and boron nitride integrated CMOS device provided by the present invention. Detailed Implementation

[0011] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0012] Example 1 Constructing CMOS devices based on diamond materials is considered an important research direction for overcoming the bottlenecks of traditional silicon-based CMOS technology. However, under current technological conditions, the realization of diamond CMOS devices is still subject to many limitations.

[0013] First, the fabrication of n / p-type MOSFETs, which constitute diamond CMOS devices, remains difficult, and their performance does not yet meet the requirements of CMOS applications. Regarding the construction of n-type devices, the activation energies of commonly used n-type dopants in diamond are typically higher than 0.5 eV, far exceeding the room-temperature activation energy of 26 meV. This results in low carrier activation efficiency at room temperature, usually less than 1%, and electron concentrations that are difficult to exceed 102. 17 cm -3 The highest migration rate is only 10 cm. 2 The V·s scale makes it difficult for NMOS devices based on intrinsic diamond materials to obtain stable and controllable conductivity characteristics. Constructing NMOS diamond transistors based on traditional semiconductor doping methods remains a key scientific and technological bottleneck that is difficult to solve at present.

[0014] In p-type devices, diamond PMOS devices currently commonly employ hydrogen-terminated surface structures, and their conductivity mechanism relies on two-dimensional hole gas on the surface, with a hole surface density typically of 10. 12 ~10 13 cm -2 Because these conductive channels exist spontaneously under zero gate bias conditions, related devices often exhibit depletion-type (normally on) characteristics, with significant channel current remaining even in the off state, resulting in high static power consumption and poor safety for non-enhancement-type (normally off) devices. Furthermore, the hydrogen-terminated diamond surface is highly sensitive to ambient atmosphere and temperature, easily undergoing hydrogen desorption and interface degradation under high temperature or oxidizing conditions, leading to unstable electrical performance and limiting its long-term reliable application in high-temperature and high-irradiation environments.

[0015] Second, in existing diamond CMOS structures, the conduction symmetry between n-type and p-type devices is poor. In existing technologies, p-type devices typically use two-dimensional hole gas on the surface of hydrogen-terminated diamond as the conductive channel, and their hole mobility is significantly affected by surface transfer doping and interface scattering. In contrast, n-type devices in existing technologies are mostly constructed by introducing gallium nitride (GaN) material systems. Specifically, hydrogen-terminated diamond p-type devices rely on surface-type two-dimensional hole gas for conductivity, with a mobility of 50–200 cm⁻¹. 2 / V·s, the threshold characteristics are quite sensitive to surface conditions and environmental conditions, while GaN n-type devices have high electron mobility (1000~2000 cm⁻¹). 2The characteristics of n-type and p-type devices include stable conductive channels and threshold values ​​that can be controlled through structural and technological means. These differences make it difficult to maintain consistency in driving capability and turn-on / turn-off behavior per unit size, thus making it difficult to achieve symmetry in the conduction characteristics of n-type and p-type devices.

[0016] To compensate for the differences in driving capabilities, based on the well-known common sense of the transistor's saturation / linear region output current equation, current CMOS circuit designs typically require size compensation for one type of device. This can be achieved by increasing the device channel width, using multi-finger parallel connections, or increasing the number of devices to balance the static operating point and dynamic driving capability. This compensation method directly results in a significant difference in the area occupied by n-type and p-type devices, and introduces larger parasitic capacitance and resistance, increasing interconnect complexity and parasitic delay.

[0017] At the circuit level, conduction asymmetry and size compensation can further cause problems such as inverter flip-point offset, inconsistent rising / falling edge speed, and reduced noise margin, which limit the circuit switching speed and lead to increased dynamic power consumption and tightened timing margin under high-frequency operating conditions. This affects the overall performance and energy efficiency of CMOS circuits, limiting their further development in high-speed, low-power and high-reliability application scenarios.

[0018] Third, the realization of monolithically integrated CMOS devices based on the diamond system remains challenging, making it difficult to fully leverage the performance advantages of diamond materials. Current technologies heterogeneously combine diamond p-type devices with gallium nitride n-type devices to construct CMOS-like circuit structures. However, this approach typically involves different material systems and substrates, leading to incompatibility issues in lattice structure, thermal expansion coefficients, and process flows. This makes monolithic integration on the same substrate difficult, often relying on multi-chip interconnects or heterogeneous packaging to achieve circuit functionality. Multi-material, multi-substrate integration not only increases the complexity of device fabrication and packaging but also introduces additional parasitic interconnect resistance and capacitance, weakening the high-speed characteristics and power consumption advantages of the devices. Furthermore, differences in thermal conductivity and inconsistent thermal management paths between different material devices prevent the excellent heat dissipation performance of diamond from being fully utilized at the system level, thus limiting the overall performance improvement of diamond CMOS technology in high-power-density, high-reliability applications. Based on the above research status, it can be seen that existing technologies mainly focus on the feasibility exploration of single devices or materials, lacking a systematic solution for synergistically introducing related structures into the same diamond substrate to form an integrated CMOS device.

[0019] In summary, existing technologies, whether traditional CMOS based on silicon materials or CMOS solutions combining diamond hydrogen terminals and gallium nitride devices, struggle to simultaneously achieve low static power consumption, long-term stability (high reliability), and high integration under extreme environments. Therefore, it is necessary to explore a new device structure and fabrication method. This method should introduce wide-bandgap materials to construct stable n-type conductive channels while improving the power consumption characteristics and environmental stability of diamond p-type devices through surface termination engineering. This would enable monolithic integration of NMOS and PMOS devices on the same diamond substrate, providing a new technological path for constructing low-power, high-temperature resistant, and highly irradiated diamond CMOS devices.

[0020] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of a silicon-terminated diamond and boron nitride integrated CMOS device provided by the present invention. The embodiment of the present invention provides a silicon-terminated diamond and boron nitride integrated CMOS device, which includes an NMOS device and a PMOS device integrated on the same diamond substrate layer 1 and spaced apart. The NMOS device is located in a first region of the diamond substrate layer 1, and the PMOS device is located in a second region of the diamond substrate layer 1. The first region is used to form the NMOS device, and the second region is used to form the PMOS device. An isolation region is provided between the first and second regions, exposing the upper surface of the diamond substrate layer 1 in the isolation region to achieve electrical isolation between the NMOS device and the PMOS device. The NMOS device includes a c-BN layer 2, which is located on a portion of the diamond substrate layer 1 in the first region. A two-dimensional electron gas is formed between the c-BN (cubic boron nitride) layer 2 and the diamond substrate layer 1, which serves as the conductive channel of the NMOS device. The PMOS device includes a silicon-terminated thin film layer 8 with C-Si bonds and two boron-doped diamond layers 7. The silicon-terminated thin film layer 8 is located on a portion of the diamond substrate layer 1 in the second region. The two boron-doped diamond layers 7 are located on a portion of the diamond substrate layer 1 in the second region and are located on both sides of the silicon-terminated thin film layer 8. The lower surface of the boron-doped diamond layer 7 is located below the upper surface of the diamond substrate layer 1, and the upper surface of the boron-doped diamond layer 7 is located above the upper surface of the diamond substrate layer 1.

[0021] To address the issues of increased leakage current, elevated static power consumption, and reliability degradation in existing silicon-based CMOS devices under high temperature or strong radiation conditions, this invention uses ultra-wide bandgap diamond (c-BN) as the substrate and key functional layer of the device. It fully leverages c-BN's advantages, such as its high bandgap, high thermal conductivity, and high breakdown electric field strength, to effectively suppress intrinsic carrier excitation and thermal failure behavior under high temperature conditions. Furthermore, c-BN has a bandgap of approximately 6.4 eV and a vacuum transition critical temperature of approximately 1800 K, exhibiting excellent thermal stability and environmental adaptability. Figure 2 As shown ( Figure 2 In this context, CBM represents the conduction band bottom, VBM represents the price band top, and E... g E represents the bandgap width. D E represents the donor's energy level. F (Representing the Fermi level). When c-BN and diamond form a heterojunction, due to the differences in electron affinity and Fermi level positions between the two materials, electron redistribution occurs at the interface, inducing the formation of an n-type conductive channel on the diamond side. By introducing the heterostructure of c-BN and diamond and surface termination engineering, the limitations of high activation energy and difficulty in effectively activating charge carriers in diamond materials are avoided, providing a stable material and device foundation for constructing diamond CMOS devices suitable for extreme environments.

[0022] Furthermore, addressing the issues of significant mobility differences, difficulty in matching driving capabilities, and the need for size compensation to achieve balance in existing diamond CMOS structures between NMOS and PMOS devices, this invention constructs an n-type conductive channel through a heterostructure of diamond and c-BN, forming a complementary structure with matched driving capabilities with a silicon-terminated diamond PMOS device. For example... Figure 3 As shown, the channel mobility of silicon-terminated diamond PMOS devices typically ranges from 10 to 50 cm⁻¹. 2 ·V -1 ·s -1 Within this range, the effective channel mobility of n-type conductive channels constructed based on heterostructures of c-BN and diamond can cover 20-500 cm⁻¹. 2 ·V -1 ·s -1 Within the specified range, the n-type and p-type mobilities of the two devices can form an effective match, significantly improving the conduction asymmetry problem between NMOS and PMOS devices. This facilitates the balance of driving capabilities of complementary devices, reduces the need for device size compensation, lowers parasitic capacitance and resistance, and thus improves the switching speed and power consumption characteristics of CMOS circuits.

[0023] To address the challenge of achieving monolithic integration using heterogeneous combinations of diamond PMOS and gallium nitride NMOS devices, a common technique in existing technologies, this invention integrates NMOS and PMOS devices on a single diamond substrate, improving the monolithic integration density and system-level reliability of CMOS devices. This invention integrates NMOS devices based on a c-BN and diamond heterostructure with silicon-terminated diamond PMOS devices on the same diamond substrate, avoiding the problems of process incompatibility, high interconnect complexity, and large parasitic parameters associated with multi-material, multi-substrate solutions. Furthermore, leveraging the excellent thermal conductivity of the diamond substrate allows for full utilization of the heat dissipation advantages of diamond materials at the system level, thereby enhancing the overall stability and reliability of CMOS devices under extreme environments such as high power density and high-temperature, high-irradiation conditions.

[0024] In this embodiment, by setting the boron-doped diamond layer 7 as an embedded structure with its lower surface lower than the upper surface of the diamond substrate layer 1 and its upper surface higher than the upper surface of the diamond substrate layer 1, a low barrier and low contact resistance p-type structure can be formed without damaging the silicon terminal diamond channel structure. + The source-drain contact region, on the other hand, avoids the direct influence of the metal electrode on the channel region, thereby improving the gate control capability of the PMOS device, reducing static power consumption, and enhancing device reliability. In a specific embodiment, please refer to... Figure 1 NMOS devices also include: The first source electrode 3 and the first drain electrode 4 are located on the remaining portion of the diamond substrate layer 1 in the first region, and the first source electrode 3 and the first drain electrode 4 are located on both sides of the c-BN layer 2. The first source electrode 3 and the first drain electrode 4 are in electrical contact with the c-BN layer 2. The first gate dielectric layer 5 is located on the c-BN layer 2, part of the first source electrode 3 and part of the first drain electrode 4; The first gate electrode 6 is located in the groove of the first gate dielectric layer 5.

[0025] In an optional embodiment, the upper surfaces of the first source electrode 3 and the first drain electrode 4 are on the same horizontal plane, and the upper surfaces of the first source electrode 3 and the first drain electrode 4 are above the upper surface of the c-BN layer 2. This allows the metal electrode to spatially span the c-BN layer 2, thereby effectively coupling with the two-dimensional electron gas channel at the heterogeneous interface formed by c-BN and diamond, avoiding the large potential barrier or contact resistance introduced by the metal electrode mainly contacting the bulk phase of c-BN. Furthermore, the above structure also facilitates the effective injection of charge carriers into the two-dimensional electron gas channel, ensuring the normal conduction of the NMOS device and improving its electrical performance stability. The lower surface of the first gate electrode 6 is above the upper surfaces of the first source electrode 3 and the first drain electrode 4, and the upper surface of the first gate electrode 6 is above the first gate dielectric layer 5. This avoids the shielding effect of the source and drain metals on the gate electric field, allowing the first gate electrode 6 to dominate the electric field control and ensuring that the two-dimensional electron gas channel formed by c-BN and diamond can be effectively gate-controlled. Simultaneously, the first gate electrode 6 being disposed above the first gate dielectric layer 5 forms a complete metal-dielectric-semiconductor gate control structure, which is beneficial for obtaining stable and controllable threshold characteristics and improving the operational reliability of the NMOS device.

[0026] In one specific embodiment, please continue to see Figure 1 PMOS devices also include: The second source electrode 9 and the second drain electrode 10 are located on a portion of the upper surface of the two boron-doped diamond layers 7, respectively. The second gate dielectric layer 11 is located on the upper surface of the remaining portion of the silicon terminal thin film layer 8 and the two boron-doped diamond layers 7. The second gate electrode 12 is located in the groove of the second gate dielectric layer 11.

[0027] In an optional embodiment, the upper surface of the silicon terminal thin film layer 8 is located below the upper surface of the boron-doped diamond layer 7. This avoids interference from the high concentration of boron doping regions on the silicon terminal surface states and the two-dimensional hole gas channels they induce, ensuring that the channel conductivity mechanism is dominated by the silicon terminal structure. Simultaneously, the presence of boron-doped diamond layers 7 on both sides of the silicon terminal thin film layer 8 facilitates the formation of low-contact-resistance source / drain contact regions without disrupting the silicon terminal channel structure, and defines the channel region in the lateral direction, thereby improving the gate control capability and operational stability of the PMOS device. The upper surfaces of the second source electrode 9 and the second drain electrode 10 are on the same horizontal plane, and the upper surfaces of the second source electrode 9 and the second drain electrode 10 are above the upper surface of the second gate dielectric layer 11, which is above the upper surface of the boron-doped diamond layer 7. The lower surface of the second gate electrode 12 is above the upper surface of the boron-doped diamond layer 7, and the upper surface of the second gate electrode 12 is above the upper surfaces of the second source electrode 9 and the second drain electrode 10. In this embodiment, placing the lower surface of the second gate electrode 12 above the upper surface of the boron-doped diamond layer 7 avoids the shielding effect of the heavily doped source / drain regions on the gate electric field, allowing the gate electric field to effectively act on the two-dimensional hole gas channel formed below the silicon terminal thin film layer 8. At the same time, placing the upper surface of the second gate electrode 12 above the upper surfaces of the second source electrode 9 and the second drain electrode 10 establishes the dominant position of the second gate electrode 12 in electric field control in space, suppresses the interference of the source / drain electrodes on the channel potential, and thus improves the gate control capability and operating stability of the PMOS device.

[0028] In one specific embodiment, the first drain electrode 4 and the second drain electrode 10 are connected by a first lead, the first gate electrode 6 and the second gate electrode 12 are connected by a second lead, the first source electrode 3 is used to ground, and the second source electrode 9 is used to connect to the power supply voltage.

[0029] Optionally, the crystal plane of the diamond substrate 1 can be any one of (100), (110) or (111), and the thickness ranges from 1 to 1000 μm.

[0030] Optionally, the thickness of the c-BN layer 2 ranges from 30 to 100 nm, and the specific thickness can be obtained by coordinating the deposition time and sputtering power; the material of the first source electrode 3 includes one or more of Ti, Al, Ni, Pt, and Au, and the thickness is 300 nm. For example, the material of the first source electrode 3 is a bottom-up stacked structure of Ti and Au, with a thickness of 60 / 240 nm; the material of the first drain electrode 4 includes one or more of Ti, Al, Ni, Pt, and Au, and the thickness is 300 nm. For example, the material of the first drain electrode 4 is a bottom-up stacked structure of Ti and Au, with a thickness of 60 / 240 nm; the material of the first gate dielectric layer 5 includes SiO2, Al2O3, and SiN. x The material of the first gate dielectric layer 5 is any one of HfO2 and MoO3, with a thickness ranging from 15 to 20 nm. For example, the material of the first gate dielectric layer 5 is Al2O3 with a thickness of 15 nm. The material of the first gate electrode 6 includes one or more of Ni, Au, Al, and Pt, with a thickness ranging from 60 to 120 nm. For example, the material of the first gate electrode 6 is Al with a thickness of 100 nm.

[0031] Optionally, the thickness of the silicon terminal thin film layer 8 ranges from 2 to 3 nm; the material of the second source electrode 9 includes one or more of Ti, Al, Ni, Pt, and Au, with a thickness of 300 nm. For example, the material of the second source electrode 9 is a bottom-up stacked structure of Ti and Au, with a thickness of 60 / 240 nm; the material of the second drain electrode 10 includes one or more of Ti, Al, Ni, Pt, and Au, with a thickness of 300 nm. For example, the material of the second drain electrode 10 is a bottom-up stacked structure of Ti and Au, with a thickness of 60 / 240 nm; the material of the second gate dielectric layer 11 includes Al2O3, with a thickness of 10 to 35 nm; the material of the second gate electrode 12 includes Al, with a thickness of 50 to 150 nm; and the thickness of the boron-doped diamond layer 7 ranges from 10 to 20 nm.

[0032] Furthermore, the boron in boron-doped diamond layer 7 is heavily doped, with a boron doping concentration greater than or equal to 1 × 10⁻⁶. 19 cm -3 For example, the concentration of boron is approximately 3 × 10⁻⁶. 20 cm -3In this embodiment, the boron in the boron-doped diamond layer is heavily doped with a doping concentration of not less than 1×10⁻⁶. 19 cm -3 This can make the boron-doped diamond layer 7 exhibit quasi-metallic properties. + This characteristic significantly reduces the contact barrier and contact resistance between the metal electrode and diamond, ensuring efficient injection of charge carriers into the two-dimensional hole gas channel induced by silicon termination. Simultaneously, the heavily doped source / drain regions are insensitive to the applied gate electric field, which helps to confine the gate control effect to the channel region, thereby improving the gate control capability, temperature stability, and overall operational reliability of the PMOS device.

[0033] The diamond substrate layer 1 of this invention is a substrate used by both PMOS and NMOS devices. Furthermore, a two-dimensional electron gas is induced between the diamond substrate layer 1 and the c-BN layer 2 at the diamond side of the c-BN-diamond heterostructure interface, serving as the conductive channel for the NMOS device. The diamond substrate layer 1, c-BN layer 2, first source electrode 3, first drain electrode 4, first gate dielectric layer 5, and first gate electrode 6 form an NMOS device based on the c-BN-diamond heterostructure. The diamond substrate layer 1, boron-doped diamond layer 7, silicon-terminated thin film layer 8, second source electrode 9, second drain electrode 10, second gate dielectric layer 11, and second gate electrode 12 form a silicon-terminated diamond PMOS device. Electrical isolation between the c-BN-diamond heterostructure NMOS device and the silicon-terminated diamond PMOS device is achieved by disrupting the local c-BN-diamond heterostructure interface to form an isolation region. Therefore, this invention constructs a monolithic integrated CMOS device structure of silicon-terminated diamond and boron nitride by integrating an NMOS device based on a c-BN and diamond heterostructure and a PMOS device based on silicon-terminated diamond on the same diamond substrate. This CMOS device avoids the limitations of high activation energy and difficulty in effectively activating carriers in n-type doping of diamond materials, while achieving controllable conductivity of the PMOS device through the synergistic regulation of silicon termination and gate dielectric. Since the NMOS and PMOS devices have good matching in terms of channel mobility, it is beneficial to achieve a balance in the driving capabilities of complementary devices, thereby reducing size compensation requirements and parasitic effects. At the same time, the integration of the NMOS and PMOS devices on the same diamond substrate fully utilizes the excellent thermal conductivity of diamond, providing a structural basis for the stable operation of the CMOS device in extreme environments such as high temperature and strong radiation.

[0034] Example 2 Please see Figures 4a-4l , Figures 4a-4lThis is a schematic diagram illustrating the fabrication process of a silicon-terminated diamond and boron nitride integrated CMOS device provided by the present invention. Based on Example 1, the present invention further provides a method for fabricating a silicon-terminated diamond and boron nitride integrated CMOS device. This method is used to fabricate the CMOS device described in Example 1, and the method includes: Step 1, as follows Figure 4a and Figure 4b As shown, a c-BN layer 2 is grown on a diamond substrate 1.

[0035] Specifically, a c-BN layer 2 is grown on the upper surface of an ultrasonically cleaned diamond substrate layer 1 using radio frequency magnetron sputtering. The region corresponding to the heterostructure of c-BN and diamond constitutes the active region basis of the NMOS device. The specific process includes: using a boron nitride target, growing the c-BN layer 2 on the diamond substrate layer 1 using radio frequency magnetron sputtering. The process parameters are: sputtering power of 65~110 W, sputtering temperature of 625~775 ℃, sputtering time of 0.5~8 hours, nitrogen flow rate of 0~20 sccm, argon flow rate of 0~80 sccm, growth pressure of 1~100 mbar, and substrate bias voltage of 0~280 V.

[0036] This embodiment modulates the band bending and interface charge state of the heterojunction between c-BN and diamond by synergistically controlling the sputtering power, atmosphere ratio, sputtering temperature, and bias parameters. By controlling the carrier distribution at the heterojunction, the surface density of the two-dimensional electron gas induced at the interface is made within an adjustable range, thereby matching the magnitude of the two-dimensional electron gas formed at the interface with the magnitude of the two-dimensional hole gas formed on the subsequent silicon-terminated diamond surface, thus reducing the asymmetry in the driving capability between NMOS and PMOS devices.

[0037] Step 2, as follows Figure 4c As shown, the c-BN layer 2 in the second region is selectively removed.

[0038] Specifically, the c-BN layer 2 is selectively removed in the second region of the pre-fabricated PMOS device, thereby causing the heterogeneous interface between c-BN and diamond in the second region to fail and removing the two-dimensional electron gas at the interface, in order to prevent the formation of n-type conductive channels in the second region, thus achieving a preliminary distinction between the active region of the NMOS device and the active region of the PMOS device.

[0039] The specific steps include: spin-coating photoresist onto the sample surface and performing exposure and development to create a window in the second region of the pre-fabricated PMOS device, while the remaining regions are protected by photoresist; subsequently, reactive ion etching is used to etch the c-BN layer 2 in the second region, with the etching depth slightly greater than the thickness of the c-BN layer 2, to disrupt the heterogeneous interface between c-BN and diamond and remove the two-dimensional electron gas formed at the interface; after etching, the surface photoresist is removed. Through these steps, the heterogeneous structure of c-BN and diamond in the second region is removed, thereby achieving a preliminary distinction between the active regions of the NMOS device and the PMOS device.

[0040] The c-BN layer 2 is removed using a dry etching process, preferably ICP-RIE (Inductively Coupled Plasma Reactive Ion Etching). The etching gases are O2 and CH4, with an O2 flow rate of 40-80 sccm, a CH4 flow rate of 2-10 sccm, an etching pressure of 5-15 mTorr, an etching power of 600-1200 W, and an etching time of 30-240 s.

[0041] Step 3, as follows Figure 4c As shown, a dielectric layer 13 is grown on the exposed diamond substrate layer 1 and the remaining c-BN layer 2.

[0042] Specifically, a dielectric layer 13 is deposited on the exposed diamond substrate 1 and the remaining c-BN layer 2 to cover the surface of the diamond substrate 1 and the surface of the c-BN layer 2. This is used to protect and differentiate different device regions. The dielectric layer 13 on the diamond substrate 1 is used for the subsequent construction of surface termination and device structure. The dielectric layer 13 on the c-BN layer 2 is used to protect the heterostructure and provide a basis for the subsequent construction of PMOS and NMOS devices.

[0043] In this embodiment, the dielectric layer 13 is a SiO2 layer, deposited using a microwave plasma chemical vapor deposition (MPCVD) process with tetraethoxysilane (TEOS) as the silicon source. Specifically, during the deposition process, TEOS is introduced into the reaction chamber as a silicon source precursor. Under the action of the plasma generated by microwave excitation, the TEOS molecules decompose and react with the oxygen source, depositing a dense and uniform SiO2 film on the surface of the diamond substrate layer 1 and the c-BN layer 2. This SiO2 film is the dielectric layer 13.

[0044] Furthermore, the deposition process parameters for dielectric layer 13 (TEOS-SiO2) include: microwave power of 900~1200 W, reaction chamber pressure of 40~80 Torr, and temperature control within the range of 350~450℃; the carrier gas is high-purity hydrogen or inert gas with a flow rate of 80~150 sccm; the TEOS precursor is introduced by vaporization with an equivalent flow rate controlled within 0.5~3 sccm; the oxygen source gas can be selected from oxygen or nitrous oxide with a flow rate of 5~20 sccm; and the deposition time is 10~30 min, thereby obtaining a SiO2 dielectric layer with a thickness of 50~200 nm. The SiO2 dielectric layer deposited by the above TEOS-MPCVD process has low intrafilm stress and good step coverage, and can form a stable interface on diamond and c-BN surfaces, which can be used for isolation, protection, and subsequent etching masking of different functional areas of the device.

[0045] Step 4, as follows Figure 4d As shown, a portion of the dielectric layer 13 in the second region is selectively removed to expose the diamond substrate layer 1, thereby defining the location of the active region of the PMOS device for subsequent formation of the silicon terminal and diamond channel structure.

[0046] Specifically, photoresist is spin-coated onto the sample surface and exposed and developed to form an opening in the second region of the pre-fabricated PMOS device, while the remaining regions are covered by photoresist and dielectric layer 13. Subsequently, reactive ion etching is used to selectively remove the dielectric layer 13 in the second region, retaining the dielectric layer 13 used to form the silicon termination region, and exposing the surface of the remaining portion of the diamond substrate layer 1.

[0047] In this embodiment, the dielectric layer 13 is a SiO2 layer, etched using an ICP-RIE process. The SiO2 layer is selectively etched in a fluorine-containing etching atmosphere. The etching gas can be selected from CF4, CHF3, SF6, or a mixture thereof. The etching power is 50~200 W, the etching pressure is 5~50 mTorr, and the etching time is 30~180 s to ensure complete exposure of the diamond substrate layer 1 surface in the second region. Through the above steps, the exposed surface of the diamond substrate layer 1 is formed in the second region, thereby defining the active region of the PMOS device and providing conditions for the subsequent formation of the silicon termination and diamond channel structure.

[0048] Step 5, as follows Figure 4eAs shown, in a mixed atmosphere of hydrogen, carbon source gas and boron source gas, two boron-doped diamond layers 7 are formed on both sides of the remaining dielectric layer 13 in the second region using a microwave plasma chemical vapor deposition process. The lower surface of the boron-doped diamond layer 7 is located below the upper surface of the diamond substrate layer 1, and the upper surface of the boron-doped diamond layer 7 is located above the upper surface of the diamond substrate layer 1. The boron-doped diamond layer 7 is used as the source and drain contact region of the PMOS device, thereby forming a low-barrier, low-contact-resistance ohmic contact structure between the metal electrode and the silicon terminal and the diamond channel.

[0049] Specifically, a boron-doped diamond layer 7 is selectively grown on the surface of the diamond substrate 1 exposed after etching using a microwave plasma chemical vapor deposition process. In this embodiment, the growth conditions for the boron-doped diamond layer 7 include: a mixed atmosphere of hydrogen, carbon source gas, and boron source gas, wherein the flow rate of hydrogen is 85 sccm, the flow rate of carbon source gas (CH4) is 5 sccm, and the boron source gas is trimethylborane (TMB) with a flow rate of 10 sccm; the growth temperature is 760~800℃, and the boron doping concentration of the resulting boron-doped diamond layer 7 is approximately 3×10⁻⁶. 20 cm -3 The boron-doped diamond layer 7 has epitaxial growth conditions only on the surface of the exposed diamond substrate layer 1, while the rest is covered and protected by the dielectric layer 13. Therefore, the boron-doped diamond layer 7 is selectively formed in the active region of the PMOS device and has no significant impact on other device regions.

[0050] It should also be noted that during the growth of the boron-doped diamond layer 7, the channel region of the PMOS device is covered by a SiO2 dielectric layer and is in a high-temperature hydrogen plasma (containing a carbon source) environment. Under these conditions, the interface between SiO2 and diamond undergoes interface activation and chemical bond reconstruction, resulting in the formation of a silicon-terminated interface structure characterized by C-Si bonding on the surface of the diamond in the channel region. This induces the formation of a two-dimensional hole gas conductive channel on the diamond subsurface, laying the foundation for the subsequent channel gate control of the PMOS device.

[0051] Step 6, as follows Figure 4f As shown, a portion of the dielectric layer 13 and a portion of the c-BN layer 2 in the first region are selectively removed to expose the diamond substrate layer 1, thereby defining the location of the active region of the NMOS device.

[0052] Specifically, photoresist is spin-coated onto the sample surface and exposed and developed to form a window in the first region, while the remaining area is protected by photoresist. Subsequently, reactive ion etching is used to etch the SiO2 dielectric layer in the first region until the underlying c-BN layer 2 is exposed. Then, the c-BN layer in the first region is etched under the same mask conditions to define the effective operating area of ​​the NMOS device. Through these steps, a heterostructure exposing c-BN and diamond is formed in the first region, thus defining the active region of the NMOS device and providing a foundation for the subsequent construction of the source / drain and gate control structures of the NMOS device.

[0053] In this embodiment, the etching of the SiO2 dielectric layer is completed using the ICP-RIE process. The SiO2 dielectric layer is selectively etched in a fluorine-containing etching atmosphere. The etching gas can be selected from CF4, CHF3, SF6 or a mixture thereof. The etching power is 50~200W, the etching pressure is 5~50mTorr, and the etching time is 30~180s.

[0054] Step 7, as follows Figure 4g As shown, the remaining dielectric layer 13 in the first and second regions is removed, and a silicon terminal thin film layer 8 with C-Si bonds is retained on the surface of the diamond substrate layer 1 between the two boron-doped diamond layers 7, thereby forming a channel structure between silicon terminals and diamond.

[0055] Specifically, a dry etching process is used to remove the remaining dielectric layer 13 in the first and second regions to expose the surface of the diamond substrate layer 1 in the second region while retaining the formed silicon terminal thin film layer 8 with C-Si bonds. In this embodiment, the dielectric layer 13 is a SiO2 layer. Reactive ion etching or inductively coupled plasma etching is used to selectively etch the SiO2 dielectric layer in a fluorine-containing etching atmosphere. The etching gas can be selected from CF4, CHF3, SF6, or a mixture thereof. The etching power is 50~200 W, the etching pressure is 5~50 mTorr, and the etching time is 30~180 s.

[0056] Through the above processing, the SiO2 dielectric layer in the first and second regions is etched away, while the C~Si bonding interface structure formed on the surface of the diamond substrate layer 1 due to the reaction between SiO2 and the diamond interface in the previous step 5 is retained and exposed, thereby retaining the silicon terminal thin film layer 8 and realizing the construction of the channel structure between the silicon terminal and the diamond.

[0057] It should be noted that the formation of the channel structure between silicon terminals and diamond is related to the C-Si bond reconstruction that occurs at the SiO2-diamond interface during the preceding high-temperature processing. The dry etching step is only used to remove the SiO2 bulk structure and expose the C-Si bond interface. This process has good controllability under controlled etching power and etching time conditions.

[0058] Step 8, as follows Figure 4h As shown, a second gate dielectric layer 11 is grown on a portion of the upper surface of the silicon terminal thin film layer 8 and the two boron-doped diamond layers 7, and grooves are formed on the second gate dielectric layer 11.

[0059] Specifically, a window is formed in the PMOS region using photolithography, with the remaining area covered by photoresist and a dielectric layer. Subsequently, an atomic layer deposition (ALD) process is used to deposit a second gate dielectric layer 11 on portions of the silicon termination thin film layer 8 and the two boron-doped diamond layers 7. In this embodiment, the second gate dielectric layer 11 is an Al2O3 layer, deposited at a temperature of 300°C, using trimethylaluminum (TMA) as the aluminum source, H2O as the oxidant, and a deposition thickness of 15 nm. Through these steps, a uniform and dense second gate dielectric layer 11 can be formed, thereby completing the construction of the gate control structure of the PMOS device. Simultaneously, the second gate dielectric layer 11 provides stability and protection for the silicon termination thin film layer 8. The deposition of the second gate dielectric layer 11 is performed after the formation of the silicon termination thin film layer 8, which reduces the risk of interface degradation caused by exposure of the silicon termination thin film layer 8 to air.

[0060] Step 9, as follows Figure 4i As shown, a first source electrode 3 and a first drain electrode 4 are formed on the diamond substrate layer 1 exposed in the first region, while a second source electrode 9 and a second drain electrode 10 are formed on the remaining upper surfaces of the two boron-doped diamond layers 7, respectively.

[0061] Specifically, a mask is formed on the sample surface using photolithography, creating windows at the source / drain locations corresponding to the first and second regions, with the remaining areas protected by photoresist. Subsequently, physical vapor deposition (PVD) is used to deposit metal electrode materials in the windowed areas. In this embodiment, the source / drain electrodes are deposited using magnetron sputtering, and the metal material is a Ti / Au bilayer structure, where the Ti layer serves as an adhesion layer and the Au layer as a conductive layer; the Ti layer has a thickness of 60 nm, and the Au layer has a thickness of 240 nm. After metal deposition, a lift-off process removes the metal layers in the non-source / drain regions, retaining only the metal electrodes on both sides of the c-BN layer 2 as the first source electrode 3 and the first drain electrode 4, as well as the second source electrode 9 and the second drain electrode 10 on the upper surfaces of the two boron-doped diamond layers 7, thus completing the construction of the source / drain structures for the NMOS and PMOS devices, respectively.

[0062] Step 10, as follows Figure 4j As shown, a first gate dielectric layer 5 is grown on the c-BN layer 2, a portion of the first source electrode 3, and a portion of the first drain electrode 4, and a groove is formed on the first gate dielectric layer 5.

[0063] Specifically, a window is formed in the first region using photolithography, with the remaining area covered by photoresist. Subsequently, an atomic layer deposition process is used to deposit a first gate dielectric layer 5 on the c-BN layer 2, a portion of the first source electrode 3, and a portion of the first drain electrode 4. In this embodiment, the first gate dielectric layer 5 is an Al2O3 layer, deposited at a temperature of 300 °C, using trimethylaluminum as the aluminum source, H2O as the oxidant, and a deposition thickness of 20 nm. Through these steps, a uniform and dense first gate dielectric layer 5 is formed, thereby completing the construction of the gate control structure of the NMOS device based on the heterostructure of c-BN and diamond.

[0064] Step 11, as follows Figure 4k As shown, the c-BN layer 2 between the first and second regions is removed.

[0065] Specifically, the c-BN layer 2 between the first and second regions is selectively removed to form a device isolation region, thereby achieving electrical isolation between the NMOS and PMOS devices.

[0066] In this embodiment, an isolation region mask is formed on the sample surface using photolithography. A window is created only in the isolation region between the first and second regions, with the remaining portion protected by photoresist. Subsequently, the isolation region is etched to disrupt the local c-BN-diamond heterogeneous interface structure. In this embodiment, reactive ion etching is used to etch the isolation region using oxygen as the etching gas, with an etching power of 80-200W and an etching pressure of 5-50 mTorr. The etching time is adjusted according to the c-BN layer thickness, ensuring that the c-BN-diamond heterogeneous interface within the isolation region no longer possesses two-dimensional electron gas conductivity. Through these steps, an electrical isolation region is formed between the NMOS and PMOS device regions, effectively suppressing leakage current channels between devices and enabling stable operation of the monolithically integrated CMOS device.

[0067] Step 12, as follows Figure 4l As shown, a first gate electrode 6 is formed in a groove in the first gate dielectric layer 5, and a second gate electrode 12 is formed in a groove in the second gate dielectric layer 11.

[0068] Specifically, a mask is formed on the sample surface using photolithography, and windows are created at the gate positions corresponding to the first and second regions, with the remaining areas protected by photoresist. Subsequently, physical vapor deposition is used to deposit the gate metal material in the windowed areas. In this embodiment, both the first gate electrode 6 and the second gate electrode 12 are deposited using magnetron sputtering, with the gate metal material being Al and a deposition thickness of 100 nm. After metal deposition, the metal layer in the non-gate regions is removed using a lift-off process, thereby forming the corresponding gate electrode structures in the first and second regions, respectively.

[0069] Step 13: Connect the first drain electrode 4 and the second drain electrode 10 through the first lead, and connect the first gate electrode 6 and the second gate electrode 12 through the second lead to realize the electrical interconnection between the NMOS device and the PMOS device. Specifically, electrical interconnect structures are formed on the device surface using photolithography and metal deposition processes to connect the gate and drain of the NMOS and PMOS devices, respectively. In this embodiment, the electrical interconnect leads employ a Ti / Au metal system stacked from bottom to top, with a Ti layer thickness of 60 nm and an Au layer thickness of 240 nm. Through these steps, electrical interconnection between the NMOS and PMOS devices is achieved on the same diamond substrate, completing the fabrication of a silicon-terminated diamond and boron nitride monolithic integrated CMOS device.

[0070] This invention achieves the co-fabrication of NMOS and PMOS devices on the same diamond substrate through a series of selective etching, heterogeneous thin film deposition, and surface termination engineering steps. By introducing a heterostructure of c-BN and diamond in the first region and combining it with gate dielectric modulation, a stable n-type conductive channel is achieved. By constructing a silicon-terminated, diamond-based MOS structure in the second region, effective gate control of the channel conductivity of the PMOS device is achieved. Simultaneously, the above fabrication process, through region-selective etching and interface isolation design, achieves monolithic isolation and integration of the NMOS and PMOS device regions. The above process flow is logically connected and highly repeatable, which is beneficial for achieving low-power, high-reliability diamond CMOS device fabrication while ensuring the quality of the heterogeneous interface and the stability of the surface termination.

[0071] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A CMOS device integrating silicon-terminated diamond and boron nitride, characterized in that, This includes an NMOS device and a PMOS device integrated on the same diamond substrate and spaced apart, wherein the NMOS device is located in a first region of the diamond substrate and the PMOS device is located in a second region of the diamond substrate, wherein: The NMOS device includes a c-BN layer located on a portion of the diamond substrate layer in the first region. A two-dimensional electron gas is formed between the c-BN layer and the diamond substrate layer, serving as a conductive channel for the NMOS device. The PMOS device includes a silicon-terminated thin film layer with C-Si bonds and two boron-doped diamond layers. The silicon-terminated thin film layer is located on a portion of the diamond substrate layer in the second region. The two boron-doped diamond layers are located on a portion of the diamond substrate layer in the second region and are located on both sides of the silicon-terminated thin film layer. The lower surface of the boron-doped diamond layer is located below the upper surface of the diamond substrate layer, and the upper surface of the boron-doped diamond layer is located above the upper surface of the diamond substrate layer.

2. The CMOS device according to claim 1, characterized in that, The NMOS device also includes: The first source electrode and the first drain electrode are located on the remaining portion of the diamond substrate layer in the first region, and the first source electrode and the first drain electrode are located on both sides of the c-BN layer, and the first source electrode and the first drain electrode both form electrical contact with the c-BN layer. The first gate dielectric layer is located on the c-BN layer, on a portion of the first source electrode, and on a portion of the first drain electrode; The first gate electrode is located in the groove of the first gate dielectric layer.

3. The CMOS device according to claim 2, characterized in that, The upper surfaces of the first source electrode and the first drain electrode are on the same horizontal plane, and the upper surfaces of the first source electrode and the first drain electrode are above the upper surface of the c-BN layer. The lower surface of the first gate electrode is above the upper surfaces of the first source electrode and the first drain electrode, and the upper surface of the first gate electrode is above the first gate dielectric layer.

4. The CMOS device according to claim 2, characterized in that, The PMOS device also includes: The second source electrode and the second drain electrode are respectively located on a portion of the upper surface of the two boron-doped diamond layers; The second gate dielectric layer is located on the upper surface of the silicon terminal thin film layer and the remainder of the two boron-doped diamond layers; The second gate electrode is located in the groove of the second gate dielectric layer.

5. The CMOS device according to claim 4, characterized in that, The upper surface of the silicon terminal thin film layer is located below the upper surface of the boron-doped diamond layer; The upper surfaces of the second source electrode and the second drain electrode are on the same horizontal plane, and the upper surfaces of the second source electrode and the second drain electrode are above the upper surface of the second gate dielectric layer, which is above the upper surface of the boron-doped diamond layer. The lower surface of the second gate electrode is above the upper surface of the boron-doped diamond layer, and the upper surface of the second gate electrode is above the upper surfaces of the second source electrode and the second drain electrode.

6. The CMOS device according to claim 4, characterized in that, The first drain electrode and the second drain electrode are connected by a first lead, the first gate electrode and the second gate electrode are connected by a second lead, the first source electrode is used to ground, and the second source electrode is used to connect to the power supply voltage.

7. The CMOS device according to claim 1, characterized in that, The boron doping concentration in the boron-doped diamond layer is greater than or equal to 1 × 10⁻⁶. 19 cm -3 .

8. A method for fabricating a CMOS device integrating silicon-terminated diamond and boron nitride, characterized in that, The fabrication method is used to fabricate the CMOS device according to any one of claims 1 to 7, and the fabrication method includes: Step 1: Grow a c-BN layer on a diamond substrate; Step 2: Selectively remove the c-BN layer in the second region; Step 3: Grow a dielectric layer on the exposed diamond substrate and the remaining c-BN layer; Step 4: Selectively remove a portion of the dielectric layer in the second region to expose the diamond substrate layer, thereby defining the location of the active region of the PMOS device; Step 5: In a mixed atmosphere of hydrogen, carbon source gas and boron source gas, two boron-doped diamond layers are formed on both sides of the remaining dielectric layer in the second region using microwave plasma chemical vapor deposition. The lower surface of the boron-doped diamond layer is located below the upper surface of the diamond substrate layer, and the upper surface of the boron-doped diamond layer is located above the upper surface of the diamond substrate layer. Step 6: Selectively remove part of the dielectric layer and part of the c-BN layer in the first region to expose the diamond substrate layer, thereby defining the location of the active region of the NMOS device; Step 7: Remove the remaining dielectric layer in the first region and the second region, and retain a silicon-terminated thin film layer with C-Si bonds on the surface of the diamond substrate layer between the two boron-doped diamond layers.

9. The preparation method according to claim 8, characterized in that, The process after step 7 also includes: Step 8: Grow a second gate dielectric layer on the silicon terminal thin film layer and on a portion of the upper surface of the two boron-doped diamond layers; Step 9: Form a first source electrode and a first drain electrode on the diamond substrate layer exposed in the first region, and simultaneously form a second source electrode and a second drain electrode on the remaining upper surfaces of the two boron-doped diamond layers, respectively. Step 10: Grow a first gate dielectric layer on the c-BN layer, on a portion of the first source electrode, and on a portion of the first drain electrode; Step 11: Remove the c-BN layer between the first region and the second region; Step 12: Form a first gate electrode in the groove of the first gate dielectric layer, and simultaneously form a second gate electrode in the groove of the second gate dielectric layer; Step 13: Connect the first drain electrode and the second drain electrode through the first lead, and connect the first gate electrode and the second gate electrode through the second lead to realize the electrical interconnection between the NMOS device and the PMOS device.

10. The preparation method according to claim 8, characterized in that, Step 1 includes: The c-BN layer was grown on the diamond substrate using a boron nitride target and a radio frequency magnetron sputtering process. The process parameters were as follows: sputtering power of 65~110 W, sputtering temperature of 625~775 ℃, sputtering time of 0.5~8 hours, nitrogen flow rate of 0~20 sccm, argon flow rate of 0~80 sccm, growth pressure of 1~100 mbar, and substrate bias of 0~280 V.

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