Image sensor and preparation method thereof

Abstract

The invention provides an image sensor and a preparation method thereof, and the method comprises the steps: providing a substrate which is provided with a first surface and a second surface which are oppositely disposed in the thickness direction of the substrate, forming an interlayer dielectric layer on the second surface of the substrate, and forming an interconnection structure in the interlayer dielectric layer; forming a groove extending inwards from the first surface in the substrate, wherein the groove exposes part of the interconnection structure; forming a conductive layer covering the bottom and the side wall of the groove and the first surface; spin-coating an etching barrier material on the conductive layer to fill at least partial depth of the trench; the etching barrier material serves as a mask, the conductive layer on the side wall of the groove and the first surface is removed through etching, only the conductive layer located at the bottom of the groove is reserved to form a bonding pad structure, and after etching is completed, the top face of the residual etching barrier material in the groove is higher than the top face of the conductive layer. According to the invention, the process steps and cost are saved, the production efficiency is improved, and the stability and reliability of the device are improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to an image sensor and a method for fabricating the same. Background Technology

[0002] Back-side illuminated CMOS image sensors (BSI CIS) are high-performance image sensors that have been widely used in smartphones, digital cameras, and security monitoring in recent years. Compared to traditional front-side illuminated CMOS image sensors (FSI CIS), BSI CIS places the photosensitive area on the back of the wafer. Light can reach the photodiode directly without passing through complex metal wiring layers, thus significantly improving quantum efficiency (QE) and signal-to-noise ratio (SNR), and enhancing image quality under low-light conditions. In the manufacturing process of BSI CIS, a key step is wafer thinning after the front-end and mid-end processes, followed by a series of back-end processes on the back side. Among these, etching deep and wide trenches on the back side of the pixel area and forming metal lines or pads within these trenches is crucial for achieving back-side electrical connections and signal output. Metal wires within trenches are typically used to connect pixel arrays to peripheral circuitry, or as pads for solder ball connections.

[0003] In related technologies, the method for generating pad structures within trenches in back-illuminated image sensors typically includes the following steps: First, trenches are etched on the back side of the substrate; then, a conductive layer is formed by depositing aluminum (Al) or other conductive metals within the trenches and on the entire substrate surface; second, photoresist is spin-coated onto the conductive layer, and after soft baking, exposure is performed using a photolithography machine and a specific photomask, followed by a series of complex photolithography steps such as post-baking, development, and hard baking, ultimately forming the desired patterned photoresist layer within the trenches; finally, using the patterned photoresist as a mask, the conductive layer around the trenches and on the sidewalls is etched away, retaining a portion of the conductive layer at the bottom of the trenches to form the pad structure. However, the steps for forming the pad structure in related technologies are cumbersome, require photomasks, and are costly. Furthermore, the formed pad structure creates grooves between the pad structure and the sidewalls of the trench, which remain after subsequent filling processes, affecting subsequent planarization processes. Summary of the Invention

[0004] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] To address the existing problems, this application provides a method for fabricating an image sensor, comprising: providing a substrate having a first surface and a second surface disposed opposite to each other along its thickness direction; forming an interlayer dielectric layer on the second surface of the substrate, wherein an interconnect structure is formed in the interlayer dielectric layer; forming a trench extending inward from the first surface in the substrate, the trench exposing a portion of the interconnect structure; forming a conductive layer covering the bottom and sidewalls of the trench and the first surface; spin-coating an etching barrier material on the conductive layer to fill at least a portion of the depth of the trench; using the etching barrier material as a mask, etching away the sidewalls of the trench and the conductive layer on the first surface, leaving only the conductive layer at the bottom of the trench to form a pad structure, wherein, after the etching is completed, the top surface of the remaining etching barrier material in the trench is higher than the top surface of the conductive layer.

[0006] For example, the trench includes a first trench and at least one second trench, each second trench being located at the bottom of the first trench, each second trench communicating with the first trench and exposing a portion of the interconnect structure.

[0007] For example, the pad structure is located at the bottom and sidewall of the second trench and at the bottom of the first trench, wherein the pad structure is connected to the interconnect structure through the second trench and the pad structure is also in contact with the sidewall of the first trench.

[0008] For example, before etching the conductive layer, the conductive layer on the trench sidewall is in direct contact with the etching barrier material, and the thickness of the etching barrier material above the bottom of the trench is greater than the depth of the trench.

[0009] For example, during the etching process of the conductive layer, the etching rate of the etching barrier material is less than the etching rate of the conductive layer.

[0010] For example, before or during etching the conductive layer, the method further includes: performing at least one ashing treatment on the etching barrier material to reduce the thickness of the etching barrier material; and / or after forming the trench and before forming the conductive layer, further includes: forming an isolation layer covering the first surface and the sidewalls of the trench.

[0011] For example, after spin-coating the etching barrier material and before etching the conductive layer, the method further includes baking the etching barrier material to harden it.

[0012] For example, after forming the pad structure, the process further includes removing the etching barrier material from the pad structure.

[0013] For example, the etching barrier material includes at least one of photoresist, bottom anti-reflective coating, top anti-reflective coating, and spin-coated insulating medium.

[0014] This application also provides an image sensor, which is obtained using the aforementioned fabrication method.

[0015] The image sensor and its fabrication method provided in this application fill trenches by spin-coating an etch stop material. In subsequent etching, the etch stop material can serve as a self-aligning mask to remove the conductive layer on the trench sidewalls and the first surface of the substrate, leaving only the conductive layer at the bottom of the trench to form a pad structure. This achieves self-alignment between the pad structure and the trench without the need for an additional photolithography mask, saving process steps and costs, and improving production efficiency. In addition, the formed pad structure eliminates the "groove" structure that is easily generated in traditional processes, reducing the difficulty of subsequent processes and improving the stability and reliability of the device. Attached Figure Description

[0016] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.

[0017] In the attached image: Figures 1A to 1D A schematic diagram showing the image sensor obtained by sequentially implementing the image sensor fabrication method of the related technology of this application is illustrated. Figure 2 A flowchart illustrating a method for fabricating an image sensor according to a specific embodiment of this application is shown; Figures 3A to 3E This illustration shows a schematic diagram of the image sensor obtained by sequentially implementing a method for fabricating an image sensor according to a specific embodiment of this application; Figure 4 A schematic diagram of a trench and pad structure according to a specific embodiment of this application is shown. Detailed Implementation

[0018] The invention will now be described more fully with reference to the accompanying drawings, which illustrate embodiments of the invention. However, the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0019] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0020] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0021] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0022] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0023] In related technologies, such as Figures 1A to 1D As shown, the method for generating the pad structure in the trench of a back-illuminated image sensor typically includes the following steps: First, etching trenches to form trenches 11 on the back side of substrate 10; next, forming a conductive layer 12 by depositing aluminum (Al) or other conductive metals in the trenches 11 and on the entire back side of substrate 10; second, spin-coating photoresist on the conductive layer 12, followed by soft baking, exposure using a photolithography machine and a specific photomask, and then a series of complex photolithography steps such as post-baking, development, and hard baking, finally forming the desired patterned photoresist layer 13 in the trenches 11; finally, etching away part of the conductive layer to form the pad structure, using the patterned photoresist layer 13 as a mask, etching away the conductive layer 12 on the sidewalls of the trenches 11 and the conductive layer 12 on the substrate 10, leaving only a portion of the conductive layer 12 at the bottom of the trenches 11 to form the pad structure 14. However, the process of forming the pad structure 14 (i.e., metal line) in the related technology is cumbersome and requires photolithography using a photomask, which is costly. In addition, a groove 15 is formed between the formed pad structure 14 and the sidewall of the trench 11. When the material is filled into the trench, the groove 15 will remain in the filled material layer, affecting the subsequent planarization process of the filled material layer and ultimately having a negative impact on the quality of the device.

[0024] Therefore, in view of the aforementioned technical problems, this application proposes a method for fabricating an image sensor, such as... Figure 2 As shown, it mainly includes the following steps: Step S1, a substrate is provided, the substrate having a first surface and a second surface disposed opposite to each other along its thickness direction, and an interlayer dielectric layer is formed on the second surface of the substrate, wherein an interconnect structure is formed in the interlayer dielectric layer; Step S2: A trench extending inward from the first surface is formed in the substrate, exposing a portion of the interconnect structure. Step S3: Form a conductive layer covering the bottom and sidewalls of the trench and the first surface; Step S4: Spin-coat an etching barrier material onto the conductive layer to fill trenches of at least a partial depth. Step S5: Using an etch stop material as a mask, the conductive layer on the sidewalls of the trench and the first surface is etched away, leaving only the conductive layer at the bottom of the trench to form a pad structure. After etching, the top surface of the remaining etch stop material in the trench is higher than the top surface of the conductive layer.

[0025] The image sensor and its fabrication method according to the embodiments of this application fill the trench by spin-coating an etch stop material. In subsequent etching, the etch stop material can be used as a self-aligning mask to remove the conductive layer on the trench sidewalls and the first surface of the substrate, leaving only the conductive layer at the bottom of the trench to form a pad structure. The self-alignment of the pad structure and the trench can be achieved without an additional photolithography mask, saving process steps and costs, and improving production efficiency. In addition, the formed pad structure eliminates the "groove" structure that is easy to generate in traditional processes, reducing the difficulty of subsequent processes and improving the stability and reliability of the device.

[0026] Example 1 Below, for reference Figure 2 as well as Figures 3A to 3E The method for fabricating the image sensor of this application is described in detail, wherein, Figure 2 A flowchart illustrating a method for fabricating an image sensor according to a specific embodiment of this application is shown. Figures 3A to 3E The diagram illustrates a method for fabricating an image sensor according to a specific embodiment of this application, showing the resulting image sensor obtained by sequential implementation.

[0027] For example, the method for fabricating the image sensor of this application includes the following steps: First, step S1 is performed, providing a substrate having a first surface and a second surface disposed opposite to each other along its thickness direction, and forming an interlayer dielectric layer on the second surface of the substrate, wherein an interconnect structure is formed in the interlayer dielectric layer.

[0028] In one example, such as Figure 3AAs shown, a substrate 20 is provided, and the material of the substrate 20 includes, but is not limited to, at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), sapphire, or other III / V compound semiconductors; or silicon on dielectric (SOI), silicon on dielectric (SSOI), silicon germanium on dielectric (S-SiGeOI), silicon germanium on dielectric (SiGeOI), and germanium on dielectric (GeOI); or it may be a double-sided polished wafer (DSP), a ceramic substrate such as alumina, a quartz, or a glass substrate, etc. Although several examples of materials that can form a substrate have been described herein, any material that can serve as a substrate falls within the spirit and scope of the invention.

[0029] For example, the substrate 20 has a first surface and a second surface disposed opposite to each other along its thickness direction, wherein the first surface can serve as a subsequent photosensitive surface and the second surface can serve as a subsequent circuit surface.

[0030] In one example, such as Figure 3A As shown, an interlayer dielectric layer 201 is formed on the second surface of the substrate 20, and an interconnect structure 202 is formed in the interlayer dielectric layer 201. Specifically, the interlayer dielectric layer 201 can be formed on the second surface using processes including but not limited to chemical vapor deposition (CVD). The interlayer dielectric layer 201 can be a single-layer structure or a multilayer composite structure, without specific limitation. For example, the interlayer dielectric layer 201 can be a multilayer composite structure composed of at least two of oxide, nitride, and low-dielectric-constant material layers. Exemplarily, after forming the interlayer dielectric layer 201, photolithography and etching processes are performed to define vias in the interlayer dielectric layer 201. Subsequently, metal material is filled into the vias using physical vapor deposition (PVD), chemical vapor deposition (CVD), or electroplating processes to form the interconnect structure 202. The interconnect structure 202 realizes the electrical connection between the pixel unit and the driving circuit, ensuring efficient signal transmission. The formation process of the interconnect structure can also employ other conventional processes in the art, the specific process of which will not be described in detail here.

[0031] Next, step S2 is performed to form a trench extending inward from the first surface in the substrate, with the trench exposing a portion of the interconnect structure.

[0032] In one example, such as Figure 3AAs shown, a trench 21 extending inward from the first surface is etched on the first surface of the substrate 20, exposing a portion of the interconnect structure 202. Exemplarily, the trench 21 includes a first trench 211 and at least one second trench 212, each second trench 212 being located at the bottom of the first trench 211, each second trench 212 communicating with the first trench 211 and exposing a portion of the interconnect structure 202.

[0033] The specific steps for forming the trench 21 include: firstly, etching the first surface of the substrate 20; specifically, forming a patterned first photoresist layer on the first surface of the substrate 20, the patterned first photoresist layer defining the shape and position of the first trench 211; using the patterned first photoresist layer as a mask to etch the first surface of the substrate 20 to form the first trench 211; the formed first trench 211 extends from the first surface of the substrate 20 to the interior of the substrate 20; and then removing the patterned first photoresist layer. Next, a second etching is performed on the substrate at the bottom of the first trench 211. Specifically, a patterned second photoresist layer is formed on the first surface of the substrate 20. The second photoresist layer covers the first surface of the substrate 20 and fills the first trench 211. The patterned second photoresist layer defines the shape and position of the second trench 212. Using the patterned second photoresist layer as a mask, the substrate at the bottom of the first trench 211 is etched to form at least one second trench 212. The formed second trench 212 is located at the bottom of the first trench 211. The second trench 212 is also connected to the first trench 211 and exposes part of the interconnect structure 202. Finally, the patterned second photoresist layer is removed. The etching of the substrate 20 can be performed using conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, and plasma etching.

[0034] Continue, perform step S3 to form a conductive layer covering the bottom and sidewalls of the trench and the first surface.

[0035] In one example, such as Figure 3A As shown, after forming trench 21 and before forming conductive layer 23, the process further includes forming an isolation layer 22 covering the first surface and the sidewalls of trench 21. Exemplarily, the material of isolation layer 22 includes, but is not limited to, silicon oxide or silicon nitride, and it can be formed using processes including, but not limited to, thermal oxidation or chemical vapor deposition (CVD). Isolation layer 22 provides electrical isolation, preventing leakage or short circuits between the subsequent conductive layer and the substrate or surrounding active devices, thereby ensuring the electrical reliability of the device. The thickness of isolation layer 22 can be set according to process requirements and is not specifically limited thereto.

[0036] In one example, such as Figure 3BAs shown, a conductive layer 23 is formed covering the bottom and sidewalls of trench 21 and the first surface. Exemplarily, the material of the conductive layer 23 includes, but is not limited to, aluminum (Al), copper (Cu), or an aluminum-copper alloy. It can be deposited on the surface of the isolation layer 22 using processes including, but not limited to, physical vapor deposition (PVD) or chemical vapor deposition (CVD). During deposition, process parameters are controlled to ensure that the conductive layer 23 has good step coverage on the sidewalls and bottom of trench 21, avoiding voids or breaks, thereby forming a continuous and uniform conductive film. This conductive layer 23 not only covers the entire inner surface of trench 21 (including the bottom and sidewalls of the first trench 211 and the second trench 212), but also covers the isolation layer on the first surface of the substrate 20, providing a material basis for the subsequent formation of the pad structure through self-aligned etching. The thickness of this conductive layer is set according to process requirements to balance conductivity and the controllability of the etching process.

[0037] Then, step S4 is performed to spin-coat an etching barrier material onto the conductive layer to fill trenches at least partially deep.

[0038] In one example, such as Figure 3C As shown, an etch stop material 24 is spin-coated onto the conductive layer 23 to fill the trench 21 at least partially. Specifically, a spin-coating process is used to coat the etch stop material 24 onto the entire first surface of the substrate 20 (i.e., the etch stop material 24 is coated onto the conductive layer 23 on the first surface) and to fill the trench 21 at least partially. Exemplarily, the etch stop material can be one or more spin-coated materials with excellent flowability and filling capacity, such as photoresist, bottom anti-reflective coating (BARC), top anti-reflective coating (TARC), or spin-on dielectric (SOD). During the spin-coating process, by adjusting the rotation speed and time, the etch stop material is allowed to fully flow into and completely fill the interior of the trench 21, while simultaneously forming an etch stop material 24 of a certain thickness on the first surface of the substrate 20, covering the conductive layer 23. The thickness of the etching barrier material 24 above the bottom of the trench 21 is greater than or less than the depth of the trench 21, ensuring that the conductive layer 23 at the bottom of the trench 21 is always protected from etching during the subsequent etching process. The conductive layer 23 on the sidewall of the trench 21 and the first surface of the substrate 20 can be selectively removed. After etching, the etching barrier material is still retained on the conductive layer 23 at the bottom of the trench 21.

[0039] In one example, after spin-coating the etch barrier material 24 and before etching the conductive layer 23, a baking process is performed on the etch barrier material 24 to harden it. Specifically, the baking temperature and time are optimized according to the characteristics of the material used. For example, if photoresist is used, the baking temperature is typically set between 90 and 120 degrees Celsius, and the time is between 60 and 120 seconds. The main purpose of this step is to remove the solvent introduced during spin-coating, promote cross-linking and curing of the material, thereby improving the mechanical strength and thermal stability of the etch barrier material, making it more effective as a mask in subsequent dry etching processes, and preventing deformation or peeling caused by etching heat or ion bombardment. For some highly stable spin-coated insulating dielectric materials, if they have sufficient etching resistance, the baking step can be omitted to simplify the process, depending on the process requirements. No specific limitations are imposed on this.

[0040] In one example, before etching the conductive layer 23, the conductive layer 23 on the sidewall of the trench 21 directly contacts the etch stop material 24. During deposition, the conductive layer 23 covers the bottom, sidewalls, and first surface isolation layer 22 of the substrate of the trench 21. Subsequently, the etch stop material 24 fills the trench 21 and directly contacts the conductive layer 23 on its sidewalls. During subsequent etching, because the etch stop material 24 is in direct contact with the conductive layer 23 on the sidewalls of the trench 21, the etching rate of the etch stop material is lower than that of the conductive layer. In the early stages of etching, the conductive layer 23 on the sidewalls of the trench 21 is quickly removed, while the conductive layer 23 at the bottom of the trench 21 is effectively protected due to the thicker thickness of the etch stop material 24 above it. Ultimately, only the conductive layer at the bottom of the trench 21 is retained. The etching process is self-aligning, eliminating the need for a photomask, and achieving precise alignment and seamless bonding between the pad structure and the trench, thus eliminating the "groove" structure easily generated in traditional processes.

[0041] Finally, step S5 is performed, using the etching barrier material as a mask to etch away the conductive layer on the sidewalls of the trench and the first surface, leaving only the conductive layer at the bottom of the trench to form a pad structure. After etching, the top surface of the remaining etching barrier material in the trench is higher than the top surface of the conductive layer.

[0042] In one example, such as Figure 3DAs shown, using the etch stop material 24 as a mask, the conductive layer 23 on the sidewalls and first surface of the trench 21 is etched away, leaving only the conductive layer 23 at the bottom of the trench 21 to form the pad structure 25. Exemplarily, during the etching of the conductive layer 23, the etching rate of the etch stop material 24 is lower than the etching rate of the conductive layer 23. Specifically, during etching using the etch stop material 24 as a mask, because the etching rate of the etch stop material 24 is lower than the etching rate of the conductive layer 23, it is slowly consumed during the etching process, ensuring that the conductive layer 23 at the bottom of the trench 21 is always effectively protected by the etch stop material during etching. Since the etch stop material 24 is relatively thick, at least one ashing treatment can be performed on the etch stop material during etching, and the thickness of the etch stop material 24 can be appropriately reduced using plasma to increase the etching rate. The ashing and etching steps can be performed alternately. For example, etching can be performed for a period of time to remove part of the conductive layer and consume part of the etch stop material. Then, an ashing process is performed to reduce the thickness of the etch stop material using plasma. Then, etching is resumed to continue removing the conductive layer, and finally, the conductive layer 23 on the first surface and the conductive layer 23 on the sidewalls of the trench 21 are removed, while the conductive layer 23 at the bottom of the trench 21 is retained to form the pad structure 25. This allows for self-alignment of the pad structure and the trench without the need for a photomask, saving process steps and costs, and improving production efficiency and process stability. This alternating ashing and etching method can be repeated multiple times, which can effectively control the consumption rate of the etch stop material, preventing it from being exhausted prematurely, and avoid problems such as etching lag caused by thick masks, thus improving the overall process stability. During the etching of the conductive layer 23, conventional etching processes such as reactive ion etching (RIE), ion beam etching, and plasma etching can be used. After etching, the top surface of the remaining etching barrier material 24 in the trench 21 is higher than the top surface of the conductive layer 23, forming a "cap-shaped" protective structure. This ensures that the pad structure fits tightly against the trench sidewall, eliminating the "groove" problem caused by photolithography deviation in traditional processes and improving device reliability. Furthermore, the etching process can also remove the isolation layer 22 on the first surface and part of the isolation layer 22 on the sidewall of the trench 21.

[0043] For example, since the etch stop material 24 is deposited thickly on the first surface of the substrate, affecting the efficiency and uniformity of subsequent etching, at least one ashing treatment can be performed on the etch stop material before etching the conductive layer 23. For example, only one ashing treatment can be performed before etching, or the ashing treatment and etch stop material layer can be alternated multiple times. The etch stop material 24 is moderately thinned using plasma to reduce its overall thickness, but the etch stop material at the bottom of the trench 21 still maintains sufficient thickness to continue protecting the conductive layer 23 below it. Etching is then performed to remove the conductive layer 23 on the sidewalls of the trench 21 and the first surface of the substrate 20, while the conductive layer 23 at the bottom of the trench 21 is retained because it is still covered by the etch stop material, forming the pad structure 25. By introducing the ashing treatment, the consumption rate of the etch stop material can be effectively controlled, avoiding premature depletion or uneven etching, while ensuring that the protection at the bottom of the trench is always effective, thereby improving process stability.

[0044] In one example, the formed pad structure 25 is located at the bottom and sidewalls of the second trench 212 and the bottom of the first trench 211, wherein the pad structure 25 is connected to the interconnect structure 202 through the second trench 212, and the pad structure 25 also contacts the sidewalls of the first trench 211. Figure 4 As shown, the formed pad structure 25 is located in the center region of the bottom of the trench 21, and the radial distance from the edge of the pad structure 25 to the edge of the trench 21 is the edging width w, where w is greater than or equal to zero.

[0045] In one example, such as Figure 3E As shown, after forming the pad structure 25, the process also includes removing the etching barrier material 24 from the pad structure 25. Exemplarily, processes such as ashing or wet cleaning can be used to remove the etching barrier material 24 and residual byproducts from the pad structure 25, ensuring a clean surface for the pad structure 25, providing a good interface for subsequent processes, and improving device reliability.

[0046] It is worth mentioning that the above steps are only examples, and the order of the steps can be adjusted without conflict.

[0047] Thus, the process steps of the image sensor fabrication method according to the embodiments of this application are completed. It is understood that the image sensor fabrication method of this embodiment includes not only the above steps, but may also include other necessary steps before, during or after the above steps, all of which are included within the scope of the fabrication method of this embodiment.

[0048] In summary, the image sensor fabrication method of this application uses spin-coating of an etch stop material to fill trenches. In subsequent etching, the etch stop material can serve as a self-aligning mask to remove the conductive layer on the trench sidewalls and the first surface of the substrate, leaving only the conductive layer at the bottom of the trench to form a pad structure. This achieves self-alignment between the pad structure and the trench without the need for an additional photolithography mask, saving process steps and costs, and improving production efficiency. Furthermore, the formed pad structure eliminates the "groove" structure that is easily generated in traditional processes, reducing the difficulty of subsequent processes and improving the stability and reliability of the device.

[0049] This application also provides an image sensor, which can be prepared by the method described in Embodiment 1 above.

[0050] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will be conceived by those skilled in the art, all of which will fall within the spirit and scope of the disclosed concept. More particularly, various modifications and changes can be made in terms of the arrangement and / or components of the subject matter within the scope of the disclosure, drawings, and appended claims. In addition to modifications and changes in components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.

Claims

1. A method for fabricating an image sensor, characterized in that, The preparation method includes: A substrate is provided having a first surface and a second surface disposed opposite to each other along its thickness direction, wherein an interlayer dielectric layer is formed on the second surface of the substrate, and an interconnect structure is formed in the interlayer dielectric layer; A trench extending inward from the first surface is formed in the substrate, the trench exposing a portion of the interconnect structure; A conductive layer is formed covering the bottom and sidewalls of the trench and the first surface; Spin-coating an etching barrier material onto the conductive layer to fill the trenches at least a portion of their depth; Using the etching barrier material as a mask, the sidewalls of the trench and the conductive layer on the first surface are etched away, leaving only the conductive layer at the bottom of the trench to form a pad structure. After the etching is completed, the top surface of the remaining etching barrier material in the trench is higher than the top surface of the conductive layer.

2. The preparation method according to claim 1, characterized in that, The trench includes a first trench and at least one second trench, each second trench being located at the bottom of the first trench, each second trench communicating with the first trench and exposing a portion of the interconnect structure.

3. The preparation method according to claim 2, characterized in that, The pad structure is located at the bottom and sidewall of the second trench and at the bottom of the first trench, wherein the pad structure is connected to the interconnect structure through the second trench and the pad structure is also in contact with the sidewall of the first trench.

4. The preparation method according to claim 1, characterized in that, Before etching the conductive layer, the conductive layer on the sidewall of the trench is in direct contact with the etching barrier material, and the thickness of the etching barrier material above the bottom of the trench is greater than or less than the depth of the trench.

5. The preparation method according to claim 4, characterized in that, During the etching process of the conductive layer, the etching rate of the etching barrier material is less than the etching rate of the conductive layer.

6. The preparation method according to claim 1, characterized in that, Before or during etching the conductive layer, the method further includes: performing at least one ashing treatment on the etching barrier material to reduce the thickness of the etching barrier material; and / or after forming the trench and before forming the conductive layer, further including: forming an isolation layer covering the first surface and the sidewalls of the trench.

7. The preparation method according to claim 1, characterized in that, After spin-coating the etching barrier material and before etching the conductive layer, the method further includes baking the etching barrier material to harden it.

8. The preparation method according to claim 1, characterized in that, After forming the pad structure, the process also includes removing the etching barrier material from the pad structure.

9. The preparation method according to claim 1, characterized in that, The etching barrier material includes at least one of photoresist, bottom anti-reflective coating, top anti-reflective coating, and spin-coated insulating medium.

10. An image sensor, characterized in that, The image sensor is obtained using any one of the preparation methods described in claims 1 to 9.

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