Display device and electronic device including the same

Abstract

A display apparatus and an electronic device including the same are provided. The display device includes a display panel including a display area and a non-display area adjacent to the display area; a pixel disposed in the display area; signal lines disposed in the display area and the non-display area and electrically connected to the pixels; a signal pad disposed in the non-display area and electrically connected to the signal line; and a first dummy pad disposed in the non-display area and spaced apart from the signal pad. The signal pad includes a first conductive pattern electrically connected to an end of the signal line, an insulating pattern disposed on the first conductive pattern, and a second conductive pattern disposed on the insulating pattern. The first dummy pad includes a first conductive pattern and a dummy pattern disposed on the first conductive pattern. A hardness of the dummy pattern is higher than a hardness of the insulating pattern.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0143694, filed on October 21, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates herein to display devices and electronic devices including display devices, and more particularly, to display devices including pad areas and electronic devices including display devices. Background Technology

[0003] Various display devices are being developed for multimedia devices such as televisions, mobile phones, tablet computers, navigation systems, and game consoles. Electronic devices that include display devices may include keyboards and mice as input devices. The display device itself may include input sensors such as touch panels as input devices.

[0004] The display device includes a display area that is activated in response to an electrical signal. The display device can not only detect input applied from the outside through the display area, but also display various images to provide information to the user.

[0005] The display device includes a display panel and a circuit board. The display panel can be connected to the motherboard via the circuit board. A driver chip can be mounted on the display panel. The driver chip can be electrically connected to the display panel via pads located in the non-display area of ​​the display panel. Summary of the Invention

[0006] This disclosure provides a display device and an electronic device in which an indentation capable of detecting initial process failure is formed on the rear surface of a display panel.

[0007] This disclosure also provides display devices and electronic devices with improved integration reliability.

[0008] An embodiment of the present invention provides a display device, comprising: a display panel including a display area and a non-display area adjacent to the display area; a pixel disposed in the display area; a signal line disposed in the display area and the non-display area and electrically connected to the pixel; a signal pad disposed in the non-display area and electrically connected to the signal line; and a first dummy pad disposed in the non-display area and positioned spaced apart from the signal pad, wherein the signal pad includes a first conductive pattern electrically connected to the end of the signal line, an insulating pattern disposed on the first conductive pattern, and a second conductive pattern disposed on the insulating pattern, the first dummy pad includes the first conductive pattern and a dummy pattern disposed on the first conductive pattern, and the hardness of the dummy pattern is higher than the hardness of the insulating pattern.

[0009] In an embodiment, the dummy pattern and the second conductive pattern may include the same material.

[0010] In an embodiment, the dummy pattern may include metal.

[0011] In an embodiment, the hardness of the dummy pattern can be higher than that of the first conductive pattern.

[0012] In an embodiment, the dummy pattern may have a thickness of approximately 1 μm to approximately 5 μm.

[0013] In an embodiment, in a plan view, the dummy pattern may be disposed inside the first conductive pattern.

[0014] In an embodiment, in a plan view, the first dummy pad may extend in one direction, the dummy pattern may be provided as a plurality of dummy patterns, and in a plan view, the plurality of dummy patterns may be positioned to be spaced apart from each other in that one direction.

[0015] In an embodiment, the first dummy pad can be electrically isolated.

[0016] In an embodiment, signal pads and first dummy pads may each be provided in multiple ways to provide multiple signal pads and multiple first dummy pads. The multiple signal pads may include first signal pads extending in a first direction in a plan view, and the multiple first dummy pads may include dummy pads 1-1 extending in a first direction in a plan view.

[0017] In an embodiment, the plurality of signal pads may further include a second signal pad spaced apart from the first signal pad in a second direction intersecting the first direction in a plan view. The second signal pad may extend in a first inclined direction intersecting the first and second directions. The plurality of first dummy pads may further include a first-second dummy pad spaced apart from the second signal pad in the second direction, and the first-second dummy pad may extend in a second inclined direction intersecting the first and second directions.

[0018] In an embodiment, in a plan view, a first signal pad may be disposed in the central area of ​​a plurality of signal pads in a second direction, and in a plan view, a first-1 dummy pad may be disposed in the central area.

[0019] In an embodiment, the first-second dummy pads can be located in the outermost area of ​​the plurality of signal pads in the second direction.

[0020] In an embodiment, in a plan view, at least some of the plurality of first dummy pads may have a length in a first direction that is substantially the same as the length of the signal pads adjacent to the at least some of the plurality of first dummy pads, and may have a length in a second direction that is substantially the same as the length of the signal pads adjacent to the at least some of the plurality of first dummy pads.

[0021] In an embodiment, the display device may further include a second dummy pad having a stacking structure different from that of the first dummy pad, wherein the second dummy pad may not include a dummy pattern.

[0022] In an embodiment of the present invention, the electronic device includes: a display panel including a display area and a non-display area adjacent to the display area; and an electronic component disposed in the non-display area, electrically connected to the display panel, and including a signal bump and a dummy bump, wherein the display panel includes: a substrate layer; an insulating layer disposed on the substrate layer; a pixel disposed in the display area; a signal pad disposed in the non-display area and corresponding to the signal bump; and a dummy pad disposed in the non-display area and corresponding to the dummy bump, the signal pad including a first conductive pattern, an insulating pattern disposed on the first conductive pattern, and a second conductive pattern disposed on the insulating pattern, the dummy pad including the first conductive pattern and a dummy pattern disposed on the first conductive pattern, and the hardness of the dummy pattern is higher than the hardness of the insulating pattern.

[0023] In an embodiment, the dummy pattern and the second conductive pattern may include the same material.

[0024] In an embodiment, the dummy pattern may include metal.

[0025] In an embodiment, the lower surface of the dummy pattern may protrude in the direction toward the base layer.

[0026] In an embodiment, the lower surface of the base layer corresponding to the dummy pad may protrude more than the lower surface of the base layer corresponding to the signal pad.

[0027] In this embodiment, the dummy pads can be electrically isolated. Attached Figure Description

[0028] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. In the drawings:

[0029] Figure 1 This is a perspective view of an electronic device according to an embodiment of the present invention.

[0030] Figure 2 This is an exploded perspective view of an electronic device according to an embodiment of the present invention.

[0031] Figure 3 This is a cross-sectional view of a display device according to an embodiment of the present invention;

[0032] Figure 4 This is a plan view of a display panel according to an embodiment of the concept of the present invention;

[0033] Figure 5 This is a cross-sectional view of a display panel according to an embodiment of the present invention;

[0034] Figure 6A This is a cross-sectional view of an input sensor according to an embodiment of the present invention;

[0035] Figure 6B This is a plan view of an input sensor according to an embodiment of the present invention;

[0036] Figure 6C It is along Figure 6B A cross-sectional view taken by line X-X';

[0037] Figure 7 This is an enlarged exploded perspective view of the pad area of ​​a display device according to an embodiment of the present invention;

[0038] Figure 8 This is a plan view showing the pad area of ​​a display panel according to an embodiment of the present invention;

[0039] Figure 9A This is an enlarged plan view of the signal pads according to an embodiment of the present invention, and Figure 9B and Figure 9C These are cross-sectional views of the signal pads;

[0040] Figure 10A This is an enlarged plan view of a dummy pad according to an embodiment of the present invention, and Figure 10B This is a cross-sectional view of a dummy pad;

[0041] Figure 11 This is a cross-sectional view of a portion of a display panel according to an embodiment of the present invention;

[0042] Figure 12 This is a cross-sectional view of a portion of a display device to which a driver chip, according to an embodiment of the present invention, is connected; and

[0043] Figure 13 and Figure 14 These are enlarged plan views of dummy pads according to other embodiments of the present invention. Detailed Implementation

[0044] In this specification, it will be understood that when an element (or area, layer or part, etc.) is referred to as being "on" another element, "connected to" or "attached to" another element, the element may be directly disposed on, directly connected to or attached to the other element, or other elements may be disposed between the element and the other element.

[0045] The same reference numerals or symbols always refer to the same elements. In the drawings, the thickness, scale, and dimensions of elements are exaggerated for the purpose of effectively describing the technical content. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items.

[0046] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, the elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element without departing from the scope of the inventive concept. Similarly, a second element may be referred to as a first element. In this specification, the singular expressions “a” and “the” are intended to also include the plural forms unless the context clearly indicates otherwise.

[0047] Additionally, terms such as "below," "on the lower side," "above," or "on the upper side" may be used to describe the relationship between the elements shown in the accompanying drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0048] It will be further understood that, when used in this specification, the terms “comprising,” “including,” “containing,” and / or “having” indicate the presence of the stated features, quantities, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or possibility of one or more other features, quantities, steps, operations, elements, components, and / or combinations thereof.

[0049] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and unless expressly defined herein, these terms shall not be interpreted in an idealized or overly formal sense.

[0050] In the following description, embodiments of the inventive concept are illustrated with reference to the accompanying drawings.

[0051] Figure 1 This is a perspective view of an electronic device ED according to an embodiment of the present invention. Figure 2 This is an exploded perspective view of an electronic device ED according to an embodiment of the present invention.

[0052] exist Figure 1 and Figure 2 In this embodiment, the electronic device ED is exemplarily shown as a mobile phone terminal. The electronic device ED according to the present invention can be a large electronic device such as a television and monitor, or a small to medium-sized electronic device such as a tablet computer, navigation system, game console, and smartwatch.

[0053] refer to Figure 1 An electronic device ED can display an image IM via a display surface ED-IS. The image IM is exemplarily shown as an icon image. The display surface ED-IS is parallel to a plane defined by a first direction DR1 and a second direction DR2. The normal direction of the display surface ED-IS (i.e., the thickness direction of the electronic device ED) is indicated as a third direction DR3. In this specification, the phrases "when viewed in a plane" or "in a plan view" may refer to the view when viewed in the third direction DR3. The front (or upper) and rear (or lower) surfaces of each layer or unit described below are defined based on the third direction DR3.

[0054] Furthermore, the display surface ED-IS may include a display area ED-DA in which an image IM is displayed, and a non-display area ED-NDA disposed adjacent to the display area ED-DA. The non-display area ED-NDA is the area in which no image is displayed. However, embodiments of the present invention are not limited thereto, and the non-display area ED-NDA may be disposed adjacent to either side of the display area ED-DA or may be omitted.

[0055] refer to Figure 2 The electronic device ED may include a window WM, a display device DD, and a housing BC. The housing BC may house the display device DD and may be connected to the window WM. Although not shown, the electronic device ED may further include other electronic modules electrically connected to the display panel DP and housed in the housing BC. For example, the electronic device ED may further include a motherboard, a camera module, a power supply module, circuit modules mounted on the motherboard, etc.

[0056] The window WM can be positioned on the upper part of the display device DD and can transmit the image provided by the display device DD to the outside. The window WM may include a transmissive area TA and a non-transmissive area NTA. The transmissive area TA can be connected to... Figure 1 The display areas ED-DA overlap and can have a shape corresponding to the shape of the display areas ED-DA.

[0057] The non-transmissive NTA can be compared with the non-display ED-NDA (see...). Figure 1 ) overlaps, and can have an overlap with the non-display area ED-NDA (see Figure 1 The shape corresponds to the shape of the non-transmissive region (NTA). The non-transmissive region (NTA) can be a region with a relatively low transmittance compared to the transmissive region (TA).

[0058] The display device DD can generate images and detect external input. The display device DD may include a display panel DP and an input sensor ISU. Although not shown, the display device DD may further include an anti-reflective component disposed on the input sensor ISU. The anti-reflective component may include a polarizer and a retarder, or a color filter and a black matrix.

[0059] According to embodiments of the present invention, the display panel DP can be a light-emitting display panel, but the type of display panel DP is not particularly limited. For example, the display panel DP can be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer of an organic light-emitting display panel may include organic light-emitting materials. The light-emitting layer of an inorganic light-emitting display panel may include quantum dots, quantum rods, or may be configured as nano-LEDs, etc. Hereinafter, the display panel DP is described as an organic light-emitting display panel.

[0060] The input sensor ISU can include any of the following: capacitive sensor, optical sensor, ultrasonic sensor, and electromagnetic induction sensor. The input sensor ISU can be formed on the display panel DP by a continuous process, or it can be manufactured separately and then attached to the display panel DP via an adhesive layer.

[0061] The display device DD according to the embodiment may further include a driver chip DC and a circuit board PB. Figure 2 The illustration shows a driver chip DC mounted on a display panel DP, but embodiments of the invention are not limited thereto. The driver chip DC can generate drive signals required for the operation of the display panel DP in response to control signals transmitted from a circuit board PB. The circuit board PB connected to the display panel DP can be bent and can be disposed on the rear surface of the display panel DP. The circuit board PB can be disposed on the substrate layer BL (see [reference]). Figure 3 One end of the circuit can be electrically connected to the circuit element layer DP-CL (see...). Figure 3 ).

[0062] In the display device DD according to an embodiment, a portion of the display panel DP can be bent so that the driving chip DC faces downwards. The non-display area DP-NDA of the display panel DP (see...) Figure 3 A portion of the circuit board PB can also be bent. However, the bending is not limited to this, and the circuit board PB can be bent.

[0063] The aforementioned electronic device ED is exemplarily shown as a mobile phone terminal; however, in this specification, the electronic device ED can be any device comprising two or more connected electronic components. The display panel DP and the driver chip DC mounted on the display panel DP correspond to different electronic components, and the electronic device ED may include only these components. Only the display panel DP and the circuit board PB connected to the display panel DP can constitute the electronic device ED, and only the motherboard and the electronic modules mounted on the motherboard can constitute the electronic device ED. In the following description of the display device DD and electronic device ED according to the present invention, the focus will be primarily on the combined structure of the display panel DP and the driver chip DC mounted on the display panel DP.

[0064] Figure 3 This is a cross-sectional view of a display device DD according to an embodiment of the present invention.

[0065] refer to Figure 3 The display panel DP may include a substrate layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin-film encapsulation layer TFE disposed on the substrate layer BL. The input sensor ISU may be disposed on the thin-film encapsulation layer TFE.

[0066] The display panel DP can include the display area DP-DA and the non-display area DP-NDA. The display area DP-DA of the display panel DP is... Figure 1 The display area shown is ED-DA or Figure 2 The transmissive area TA shown corresponds to the non-display area DP-NDA of the display panel DP, and is consistent with... Figure 1 The non-display area ED-NDA shown in the image or Figure 2 The non-transmissive region NTA is shown in the figure.

[0067] The substrate layer BL may include a display area DP-DA and a non-display area DP-NDA surrounding the display area DP-DA. The substrate layer BL may include a synthetic resin layer. The substrate layer BL may have a multilayer structure. For example, the substrate layer BL may have a three-layer structure consisting of a synthetic resin layer, an inorganic layer, and a synthetic resin layer. Specifically, the synthetic resin layer may be a polyimide resin layer, and the material of the synthetic resin layer is not particularly limited. The synthetic resin layer may include at least one of acrylic resins, methacrylic resins, polyisoprene resins, vinyl resins, epoxy resins, urethane resins, cellulose resins, siloxane resins, polyamide resins, and perylene resins. Furthermore, the substrate layer BL may include a glass substrate, a metal substrate, or an organic / inorganic composite substrate, etc.

[0068] The circuit element layer DP-CL may include circuit elements and at least one insulating layer. The insulating layer may include at least one inorganic layer and at least one organic layer. The circuit elements may include signal lines, pixel driving circuits, etc. The insulating layer, semiconductor layer, and conductive layer are formed by coating processes, deposition processes, etc. Thereafter, the insulating layer, semiconductor layer, and conductive layer may be selectively patterned by performing photolithography and etching processes. In this process, semiconductor patterns, conductive patterns, signal lines, etc., are formed. Patterns disposed on the same layer are formed by the same process. In the following text, the phrase "patterns are formed by the same process" means that the patterns include the same material, have the same stacking structure, and are formed simultaneously.

[0069] The display element layer of a DP-OLED may include organic light-emitting elements. The display element layer of a DP-OLED may further include an organic layer such as a pixel-defining film.

[0070] A thin-film encapsulation layer (TFE) can be disposed on the circuit element layer (DP-CL) to cover the display element layer (DP-OLED). The TFE can protect the pixels from moisture, oxygen, and external foreign matter. However, embodiments of the present invention are not limited thereto, and in addition to the TFE, the display panel (DP) may further include an additional insulating layer. For example, it may further include an optical insulating layer for controlling the refractive index.

[0071] The input sensor ISU can be directly formed on the display panel DP. In this specification, the phrase "component A is directly disposed on or formed on component B" means that an adhesive layer is not disposed between component A and component B. In this embodiment, the input sensor ISU can be directly formed on the display panel DP through a continuous process without an adhesive layer between the display panel DP and the input sensor ISU. However, the inventive concept is not limited to this, and the input sensor ISU can be provided as a separate panel and can be attached to the display panel DP via an adhesive layer. According to embodiments, the input sensor ISU can also be omitted.

[0072] Figure 4 This is a plan view of a display panel DP according to an embodiment of the present invention. Figure 4 It shows Figure 3 The planar shape of the display panel DP is shown in the figure.

[0073] refer to Figure 4 The display panel DP can include multiple pixels (PX), gate drive circuit (GDC), multiple signal lines (SGL), and multiple pads (DP-PD).

[0074] Pixels PX are disposed in the display area DP-DA. Each pixel PX may include a light-emitting element and a pixel driving circuit connected to the light-emitting element. A gate driving circuit GDC sequentially outputs gate signals to multiple gate lines GL, which will be described later. The transistors of the gate driving circuit GDC can be formed using the same process as the transistors of the pixel PX (e.g., low-temperature polycrystalline silicon (LTPS) process or low-temperature polycrystalline oxide (LTPO) process). The display panel DP may further include another driving circuit that provides light-emitting control signals to the pixels PX.

[0075] The signal line SGL may include gate lines GL, data lines DL, power lines PWL, and control signal lines CSL. Gate lines GL are connected to corresponding pixels PX, and data lines DL are connected to corresponding pixels PX. Power lines PWL are connected to pixels PX. The control signal lines CSL can be connected to the gate drive circuit GDC and can provide control signals to the gate drive circuit GDC.

[0076] Signal lines SGL can be set in the display area DP-DA and the non-display area DP-NDA. Each signal line SGL can include a wiring section LP. The wiring section LP can be set in the display area DP-DA and the non-display area DP-NDA.

[0077] Multiple pads DP-PD may include a first pad PD1, a second pad PD2, and a third pad PD3. The area where the first pad PD1 and the second pad PD2 are provided can be defined as the first pad area PA1, and the area where the third pad PD3 is provided can be defined as the second pad area PA2.

[0078] The first pad area PA1 contains the driver chip DC (see...). Figure 2 The area connected to the display panel DP is the second pad area PA2, where the circuit board PB (see...) is located. Figure 2 The first pad area PA1 may include a first area B1 in which a first pad PD1 is disposed and a second area B2 in which a second pad PD2 is disposed. The first pad area PA1 and the second pad area PA2 may be disposed within the non-display area DP-NDA. The first pad area PA1 and the second pad area PA2 may be spaced apart from each other in a first direction DR1. The first pad area PA1 may be disposed closer to the display area DP-DA than the second pad area PA2, and the second pad area PA2 may be spaced apart from the display area DP-DA, wherein the first pad area PA1 is disposed between the display area DP-DA and the second pad area PA2.

[0079] The first pad PD1 can be connected to the corresponding data line DL in the data line DL. Although not shown, the first pad PD1 and the second pad PD2 can be electrically connected to each other. The second pad PD2 can be connected to the third pad PD3 via the connection signal line S-CL.

[0080] The circuit board PB may include multiple circuit pads PB-PD. The circuit pads PB-PD may be arranged on the second direction DR2. The circuit pads PB-PD of the circuit board PB may be connected to a third pad PD3 in the second pad area PA2 to make contact with the third pad PD3.

[0081] Figure 5 This is a cross-sectional view of a display panel DP according to an embodiment of the present invention.

[0082] refer to Figure 5 The display panel DP may include a substrate layer BL and a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE disposed on the substrate layer BL.

[0083] Multiple insulating layers are disposed on the upper surface of the substrate layer BL. The multiple insulating layers may include a barrier layer BRL and a buffer layer BFL. The multiple insulating layers may further include first insulating layers 10 to sixth insulating layers 60. The barrier layer BRL prevents foreign matter from being introduced from the outside. The barrier layer BRL may include a silicon oxide layer and a silicon nitride layer. Multiple silicon oxide layers and multiple silicon nitride layers may each be provided, and the multiple silicon oxide layers and multiple silicon nitride layers may be stacked alternately.

[0084] The buffer layer (BFL) enhances the adhesion between the substrate layer (BL) and the semiconductor pattern and / or conductive pattern. The buffer layer (BFL) may include a silicon oxide layer and a silicon nitride layer. Multiple silicon oxide and silicon nitride layers may each be provided, and the multiple silicon oxide layers and multiple silicon nitride layers may be stacked alternately.

[0085] Semiconductor patterns can be disposed on the buffer layer BFL. The semiconductor patterns can include polycrystalline silicon. The semiconductor patterns can also include amorphous silicon, crystalline silicon semiconductors, or metal-oxide semiconductors. Meanwhile, Figure 5 A portion of a semiconductor pattern is shown in the plan view, and the semiconductor pattern can be further disposed in another area of ​​the display panel DP. The semiconductor pattern can be doped with N-type or P-type dopant. The semiconductor pattern can include highly doped regions and lightly doped regions. The highly doped region can have a higher conductivity than the lightly doped region and can essentially serve as the source (S) and drain (D) of the transistor TR. The lightly doped region can essentially correspond to the active portion (A) (or channel) of the transistor TR.

[0086] The drain D, active portion A, and source S can be disposed on the buffer layer BFL within a semiconductor pattern. The drain D, active portion A, and source S can define the transistor TR together with the gate G, which will be described later. When the display panel DP includes another transistor besides the transistor TR, this other transistor can comprise a material different from that of the transistor TR and can be disposed on a different layer than the transistor TR. The source S, active portion A, and drain D of the transistor TR can be part of the semiconductor pattern.

[0087] A first insulating layer 10 may be disposed on a buffer layer BFL. The first insulating layer 10 may cover a semiconductor pattern. The gate G of a transistor TR may be disposed on the first insulating layer 10. A second insulating layer 20 may be disposed on the gate G. The gate G may be part of a metal pattern. The gate G may overlap with the active portion A. During the process of doping the semiconductor pattern, the gate G may be used as a self-aligned mask.

[0088] The gate G may include titanium (Ti), silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, or aluminum nitride (AlN). x ), tungsten (W), tungsten nitride (WN) x The invention may contain at least one of copper (Cu), indium tin oxide (ITO), indium zinc oxide (IZO), etc., but the embodiments of the present invention are not limited thereto.

[0089] A second insulating layer 20 covering the gate G may be disposed on the first insulating layer 10. Although not shown, the transistor TR according to the embodiment may further include an upper electrode disposed on the second insulating layer 20 and overlapping the gate G. A third insulating layer 30 may be disposed on the second insulating layer 20. A fourth insulating layer 40 may be disposed on the third insulating layer 30. The first insulating layer 10 to the fourth insulating layer 40 may each be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multilayer structure.

[0090] The connection electrode CNE may include a first connection electrode CNE1 and a second connection electrode CNE2 for connecting the transistor TR and the light-emitting element OLED. The first connection electrode CNE1 may be disposed on the fourth insulating layer 40 and may be connected to the drain electrode D via a first contact hole CH1 defined in the first insulating layer 10 to the fourth insulating layer 40.

[0091] A fifth insulating layer 50 may be disposed on the first connecting electrode CNE1 and the fourth insulating layer 40. The fifth insulating layer 50 may be an organic layer. A second connecting electrode CNE2 may be disposed on the fifth insulating layer 50. The second connecting electrode CNE2 may be connected to the first connecting electrode CNE1 via a second contact hole CH2 defined in the fifth insulating layer 50.

[0092] A sixth insulating layer 60 may be disposed on the second connecting electrode CNE2 and the fifth insulating layer 50. The layer from the buffer layer BFL to the sixth insulating layer 60 may be defined as a circuit element layer DP-CL. The sixth insulating layer 60 may be an organic layer. A first electrode AE ​​may be disposed on the sixth insulating layer 60. The first electrode AE ​​may be connected to the second connecting electrode CNE2 via a third contact hole CH3 defined in the sixth insulating layer 60. The first electrode AE ​​may be connected to the transistor TR via the first connecting electrode CNE1 and the second connecting electrode CNE2. A pixel defining film PDL, wherein an opening PX_OP is defined in a portion of the first electrode AE, may be disposed on the first electrode AE ​​and the sixth insulating layer 60.

[0093] The hole control layer (HCL) can be disposed on the first electrode (AE) and the pixel defining film (PDL). The hole control layer (HCL) may include a hole transport layer and a hole injection layer.

[0094] The luminescent layer (EML) can be disposed on the hole control layer (HCL). The EML can be disposed in the region corresponding to the opening (PX_OP). The EML can include organic and / or inorganic materials. The EML can produce light of one of the colors red, green, and blue.

[0095] An electron control layer (ECL) can be disposed on the light-emitting layer (EML) and the hole control layer (HCL). The ECL may include an electron transport layer and an electron injection layer. The hole control layer (HCL) and the ECL can be disposed together in the light-emitting region (LA) and the non-light-emitting region (NLA).

[0096] The second electrode CE can be disposed on the electronic control layer ECL. The second electrode CE can also be disposed together on each pixel PX (see [link to PX]). Figure 4 In this context, the pixel-defining film (PDL) and the layers constituting the light-emitting element (OLED) can be defined as the display element layer (DP-OLED).

[0097] The thin-film encapsulation layer TFE can be disposed on the second electrode CE to cover the pixel PX (see...). Figure 4 Although not shown, the thin-film encapsulation layer TFE may include multiple layers. Some of these multiple layers may include protective pixels PX (see [reference]). Figure 4 An inorganic layer that protects against moisture or oxygen. Other layers among these may include protective pixels (PX) (see...). Figure 4 An organic layer that protects against foreign objects such as dust particles.

[0098] A first voltage can be applied to the first electrode AE ​​via transistor TR, and a second voltage having a lower level than the first voltage can be applied to the second electrode CE. Holes and electrons injected into the light-emitting layer EML recombine to form excitons, and the excitons transition to the ground state, enabling the light-emitting element OLED to emit light.

[0099] Figure 6A This is a cross-sectional view of the input sensor ISU according to an embodiment of the present invention. Figure 6B This is a plan view of an input sensor ISU according to an embodiment of the present invention. Figure 6C It is along Figure 6B A cross-sectional view taken by line X-X'.

[0100] The input sensor ISU may include a first insulating layer IS-IL1 (hereinafter, the first sensor insulating layer), a first conductive patterning layer IS-CL1, a second insulating layer IS-IL2 (hereinafter, the second sensor insulating layer), a second conductive patterning layer IS-CL2, and a third insulating layer IS-IL3 (hereinafter, the third sensor insulating layer). The first sensor insulating layer IS-IL1 may be formed directly on the thin-film encapsulation layer TFE.

[0101] According to embodiments of the present invention, the first sensor insulating layer IS-IL1 and / or the third sensor insulating layer IS-IL3 can be omitted. When the first sensor insulating layer IS-IL1 is omitted, the first conductive pattern layer IS-CL1 can be directly formed on the top insulating layer of the thin-film encapsulation layer TFE. The third sensor insulating layer IS-IL3 can also be replaced by the insulating layer of the anti-reflective member disposed on the adhesive layer or the input sensor ISU.

[0102] The first conductive patterned layer IS-CL1 and the second conductive patterned layer IS-CL2 may each have a single-layer structure or a multilayer structure in which the layers are stacked along a third direction DR3. The multilayer conductive pattern may include at least two layers, namely a transparent conductive layer and a metal layer. The multilayer conductive pattern may include metal layers containing different metals. The transparent conductive layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, metal nanowires, or graphene. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or alloys thereof. A detailed description of the stacking structure of each of the first conductive patterned layer IS-CL1 and the second conductive patterned layer IS-CL2 will be provided later.

[0103] In this embodiment, each of the first sensor insulating layer IS-IL1 to the third sensor insulating layer IS-IL3 may include an inorganic layer or an organic layer. The inorganic layer may include silicon oxide, silicon nitride, or silicon oxynitride. According to embodiments of the present invention, at least one of the first sensor insulating layer IS-IL1 to the third sensor insulating layer IS-IL3 may include an organic layer. For example, the third sensor insulating layer IS-IL3 may include an organic layer. The organic layer may include at least one of acrylic resins, methacrylic resins, polyisoprene resins, vinyl resins, epoxy resins, urethane resins, cellulose resins, siloxane resins, polyimide resins, polyamide resins, and perylene resins.

[0104] refer to Figure 6B The input sensor ISU may include a sensing area IS-DA and a non-sensing area IS-NDA adjacent to the sensing area IS-DA. The sensing area IS-DA and the non-sensing area IS-NDA may be respectively connected to... Figure 4 The display area DP-DA shown corresponds to the non-display area DP-NDA.

[0105] The input sensor ISU may include multiple sensing electrodes disposed in the sensing area IS-DA. The sensing electrodes may include first sensing electrodes E1-1 to E1-5 (hereinafter, first electrodes) that are mutually insulated and cross each other, and second sensing electrodes E2-1 to E2-4 (hereinafter, second electrodes). The input sensor ISU may include a first signal line SL1 electrically connected to the first electrodes E1-1 to E1-5 and a second signal line SL2 electrically connected to the second electrodes E2-1 to E2-4, and the first signal line SL1 and the second signal line SL2 are disposed in the non-sensing area IS-NDA. The first electrodes E1-1 to E1-5, the second electrodes E2-1 to E2-4, the first signal line SL1, and the second signal line SL2 can be referenced. Figure 6A The first conductive pattern layer IS-CL1 and the second conductive pattern layer IS-CL2 are formed as described.

[0106] The first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 may each include multiple conductive lines that intersect each other. The multiple conductive lines may define multiple openings, and the first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 may form a grid shape. Each of the multiple openings may be defined as... Figure 5 The opening PX_OP of the pixel-defined film PDL shown in the figure corresponds to this.

[0107] One of the first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 may have an integral shape. In this embodiment, the first electrodes E1-1 to E1-5 with an integral shape are exemplaryly shown. The first electrodes E1-1 to E1-5 may each include a sensing portion SP1 and an intermediate portion CP1. A portion of the conductive pattern of the second conductive pattern layer IS-CL2 may correspond to the first electrodes E1-1 to E1-5.

[0108] The second electrodes E2-1 to E2-4 may respectively include a sensing pattern SP2 and a bridge pattern CP2 (or a connection pattern). For example... Figure 6B and Figure 6C As shown, two adjacent sensing patterns SP2 can be connected to two bridge patterns CP2 via contact holes CH-I passing through the second sensor insulating layer IS-IL2, but the number of bridge patterns CP2 is not limited. A portion of the conductive pattern of the aforementioned second conductive pattern layer IS-CL2 can correspond to the sensing pattern SP2. A portion of the conductive pattern of the aforementioned first conductive pattern layer IS-CL1 can correspond to the bridge pattern CP2.

[0109] One of the first signal line SL1 and the second signal line SL2 transmits a transmission signal from the external circuit for detecting external input to the corresponding electrodes among the first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4, and the other of the first signal line SL1 and the second signal line SL2 transmits the capacitance change between the first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 as a received signal to the external circuit.

[0110] A portion of the conductive pattern of the second conductive pattern layer IS-CL2 may correspond to the first signal line SL1 and the second signal line SL2. The first signal line SL1 and the second signal line SL2 may have a multilayer structure, or may comprise a first layer of lines formed by the first conductive pattern layer IS-CL1 and a second layer of lines formed by the second conductive pattern layer IS-CL2. The first and second layer lines may pass through the second sensor insulating layer IS-IL2 (see...). Figure 6A ( ) contact hole connection.

[0111] Figure 7 This is an enlarged exploded perspective view of the pad areas PA1 and PA2 of the display device DD according to an embodiment of the present invention. For example, Figure 7 The image shows the driver chip DC and circuit board PB being disassembled from the display panel DP. Figure 7 The first pad PD1, the second pad PD2, the connection signal line S-CL, and the third pad PD3 shown are... Figure 4 Those that are the same or similar in the text, and therefore their detailed descriptions can be omitted.

[0112] The driver chip DC can be connected to the first pad area PA1 via the first adhesive layer CF1, and the circuit board PB can be connected to the second pad area PA2 via the second adhesive layer CF2.

[0113] According to an embodiment of the present invention, the first adhesive layer CF1 and the second adhesive layer CF2 may be non-conductive films. That is, the first adhesive layer CF1 and the second adhesive layer CF2 may not include conductive balls and may include a viscous synthetic resin. The synthetic resin does not need to maintain the arrangement of the conductive balls, and therefore, the synthetic resin can have a relatively low viscosity.

[0114] When the first adhesive layer CF1 is cured, the first pad PD1 and the first bump BP1 in the driver chip DC can be fixed and in contact with each other, and the second pad PD2 and the second bump BP2 in the driver chip DC can be fixed and in contact with each other. When the second adhesive layer CF2 is cured, the third pad PD3 and the third bump BP3 to be connected to the circuit pad PB-PD can also be fixed and in contact with each other.

[0115] The driver chip DC may include a driver integrated circuit and a driver bump DC-BP mounted below the driver integrated circuit. The driver chip DC may include an upper surface DC-US and a lower surface DC-DS, and the lower surface DC-DS may be the surface facing the first pad PD1 and the second pad PD2. The driver bump DC-BP may be disposed on the lower surface DC-DS of the driver chip DC.

[0116] The drive bump DC-BP may include a first bump BP1 electrically connected to a corresponding first pad PD1 and a second bump BP2 electrically connected to a corresponding second pad PD2. The first bump BP1 may be arranged along a second direction DR2, and the second bump BP2 may be spaced apart from the first bump BP1 in a first direction DR1 and may be arranged along the second direction DR2.

[0117] The driver chip DC can receive a first signal from the outside via the second pad PD2 and the second bump BP2. The driver chip DC can provide a second signal, generated based on the first signal, to the first pad PD1 via the first bump BP1. For example, the driver chip DC may include a data driving circuit. The first signal may be an image signal (which is a digital signal applied externally), and the second signal may be a data signal (which is an analog signal). The driver chip DC can generate an analog voltage corresponding to the grayscale value of the image signal. The data signal can be received via... Figure 4 The data line DL shown is provided to pixel PX.

[0118] For ease of description, Figure 7The planar shape of the drive bump DC-BP is shown as a dashed line, but the first bump BP1 and the second bump BP2 may each have a shape that protrudes from the lower surface DC-DS of the drive chip DC and is exposed to the outside.

[0119] The circuit board PB can be mounted on the display panel DP. The circuit board PB can be mounted on the third pad PD3. The circuit board PB may include an upper surface PB-US and a lower surface PB-DS, and the lower surface PB-DS may be the surface facing the third pad PD3. The circuit board PB may include multiple circuit pads PB-PD electrically connected to the third pad PD3. The circuit pads PB-PD may be mounted on the lower surface PB-DS of the circuit board PB. The circuit pads PB-PD may be arranged on the second direction DR2. The circuit board PB can provide image signals, drive voltages, and other control signals to the driver chip DC.

[0120] Figure 8 This is a plan view illustrating the pad area PA of a display panel DP according to an embodiment of the present invention. The pad area PA may include a first pad area PA1 and a second pad area PA2. Figure 8 This is an enlarged view showing the first pad area PA1 and the second pad area PA2. The first pad area PA1 and the second pad area PA2 are located in the non-display area DP-NDA of the display panel DP. The driver chip DC (see...) Figure 7 ) is connected to the first pad area PA1, and the circuit board PB (see Figure 7 Connect to the second pad area PA2.

[0121] The description of the first pad area PA1 can be similarly applied to the second pad area PA2, and the descriptions of the first pad PD1 and the second pad PD2 can be similarly applied to the third pad PD3. Furthermore, in this specification, the first direction DR1 can also refer to the column direction, and the second direction DR2 can also refer to the row direction.

[0122] The first pad PD1 may include a signal pad PD and a dummy pad DMP arranged side-by-side with the signal pad PD. The signal pad PD may refer to each of these pads being electrically connected to a data line DL (see [link to relevant documentation]). Figure 4 The pads are defined as follows: a first pad PD1 can include multiple input rows P-1, P-2, P-3, P-4, and P-5, each extending in the second direction DR2. A second pad PD2 can include an output row P-10 extending in the second direction DR2. The spacing between first pads PD1 on the same input row can be equal. A description of one row of multiple rows can be similarly applied to the other rows.

[0123] In the following text, Figure 8 This will be described based on a single line. The first central pad PD1, located in the center on the second direction DR2, can be located on the reference line VL. The central area CA of the first pad PD1 can be defined as the area adjacent to the reference line VL. That is, the central area CA can be the area adjacent to the center of the first pad PD1 on the second direction DR2.

[0124] Multiple signal pads (PDs) can be provided in the central area (CA), and each of the multiple signal pads (PDs) in the central area (CA) can be a first signal pad (PD-1). Each of the multiple first signal pads (PD-1) can extend along a first direction (DR1). Multiple dummy pads (DMPs) can be provided in the central area (CA), and each of the multiple dummy pads (DMPs) in the central area (CA) can be a first-1 dummy pad (DMP1-1). Each of the first-1 dummy pads (DMP1-1) can extend along a first direction (DR1).

[0125] In the first pad PD1, the first pad PD1 located to the left of the central area CA can be configured to have a preset tilt angle relative to the reference line VL. The first pad PD1 located to the left of the central area CA can extend along a first tilt direction CDR1 that intersects with the first direction DR1 and the second direction DR2. In the first pad PD1, the first pad PD1 located to the right of the reference line VL can extend along a second tilt direction CDR2 that is symmetrical to the first tilt direction CDR1 with respect to the first direction DR1. The first pad PD1 located to the left of the central area CA can be configured to form an acute angle with respect to the reference line VL in a clockwise direction. The first pad PD1 located to the right of the central area CA can be configured to form an acute angle with respect to the reference line VL in a counterclockwise direction.

[0126] The second signal pad PD-2 can refer to a pad spaced apart from the first signal pad PD-1 on the second direction DR2. The second signal pad PD-2 can be located in the outer area of ​​the central area CA of the first pad PD1. The second signal pad PD-2 can be located to the left and right of the central area CA.

[0127] The signal pad PD may include a first signal pad PD-1 and a second signal pad PD-2, and the first dummy pad DMP1 may include a first-1 dummy pad DMP1-1 and a first-2 dummy pad DMP1-2. At least some of the first dummy pads DMP1 may have a length substantially the same as the length of the signal pad PD in the first direction DR1, and may have a length substantially the same as the length of the signal pad PD in the second direction DR2.

[0128] The first and second dummy pads DMP1-2 can refer to dummy pads spaced apart from the second signal pad PD-2 on the second direction DR2. The first and second dummy pads DMP1-2 can be located between the second signal pads PD-2 and in the outermost area of ​​the first pad PD1 on the second direction DR2. That is, the first and second dummy pads DMP1-2 can be located in the outer area of ​​the central area CA of the first pad PD1, and can be located to the left and right of the central area CA.

[0129] Furthermore, in this specification, the term "substantially identical" includes cases where the components have exactly the same value for each of the length, width, etc., and cases where, although they are designed identically, the components have the same value within the range of differences that may occur due to manufacturing tolerances.

[0130] The second dummy pad DMP2 can be a dummy pad with a stacking structure different from that of the first dummy pad DMP1. The second dummy pad DMP2 can be a dummy pad that does not include the dummy pattern DML, which will be described later (see [link to dummy pad DMP2]). Figure 10A The second dummy pad DMP2 is not necessarily included in the first pad PD1. The second dummy pad DMP2 can be located between signal pads PD, in the central area CA where the first dummy pad DMP1-1 is located, and in the outermost area of ​​the first pad PD1 where the first dummy pad DMP1-2 is located. Furthermore, the second dummy pad DMP2 can have a length substantially the same as the first dummy pad DMP1 in the first direction DR1, and can also have a length substantially the same as the first dummy pad DMP1 in the second direction DR2.

[0131] Figure 9A This is an enlarged plan view of the signal pad PD according to an embodiment of the present invention, and Figure 9B and Figure 9C This is a cross-sectional view of the signal pad PD.

[0132] The signal pad PD may include a first conductive pattern CL1, a second conductive pattern CL2, and an insulating pattern PP. Figure 9A The data line DL, including the DL-E terminal, is shown (see [link]). Figure 4 ) as signal line SGL (see Figure 4 (Example, but) Figure 4 The other signal lines SGL shown can have the same characteristics as those shown. Figure 9A The configuration is the same as the one disclosed in [the document]. For ease of description, only the data line DL (see [reference]) is shown. Figure 4 The terminal DL-E of )

[0133] Although not shown in the plan view, the first conductive pattern CL1 can be connected to the data line DL via at least one contact hole (see...). Figure 4 The end DL-E of the terminal DL-E. In the plan view, the end DL-E may have a shape extending in the first direction DR1. That is, the length or width of the end DL-E in the first direction DR1 may be greater than the length or width of the end DL-E in the second direction DR2.

[0134] Figure 9A A signal pad PD is shown comprising six insulating patterns PP1 to PP6, but the number of insulating patterns PP is not limited to this. In a plan view, the insulating patterns PP may overlap with a first conductive pattern CL1 and a second conductive pattern CL2. In a plan view, the insulating patterns PP may be arranged along a first direction DR1. The insulating patterns PP may be positioned to be spaced apart from each other in the first direction DR1.

[0135] The insulating pattern PP can comprise a polymer. The insulating pattern PP can comprise a thermosetting polymer. However, embodiments of the present invention are not limited thereto, and the insulating pattern PP can comprise a thermoplastic polymer.

[0136] In the planar drawing, the insulating pattern PP is shown as having a square shape, but the shape of the insulating pattern PP is not limited to this. For example, the planar shape of the insulating pattern PP can be other polygonal shapes, circular shapes, elliptical shapes, etc., besides square shapes. Furthermore, the shape of the insulating pattern PP is not limited to the same shape.

[0137] In the plan view, the second conductive pattern CL2 may have a larger area than the first conductive pattern CL1, and the first conductive pattern CL1 may be disposed inside the second conductive pattern CL2. In addition to the first conductive pattern CL1 and the second conductive pattern CL2, additional conductive patterns may be included, and embodiments of the present invention are not limited thereto.

[0138] Figure 9B It shows along Figure 9A The cross section intercepted by line I-I', and Figure 9C It shows along Figure 9A The cross section intercepted by line II-II'. Figure 9B and Figure 9C In the middle, for reference Figure 5 and Figure 9A The description of the above components can be omitted.

[0139] refer to Figure 9B and Figure 9C The terminal DL-E can be disposed on the first insulating layer 10. The terminal DL-E and the gate G (see...) Figure 5) can be set on the same layer. The terminal DL-E and gate G (see...) Figure 5 These can be formed using the same process and can include the same materials. However, the location of the terminal DL-E is not limited to this. Some of the multiple signal lines and the gate G (see...) Figure 5 The signal lines can be set on the same layer (e.g., on the first insulating layer 10), and the other signal lines among the multiple signal lines can be set on the second insulating layer 20.

[0140] A first conductive pattern CL1 may be disposed on a fourth insulating layer 40. The first conductive pattern CL1 may be connected to the end DL-E via contact holes passing through the second to fourth insulating layers 20, 30 and 40. That is, the first conductive pattern CL1 may contact the end DL-E via contact holes. The first conductive pattern CL1 and the end DL-E may be separated by the second to fourth insulating layers 20, 30 and 40 disposed between the first conductive pattern CL1 and the end DL-E.

[0141] refer to Figure 9B and Figure 9C The second conductive pattern CL2 can be disposed on the first conductive pattern CL1. The area of ​​the second conductive pattern CL2 that does not overlap with the insulating pattern PP can be in direct contact with the first conductive pattern CL1. The area of ​​the second conductive pattern CL2 that overlaps with the insulating pattern PP can be in contact with the insulating pattern PP.

[0142] Meanwhile, the first conductive pattern CL1 and the second conductive pattern CL2 may each include elements included in the aforementioned circuit element layer DP-CL (see...). Figure 5 The first conductive pattern CL1 and the second conductive pattern CL2 may each include at least some of the conductive layers (e.g., connecting electrodes CNE) (see...). Figure 5 The materials are the same.

[0143] In an embodiment, the first conductive pattern CL1 can be connected to the first connection electrode CNE1 (see [reference]). Figure 5 The second conductive pattern CL2 can be formed using the same process as that used for the second connection electrode CNE2 (see [link to process]). Figure 5 The first conductive pattern CL1 and the first connecting electrode CNE1 (see...) are formed using the same process. Figure 5 The second conductive pattern CL2 and the second connecting electrode CNE2 (see...) may include the same material, and the second conductive pattern CL2 and the second connecting electrode CNE2 (see...) Figure 5 () can include the same material.

[0144] In an embodiment, the second conductive pattern CL2 may be disposed on the input sensor ISU (see [reference]). Figure 6AThe sensor insulating layer IS-IL may be located on the sensor insulating layer IS-IL. Figure 6A At least one of the first sensor insulating layer IS-IL1 and the second sensor insulating layer IS-IL2 shown in the figure. The second conductive pattern CL2 may include Figure 6A At least one of the first conductive patterned layer IS-CL1 and the second conductive patterned layer IS-CL2 shown in the figure.

[0145] Figure 9B and Figure 9C An exemplary embodiment of a first conductive pattern CL1 disposed on a fourth insulating layer 40 is shown. However, according to the embodiment, the first conductive pattern CL1 may also be disposed on a third insulating layer 30, and the fourth insulating layer 40 may not be disposed. However, embodiments of the inventive concept are not limited thereto, and as long as first conductive patterns CL1 and second conductive patterns CL2 disposed on different layers can be provided, a combination of the first conductive patterns CL1 and second conductive patterns CL2 formed by the same process as that used for connecting electrodes can be used according to the circuit element layer DP-CL (see...). Figure 5 The stacking structures were chosen differently.

[0146] Figure 10A This is an enlarged plan view of a dummy pad DMP according to an embodiment of the present invention, and Figure 10B This is a cross-sectional view of the dummy pad DMP. Figure 11 This is a cross-sectional view of a portion of a display panel DP according to an embodiment of the present invention. Figure 11 It is the pad area PA (see Figure 8 A cross-sectional view of a portion of ( ). In Figure 10A , Figure 10B and Figure 11 In the middle, for reference Figures 9A to 9C The description of the above components can be omitted.

[0147] Dummy pads (DMPs) can be electrically isolated conductive patterns. That is, dummy pads (DMPs) can be floating patterns. DMPs can be positioned between signal pads (PDs) and also in the outermost area of ​​the signal pads (PDs). DMPs can reduce electrical interference between adjacent signal pads (PDs) and reduce potential fluctuations in the signal pads (PDs) caused by adjacent signal pads (PDs). Accordingly, noise between signal pads (PDs) is reduced, and therefore electrical stability is improved. Furthermore, the presence of dummy pads (DMPs) prevents the display panel (DP) and electronic components from being bent or broken during the bonding process.

[0148] like Figure 10AAs shown in the diagram, in a plan view, the dummy pad DMP may include a first conductive pattern CL1 and a dummy pattern DML. In the plan view, the dummy pattern DML may be disposed inside the first conductive pattern CL1.

[0149] Figure 10A A dummy pad DMP is shown, comprising three dummy patterns DML1 to DML3, but the number of dummy patterns DML is not limited to this. Furthermore, in a planar view, the dummy patterns DML may overlap with the first conductive pattern CL1. In a planar view, the dummy patterns DML may be arranged along a first direction DR1 and may be spaced apart from each other in the first direction DR1.

[0150] Figure 10B It shows along Figure 10A The cross-section taken by line III-III'. The dummy pattern DML can be set on the first conductive pattern CL1. Reference Figure 10B and Figure 11 Even if the dummy pattern DML and the insulating pattern PP are set on the same layer, the dummy pattern DML and the insulating pattern PP can be formed by different processes. In addition, the dummy pattern DML can include a different material than the insulating pattern PP.

[0151] The dummy pattern DML of the embodiment of the present invention has a higher hardness than the insulating pattern PP. That is, the dummy pattern DML of the dummy pad DMP can have a higher physical pressure resistance than the insulating pattern PP of the signal pad PD, and therefore, the dummy pattern DML of the dummy pad DMP is less susceptible to compression or deformation due to physical pressure. Furthermore, the dummy pattern DML can include a metal. For example, the dummy pattern DML can include high-hardness metals such as titanium (Ti), aluminum (Al), or zirconium (Zr). In addition, the dummy pattern DML can further include high-hardness organic materials such as polycarbonate, polyurethane, polyamide resins, or epoxy resins.

[0152] In this embodiment, the hardness of the dummy pattern DML can be higher than the hardness of the first conductive pattern CL1. That is, when physical pressure is applied from the upper part of the dummy pad DMP to the lower part of the dummy pad DMP, the pressure applied to the dummy pattern DML can be transmitted to the first conductive pattern CL1, and therefore, the first conductive pattern CL1 can be compressed or deformed.

[0153] In an embodiment, the dummy pattern DML and the second conductive pattern CL2 may comprise the same material and can be formed using the same process. However, the dummy pattern DML and the second conductive pattern CL2 may be formed using separate processes. For example, the second conductive pattern CL2 may be formed, and then the dummy pattern DML, having a thickness different from that of the second conductive pattern CL2, may be formed using separate processes. However, the order of the above processes is not limited. Similarly, the dummy pattern DML may be formed, and then the second conductive pattern CL2 may be formed.

[0154] like Figure 11 As shown, when connected to the driver chip DC (see...) Figure 2 Previously, the thickness T1 of the dummy pattern DML could be less than that connected to the driver chip DC (see...). Figure 2 The thickness T2 of the insulating pattern PP before connection. In an embodiment, the thickness T2 is the thickness of the insulating pattern PP before connection to the driver chip DC (see...). Figure 2 The dummy pattern DML can have a thickness T1 of approximately 1 μm to approximately 5 μm. Accordingly, during the bonding process with electronic components, the signal pad PD can be connected to the driver chip DC via the dummy pad DMP (see [link to relevant documentation]). Figure 2 First connect it to the driver chip DC (see) Figure 2 Then connect it to the electronic components.

[0155] Figure 12 This is a cross-sectional view of a portion of a display device DD to which the driver chip DC is connected, according to an embodiment of the present invention. Figure 12 The diagram shows the contact states of the signal pad PD and the dummy pad DMP with the driver chip DC. Descriptions of these components may be omitted below.

[0156] The driver chip DC may include a driver integrated circuit DC-BS and a driver bump DC-BP disposed under the driver integrated circuit DC-BS. The driver bump DC-BP may include signal bumps and dummy bumps, and the signal bumps and dummy bumps may correspond to signal pads PD and dummy pads DMP, respectively.

[0157] The driver bump DC-BP of the driver chip DC can contact the signal pad PD and the dummy pad DMP through a bonding process. The driver bump DC-BP can contact the second conductive pattern CL2 of the signal pad PD and the dummy pattern DML of the dummy pad DMP. Since the display device DD of this invention does not include conductive particles such as conductive balls, short-circuit failures caused by conductive particles can be reduced even when the signal pad PD is densely arranged. Furthermore, conductive failures that occur when conductive particles are not arranged between the signal pad PD and the driver bump DC-BP can be prevented, and therefore, the electrical connection characteristics between the signal pad PD and the driver bump DC-BP can be improved.

[0158] like Figure 12 As shown, the dummy pad DMP and signal pad PD can have different stacking structures. During the process in which the dummy pad DMP and signal pad PD are each connected to the drive bump DC-BP, pressure can be applied to the insulating layer 10 to 15-11-11, the buffer layer BFL, the barrier layer BRL, and the base layer BL disposed beneath the dummy pad DMP and signal pad PD. The pressure can be concentrated at the portions of the dummy pad DMP and signal pad PD that overlap with the drive bump DC-BP.

[0159] When pressure is applied to the signal pad PD that overlaps with the signal bump, the insulating pattern PP can be compressed. As described above, since the hardness of the insulating pattern PP is lower than that of the dummy pattern DML, the thickness T2 of the insulating pattern PP can be reduced when pressure is applied. That is, the insulating pattern PP can be used as a buffer to absorb bonding pressure, and therefore, the lower surfaces of the insulating layers 10 to 15-11-11, the buffer layer BFL, the barrier layer BRL, and the base layer BL that overlap with the signal pad PD can remain undeformed.

[0160] Conversely, when pressure is applied to the dummy pattern DML that overlaps with the dummy bump, the lower surface of the dummy pattern DML may have a convex shape in the direction toward the substrate layer BL. Similarly, the lower surfaces of the insulating layers 10 to 15-11-11, the buffer layer BFL, the barrier layer BRL, and the substrate layer BL that overlap with the dummy pattern DML may also have a convex shape in the direction toward the substrate layer BL.

[0161] In embodiments of the present invention, the lower surface of the substrate layer BL corresponding to the dummy pad DMP can have a shape that protrudes beyond the lower surface of the substrate layer BL corresponding to the signal pad PD. Accordingly, an indentation IDM caused by bonding pressure can be formed on the lower surface of the substrate layer BL corresponding to the dummy pattern DML. That is, the indentation IDM can be formed on the rear surface of the display panel corresponding to the dummy pad DMP, but may not be formed on the rear surface of the display panel corresponding to the signal pad PD. The indentation IDM can be used to inspect the flatness of electronic components and the display panel, as well as unbonded areas caused by foreign matter. Accordingly, initial process failures can be easily detected. Furthermore, since the indentation IDM is not formed on the rear surface of the display panel corresponding to the signal pad PD, the breakage of the conductive patterns CL1 or CL2 due to bonding pressure can be reduced, and therefore, physical damage to the display panel can be reduced.

[0162] refer to Figure 11 and Figure 12 Due to the bonding process, the thickness T1' of the dummy pattern DML after bonding can be reduced compared to the thickness T1 of the dummy pattern DML before bonding, or the thickness T1' of the dummy pattern DML after bonding can be the same as the thickness T1 of the dummy pattern DML before bonding. Since the dummy pattern DML comprises a high-hardness material, it does not absorb bonding pressure, and therefore the pressure can be transmitted to the lower surface of the dummy pattern DML. Conversely, the thickness T2' of the insulating pattern PP after bonding can be reduced compared to the thickness T2 of the insulating pattern PP before bonding. As described above, since the insulating pattern PP absorbs bonding pressure, the thickness T2 of the insulating pattern PP can be reduced according to the bonding process. Therefore, the thickness change of the dummy pattern DML according to the bonding process can be less than the thickness change of the insulating pattern PP.

[0163] Figure 13 and Figure 14 These are enlarged plan views of dummy pads (DMPs) according to other embodiments of the present invention. Figure 13 A dummy pad DMP is shown, comprising six dummy patterns DML1 to DML6, and Figure 14 A dummy pad DMP is shown, which includes two dummy patterns DML1 and DML2, but the number of dummy patterns DML is not limited to this.

[0164] also, Figure 13 The dummy pattern DML is shown to have an elliptical shape, and Figure 14The dummy pattern DML is shown to have a rectangular shape extending in the first direction DR1. However, the planar shape of the dummy pattern DML can also be a polygonal shape, a circular shape, etc., other than a rectangular shape. Furthermore, the shape of the dummy pattern DML is not limited to the same shape.

[0165] According to embodiments of the present invention, the display panel can be connected to electronic components without an anisotropic conductive film. Even when signal pads are densely arranged in the pad area, short-circuit failures caused by conductive particles can be reduced.

[0166] The insulating pattern on the signal pads of the display panel allows the conductive pattern of the signal pads to protrude toward the electronic components. Accordingly, the proximity between the signal pads of the display panel and the bumps or pads of the electronic components can be enhanced, and thus, bonding performance can be improved.

[0167] Because the dummy pads in the pad area of ​​the display panel include dummy patterns with a relatively higher hardness than the insulating pattern, indentations can be formed on the back surface of the display panel during the bonding process between the display panel and the electronic components. These indentations can be used to inspect the flatness of the electronic components and the display panel, as well as unbonded areas caused by foreign matter, and therefore, initial process failures can be easily detected.

[0168] In the foregoing description, embodiments of the inventive concept have been described with reference to the present invention. However, those skilled in the art will understand that various modifications and alterations can be made to the inventive concept, as long as such modifications and alterations do not depart from the spirit and scope of the inventive concept as set forth in the claims. Therefore, the scope of the inventive concept is not limited to the contents stated in the detailed description of the specification, but should be determined by the claims.

Claims

1. A display device, comprising: The display panel includes a display area and a non-display area adjacent to the display area; Pixels are set in the display area; Signal lines are disposed in the display area and the non-display area and are electrically connected to the pixels; Signal pads, disposed in the non-display area and electrically connected to the signal lines; and The first dummy pad is located in the non-display area and spaced apart from the signal pad. The signal pad includes a first conductive pattern electrically connected to the end of the signal line, an insulating pattern disposed on the first conductive pattern, and a second conductive pattern disposed on the insulating pattern. Wherein, the first dummy pad includes the first conductive pattern and a dummy pattern disposed on the first conductive pattern, and The hardness of the dummy pattern is higher than that of the insulating pattern.

2. The display device according to claim 1, wherein, The dummy pattern and the second conductive pattern both use the same material.

3. The display device according to claim 1, wherein, The dummy pattern includes metal.

4. The display device according to claim 1, wherein, The hardness of the dummy pattern is higher than that of the first conductive pattern.

5. The display device according to claim 1, wherein, The dummy pattern has a thickness of 1 μm to 5 μm.

6. The display device according to claim 1, wherein, In the plan view, the dummy pattern is disposed inside the first conductive pattern.

7. The display device according to claim 1, wherein, In the plan view, the first dummy pad extends in one direction. The dummy pattern is provided in multiple ways to provide multiple dummy patterns, and In the plan view, the plurality of dummy patterns are positioned to be spaced apart from each other in one direction.

8. The display device according to any one of claims 1 to 7, wherein, The first dummy pad is electrically isolated.

9. An electronic device, comprising: The display panel includes a display area and a non-display area adjacent to the display area; as well as Electronic components, disposed in the non-display area, are electrically connected to the display panel and include signal bumps and dummy bumps. The display panel includes: basal layer; An insulating layer is disposed on the substrate layer; Pixels are set in the display area; Signal pads, disposed in the non-display area and corresponding to the signal bumps; and A dummy pad is set in the non-display area and corresponds to the dummy bump. The signal pad includes a first conductive pattern, an insulating pattern disposed on the first conductive pattern, and a second conductive pattern disposed on the insulating pattern. The dummy pad includes the first conductive pattern and a dummy pattern disposed on the first conductive pattern, and The hardness of the dummy pattern is higher than that of the insulating pattern.

10. The electronic device according to claim 9, wherein, The lower surface of the substrate layer corresponding to the dummy pad protrudes more than the lower surface of the substrate layer corresponding to the signal pad.

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