Manufacturing method of embedded heterogeneous chip hybrid system-in-package
By setting a metal cover on a multilayer packaging substrate and forming a chip cavity using plasma etching, the problem of mixed packaging of double-sided and single-sided I/O chips in the prior art is solved, and high-precision three-dimensional packaging and conduction are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SUZHOU YIMAI SILICON SEMICON TECH CO LTD
- Filing Date
- 2025-12-29
- Publication Date
- 2026-04-21
AI Technical Summary
Existing embedded packaging technology cannot achieve hybrid packaging of double-sided and single-sided I/O chips, and there is a problem that chip displacement deviation affects wiring density.
A multi-layer packaging substrate structure is adopted, a metal cover is set and a chip cavity is formed by plasma etching. The chip is vertically embedded and encapsulated. Then, wiring is performed on the upper and lower surfaces of the substrate to ensure the conduction of double-sided I/O chips and single-sided I/O chips.
Hybrid packaging of double-sided and single-sided I/O chips was achieved, which improved etching accuracy, saved space, and ensured the continuity between the chip and the metal circuit, thus realizing three-dimensional packaging.
Smart Images
Figure CN121908899A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of packaging substrate technology, and in particular to a method for fabricating an embedded heterogeneous chip hybrid system-in-package. Background Technology
[0002] Packaging substrates provide electrical connections, protection, support, heat dissipation, and assembly for chips, enabling multi-pin configurations, reduced package size, improved electrical performance and heat dissipation, ultra-high density, or multi-chip modularization. Most of the substrates currently used are semiconductor packaging substrates.
[0003] Existing embedded packaging technology mainly involves creating cavities in the inner layer of a substrate to place the chip, and then fixing the chip in the substrate in a surface mount manner. This can only achieve semiconductor device packaging technology on a two-dimensional plane. Existing technology completes chip embedding first, but in this process, it is impossible to avoid large deviations in chip displacement, which will affect the density of subsequent double-sided wiring. As a result, it is impossible to achieve the wiring accuracy required for multi-IO products, and it is impossible to achieve hybrid packaging of double-sided IO chips and single-sided IO chips. Summary of the Invention
[0004] The purpose of this invention is to provide a method for manufacturing a hybrid system-in-package (SIP) of embedded heterogeneous chips, which can realize the hybrid packaging of double-sided I / O chips and single-sided I / O chips.
[0005] The technical solution adopted in the method for fabricating an embedded heterogeneous chip hybrid system-in-package disclosed in this invention is as follows: A method for fabricating an embedded heterogeneous chip hybrid system-in-package includes the following steps: S1, Prepare a substrate by using a dielectric material to prepare a multilayer packaging substrate structure, wherein the multilayer packaging substrate has metal lines inside and on the surface, and copper pillars are embedded in the multilayer packaging substrate, and some of the metal lines can be connected through the copper pillars. S2, Set metal covers: Multiple metal covers are set on the surface of the multilayer packaging substrate, and the metal covers avoid the positions where the chips need to be packaged. S3, etching cavity: The plasma generator is used to etch the area on the surface of the multilayer packaging substrate without a metal cover to form the cavity of the packaged chip, and the etching stops when it encounters a metal line. S4, Remove the metal cover: Remove the metal cover that is placed on the surface of the multilayer packaging substrate; S5, chip molding, the chip is placed vertically in the cavity for molding and embedding, and the height of the potting is consistent with the surface height of the multilayer packaging substrate; S6, double-sided wiring: wiring is performed on both the upper and lower surfaces of the multilayer packaging substrate after molding.
[0006] As a preferred embodiment, the multilayer packaging substrate comprises multiple dielectric material layers stacked sequentially from top to bottom to form a multilayer structure, and the metal lines are disposed on the surface of each dielectric material layer. The copper pillars are all embedded in the dielectric material layers. The copper pillars can be used to connect the metal lines of each dielectric material layer, and the copper pillars extend to the upper and lower surfaces of the multilayer packaging substrate respectively.
[0007] As a preferred embodiment, when etching the cavity in step S3, the depth and position of the etched cavity are limited according to the chip structure to be packaged. When the chip is a double-sided I / O chip, it is necessary to ensure that the bottom of the cavity is connected to the metal circuit and that the depth of the cavity is greater than the height of the chip.
[0008] As a preferred embodiment, step S3 uses a plasma generator of 10 kW or higher to etch the substrate surface. Taking advantage of the characteristic that CF4 plasma can only attack and etch organic dielectric materials but cannot etch metals, the resin dielectric material is etched at high speed in the non-metallic shield protection zone on the multilayer packaging substrate to form a cavity.
[0009] As a preferred embodiment, in step S6, the specific wiring steps are as follows: corresponding to the position of the encapsulated chip, blind holes are laser-drilled on the upper surface of the multilayer packaging substrate, and then through exposure, development, and blind hole pattern electroplating processes, metal lines are formed on the upper surface of the multilayer packaging substrate. The chip is connected to the metal lines on the upper surface of the multilayer packaging substrate through the blind holes. Metal lines are also set on the lower surface of the multilayer packaging substrate corresponding to the copper pillar positions.
[0010] The beneficial effects of the embedded heterogeneous chip hybrid system-in-package method disclosed in this invention are as follows: By setting a metal cover on the surface of the multilayer packaging substrate, damage to the unetched parts of the multilayer packaging substrate caused by the subsequent etching cavity is avoided, and the etching accuracy is also improved. The chip is placed vertically in the cavity for plastic encapsulation embedding. The chip is packaged in a three-dimensional manner instead of the traditional two-dimensional planar surface mount method, saving the surface space of the multilayer packaging substrate. When the double-sided I / O chip is embedded, the pins at the bottom of the chip make contact and conduction with the metal lines in the multilayer packaging substrate. Then, the chip is fixed and packaged by plastic encapsulation. Finally, by setting wiring on both the upper and lower surfaces of the multilayer packaging substrate, the double-sided packaging structure of the multilayer packaging substrate is realized, and it is ensured that both double-sided I / O chips and single-sided I / O chips can be packaged and conduction. Attached Figure Description
[0011] Figure 1 This is a schematic diagram of step S1 of the fabrication method of an embedded heterogeneous chip hybrid system-in-package according to the present invention.
[0012] Figure 2This is a schematic diagram of steps S2 and S3 of the fabrication method of an embedded heterogeneous chip hybrid system-in-package according to the present invention.
[0013] Figure 3 This is a schematic diagram of steps S4 and S5 of the fabrication method of an embedded heterogeneous chip hybrid system-in-package according to the present invention.
[0014] Figure 4 This is a schematic diagram of step S6 of the fabrication method of an embedded heterogeneous chip hybrid system-in-package according to the present invention. Detailed Implementation
[0015] The present invention will be further described and illustrated below with reference to specific embodiments and the accompanying drawings: Please refer to Figure 1 A method for fabricating an embedded package chip 20 substrate includes the following steps: S1, Prepare a substrate. A multilayer packaging substrate 10 structure is prepared using a dielectric material. Metal lines 11 are provided inside and on the surface of the multilayer packaging substrate 10. Copper pillars 12 are embedded in the multilayer packaging substrate 10. Some of the metal lines 11 can be connected through the copper pillars 12.
[0016] The multilayer packaging substrate 10 includes multiple dielectric material layers stacked sequentially from top to bottom to form a multilayer structure, and metal lines 11 are disposed on the surface of each dielectric material layer. Copper pillars 12 are embedded in the dielectric material layers. The copper pillars 12 can be used to connect the metal lines 11 of each dielectric material layer, and the copper pillars 12 extend to the upper and lower surfaces of the multilayer packaging substrate 10 respectively.
[0017] The multi-layer structure enables different layers of wiring to be arranged inside the multi-layer packaging substrate 10, thereby increasing the overall wiring space of the multi-layer packaging substrate 10. In order to meet the design requirements between different layers, copper pillars 12 are used for conduction. Copper pillars 12 are provided in the dielectric material layers at the top and bottom for subsequent wiring conduction.
[0018] Please refer to Figure 2 S2, Set metal cover 13, Set multiple metal covers 13 on the surface of multilayer packaging substrate 10, and the metal covers 13 avoid the position of the chip 20 to be packaged. S3, etching cavity: The plasma generator is used to etch the area on the surface of the multilayer packaging substrate 10 where there is no metal cover 13 to form the cavity of the packaged chip 20, and the etching stops when it encounters the metal line 11.
[0019] When etching the cavity in step S3, the depth and position of the etched cavity are defined according to the structure of the chip 20 to be packaged. When the chip 20 is a double-sided IO chip 20, it is necessary to ensure that the bottom of the cavity is connected to the metal line 11 and that the depth of the cavity is greater than the height of the chip 20.
[0020] Step S3 uses a plasma generator of 10 kW or higher to etch the substrate surface. Taking advantage of the fact that CF4 plasma can only attack and etch organic dielectric materials but cannot etch metals, the resin dielectric material is etched at high speed in the non-metallic shield 13 protection zone on the multilayer packaging substrate 10 to form a cavity.
[0021] Please refer to Figure 3 and 4 S4, Remove the metal cover 13. Remove the metal cover 13 that is placed on the surface of the multilayer packaging substrate 10. S5, chip 20 is encapsulated by placing the chip 20 vertically in the cavity for encapsulation embedding, and the height of the encapsulation is consistent with the surface height of the multilayer packaging substrate 10.
[0022] The chip 20 is first embedded in the cavity and then encapsulated with a molding dielectric material. There is no film flow, and the embedded chip 20 will not shift, thus providing the loading accuracy of the chip 20, thereby realizing the embedding fabrication of the high IO chip 20.
[0023] Please refer to Figure 4 S6, double-sided wiring: wiring is set on both the upper and lower surfaces of the multilayer packaging substrate 10 after molding.
[0024] The specific wiring steps are as follows: corresponding to the position of the encapsulated chip 20, blind holes are laser-drilled on the upper surface of the multilayer packaging substrate 10, and then through exposure, development, and blind hole pattern electroplating processes, metal lines 11 are set on the upper surface of the multilayer packaging substrate. The chip 20 is connected to the metal lines 11 on the upper surface of the multilayer packaging substrate 10 through the blind holes. Metal lines 11 are also set on the lower surface of the multilayer packaging substrate 10 corresponding to the position of the copper pillar 12.
[0025] By placing a metal shield on the surface of the multilayer packaging substrate, damage to the unetched parts of the multilayer packaging substrate by the subsequent etching cavity is avoided, and the etching accuracy is also improved. The chip is placed vertically in the cavity for plastic encapsulation embedding. The chip is packaged in a three-dimensional manner instead of the traditional two-dimensional planar surface mount method, saving surface space of the multilayer packaging substrate. When the double-sided I / O chip is embedded, the pins at the bottom of the chip make contact with the metal lines in the multilayer packaging substrate and conduction. Then, the chip is fixed and packaged by plastic encapsulation. Finally, by setting wiring on both the upper and lower surfaces of the multilayer packaging substrate, the double-sided packaging structure of the multilayer packaging substrate is realized, and it is ensured that both double-sided I / O chips and single-sided I / O chips can be packaged and conduction.
[0026] This invention provides a method for fabricating an embedded heterogeneous chip hybrid system-in-package. By setting a metal shield on the surface of a multilayer packaging substrate, damage to the unetched parts of the multilayer packaging substrate caused by subsequent etching cavities is avoided, and etching accuracy is also improved. The chip is placed vertically in the cavity for plastic encapsulation embedding. The chip is packaged in a three-dimensional manner instead of the traditional two-dimensional planar surface mount method, saving surface space of the multilayer packaging substrate. When the double-sided I / O chip is embedded, the pins at the bottom of the chip make contact and conduction with the metal lines in the multilayer packaging substrate. Then, the chip is fixed and packaged by plastic encapsulation. Finally, by setting wiring on both the upper and lower surfaces of the multilayer packaging substrate, a double-sided packaging structure of the multilayer packaging substrate is realized, ensuring that both double-sided and single-sided I / O chips can be packaged and conduct.
[0027] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit the scope of protection of the present invention. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the essence and scope of the technical solutions of the present invention.
Claims
1. A method for fabricating an embedded heterogeneous chip hybrid system-in-package, characterized in that, Includes the following steps: S1, Prepare a substrate. A multilayer packaging substrate structure is prepared using a dielectric material. Metal lines are provided inside and on the surface of the multilayer packaging substrate. Copper pillars are embedded in the multilayer packaging substrate, and some of the metal lines can be connected through the copper pillars. S2, Set metal covers: Multiple metal covers are set on the surface of the multilayer packaging substrate, and the metal covers avoid the positions where the chips need to be packaged. S3, etching cavity: The plasma generator is used to etch the area on the surface of the multilayer packaging substrate without a metal cover to form the cavity of the packaged chip, and the etching stops when it encounters a metal line. S4, Remove the metal cover: Remove the metal cover that is placed on the surface of the multilayer packaging substrate; S5, chip molding, the chip is placed vertically in the cavity for molding and embedding, and the height of the potting is consistent with the surface height of the multilayer packaging substrate; S6, double-sided wiring: wiring is configured on both the upper and lower surfaces of the multilayer packaging substrate after molding.
2. The method for fabricating an embedded heterogeneous chip hybrid system-in-package as described in claim 1, characterized in that, The multilayer packaging substrate comprises multiple dielectric material layers stacked sequentially from top to bottom to form a multilayer structure, and the metal lines are disposed on the surface of each dielectric material layer. The copper pillars are embedded in the dielectric material layers and can be used to connect the metal lines of each dielectric material layer. The copper pillars extend to the upper and lower surfaces of the multilayer packaging substrate respectively.
3. The method for fabricating an embedded heterogeneous chip hybrid system-in-package as described in claim 2, characterized in that, When etching the cavity in step S3, the depth and position of the etched cavity are limited according to the chip structure to be packaged. When the chip is a double-sided I / O chip, it is necessary to ensure that the bottom of the cavity is connected to the metal circuit and that the depth of the cavity is greater than the height of the chip.
4. The method for fabricating an embedded heterogeneous chip hybrid system-in-package as described in claim 3, characterized in that, Step S3 uses a plasma generator of 10 kW or higher to etch the substrate surface. Taking advantage of the fact that CF4 plasma can only attack and etch organic dielectric materials but cannot etch metals, the resin dielectric material is etched at high speed in the non-metallic shield protection area on the multilayer packaging substrate to form a cavity.
5. The method for fabricating an embedded heterogeneous chip hybrid system-in-package as described in claim 2, characterized in that, In step S6, the specific wiring steps are as follows: corresponding to the position of the encapsulated chip, blind holes are laser-drilled on the upper surface of the multilayer packaging substrate, and then through exposure, development, and blind hole pattern electroplating processes, metal lines are set on the upper surface of the multilayer packaging substrate. The chip is connected to the metal lines on the upper surface of the multilayer packaging substrate through the blind holes. Metal lines are also set on the lower surface of the multilayer packaging substrate corresponding to the copper pillar positions.