Error correction using on-die parity storage and transition signals

Abstract

The described technology provides a multi-level error correction method including encoding data received from a dual data rate (DDR) memory by performing primary encoding to generate transition symbols, where the primary encoding includes at least one of cyclic redundancy check (CRC) encoding and single error correction dual error detection (SECDED) encoding; performing secondary encoding on the transition symbol to generate an inner code, the inner code including a Code 1 parity generated from the transition symbol and a Code 2 parity generated from the transition symbol and metadata stored on the DDR memory, where the secondary encoding includes Reed-Solomon (RS) encoding, and saving the inner code on a parity storage location on a die of the DDR memory.

Description

Background Technology

[0001] In many computer systems, error detection and correction (ECC) is used to detect and correct errors in data stored in the computer system's memory. To protect data using ECC, an algorithm is applied to the data before it is stored in memory, generating a corresponding error correction code. Depending on the type of ECC used, the code may allow the detection of one or more error bits in the data and may also allow the correction of one or more such error bits. For any dynamic random access memory (DRAM) device, simple protection such as adding parity bits can be used to prevent potential failures. Using too many parity bits for data protection is a waste of memory. On the other hand, using too few parity bits may not allow for error detection or correction. For example, if Hamming codes are used for parity bit correction, the amount of parity data added to the Hamming codes is determined by Equation 2. p ≥d+p+1 is given, where p It is the number of parity bits, and d This refers to the number of data bits. Therefore, the number of parity bits... p The higher the value, the more data bits it covers. d The higher. Summary of the Invention

[0002] The described technique provides a multi-level error correction method comprising: encoding data received from a dual data rate (DDR) memory to generate a transition symbol by performing primary encoding, wherein the primary encoding includes at least one of cyclic redundancy check (CRC) encoding and single error corrected double error detection (SECDED) encoding; performing secondary encoding on the transition symbol to generate an inner code, the inner code including code 1 parity check generated from the transition symbol and code 2 parity check generated from the transition symbol and metadata stored on the DDR memory, wherein the secondary encoding includes Reed-Solomon (RS) encoding; and storing the inner code at a parity bit storage location on the DDR memory die.

[0003] The foregoing provides a brief summary of the invention to offer a basic understanding of some of the implementations described herein. This summary is not a broad overview of the claimed subject matter. It is neither intended to identify key or essential elements of the claimed subject matter nor to define the scope of the invention. Its sole purpose is to present some concepts of the claimed subject matter in a simplified form as a prelude to the more detailed description that follows.

[0004] This article also describes and lists other implementation methods. Attached Figure Description

[0005] Examples are illustrated in the accompanying drawings. The examples and drawings disclosed herein are intended to be illustrative rather than limiting.

[0006] Figure 1 The illustration shows an example computing system that includes an ECC management system that uses parity bits stored on the die.

[0007] Figure 2 The illustration shows example details of the transition symbols and parity bits generated by the ECC management system disclosed in this article.

[0008] Figure 3 The illustration shows an example operation for decoding data from DDR using transition symbols and internal codes.

[0009] Figure 4 The diagram illustrates an example block diagram showing the flow of data and parity bits between a data storage die and an ECC management system that uses parity bits stored on the die.

[0010] Figure 5 The illustration shows an example where the DDR has a fault on the first die and a fault on the second die.

[0011] Figure 6 The illustration shows an example where the DDR has an error in the data section of the first die, an error in the data section of the second die, and an error in the parity bit on the second die.

[0012] Figure 7 The illustration shows an example where the DDR has an error in the parity section of the first die, an error in the data section of the second die, and also an error in the parity section of the second die.

[0013] Figure 8 The diagram illustrates a scenario where the DDR has an error in the parity section of the first die, an error in the data section of the second die, and also an error in the parity section of the second die.

[0014] Figure 9 The illustration shows examples of DDR chips having errors in the parity section of the die, errors in the data section of the die, and errors in the parity section of the die.

[0015] Figure 10 The illustration shows examples of DDR chips having errors in the data section of the die, errors in the data section of the die, and errors in the parity section of the die.

[0016] Figure 11The illustration shows examples of DDR chips having errors in the parity section of the die, errors in the data section of the die, and errors in the parity section of the die.

[0017] Figure 12 The illustration shows examples of DDR chips having errors in the parity section of the die, errors in the data section of the die, and errors in the parity section of the die.

[0018] Figure 13 The illustration shows an alternative implementation of the disclosed technology using DDR with a 5×8 configuration, wherein there are five dies, each with 128 bits of data and 8 bits of parity.

[0019] Figure 14 The illustration shows an alternative implementation of the disclosed technology using a DDR with a 9×4 configuration, wherein there are 9 dies, each with 64 bits of data and 4 bits of parity.

[0020] Figure 15 The illustration shows an example computing system that can be used to implement the ECC management system disclosed herein. Detailed Implementation

[0021] The techniques disclosed herein relate to the use of error correction code (ECC) storage capacity provided by the host at the memory (DDR) level. Memory manufacturers provide on-die parity bits that can be used to correct errors in memory blocks. Currently, the host (CPU) cannot access the on-die parity bit storage location. In the techniques disclosed herein, the ECC is still stored in the dual in-line memory module (DIMM) of RAM, but it is used by the host memory controller. The techniques disclosed herein generate parity bits by performing multi-level ECC on data received from memory and storing the parity bits in the on-die parity bit storage location.

[0022] The techniques disclosed herein employ two-level error coding of data to generate parity bits that can be stored back into memory, enabling the erase decoding algorithm used by the host to determine the location of the error in memory (which die). Information about the error's location allows the host's erase decoding algorithm to recover data more efficiently. Specifically, the multi-layer ECC system disclosed herein uses erase decoding to perform error correction coding with as few bits as possible, while still providing a reasonable number of individual bit errors.

[0023] The specific implementation disclosed herein illustrates the execution of ECC on data from each die in memory to generate transition symbols for each of the first and second series of transition symbols. Transition symbols, or transition data, are transient because they are not permanently stored. For example, such transition symbols can be computed from data on DRAM and used to generate the internal code as disclosed herein. Once the internal code is generated, the transition symbols are not stored anywhere, neither in DRAM nor by the host. Subsequently, RS encoding of the first series of transition symbols generates Code 1 parity, and RS encoding of the second series of transition symbols generates Code 2 parity, where Code 2 parity is a 16-bit parity check, four 4-bit P12, P22, P32, and P42, generated by applying the Reed-Solomon (RS) algorithm to 11 4-bit second series transition symbols. Code 1 and Code 2 parity together allow the host to identify dies on which a fault has occurred. Providing the host with the identification of the faulty die allows the host to recover the data using erase decoding. In one implementation, code 1 parity and code 2 parity are stored in the parity storage location on the die, thus making the bits on the die available for storing parity bits.

[0024] Figure 1 The illustration depicts a computing system 100 including an ECC management system that uses on-die parity bit storage. The computing system 100 may include a computing device 102 such as a server, desktop computer, laptop computer, mobile device, etc. One or more modules on the computing device 102 may include a processor, input and output modules, a communication bus, a power supply module, etc. Further details of one or more components of the computing system 102 are provided below. Figure 15 The details are disclosed further. In the illustrated implementation, the computing system 102 also includes an error correction code (ECC) manager 106. Specifically, the ECC manager 106 can be configured to use the on-die parity bit storage capacity of various DRAM memory modules, and it is not necessary to store them on the ECC manager 106. The ECC manager 106 can regenerate transition symbols from the data stored on the DRAM memory modules for decoding purposes, and use them to regenerate the internal code.

[0025] The illustrated implementation shows an ECC manager 106 communicating with DRAM 120, which may be, for example, a dual data rate (DDR) DRAM. Examples of DDR DRAM 120 may include any synchronous DDR, such as DDR5 DRAM, DDR6 DRAM, etc., which provides storage capacity for parity bits on the die for DDR. Specifically, DDR 120 may include multiple data blocks 122 or dies 122. In the illustrated implementation, DDR 120 has ten (10) dies 122, and each die is configured to store 64 bits of data and 4 bits of parity data and / or metadata. The processor of computing device 102 may use the 64 bits of data from each die as a cache line. The data DDR 120 also has nine (9) 4-bit parity storage spaces 124.

[0026] ECC manager 120 includes a transition symbol generator 130 and an internal code encoder 140. The transition symbol generator 130 can perform primary encoding on 64-bit data from die 122 to generate transition symbols 134. Primary error correction encoding can include using Cyclic Redundancy Check-8 (CRC-8) codes or Single Error Corrected Double Error Detection (SECDED) Hamming codes. Specifically, transition symbols 130 can include a first series of transition symbols 136 and a second series of transition symbols 138. In one implementation, the transition symbol generator 130 can use Cyclic Redundancy Check-8 (CRC-8) codes or Single Error Corrected Double Error Detection (SECDED) Hamming codes to generate transition symbols 134. However, in other implementations, alternative codes can be used to generate transition symbols 134. Each symbol in the first series of transition symbols 136 can be a four-bit symbol. Similarly, each symbol in the second series of transition symbols 138 can also be a four-bit symbol.

[0027] The first series of transition symbols 136 may include 4 bits (Si1), where i indicates the number of dies, which in this case could be 1 to 10 per die of DDR 120. Similarly, the second series of transition symbols 138 may also include 4 bits (Si2), where i indicates the number of dies, which in this case could be 1 to 10 per die of DDR 120. Therefore, for each die of DDR 120, an 8-bit parity bit is generated from the 64-bit data on the die. For example, die 1 has 4 bits S11 in the first series of transition symbols 136 and 4 bits S12 in the second series of transition symbols 138, die 2 has 4 bits S21 in the first series of transition symbols 136 and 4 bits S22 in the second series of transition symbols 138, and so on.

[0028] Subsequently, the internal code decoder 140 can perform secondary ECC on the transition symbols 134 to generate the internal code 144. In one implementation, the internal code 144 may include a code-1 parity check 146 generated from a first series of transition symbols 136 and a code-2 parity check 148 generated from a second series of transition symbols 138 and metadata 126 stored in memory. Specifically, the code-1 parity check 146 includes five 4-bit parity checks P11, P21, P31, P41, and P51 generated from ten 4-bit transition symbols. In one implementation, the internal decoder 140 may use a Reed-Solomon (RS) decoder to generate the code-1 parity check 146 and the code-2 parity check 148.

[0029] In one implementation, the code 2 parity check 148 is generated by an RS (15, 11) encoder, which takes 11 symbols, including ten 4-bit second series transition symbols 138 and 4-bit metadata 126, as input, and outputs 15 symbols, including four (4) code 2 parity checks (each 4 bits). Therefore, the code 2 parity check 148 has 16 bits.

[0030] Similarly, code 1 parity 146 is generated by an RS(15,10) encoder, which takes 10 symbols, including 10 four-bit first series transition symbols from 4-bit first series transition symbols 138, as input and outputs five (5) code 1 parity codes, each 4 bits. Therefore, code 1 parity 146 has 20 bits. Since code 1 parity 146 is generated from 10 transition symbols and it has five (5) 4-bit codes, it is a stronger internal code parity check than code 2 parity 148, which uses 10 transition symbols and metadata to generate four (4) 4-bit codes.

[0031] Subsequently, five (5) 4-bit parity 1 and four (4) 4-bit parity 2 are stored in nine (9) 4-bit parity memory spaces 124 on the DDR 120 (therefore, a total of nine (9) 4-bit parity 144). In one implementation, five (5) 4-bit parity 1 (P11, P21, P31, P41, P51) and four (4) 4-bit parity 2 (P12, P22, P32, P42) are alternatively stored in the parity memory space 124. Thus, the parity memory space 124 can store parity 144 P11, P12, P21, P22, P31, P32, P41, P42, and P51.

[0032] In the illustrated implementation, transition symbol 134 is not directly used to correct errors that may occur in the data stored in DDR 120. When host computing system 102 reads data from DDR 120, host computing system 102 can reconstruct them. Given that code 1 parity 146 is stronger, code 1 parity can be decoded first, and then code 2 parity 148 can be erased and decoded.

[0033] Because the implementation shown in the diagram uses metadata bit 126 when generating the parity bit of code 2, the host computing system 102 does not need to store metadata, and the host computing system 102 can still recover data if the entire die is damaged (also known as a chip damage case of data corruption).

[0034] Figure 2 The illustration shows details regarding the transition symbols and parity bits generated by the ECC management system disclosed herein. Specifically, Figure 2 The diagram illustrates an implementation of DDR 200 with 10 dies 222, each die having 64 data bits and four parity bits 224 and / or four metadata bits 226. Specifically, the first nine dies have four parity bits, and the tenth die has four bits for metadata.

[0035] An ECC manager implemented on a computing device can generate a first series of transition symbols 236 and a second series of transition symbols 238 based on 64 bits of data stored in die 222. The first series of transition symbols 238 may include S11, S21, ... S101, each with four bits. Conversely, the second series of transition symbols 236 may include S12, S22, ... S102, each with four bits and four metadata bits. Each transition symbol in the first series of transition symbols 236 and the second series of transition symbols 238 can be generated using a CRC-8 or SECDED encoder.

[0036] Furthermore, the ECC manager generates code 1 parity bit 246 from the first series of transition symbols 236 and code 2 parity bit 248 from the second series of transition symbols 238 and metadata bits. As shown herein, code 1 parity bit 246 comprises five 4-bit codes P11, P21, P31, P41, and P51. Code 2 parity bit 248 comprises four 4-bit codes P12, P22, P32, and P42. In the implementation disclosed herein, code 1 parity bits P11, P21, P31, P41, and P51, and code 2 parity bits P12, P22, P32, and P42 are stored at parity storage location 224 on DDR 200. Therefore, 36 of the 40 parity bit storage locations are used to store the parity bits generated by the ECC manager, and 4 bits are used to store metadata.

[0037] During the operation of reading data from a given die 222a of DDR 200, the data from die 222a is used to generate transition symbols S11 and S12 using CRC-8. If there is no error on die 222a, the transition symbols S11 and S12 will be the same when the internal code is encoded. If there is no error on any die 222, all transition symbols 236 and 238 will be the same as during the encoding of the internal code, and therefore code 1 parity check 246 and code 2 parity check 248 will also be the same. However, if there is an error on die 222a, S11 and S12 will be different from the values ​​they generated during the encoding of the internal code. In this case, because code 1 parity check 246 can detect up to three errors on the first series of transition symbols 236, it can detect that S11 has an error, which indicates an error on die 222a. Information about the location of the error (i.e., which die has the error) can be passed to the ECC manager used by the host. In this situation, the host can use erase decoding to correct the error on die 222a.

[0038] When the host knows the location of the error, i.e., the die on which the error may have occurred, it can more effectively correct the error and recover data from that die. Therefore, the technique disclosed herein provides a technical benefit to the host by making its erase decoding operation more efficient. For example, when the ECC decoder at the host knows the location of the error, it can correct errors on up to two of the ten dies 222. As a result, the probability of miscorrection by the host ECC decoder is also eliminated as long as only two dies of 222 contain errors, except when each of the two dies has an error in every bit of its data bits and parity bits.

[0039] Figure 3The illustration shows an example operation 300 of decoding data from DDR using transition symbols and internal codes. Specifically, operation 302 begins by decoding internal code 1, such as... Figure 2 The disclosed implementation uses code 1 parity check 246. The disclosed implementation begins with decoding internal code 1 because internal code 1 is stronger than internal code 2 (such as code 2 parity check 248) and has a higher correction capability. Operation 304 determines whether code 1 is decodeable. If so, the information generated during the decoding of internal code 1 parity check is passed to the erasure decoding of internal code 2 parity check, and operation 306 performs erasure decoding on code 2 parity check. Subsequently, operation 308 passes the error location to the host decoder, such as an RS decoder, also known as an external RS encoder.

[0040] If operation 304 determines that code 1 is undecodeable, then operation 310 decodes code 2 parity. Specifically, when there are three errors in the first series of transition symbols 236, the second series of transition symbols 238 has at most two errors (such as die failure and a single error on a different die). Therefore, the second series of transition symbols 238 can be decoded directly from code 2 parity. Subsequently, the output of the decoding operation at 310 is passed to the erase decoding, and at operation 312 it is used to perform erase decoding on code 1 parity. Subsequently, at operation 314, the error location information generated by the erase decoding operation 312 is transmitted to a host decoder such as an RS decoder.

[0041] Figure 4 A sample block diagram 400 is illustrated, showing the flow of data and parity bits between the data storage die and the ECC management system using the parity bits stored on the die. Specifically, block diagram 400 illustrates that 64 bytes of cache line data 416 are input to an external RS encoder 402 to generate a 16-byte parity bit 418, which is then input to a transition symbol generator 404. The transition symbol generator 404 generates a transition symbol 420 for each die. In one implementation, the transition symbol generator 404 may use CRC encoding to generate the transition symbol 420. The transition symbol 420 and metadata 422 are input to an internal code encoder 406 that generates an internal code parity 424, and the internal code parity 424 and metadata 422 are written back to the ECC bit 408 on the DDR die.

[0042] During the decoding operation, 64 bytes of cache line data 426 from the DDR is read into the external RS encoder 414. Parity bits 428 from the two dies on the DDR are also input along with the 64 bytes of cache line data 426 to the transition symbol regenerator 410 to generate a transition symbol 432. The transition symbol 432, along with internal code + metadata 434, is input to the internal code decoder 412 to generate erase information 436. This erase information 436 can provide the location of the die on which an error may have occurred. For example, the erase information 436 can provide that die x and / or y on the DDR has erroneous data. The external RS encoder 414 uses the erase information 436, the 64 bytes of cache line data 426, and the parity bits 428 to regenerate the corrected 64 bytes of user data. The internal code decoder 412 also decodes the metadata 436 transmitted to the host.

[0043] Figure 5 The illustration depicts a scenario 500 where the DDR 520 has an error in the first die 522 and an error in the second die 524. Specifically, in this example, each die 522 and 524 has an error in the main data portion of the die, but no errors in the parity portions P11 and P12. In this case, operation 502 first begins decoding the code 1 parity (C1). Operation 504 determines whether C1 is decodeable. In this case, given the two errors in the data portions of dies 522 and 524, there will be two errors on the first series transition symbol 532, namely S01 and S11. Similarly, there are two errors on the second series transition symbol 534, namely S02 and S12.

[0044] Code 1 can correct up to two errors, therefore, control is transferred from operation 504 to operation 506, which performs erase decoding on code 2 (C2) because it has fewer than three errors. As a result, operation 506 is able to decode code 2, and operation 508 passes the erase information (in this case, the location of the error on the data portions of dies 522 and 524) to an external decoder.

[0045] Figure 6 The illustration depicts a scenario 600 where the DDR 620 has errors in the data portion of the first die 622, errors in the data portion of the second die 624, and an error in the parity bit P12 on the second die 624. In this case, the first series transition symbol 632 has two errors in symbols S01 and S11 that can be corrected. However, the second series transition symbol 634 cannot be corrected because it has three errors. However, because the errors in the first series transition symbol 632 can be corrected, it can provide the location of the errors.

[0046] In this scenario, operation 602 first begins decoding code 1 (C1). Operation 604 determines whether C1 is decodeable. Code 1 can correct up to two errors, therefore, control is transferred from operation 604 to operation 606, which performs erasure decoding on code 2 (C2) because it has fewer than three errors and their locations are known (i.e., S02, S12, and P12). As a result, operation 606 is able to decode code 2, and operation 608 passes erasure information to an external decoder, in this case, the erasure information being the locations of errors on the data portions of dies 622 and 624 and the parity portion of die 624.

[0047] Figure 7 The illustration shows case 700, where the DDR 720 has an error in the parity section P11 of the first die 722, an error in the data section of the second die 724, and an error in the parity section P12 of the second die 724. In this case, the first series transition symbol 732 has an error in S11, and the second series transition symbol 734 has an error in S12.

[0048] In this scenario, operation 702 first begins decoding code 1 parity check (C1). Operation 704 determines whether C1 is decodeable. Code 1 can correct up to two errors, and in this case, there is only one error in S11 of the first series of transition symbols 732 and one error in parity check P11, therefore 704 can correct code 1. Control is transferred from operation 704 to operation 706. Operation 706 is able to perform erasure decoding on code 2 because it has only two errors, namely the errors in S11 and P12. As a result, operation 706 is able to decode code 2, and operation 708 passes the erasure information (in this case, the location of the error) to an external decoder.

[0049] Figure 8 The diagram illustrates scenario 800, where the DDR 820 has an error in the parity section P11 of the first die 822, an error in the data section of the second die 824, and an error in the parity section P12 of the second die 824. In this case, the first series transition symbol 832 has an error in S11, and the second series transition symbol 834 has an error in S12.

[0050] Operation 802 first begins decoding code 1 parity check (C1). Operation 804 determines whether C1 is decodeable. Code 1 can correct up to two errors, and in this case, there is one error in S11 of the first series of transition symbols 832 and one error in parity check P11, so 804 can correct code 1. Control is transferred from operation 804 to operation 806. Operation 806 can perform erase decoding on code 2 because it has only two errors, namely errors in S12 and P12. As a result, operation 806 can decode code 2, and operation 808 passes the erase information (in this case, the location of the error) to the external decoder. Specifically, only the data portion of die 824 is transmitted to the external decoder as erase information.

[0051] Figure 9 The illustration shows a scenario 900 where the DDR 920 has an error in the parity section P22 of die 922, an error in the data section of die 924, and an error in the parity section P12 of die 924. In this case, there is only one error in code 1 parity check, namely S11, and three errors in code 2 parity check, namely S12, P12, and P22.

[0052] Operation 902 first begins decoding code 1 parity check (C1). Operation 904 determines whether C1 is decodeable. Code 1 can correct up to two errors, and in this case, there is an error in S11 of the first series of transition symbols 832, so 904 can correct code 1. Control is transferred from operation 904 to operation 906. Operation 906 can perform erasure decoding on code 2 because it has three errors, namely errors in S12, P12, and P22, but the locations of these two errors are known. As a result, operation 906 can decode code 2, and operation 808 passes the erasure information (in this case, the location of the errors) to an external decoder.

[0053] Figure 10 The illustration depicts case 1000 where the DDR 1020 has errors in the data section of die 1022, errors in the data section of die 1024, and errors in the parity check section P21 on die 1024. In this case, there are three errors in code 1 parity check, namely S01, S21, and P21, and two errors in code 2 parity check, namely S02 and S22.

[0054] Operation 1002 first begins decoding code 1 parity (C1). Operation 1004 determines whether C1 is decodeable. Code 1 can correct up to two errors, and in this case, there are three code 1 errors: S01, S21, and P21. Therefore, control is transferred to operation 1010 to determine code 2 parity. Operation 1010 is able to decode code 2 because it has only two errors, and it determines the location of the errors on dies 1022 and 1024. This information is passed to operation 1012, which, if it knows the locations, can erase and decode up to five parity checks. In this case, it knows the errors are in one of S01, S21, P11, and P21. Therefore, operation 1012 is able to decode code 1, and in operation 1014, the locations of the errors in dies 1022 and 1024 are passed to an external decoder.

[0055] Figure 11 The illustration shows a scenario 1100 in which the DDR 1120 has an error in the parity section P11 of die 1122, an error in the data section of die 1124, and an error in the parity section P21 of die 1124. In this case, there are three errors in the parity bit 1, namely P11, S21, and P21, while there is only one error in the parity bit 2, namely S22.

[0056] Operation 1102 first begins decoding code 1 parity (C1). Operation 1104 determines whether C1 is decodeable. Code 1 can correct up to two errors, and in this case, there are three code 1 errors: P11, S21, and P21. Therefore, control is transferred to operation 1110 to determine code 2 parity. Operation 1110 is able to decode code 2 because it has only one error, and it determines the location of the error on dies 1122 and 1124. This information is passed to operation 1112, which, if it knows the location, can erase and decode up to five parity checks. Therefore, operation 1112 is able to decode code 1, and at operation 1114, the location of the error in dies 1122 and 1124 is passed to an external decoder.

[0057] Figure 12 The illustration shows case 1200 where the DDR 1220 has errors in the parity section P22 of die 1224, errors in the data section of die 1222, and errors in the parity section P21 of die 1222. In this case, there are two errors in code 1 parity check, namely P21 and S21, and two errors in code 2 parity check, namely S22 and P22.

[0058] Operation 1202 first begins decoding code 1 parity (C1). Operation 1204 determines whether C1 is decodeable. Code 1 can correct up to two errors, and in this case, there are two code 1 errors, P21 and S21. Therefore, control is transferred to operation 1206 to determine code 2 parity. Operation 1206 is able to decode code 2 because it has only two errors and knows the location of S22, determining the location of the errors on dies 1222 and 1224. Therefore, operation 1206 is able to decode code 2, and at operation 1208, the location of the errors in dies 1222 and 1224 is passed to an external decoder.

[0059] The techniques disclosed herein allow for the correction of DDR die errors with a higher probability when more than one error exists on a single die. Specifically, there is a probability of a die having multiple single bit (SB) errors when multiple single errors exist in a cache line or data portion of the DDR. Previous techniques (such as Single Die Correction (SEC)) fail if more than one error exists on the die, compared to the techniques disclosed herein. Specifically, using the disclosed techniques, the correction power (through erase decoding) is twice that of correcting symbols without such information because the host decoder has information about the error location. Furthermore, the increased correction power of external ECC due to the ability to use erase decoding allows the techniques disclosed herein to store additional metadata bits without sacrificing the required data protection.

[0060] Figure 13 The illustration shows an alternative implementation 1300 of the disclosed technology, in which the DDR 1320 has a 5×8 configuration with five dies, each having 128 bits of data and 8 bits of parity P1 to P5. In this implementation, the CRC encoder generates transition symbols 1330, which includes five 8-bit transition symbols S1 to S5. The transition symbols 1330 and 8 bits of metadata (MB) are used to generate the internal code parity 1340, which includes five internal code parity P1 to P5 that can be stored at parity bit position 1324 in the DDR 1320.

[0061] The decoding operation first decodes internal code 1340 to determine the location of the error and informs the host decoder of which dies have the error. The host decoder can use this information to perform erase decoding more efficiently. This implementation allows for the correction of full-die faults where both data bit 1322 and parity bit 1324 of a single die in a DDR 1320 are faulty.

[0062] Figure 14The illustration shows an alternative implementation 1400 of the disclosed technology, where the DDR 1420 has a 9×4 configuration with nine dies, each with 64 bits of data and 4 bits of parity. In this case, eight of the nine dies are used for data, while the ninth die is used for parity information. Since only one die is used for parity information, the host has less information available for error correction.

[0063] In the implementation described in this paper, the CRC encoder generates transition symbol 1430, which includes a first series of transition symbols 1432 and a second series of transition symbols 1434. Transition symbol 1430 and 4 bits of metadata (MB) are used to generate internal code parity check 1440, which includes four (4) code-1 parity checks 1442 and four (4) code-2 parity checks 1444. As a result, code-1 parity check 1442 and code-2 parity check 1444 have the same decoding power.

[0064] Figure 15 The diagram can be used to implement the example system 1500 for ECC management disclosed herein. It is used to implement the described techniques. Figure 15 Example hardware and operating environments include computing devices such as computers 20, mobile phones, personal digital assistants (PDAs), tablet computers, smartwatches, game controllers, or other general-purpose computing devices. For example, in Figure 15 In some implementations, for example, computer 20 includes a processing unit 21, system memory 22, and a system bus 23 that operatively couples various system components, including the system memory 22, to the processing unit 21. There may be only one processing unit 21 or more processing units 21, such that the processor of computer 20 includes a single central processing unit (CPU) or multiple processing units, commonly referred to as a parallel processing environment. Computer 20 may be a conventional computer, a distributed computer, or any other type of computer; these implementations are not limited to these.

[0065] In an example implementation of computing system 1500, computer 20 also includes the ECC management system 1510 disclosed herein.

[0066] System bus 23 can be any type of bus architecture among several types of bus architectures, including memory bus or memory controller, peripheral bus, switching architecture, point-to-point connection, and local bus using any bus architecture of various bus architectures. System memory can also be simply referred to as memory and includes read-only memory (ROM) 24 and random access memory (RAM). Basic input / output system (BIOS) 26 is stored in ROM 24 and contains basic routines such as those that help transfer information between components within computer 20 during startup. Computer 20 also includes hard disk drive 27 for reading from or writing to a hard disk (not shown), disk drive 28 for reading from or writing to a removable disk 29, and optical disk drive 30 for reading from or writing to a removable optical disk 31 such as a CD ROM, DVD, or other optical media.

[0067] In one implementation, one or more instructions for interpreting the signal output generated by the ECC management system 1510 may be stored in the memory of the computer 20, such as read-only memory (ROM) 24 and random access memory (RAM) 25.

[0068] Hard disk drive 27, disk drive 28, and optical disk drive 30 are connected to system bus 23 via hard disk drive interface 32, disk drive interface 33, and optical disk drive interface 34, respectively. The drives and their associated tangible computer-readable media provide non-volatile storage of computer-readable instructions, data structures, program modules, and other data to computer 20. Those skilled in the art will understand that any type of tangible computer-readable media can be used in the example operating environment.

[0069] Multiple program modules can be stored on a hard disk, disk 29, optical disk 31, ROM 24, or RAM 25. These program modules include an operating system 35, one or more applications 36, other program modules 37, and program data 38. Users can generate prompts on the personal computer 20 using input devices such as a keyboard 40 and a pointing device 42. Other input devices (not shown) may include a microphone (e.g., for voice input), a camera (e.g., for a Natural User Interface (NUI)), a joystick, a game controller, a satellite dish, a scanner, etc. These and other input devices are typically connected to the processing unit 21 via a serial port interface 46 coupled to the system bus 23, but may also be connected via other interfaces such as a parallel port, a game port, or a Universal Serial Bus (USB). A monitor 47 or other type of display device is also connected to the system bus 23 via an interface such as a video adapter 48. In addition to the monitor, the computer typically includes other peripheral output devices (not shown), such as speakers and printers.

[0070] Computer 20 can operate in a networked environment using logical connections to one or more remote computers, such as remote computer 49. These logical connections are implemented through communication devices coupled to or part of computer 20; these implementations are not limited to a particular type of communication device. Remote computer 49 can be another computer, server, router, network PC, client, peer device, or other public network node, and typically includes many or all of the elements described above with respect to computer 20. Figure 12 The described logical connections include Local Area Networks (LAN) 51 and Wide Area Networks (WAN) 52. This type of network environment is common in office networks, enterprise-wide computer networks, intranets, and the Internet, all of which are various types of networks.

[0071] When used in a LAN network environment, computer 20 connects to local area network 51 via a network interface or adapter 53, which is a type of communication device. When used in a WAN network environment, computer 20 typically includes a modem 54, a network adapter, a communication device, or any other type of communication device for establishing communication over wide area network 52. Modem 54 can be internal or external and is connected to system bus 23 via serial port interface 46. In a networked environment, the program engine or a portion thereof depicted relative to personal computer 20 may be stored in a remote memory storage device. It should be understood that the network connections shown are examples, and other means of communication devices for establishing communication links between computers can be used.

[0072] In the example implementation, software or firmware instructions for the ECC management system 1510 may be stored in system memory 22 and / or storage device 29 or 31 and processed by processing unit 21. The ECC management system 1510 and the data used by it may be stored in system memory 22 and / or storage device 29 or 31 as persistent data storage.

[0073] Compared to tangible computer-readable storage media, intangible computer-readable communication signals can embody computer-readable instructions, data structures, program modules, or other data residing in modulated data signals such as carrier waves or other signal transmission mechanisms. The term "modulated data signal" refers to a signal whose characteristics are set or altered in a manner that encodes information within the signal. By way of example and not limitation, intangible communication signals include wired media such as wired networks or direct-wire connections, and wireless media such as acoustic, RF, infrared, and other wireless media.

[0074] Some implementations of an ECC management system may include artifacts. Artifacts may include tangible storage media for storing logic. Examples of storage media may include one or more types of computer-readable storage media capable of storing electronic data, including volatile or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or rewritable memory, etc. Examples of logic may include various software elements, such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application programming interfaces (APIs), instruction sets, computational code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. In one implementation, for example, the artifact may store executable computer program instructions that, when executed by a computer, cause the computer to perform methods and / or operations according to the described implementation. Executable computer program instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, etc. Executable computer program instructions can be implemented according to predefined computer languages, methods, or syntaxes to instruct a computer to perform specific functions. These instructions can be implemented using any appropriate high-level, low-level, object-oriented, visual, compiled, and / or interpreted programming languages.

[0075] The ECC management sensing system disclosed herein may include various tangible computer-readable storage media and intangible computer-readable communication signals. Tangible computer-readable storage devices may be embodied by any available medium accessible by the ECC management system disclosed herein, and include both volatile and non-volatile storage media, removable and non-removable storage media. Tangible computer-readable storage media do not include intangible and transient communication signals, and include volatile and non-volatile, removable and non-removable storage media implemented using any method or technique for storing information such as computer-readable instructions, data structures, program modules, or other data. Tangible computer-readable storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CDROM, digital versatile disc (DVD) or other optical disc storage devices, magnetic tape cassettes, magnetic tape, disk storage devices or other magnetic storage devices, or any other tangible medium that can be used to store desired information and is accessible by the ECC management system disclosed herein. In contrast to tangible computer-readable storage media, intangible computer-readable communication signals may embody computer-readable instructions, data structures, program modules, or other data residing in modulated data signals such as carrier waves or other signal transmission mechanisms. The term "modulated data signal" refers to a signal whose characteristics are set or altered in a manner that encodes information in the signal. By way of example and not limitation, intangible communication signals include signals that move through wired media such as wired networks or direct-line connections, as well as signals that move through wireless media such as acoustic, RF, infrared, and other wireless media.

[0076] The described technique provides a multi-level error correction method comprising: encoding data received from a dual data rate (DDR) memory to generate a transition symbol by performing primary encoding, wherein the primary encoding includes at least one of cyclic redundancy check (CRC) encoding and single error correction double error detection (SECDED) encoding; performing secondary encoding on the transition symbol to generate an inner code, the inner code including code 1 parity check generated from the transition symbol and code 2 parity check generated from the transition symbol and metadata stored on the DDR memory, wherein the secondary encoding includes Reed-Solomon (RS) encoding; and storing the inner code at a parity bit storage location on the DDR memory die.

[0077] Alternatively, the computing system disclosed herein includes a memory, one or more processor units, and an error correction code (ECC) management system stored in the memory and executable by the one or more processor units. The ECC management system encodes computer-executable instructions on the memory for execution on the one or more processor units of a computer process for multi-level error correction. The computer process includes encoding data received from a dual data rate (DDR) memory to generate transition symbols by performing primary encoding, wherein the primary encoding includes at least one of cyclic redundancy check (CRC) encoding and single error correction double error detection (SECDED) encoding; and performing secondary encoding on the transition symbols to generate an inner code. The inner code includes a code-1 parity check generated from the transition symbols and a code-2 parity check generated from the transition symbols and metadata stored on the DDR memory, wherein the secondary encoding includes Reed-Solomon (RS) encoding, and storing the inner code at a parity bit storage location on the DDR memory die.

[0078] In another implementation, a physical article of art includes one or more tangible computer-readable storage devices that encode computer-executable instructions for performing a computer process for multi-level error correction on a computer system. The computer process includes encoding data received from a dual data rate (DDR) memory to generate transition symbols by performing primary encoding, wherein the primary encoding includes at least one of cyclic redundancy check (CRC) encoding and single error correction double error detection (SECDED) encoding; performing secondary encoding on the transition symbols to generate an inner code, the inner code including code 1 parity generated from the transition symbols and code 2 parity generated from the transition symbols and metadata stored on the DDR memory, wherein the secondary encoding includes Reed-Solomon (RS) encoding; and storing the inner code at a parity bit storage location on the die of the DDR memory.

[0079] The implementations described herein are implemented as logical steps in one or more computer systems. Logical operations can be implemented as (1) a sequence of processor-implemented steps executed in one or more computer systems, and (2) interconnected machine or circuit modules within one or more computer systems. The implementation is a matter of choice, depending on the performance requirements of the computer system utilized. Therefore, the logical operations constituting the implementations described herein are referred to differently as operations, steps, objects, or modules. Furthermore, it should be understood that logical operations can be performed in any order unless otherwise expressly stated or the language of the claims inherently requires a specific order. The foregoing specification, examples, and data, together with the appendix, provide a complete description of the structure and use of exemplary implementations.

[0080] As used herein, the terms “component,” “system,” “interface,” etc., are intended to refer to computer-related entities, including hardware, software (e.g., in execution), and / or firmware. For example, a component can be a process running on a processor, a processor, an object, an executable program, a program, and / or a computer. For illustration, both an application running on a server and the server itself can be components. One or more components may reside within a process, and components may reside on a single computer and / or be distributed across two or more computers.

[0081] The claimed subject matter is described with reference to the accompanying drawings, wherein the same reference numerals are consistently used to refer to the same elements. In the following description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of the invention. However, it will be apparent that the claimed subject matter can be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form to aid in the description of the invention.

Claims

1. A multi-level error correction method, comprising: Data received from a dual data rate (DDR) memory is encoded by performing primary encoding to generate transition symbols, wherein the primary encoding includes at least one of cyclic redundancy check (CRC) encoding and single error corrected double error detection (SECDED) encoding; Secondary encoding is performed on the transition symbols to generate internal codes, the internal codes comprising: Code 1 parity check generated from the transition symbol and code 2 parity check generated from the transition symbol and metadata stored in the DDR memory, wherein the secondary coding includes Reed-Solomon (RS) coding; as well as The internal code is stored in the parity bit storage location on the die of the DDR memory.

2. The method of claim 1, wherein the transition symbols comprise a first series of transition symbols and a second series of transition symbols, and wherein performing the secondary encoding further comprises: Perform the Reed-Solomon (RS) encoding on the parity check of the first series of transition symbols to generate the Code 1 parity check; as well as The RS encoding is performed on the second series of transition symbols and the metadata to generate the Code 2 parity check.

3. The method of claim 1, wherein performing primary encoding to generate transition symbols further comprises: Perform a cyclic redundancy check (CRC) on the data.

4. The method of claim 1, wherein performing primary encoding to generate transition symbols further comprises: Perform single error correction double error detection (SECDED) on the data.

5. The method of claim 1, wherein for the memory comprising ten (10) dies, the code 1 parity check comprises twenty (20) bits and wherein the code 2 parity check comprises sixteen (16) bits.

6. The method according to claim 1, further comprising: The data is recovered from the memory using an erase decoder, which uses code 1 parity and code 2 parity.

7. The method according to claim 6, further comprising: The code 1 parity check is used to recover data from the memory before the code 2 parity check.

8. The method of claim 1, wherein the memory comprises nine (9) dies, the code 1 parity check comprises sixteen (16) bits, and wherein the code 2 parity check comprises sixteen (16) bits.

9. The method of claim 1, wherein the memory comprises five (5) bits and the code 1 parity check comprises twenty (20) bits.

10. The method according to claim 1, further comprising: Decode the code 1 parity check and the code 2 parity check to generate information about the location of a single bit error on the memory.

11. The method of claim 1, wherein the transition symbol is not stored on the DDR.

12. The method according to claim 1, wherein storing the internal code in the parity bit storage location on the die of the DDR memory further comprises: The host is allowed to use the parity bit storage space at the host for other data storage.

13. A computing system, comprising: Memory; One or more processing units; as well as An error correction code (ECC) management system stored in the memory and executable by the one or more processor units, the ECC management system encoding computer-executable instructions on the memory for executing computer processes for multi-level error correction on the one or more processor units, the computer processes including: Data received from dual data rate (DDR) memory is encoded by performing primary encoding to generate transition symbols; Secondary encoding is performed on the transition symbols to generate an internal code, the internal code comprising: code 1 parity check generated from the first series of transition symbols and code 2 parity check generated from the second series of transition symbols and metadata stored in the DDR memory, wherein the secondary encoding comprises Reed-Solomon (RS) encoding; and The internal code is stored in the parity bit storage location on the die of the dual data rate (DDR) memory.

14. The computing system of claim 11, wherein the transition symbols comprise a first series of transition symbols and a second series of transition symbols, and wherein performing the secondary encoding further comprises: Reed-Solomon (RS) encoding is performed on the first series of transition symbols to generate the code 1 parity check; as well as RS encoding is performed on the second series of transition symbols and the metadata to generate the code 2 parity check.

15. The computing system of claim 11, wherein performing primary encoding to generate transition symbols further comprises: Perform a cyclic redundancy check (CRC) on the data.

16. The computing system of claim 11, wherein performing primary encoding to generate transition symbols further comprises: Perform single error correction double error detection (SECDED) on the data.

17. The computing system of claim 11, wherein the memory comprises ten (10) dies, the code 1 parity check comprises twenty (20) bits, and wherein the code 2 parity check comprises 16 bits.

18. A physical article comprising one or more tangible computer-readable storage devices, said one or more tangible computer-readable storage devices encoding computer-executable instructions for performing a computational process for multi-level error correction codes on a computing system, said computational process comprising: Data received from a dual data rate (DDR) memory is encoded by performing primary encoding to generate transition symbols, wherein the primary encoding includes at least one of cyclic redundancy check (CRC) encoding and single error correction double error detection (SECDED) encoding; Secondary encoding is performed on the transition symbols to generate an inner code, the inner code including: code 1 parity check generated from the first series of transition symbols and code 2 parity check generated from the second series of transition symbols and metadata stored on the DDR memory, wherein the secondary encoding includes Reed-Solomon (RS) encoding. as well as The internal code is stored in the parity bit storage location on the die of the DDR memory.

19. The physical article of claim 18, wherein the transition symbols comprise a first series of transition symbols and a second series of transition symbols, and wherein performing the secondary encoding further comprises: Perform Reed-Solomon (RS) encoding on the parity check of the first series of transition symbols to generate the code 1 parity check; as well as RS encoding is performed on the second series of transition symbols and the metadata to generate the code 2 parity check.

20. The physical article of claim 18, wherein performing primary coding to generate transition symbols further comprises: Perform a cyclic redundancy check (CRC) on the data.

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