Memory device including non-integer average number of memory opening fill structures per column

Abstract

A memory device includes: an alternating stack of insulating layers and conductive layers extending along a first horizontal direction, in which the conductive layers include word lines and drain-side select gate electrodes overlying the word lines; and a memory opening fill structure extending vertically through the alternating stack. Each of the memory opening filling structures includes a vertical stack of memory elements and a vertical semiconductor channel. The memory opening filling structures are arranged in columns extending in a second horizontal direction perpendicular to the first horizontal direction. An average number of memory opening fill structures per column extending through each of the drain-side select gate electrodes is a non-integer greater than zero.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit and priority of U.S. Nonprovisional Patent Application Serial No. 18 / 602,790, filed on March 12, 2024. Technical Field

[0003] This disclosure relates generally to the field of semiconductor devices, and more particularly to a memory device and a method of forming the same, wherein each column contains a non-integer average number of memory openings. Background Technology

[0004] A three-dimensional vertical NAND string with one bit per cell was disclosed in an article by T. Endoh et al. entitled “Novel Ultra High Density Memory With AStacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM Proceedings (2001), pp. 33-36. Summary of the Invention

[0005] According to one aspect of this disclosure, a memory device includes: an alternating stack of insulating and conductive layers extending along a first horizontal direction, wherein the conductive layers include word lines and drain-side selected gate electrodes overlying the word lines; and memory aperture-filling structures extending vertically through the alternating stack. Each memory aperture-filling structure includes a vertical stack of memory elements and a vertical semiconductor channel. The memory aperture-filling structures are arranged in columns extending in a second horizontal direction perpendicular to the first horizontal direction. The average number of each column of memory aperture-filling structures extending through each drain-side selected gate electrode is a non-integer number greater than zero.

[0006] According to another aspect of this disclosure, a memory device includes: an alternating stack of insulating and conductive layers, wherein the alternating stack is located between a first lateral isolation trench fill structure and a second lateral isolation trench fill structure, the first and second lateral isolation trench fill structures extending laterally along a first horizontal direction and laterally spaced apart from each other along a second horizontal direction, wherein the conductive layer includes word lines extending laterally from the first and second lateral isolation trench fill structures continuously to the second lateral isolation trench fill structure, and further includes drain-side selected gate electrodes overlying the word lines, wherein each of the drain-side selected gate electrodes includes a corresponding plurality of drain-side selected gate electrodes, the corresponding plurality of drain-side selected gate electrodes being laterally spaced apart from each other along the second horizontal direction by at least one drain-select level dielectric isolation structure extending generally along the first horizontal direction; A memory opening, the memory opening extending vertically through the alternating stack and arranged in multiple rows such that each of the multiple rows is arranged along the first horizontal direction and adjacent rows of the multiple rows are laterally spaced from each other along the second horizontal direction; and a memory opening filling structure located in the memory opening, wherein each set of memory opening filling structures extending vertically between a corresponding adjacent pair of isolation structures selected from the first lateral isolation trench filling structure, the second lateral isolation trench filling structure and the at least one drain selection level dielectric isolation structure defines a memory string group, and each memory string group includes all memory opening filling structures within a corresponding set of each row of memory opening filling structures, and includes a non-zero fraction of memory opening filling structures within a corresponding additional row of memory opening filling structures, the non-zero fraction being smaller than the total number of memory opening filling structures within the corresponding additional row. Attached Figure Description

[0007] Figure 1 This is a schematic vertical cross-sectional view of an exemplary structure following an alternating stack of insulating and sacrificial material layers formed over a carrier substrate, according to an embodiment of the present disclosure.

[0008] Figure 2 This is a schematic vertical cross-sectional view of an exemplary structure after the formation of a stepped surface and a stepped dielectric material portion, according to an embodiment of the present disclosure.

[0009] Figure 3A This is a schematic vertical cross-sectional view of an exemplary structure after the formation of the memory opening and the support opening, according to an embodiment of the present disclosure.

[0010] Figure 3B yes Figure 3A A top view of an exemplary structure. The hinged vertical cross-sectional plane A-A' is Figure 3A A cross-sectional view of the vertical cross section.

[0011] Figures 3C to 3G Is Figure 3A and Figure 3B A top view of an alternative configuration of the exemplary structure at the processing steps.

[0012] Figure 4 This is a schematic vertical cross-sectional view of an exemplary structure after the formation of the sacrificial opening fill structure according to an embodiment of the present disclosure.

[0013] Figure 5 This is a vertical cross-sectional view of an exemplary structure after the formation of the support column structure, according to an embodiment of the present disclosure.

[0014] Figure 6 This is a schematic vertical cross-sectional view of an exemplary structure after removing the sacrificial memory opening fill structure according to an embodiment of the present disclosure.

[0015] Figures 7A to 7F It is a vertical cross-sectional view of the memory opening sequence during the formation of the memory opening filling structure according to an embodiment of the present disclosure.

[0016] Figure 8A This is a schematic vertical cross-sectional view of an exemplary structure after the formation of the memory opening filling structure according to an embodiment of the present disclosure.

[0017] Figure 8B yes Figure 8A A top view of an exemplary structure. Vertical plane AA is... Figure 8A A cross-sectional view of the vertical cross section.

[0018] Figure 9A This is a vertical cross-sectional view of an exemplary structure after the formation of a lateral isolation trench, according to an embodiment of the present disclosure.

[0019] Figure 9B yes Figure 9A A top view of an exemplary structure. Vertical plane AA is... Figure 9A A cross-sectional view of the vertical cross section.

[0020] Figure 10 This is a vertical cross-sectional view of an exemplary structure after the formation of the lateral extension cavity, according to an embodiment of the present disclosure.

[0021] Figure 11 This is a schematic vertical cross-sectional view of an exemplary structure after the formation of a conductive layer, according to an embodiment of the present disclosure.

[0022] Figure 12AThis is a vertical cross-sectional view of an exemplary structure after forming a lateral isolation trench filling structure and a drain selection dielectric isolation structure according to an embodiment of the present disclosure.

[0023] Figure 12B yes Figure 12A A top view of an exemplary structure. Vertical plane AA is... Figure 12A A cross-sectional view of the vertical cross section.

[0024] Figures 12C to 12G Is Figure 12A and Figure 12B A top view of an alternative configuration of the exemplary structure at the processing steps.

[0025] Figure 13A This is a vertical cross-sectional view of an exemplary structure following the formation of a layer contact via structure and a drain contact via structure according to an embodiment of this disclosure.

[0026] Figure 13B yes Figure 13A A top view of an exemplary structure. Vertical plane AA is... Figure 13A A cross-sectional view of the vertical cross section.

[0027] Figures 13C to 13G Is Figure 13A and Figure 13B A top view of an alternative configuration of the exemplary structure at the processing steps.

[0028] Figure 14A This is a vertical cross-sectional view of an exemplary structure after the formation of the connecting via structure and bit line according to an embodiment of the present disclosure.

[0029] Figure 14B yes Figure 14A A top view of an exemplary structure. Vertical plane AA is... Figure 14A A cross-sectional view of the vertical cross section.

[0030] Figures 14C to 14G Is Figure 14A and Figure 14B A top view of an alternative configuration of the exemplary structure at the processing steps.

[0031] Figure 15 This is a vertical cross-sectional view of an exemplary structure after the formation of a memory die, according to an embodiment of the present disclosure.

[0032] Figure 16 This is a vertical cross-sectional view of an exemplary structure after a logic die has been attached to a memory die, according to an embodiment of the present disclosure.

[0033] Figure 17AThis is a vertical cross-sectional view of an exemplary structure after the removal of the carrier substrate, according to an embodiment of the present disclosure.

[0034] Figure 17B yes Figure 17A An enlarged view of the area of ​​an exemplary structure.

[0035] Figure 18 This is a vertical cross-sectional view of a region of an exemplary structure surrounding the end portion of a memory stack structure according to an embodiment of the present disclosure.

[0036] Figure 19A This is a vertical cross-sectional view of an exemplary structure after the source contact structure has been formed, according to an embodiment of the present disclosure.

[0037] Figure 19B yes Figure 19A An enlarged view of the area of ​​an exemplary structure. Detailed Implementation

[0038] As discussed above, embodiments of this disclosure relate to a memory device and a method of forming the same, each column containing a non-integer average number of memory openings. Various aspects of the memory device and these methods are described below. Embodiments of this disclosure can be used to form various structures including multi-level memory structures. Non-limiting examples of such multi-level memory structures include three-dimensional memory devices comprising multiple memory strings.

[0039] The accompanying drawings are not to scale. Multiple instances of an element may be reproduced where only a single instance is illustrated, unless otherwise explicitly described or clearly indicated that a reproduction of the element does not exist. Ordinal numbers such as “first,” “second,” and “third” are used only to identify similar elements, and different ordinal numbers may be used in the specification and claims of this disclosure. The term “at least one” element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0040] Like reference numerals denote the same or similar elements. Unless otherwise specified, elements with the same reference numerals are considered to have the same composition and the same function. Unless otherwise specified, “contact” between elements means direct contact between elements providing an edge or surface shared by these elements. If two or more elements are not in direct contact with each other or are not in direct contact with each other, the two elements are “separated” from each other or “separated” from each other. As used herein, an element located “on” a second element may be located on the outer side of the surface of the second element or on the inner side of the second element. As used herein, if there is physical contact between the surface of an element and the surface of a second element, the element is “directly” located “on” the second element. As used herein, if there is a conductive path consisting of at least one conductive material between an element and a second element, the element is “electrically connected” to the second element. As used herein, a “prototype” structure or a “process” structure refers to a transient structure whose shape or composition is subsequently modified.

[0041] As used herein, a “layer” refers to a portion of material comprising a region of thickness. A layer may extend over the entire underlying or overlying structure, or its extent may be less than that of the underlying or overlying structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between or at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, or may have one or more layers on, above, and / or below it.

[0042] Generally, a semiconductor die or semiconductor package can include a memory chip. Each semiconductor package contains one or more dies (e.g., one, two, or four). A die is the smallest unit capable of independently executing commands or reporting status. Each die contains one or more planes (typically one or two). Despite some limitations, the same concurrent operations can be performed on each plane. Each plane contains multiple blocks, which are the smallest units that can be erased in a single erase operation. Each block contains multiple pages, which are the smallest programmable units, i.e., the smallest units on which read operations can be performed.

[0043] As used in this article, "semiconductor material" refers to a material with an electrical conductivity of 1×10⁻⁶. -5 S / m to 1×10 5 Materials in the S / m range. As used herein, "semiconductor material" refers to a material in which the electrical conductivity is in the absence of electrical dopants and is 1 × 10⁻⁶. -5 Materials in the range of S / m to 1 S / m, and which, after appropriate doping with an electrical dopant, can produce conductivity in the range of 1 S / m to 1 × 10⁻⁶.7 Doped materials in the S / m range. As used herein, “electrical dopant” refers to a p-type dopant that adds holes to the valence band within the band structure, or an n-type dopant that adds electrons to the conduction band within the band structure. As used herein, “conductive material” refers to a material with a conductivity greater than 1 × 10⁻⁶. 5 Materials with a conductivity of S / m. As used herein, "insulating material" or "dielectric material" refers to materials with a conductivity less than 1 × 10⁻⁶. -5 Materials with a S / m ratio. As used herein, "heavily doped semiconductor material" refers to a semiconductor material doped with an electrically conductive agent at a sufficiently high atomic concentration to become a conductive material, which is formed as a crystalline material or transformed into a crystalline material through an annealing process (e.g., from an initial amorphous state), i.e., providing a value greater than 1 × 10⁻⁶. 5 The conductivity is S / m. "Doped semiconductor material" can be a heavily doped semiconductor material, or it can be a semiconductor material comprising electrically dopants (i.e., p-type dopants and / or n-type dopants) at a concentration of 1 × 10⁻⁶. -5 S / m to 1×10 7 Conductivity in the S / m range. "Intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrically conductive agent. Therefore, a semiconductor material can be semiconductor or conductive, and can be intrinsic or doped. A doped semiconductor material can be semiconductor or conductive, depending on the atomic concentration of the electrically conductive agent therein. As used herein, "metallic material" refers to a conductive material that includes at least one metallic element. All conductivity measurements were performed under standard conditions.

[0044] refer to Figure 1 An exemplary structure according to embodiments of the present disclosure is illustrated. This exemplary structure includes a carrier substrate 9, which may be a semiconductor substrate or a conductive substrate. For example, the carrier substrate 9 may include a commercially available silicon wafer. Alternatively, the carrier substrate 9 may include any material that can be selectively removed relative to the material of the insulating layer 32 and the dielectric material portion to be subsequently formed.

[0045] Alternating stacks of a first material layer and a second material layer may be formed on a carrier substrate 9. The first material layer may be an insulating layer, and the second material layer may be a spacer material layer. In one embodiment, the spacer material layer may include a sacrificial material layer 42. In this case, alternating stacks (32, 42) of insulating layer 32 and sacrificial material layer 42 may be formed over the carrier substrate 9. Insulating layer 32 includes an insulating material such as undoped silicate glass or doped silicate glass, and sacrificial material layer 42 includes a sacrificial material such as silicon nitride or a silicon-germanium alloy. In one embodiment, insulating layer 32 (i.e., the first material layer) may include a silicon oxide layer, and sacrificial material layer 42 (i.e., the second material layer) may include a silicon nitride layer.

[0046] The alternating stacks (32, 42) may include multiple repetitions of a unit layer stack comprising an insulating layer 32 and a sacrificial material layer 42. The total number of repetitions of the unit layer stacks within the alternating stacks (32, 42) may be, for example, in the range of 8 to 1,024, such as 32 to 256, but smaller and larger repetitions may also be used. Hereinafter, the topmost insulating layer of the insulating layers 32 is referred to as the topmost insulating layer 32T. The bottommost insulating layer of the insulating layers 32 is the insulating layer 32 closest to the carrier substrate 9, and this insulating layer is referred to herein as the bottommost insulating layer 32B.

[0047] Each insulating layer in the insulating layers 32, except for the topmost insulating layer 32T, may have a thickness ranging from 20 nm to 100 nm, such as 30 nm to 60 nm, but smaller and larger thicknesses are also possible. Each sacrificial material layer in the sacrificial material layers 42 may have a thickness ranging from 20 nm to 100 nm, such as 30 nm to 60 nm, but smaller and larger thicknesses are also possible. In one embodiment, the topmost insulating layer 32T may have a thickness approximately half that of the other insulating layers 32.

[0048] An exemplary structure includes a memory array region 100 and a contact region 300, in which a three-dimensional array of memory elements will subsequently be formed, and in the contact region, a layer contact via structure for contact word lines will subsequently be formed.

[0049] While an embodiment in which the spacer material layer is formed as sacrificial material layer 42 is described, in an alternative embodiment, the spacer material layer may be formed as a conductive layer. Generally, the spacer material layer of this disclosure may be formed as a conductive layer, or may subsequently be at least partially replaced with a conductive layer.

[0050] refer to Figure 2 Optional stepped surfaces are formed in the contact area 300. As used herein, a “stepped surface” refers to a set of surfaces comprising at least two horizontal surfaces and at least two vertical surfaces, such that each horizontal surface is adjacent to a first vertical surface extending upward from an edge of the horizontal surface and to a second vertical surface extending downward from a second edge of the horizontal surface. A stepped cavity is formed within the volume by removing portions of the alternatingly stacked (32, 42) from the stepped cavity by forming the stepped surfaces. A “stepped cavity” refers to a cavity having stepped surfaces.

[0051] The stepped cavity can have different stepped surfaces, such that the horizontal cross-sectional shape of the stepped cavity varies in a stepped manner with a vertical distance from the top surface of the supporting substrate 9. In one embodiment, the stepped cavity can be formed by repeatedly performing a set of processing steps. This set of processing steps may include, for example, a first type of etching process and a second type of etching process, wherein the first type of etching process vertically increases the depth of the cavity by one or more levels, and the second type of etching process laterally extends the area vertically etched in a subsequent first type of etching process. As used herein, a “level” comprising alternating plurality of structures is defined as the relative position of a pair of first and second material layers within the structure.

[0052] Each sacrificial material layer 42 within the alternating stacks (32, 42), except for the topmost sacrificial material layer 42, extends laterally further than any overlying sacrificial material layer 42 within the alternating stacks (32, 42) in the mezzanine area. The stepped surface of the alternating stacks (32, 42) extends continuously from the bottommost layer (such as the bottommost insulating layer 32B) within the alternating stacks (32, 42) to the topmost layer (such as the topmost insulating layer 32T) within the alternating stacks (32, 42).

[0053] A stepped dielectric material portion 65 (i.e., an insulating filler portion) can be formed in a stepped cavity by depositing dielectric material therein. For example, a dielectric material such as silicon oxide can be deposited in the stepped cavity. Excess portions of the deposited dielectric material can be removed, for example, from the top surface of the topmost insulating layer 32T by chemical mechanical planarization (CMP). The remaining portion of the deposited dielectric material filling the stepped cavity constitutes the stepped dielectric material portion 65. As used herein, a “stepped” element refers to an element having a stepped surface and a horizontal cross-sectional region that increases or decreases in steps as a function of the vertical distance from the top surface of the substrate on which the element is situated. If silicon oxide is used for the stepped dielectric material portion 65, the silicon oxide of the stepped dielectric material portion 65 may or may not be doped with dopants such as B, P, and / or F.

[0054] Figure 3A This is a schematic vertical cross-sectional view of an exemplary structure after the formation of the memory opening 49 and the support opening 19, according to an embodiment of the present disclosure. Figure 3B yes Figure 3A A top view of an exemplary structure. The hinged vertical cross-sectional plane A-A' is Figure 3A A cross-sectional view of the vertical cross section. Figures 3C to 3G Is Figure 3A and Figure 3B A top view of an alternative configuration of the exemplary structure at the processing steps.

[0055] refer to Figures 3A to 3GAn etch mask layer (such as a photoresist layer) may be formed over the alternating stacks (32, 42) and may be photolithographically patterned to form openings in the memory array region 100 and in the contact region 300. An anisotropic etching process may be performed to transfer the pattern of the openings in the etch mask layer through the stepped dielectric portion 65 and the alternating stacks (32, 42). Memory openings 49 are formed through the alternating stacks (32, 42) in the memory array region 100. Support openings 19 may optionally be formed through the stepped dielectric portion 65 and the alternating stacks (32, 42) in the contact region 300.

[0056] Each of the memory opening 49 and the support opening 19 may extend vertically into the carrier substrate 9. In one embodiment, the bottom surfaces of the memory opening 49 and the support opening 19 may be formed at or below the top surface of the carrier substrate 9. The diameter of the memory opening 49 may be in the range of 60 nm to 400 nm (e.g., from 120 nm to 300 nm), but may have smaller and larger thicknesses. The support opening 19 may have a diameter in the range of 60 nm to 400 nm (e.g., from 120 nm to 300 nm), but may have smaller and larger thicknesses.

[0057] Each cluster of memory openings 49 (corresponding to a region of a memory block) may include multiple rows of memory openings 49. Each row of memory openings 49 may include multiple memory openings 49 arranged at a consistent pitch along a first horizontal direction hd1 (which may be a word line direction). The rows of memory openings 49 may be laterally spaced from each other along a second horizontal direction hd2 (which may be a bit line direction), which may be perpendicular to the first horizontal direction hd1. In one embodiment, each cluster of memory openings 49 may be formed as a two-dimensional periodic array of memory openings 49.

[0058] The patterns of the memory opening 49 and the support opening 19 may be formed periodically along the second horizontal direction hd2. A portion of the exemplary structure including a cell pattern repeating along the second horizontal direction hd2 is referred to herein as a repeating cell RU. The repeating cell may correspond to a memory block. For example... Figure 3B As shown, each repeating unit RU includes multiple rows and columns of memory openings 49. Each column of memory openings 49 is arranged along a second horizontal direction hd2. The column memory openings 49 are laterally spaced from each other along a first horizontal direction hd1. Each row of memory openings 49 is arranged along the first horizontal direction hd1. The row memory openings 49 are laterally spaced from each other along a second horizontal direction hd2. In one embodiment, each row of memory openings 49 may include Q memory openings 49. The integer Q can be 2... 4 Up to 2 16 Such as 2 6 Up to 2 13Within the range, but fewer or more quantities can also be used.

[0059] The memory openings 49 within each repeating unit RU can be arranged as a two-dimensional periodic array, which can be a hexagonal periodic array (i.e., a hexagonal lattice with memory openings at the vertices and center of each unit hexagon). According to one aspect of this disclosure, each two-dimensional array of memory openings 49 located within a corresponding repeating unit RU may include and / or be composed of BCG = M × P + K block columns (“BCG”) of memory openings 49, where M is an integer greater than 1 and less than 13, P is an integer greater than 1 and less than 9, and K is a positive integer less than M. A block column is a group of memory openings 49 with repeating patterns in each column.

[0060] exist Figure 3B In the illustrated example, M is 2, P is 4, K is 1, and BCG is 9 (i.e., 2 × 4 + 1 = 9). Column 1 contains five memory slots, column 2 contains four memory slots, column 3 contains five memory slots, column 4 contains four memory slots, and so on. Therefore, Figure 3B Each pair of adjacent columns of the memory opening 49 forms a BCG. For example, there are a total of nine memory openings 49 in a BCG that includes columns 1 and 2.

[0061] exist Figure 3C In the example shown, M is 4, P is 4, K is 2, and BCG is 18. Figure 3D In the example shown, M is 3, P is 4, K is 1, and BCG is 13. Figure 3E In the example shown, M is 6, P is 4, K is 2, and BCG is 26. Figure 3F In the example shown, M is 3, P is 5, K is 1, and BCG is 16. Figure 3G In the illustrated example, M is 6, P is 5, K is 2, and BCG is 32. While the above describes an implementation of a selected example containing integers M, P, and K, other implementations are explicitly envisioned for all other variations, where M is an integer greater than 1 and less than 13, P is an integer greater than 1 and less than 9, and K is a positive integer less than M. Generally, the lateral spacing between adjacent pairs of memory openings 49 can be consistent or varied for the purpose of subsequently forming a drain-select level dielectric isolation structure.

[0062] refer to Figure 4Optional sacrificial liner layers (such as thin silicon oxide layers) and sacrificial filler materials can be deposited in the memory opening 49 and the support opening 19. The sacrificial filler materials may include carbon-based materials (such as amorphous carbon or diamond-like carbon), semiconductor materials (such as amorphous silicon or silicon-germanium), polymeric materials, or dielectric materials (such as borosilicate glass or organosilicon glass). Excess sacrificial filler materials can be removed from a horizontal plane above the top surface, including the topmost insulating layer 32T. The sacrificial filler material filling each remaining portion of the memory opening 49 constitutes a sacrificial memory opening filling structure 48. The sacrificial filler material filling each remaining portion of the support opening 19 constitutes a sacrificial support opening filling structure 18.

[0063] refer to Figure 5 A photoresist layer (not shown) may be applied over the exemplary structure and may be photolithographically patterned to cover the sacrificial memory opening-fill structure 48 in the memory array region 100, but not the sacrificial support opening-fill structure 18 in the contact region 300. The sacrificial support opening-fill structure 18 is then selectively removed relative to the materials of the insulating layer 32, the sacrificial material layer 42, and the carrier substrate 9 by ashing or selective etching. A void is formed in the volume of the support opening 19 from which the sacrificial support opening-fill structure 18 is removed.

[0064] Dielectric filler material (such as silicon oxide) can be deposited in the support openings 19 using a conformal deposition process. Excess dielectric filler material can be removed, for example, from the top surface of the topmost insulating layer 32T using a recess etching process. The filling of each portion of the corresponding support opening 19 with dielectric filler material constitutes a support pillar structure 20, which can be used to provide structural support to the insulating layer 32 and the stepped dielectric material portion 65 during the replacement of the sacrificial material layer 42 with a conductive layer. Alternatively, the support openings 19 can be formed simultaneously with the memory openings in a later step, and the support pillar structure 20 can be formed in the support openings 19 while the memory opening filling structure is formed in the memory openings, as will be described below.

[0065] refer to Figure 6 Subsequently, the sacrificial memory opening fill structure 48 is selectively removed relative to the materials of the insulating layer 32, the sacrificial material layer 42, and the carrier substrate 9. A void is formed in the volume of the memory opening 49 from which the sacrificial memory opening fill structure 48 is removed.

[0066] Figures 7A to 7F It is a continuous vertical cross-sectional view of the memory opening 49 during the formation of the memory opening filling structure 58 according to an embodiment of the present disclosure.

[0067] refer to Figure 7A Examples are shown in Figure 6 The memory opening 49 after the processing steps.

[0068] refer to Figure 7B A layer stack including a memory material layer 54 may be conformally deposited. In an exemplary example, the layer stack may include an optional barrier dielectric layer 52, a memory material layer 54, and an optional dielectric liner 56. The memory material layer 54 includes a memory material, i.e., a material in which data bits can be stored. The memory material layer 54 may include a charge storage material (such as silicon nitride), a ferroelectric material, a phase-change memory material, or any other memory material that can store data bits by inducing changes in resistivity, ferroelectric polarization, or any other measurable physical property. Where the memory material layer 54 includes a charge storage material, the optional dielectric liner 56 may include a tunneling dielectric layer.

[0069] refer to Figure 7C A semiconductor channel material layer 60L can be deposited over each memory film 50 by performing a conformal deposition process. If the semiconductor channel material layer 60L is doped, it can have doping of a first conductivity type, which can be p-type or n-type. The thickness of the semiconductor channel material layer 60L can be in the range of 5 nm to 50 nm (e.g., 10 nm to 30 nm), but smaller and larger thicknesses are also possible.

[0070] refer to Figure 7D A dielectric core layer 62L comprising a dielectric filling material (such as silicon oxide) can be deposited in the remaining volume of the memory opening 49. While conformal deposition processes (such as chemical vapor deposition) can be used to deposit the dielectric core layer 62L, the consistency of such conformal deposition processes may not be perfect. Therefore, the thickness of the bottom portion of the dielectric core layer 62L at the bottom of each memory opening 49 may be less than the thickness of the upper portion of the dielectric core layer 62L at the top of each memory opening 49.

[0071] refer to Figure 7E The dielectric core layer 62L can be vertically recessed such that each remaining portion of the dielectric core layer has a top surface at or near a horizontal plane including the bottom surface of the topmost insulating layer 32. Each remaining portion of the dielectric core layer constitutes the dielectric core 62.

[0072] refer to Figure 7F A doped semiconductor material with a second conductivity type can be deposited in each recessed region on the dielectric core 62. The second conductivity type is the opposite of the first conductivity type. For example, if the first conductivity type is p-type, then the second conductivity type is n-type, and vice versa. The dopant concentration in the deposited semiconductor material can be 5 × 10⁻⁶. 18 / cm 3 Up to 2×10 21 / cm 3Within a certain range, but smaller or larger dopant concentrations can also be used. The doped semiconductor material can be, for example, doped polysilicon.

[0073] Excess portions of the deposited semiconductor material doped with a second conductivity type and the horizontal portions of the semiconductor channel material layer 60L can be removed, for example, from a horizontal plane above the top surface, including the top insulating layer 32T, using chemical mechanical planarization (CMP) or recess etching processes. Each remaining portion of the doped semiconductor material with the second conductivity type constitutes a drain region 63. Each remaining portion of the semiconductor channel material layer 60L (which has doping with a first conductivity type) constitutes a vertical semiconductor channel 60.

[0074] Each portion of the layer stack, including the memory material layer 54 retained in the respective memory opening 49, constitutes a memory film 50. In one embodiment, the memory film 50 may include an optional barrier dielectric layer 52, a memory material layer 54, and an optional dielectric liner 56. Each adjacent combination of the memory film 50 and the vertical semiconductor channel 60 constitutes a memory stack structure 55. Each combination of the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 constitutes a memory opening fill structure 58. Each memory opening fill structure 58 includes a respective vertical stack of memory elements, which may include portions of the memory material layer 54 located at each level of the sacrificial material layer 42 (or generally, at each level of a spacer material layer that may be formed as a conductive layer or subsequently at least partially replaced by a conductive layer).

[0075] In an alternative embodiment, the support pillar structure 20 may be formed in the support opening 19 simultaneously with the memory opening filling structure 58 formed in the memory opening 49. In this case, the support pillar structure 20 comprises the same material as the memory opening filling structure 58.

[0076] An annealing process can be performed to activate the electrically dopants in the source region 63 and the vertical semiconductor channel 60. In this case, any amorphous semiconductor material in the vertical semiconductor channel 60 is converted into a polycrystalline semiconductor material. In one embodiment, the grains within the vertical semiconductor channel 60 may extend primarily along a corresponding local direction perpendicular to a corresponding proximal portion of the inner sidewall of the vertical semiconductor channel 60 and perpendicular to a corresponding proximal portion of the outer sidewall of the vertical semiconductor channel 60. As used herein, if more than 50% of the drain extends along a particular direction, the grains extend primarily along that particular direction.

[0077] refer to Figure 8A and Figure 8BThis illustrates an exemplary structure after a memory aperture fill structure 58 is formed within a memory aperture 49. The memory aperture fill structure 58 is located within the memory aperture 49. Each memory aperture fill structure in the memory aperture fill structure 58 includes a corresponding memory film 50 and a corresponding vertical semiconductor channel 60.

[0078] refer to Figure 9A and Figure 9B Dielectric material (such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass) can be deposited over alternating stacks (32, 42) to form a contact-level dielectric layer 80. The thickness of the contact-level dielectric layer 80 can be in the range of 100 nm to 600 nm, such as 200 nm to 400 nm, but smaller and larger thicknesses are also possible.

[0079] A photoresist layer (not shown) may be applied over the contact-level dielectric layer 80 and may be photolithographically patterned to form elongated openings extending laterally between adjacent clusters of the memory aperture-filled structure 58 along a first horizontal direction hd1. An anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer through the contact-level dielectric layer 80, the alternating stacks (32, 42), and the stepped dielectric material portions 65, and to the top surface of the carrier substrate 9. Lateral isolation trenches 79 extending laterally along the first horizontal direction hd1 may be formed through the alternating stacks (32, 42), the stepped dielectric material portions 65, and the contact-level dielectric layer 80. Each lateral isolation trench 79 may include a corresponding pair of longitudinal sidewalls parallel to the first horizontal direction hd1 and extending vertically from the top surface of the contact-level dielectric layer 80 to the top surface of the carrier substrate 9. The surface of the carrier substrate 9 may be physically exposed beneath each lateral isolation trench 79. The photoresist layer can then be removed, for example, by ashing.

[0080] refer to Figure 10 For example, an isotropic etching process can be used to introduce an etchant into the lateral isolation trench 79, which selectively etches the material of the sacrificial material layer 42 relative to the material of the insulating layer 32. Lateral recesses 43 are formed in the volume where the sacrificial material layer 42 is removed. The sacrificial material layer 42 can be selectively removed with respect to the materials of the insulating layer 32, the stepped dielectric portion 65, and the outermost layer of the memory film 50. In one embodiment, the sacrificial material layer 42 may comprise silicon nitride, and the materials of the insulating layer 32 and the stepped dielectric portion 65 may comprise silicon oxide.

[0081] The etching process that selectively removes the second material relative to the first material and the outermost layer of the memory film 50 can be a wet etching process using a wet etching solution, or a vapor-phase (dry) etching process in which an etchant is introduced in the vapor phase into the lateral isolation trench 79. For example, if the sacrificial material layer 42 comprises silicon nitride, the etching process can be a wet etching process in which the exemplary structure is immersed in a wet etching bath containing phosphoric acid, which selectively etches silicon nitride relative to silicon oxide, silicon, and various other materials used in the art. The support pillar structure 20, the stepped dielectric material portion 65, and the memory stack structure 55 provide structural support, while the lateral recess 43 exists within the volume previously occupied by the sacrificial material layer 42.

[0082] Each lateral recess 43 may be a laterally extending cavity with a lateral dimension greater than the vertical extent of the cavity. In other words, the lateral dimension of each lateral recess 43 may be greater than the height of the lateral recess 43. Multiple lateral recesses 43 may be formed in the volume from which the second material from which the sacrificial material layer 42 is removed. Compared to the lateral recesses 43, the memory opening in which the memory stack structure 55 is formed is referred to herein as a front opening or a front cavity.

[0083] Each of the plurality of lateral recesses 43 may extend substantially parallel to the top surface of the carrier substrate 9. The lateral recesses 43 may be vertically defined by the top surface of the underlying insulating layer 32 and the bottom surface of the overlying insulating layer 32. In one embodiment, each lateral recess 43 may always have a consistent height.

[0084] refer to Figure 11 Optionally, an external barrier dielectric layer (not explicitly illustrated) may be formed. The external barrier dielectric layer (if present) comprises a dielectric material that acts as a control gate dielectric for a control gate subsequently formed in the lateral recess 43. The external barrier dielectric layer is optional if a barrier dielectric layer 52 is present within each memory opening. An external barrier dielectric layer is present if the barrier dielectric layer 52 is omitted.

[0085] At least one conductive material can be deposited in the lateral recess 43 by providing at least one reactive gas into the lateral recess 43 via a lateral isolation trench 79. A metal barrier layer can be deposited in the lateral recess 43. The metal barrier layer comprises a conductive metal material that can be used as a diffusion barrier layer and / or adhesion promoting layer for a subsequently deposited metal filler material. The metal barrier layer may comprise a conductive metal nitride material, such as TiN, TaN, WN, or a stack thereof, or may comprise a conductive metal carbide material, such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metal barrier layer can be deposited using a conformal deposition process, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metal barrier layer can range from 2 nm to 8 nm (e.g., 3 nm to 6 nm), but smaller and larger thicknesses are also possible. In one embodiment, the metal barrier layer may consist substantially of a conductive metal nitride such as TiN.

[0086] A metal filler material is deposited in a plurality of lateral recesses 43, on the sidewalls of at least one lateral isolation trench 79, and above the top surface of the contact-level dielectric layer 80 to form a metal filler material layer. The metal filler material can be deposited using conformal deposition methods, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or combinations thereof. In one embodiment, the metal filler material layer may consist substantially of at least one elemental metal. The at least one elemental metal of the metal filler material layer may be selected from, for example, tungsten, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the metal filler material layer may consist substantially of a single elemental metal. In one embodiment, a fluorine-containing precursor gas (such as WF6) may be used to deposit the metal filler material layer. In one embodiment, the metal filler material layer may be a tungsten layer including residual levels of fluorine atoms as impurities. The metal filler material layer is separated from the insulating layer 32 and the memory stack structure 55 by a metal barrier layer, which is a metal barrier layer that prevents fluorine atoms from diffusing through it.

[0087] Multiple conductive layers 46 may be formed in multiple lateral recesses 43, and a continuous metal material layer may be formed on the sidewalls of each lateral isolation trench 79 and over the contact level dielectric layer 80. Each conductive layer 46 includes a portion of a metal barrier layer and a portion of a metal filler layer, these portions being located between a pair of vertically adjacent dielectric material layers (such as a pair of insulating layers 32). The continuous metal material layer includes continuous portions of a metal barrier layer and continuous portions of a metal filler layer, these continuous portions being located in the lateral isolation trench 79 or over the contact level dielectric layer 80.

[0088] The deposited metal material of the continuous conductive material layer is etched back from the sidewalls of each lateral isolation trench 79 and from above the contact level dielectric layer 80 by performing an isotropic etching process of at least one conductive material in the lateral isolation trench 43. Each remaining portion of the metal material deposited in the lateral recess 43 constitutes a conductive layer 46. Each conductive layer 46 may be a wire structure. Thus, the sacrificial material layer 42 is replaced by the conductive layer 46. Generally, the conductive layer 46 can be formed by providing a metal precursor gas into the lateral isolation trench 79 and the lateral recess 43. At least one uppermost conductive layer 46 may include a drain-side select layer 46DL. At least one bottommost conductive layer 46 may include a source-side select gate electrode 46S. The remaining conductive layers 46 may include word lines 46W. Each word line 46W serves as a common control gate electrode for a plurality of vertical NAND strings (e.g., memory aperture fill structure 58).

[0089] Memory strings are disposed in and around memory aperture filling structures 58. Specifically, each memory string is disposed in and around each memory aperture filling structure 58. A “memory string” refers to a group of memory cells electrically connected in series. In an exemplary structure, each memory string includes a memory stack structure 55 that includes a corresponding vertical semiconductor channel 60 and a corresponding memory film 50 that includes a corresponding vertical stack of memory elements. Each memory string also includes proximal portions of a conductive layer 46 that act as control gate electrodes for the NAND memory string.

[0090] Typically, in NAND memory devices, memory cells are organized into a set of pages, and each page includes a corresponding set of memory blocks. All the memory strings in this set (e.g., memory aperture filling structures 58 and associated select gate electrodes and word lines / control gate electrodes) between adjacent pairs of lateral isolation trenches 79 constitute a memory block.

[0091] Figure 12A This is a vertical cross-sectional view of an exemplary structure after the formation of the lateral isolation trench filling structure 76 and the drain selection level dielectric isolation structure 72, according to an embodiment of the present disclosure. Figure 12B yes Figure 12A A top view of an exemplary structure. Vertical plane AA is... Figure 12A A cross-sectional view of the vertical cross section. Figures 12C to 12G Is Figure 12A and Figure 12B A top view of an alternative configuration of the exemplary structure at the processing steps.

[0092] According to one aspect of this disclosure, each memory block is divided into multiple memory string groups (“MSGs”) by forming a drain-select-level dielectric isolation structure 72. Each group of memory strings located between adjacent pairs of drain-select-level isolation structures constitutes a memory string group. Since the drain-select-level isolation structure 72 divides the drain-side select gate electrode (i.e., the uppermost conductive layer 46) but does not divide the lower word line or source-side select gate electrode, the region of each drain-side select gate electrode 46D covers the corresponding MSG.

[0093] refer to Figures 12A to 12G A photoresist layer (not shown) may be applied over the contact-level dielectric layer 80 and may be photolithographically patterned to form openings generally extending along a first horizontal direction hd1 within the region of the memory array region 100, these openings having lateral undulations along a second horizontal direction hd2. An anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer through the contact-level dielectric layer 80 and a subgroup of conductive layers 46 including at least the topmost conductive layer 46. The anisotropic etching process etches the material of the contact-level dielectric layer 80 and the alternating stacked subgroups of layers (32, 46) to form drain-select level isolation trenches.

[0094] The drain-side select layers 46DL, defined by lateral isolation trenches, are referred to herein as drain-side select gate electrodes 46D. These drain-side select gate electrodes may be located at a single layer or span multiple layers (such as 2 to 10 layers). Subgroups of conductive layers 46 that are not defined during the anisotropic etching process and are used as control gate electrodes for memory strings are referred to as word lines 46W. Subgroups of conductive layers 46 located near the carrier substrate 9 may be used as source-side select gate electrodes 46S. The photoresist layer may subsequently be removed, for example, by ashing.

[0095] Dielectric filler materials, such as undoped silicate glass (e.g., silicon oxide) or doped silicate glass, can be deposited in the lateral isolation trench 79 and the drain selection level trench. Excess dielectric filler material can be removed from above the contact level dielectric layer 80. The dielectric filler material filling each remaining portion of a corresponding lateral isolation trench in the lateral isolation trench 79 constitutes a lateral isolation trench filling structure 76, which may be a dielectric wall structure. The dielectric filler material filling each remaining portion of a corresponding drain selection level isolation trench in the drain selection level isolation trench constitutes a drain selection level dielectric isolation structure 72.

[0096] In an alternative embodiment, the lateral isolation trench fill structure 76 may be formed during a different processing step than the drain-selective dielectric isolation structure 72. In this case, the material composition of the lateral isolation trench fill structure 76 and the drain-selective dielectric isolation structure 72 may be the same or different. For example, the drain-selective dielectric isolation structure 72 may be formed in an alternating stack of insulating layer 32 and sacrificial material layer 42 before the sacrificial material layer 42 is replaced by conductive layer 46.

[0097] In another alternative embodiment, an insulating spacer with a tubular configuration may be formed in the peripheral portion of each lateral isolation trench 79, and a through-stacked conductive via structure may be formed within a corresponding insulating spacer. In this case, each lateral isolation trench filling structure 76 may include a combination of the through-stacked conductive via structure and an insulating spacer laterally surrounding the through-stacked conductive via structure. In this case, the drain-selective isolation trench and the drain-selective dielectric isolation structure 72 may be formed before or after the formation of the lateral isolation trench filling structure 76.

[0098] Generally, each lateral isolation trench fill structure in the lateral isolation trench fill structure 76 includes a pair of longitudinal dielectric sidewalls that contact a pair of alternately stacked longitudinal sidewalls (32, 46). Each drain-selection level dielectric isolation structure 72 has sidewalls that contact a corresponding pair of separated portions of at least one drain-selection level electrode layer 46D. Each separated portion of the drain-side selection layer 46DL is referred to as a drain-side selection gate electrode 46D.

[0099] Generally, each alternating stack (32, 46) of insulating layer 32 and conductive layer 46 may be formed between an adjacent pair of lateral isolation trenches 79, i.e., between a first lateral isolation trench 79 and a second lateral isolation trench 79 (i.e., in each memory block). A first lateral isolation trench fill structure 76 and a second lateral isolation trench fill structure 76 may be formed in the first lateral isolation trench 79 and the second lateral isolation trench 79, respectively. At least one drain-select level dielectric isolation structure 72 may be formed such that at least one drain-select level dielectric isolation structure 72 exists in the upper portion of the alternating stack (32, 46). Word line 46W extends laterally from the first lateral isolation trench fill structure 76 to the second lateral isolation trench fill structure 76 continuously. Drain-side select gate electrodes 46D are laterally spaced from each other along the second horizontal direction hd2 by the respective drain-select level dielectric isolation structures 72.

[0100] Each set of memory opening fill structures 58, located between a corresponding pair of adjacent isolation structures (72, 76) selected from the first or second lateral isolation trench fill structure 76 and the drain-selective dielectric isolation structure 72, defines a memory string group (MSG). For example, as Figure 12B As shown, each memory block (MB) comprises two memory strings (MSGs) separated from each other by a drain-selection-level dielectric isolation structure 72 (e.g., MSG1 and MSG2). According to one aspect of this disclosure, each memory string group (MSG) comprises all memory aperture fill structures 58 within a corresponding set of row memory aperture fill structures 58, and includes a non-zero fraction of memory aperture fill structures 58 within a corresponding additional row memory aperture fill structure 58. The non-zero fraction of a row is less than the total number of rows, but greater than zero memory aperture fill structures 58. In one embodiment, a two-dimensional array of memory strings may be located within each repeating unit RU (e.g., memory block MB) between adjacent pairs of lateral isolation trench fill structures 76. Each memory string includes a corresponding memory stack structure 55 and an adjacent portion of the conductive layer 46. The two-dimensional array of memory strings may include and / or may be composed of multiple block string groups (BSGs), where each BSG = M × P + K, as described above.

[0101] according to Figure 12B In one aspect of this disclosure, (M-1) drain-select level dielectric isolation structures 72 may be disposed in each memory block MB between the first lateral isolation trench fill structure 76 and the second lateral isolation trench fill structure 76, and M memory string groups MSG may be disposed in each memory block MB between the first lateral isolation trench fill structure 76 and the second lateral isolation trench fill structure 76. For at least two of the M memory string groups, the non-zero fraction of the rows is given by K / M, where M is an integer greater than 1 and less than 13 and equal to the number of MSGs, and K is a positive integer less than M. In one embodiment, each memory string group MSG may include P+K / M rows of memory strings, that is, it may include P rows of complete memory strings and fractional rows of memory strings (which are K / M rows of memory strings). Fractional rows of memory strings are defined as subgroups or portions of complete rows of memory strings that are smaller than the whole of the entire row of memory strings. Figure 12B In the illustrated example, M is 2 (i.e., there are 2 MSGs), M-1 is 1 (i.e., each memory block MB has one isolation structure 72), P is 4 (i.e., each MSG has four whole-line memory strings (e.g., memory opening-filled structure 58)), and K is 1 (i.e., there is one fractional-line memory string). Because in Figure 12B In the example, K / M equals 1 / 2, so each fractional row contains half of a whole row. Figure 12C In the example shown, M is 4, P is 4, and K is 2. Figure 12DIn the illustrated example, M is 3, P is 4, and K is 1 (i.e., the fractional row contains K / M = 1 / 3 of the whole row, while the complementary part of the fractional row contains 2 / 3 of the whole row, where the two complementary parts of the fractional row in the second MSG2 can be considered as one row). Figure 12E In the example shown, M is 6, P is 4, and K is 2. Figure 12F In the example shown, M is 3, P is 5, and K is 1. Figure 12G In the example shown, M is 6, P is 5, and K is 2.

[0102] In one embodiment, at least one drain-select level dielectric isolation structure 72 is formed having lateral undulations along a second horizontal direction hd2. In one embodiment, the drain-select level dielectric isolation structure 72 is formed between an adjacent pair of memory string groups, including a first memory string group and a second memory string group. In one embodiment, the drain-select level dielectric isolation structure 72 meanders around a row of memory aperture fill structures 58, such that a first subgroup of memory aperture fill structures 58 within that row of memory aperture fill structures 58 belongs to the first memory string group, and a second subgroup of memory aperture fill structures 58 belongs to the second memory string group. In one embodiment, the drain-select level dielectric isolation structure 72 does not cut through any of the memory aperture fill structures 58, such that all memory aperture fill structures 58 in each memory string group are “complete” memory aperture fill structures 58 without any cut-off portions or flat vertical sidewalls. In one embodiment, each complete memory aperture fill structure 58 has a circular or substantially circular horizontal cross-sectional shape. A substantially circular shape may occur due to unintentional variations in the photolithography and etching of the memory aperture 49, resulting in a slight deviation from a precise circular shape.

[0103] In one embodiment, alternating stacks (32, 46) of insulating layer 32 and conductive layer 46 extend along a first horizontal direction hd1. Conductive layer 46 includes word lines 46W and drain-side selected gate electrodes 46D overlying the word lines 46. Memory aperture fill structures 58 extend vertically through the alternating stacks (32, 46). Each memory aperture fill structure in memory aperture fill structures 58 includes a vertical stack of memory elements (e.g., a portion of memory film 50 or a floating gate) and a vertical semiconductor channel 60. Figure 12B As shown, the memory aperture filling structures 58 are arranged in columns extending in a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. The average number of each column of memory aperture filling structures 58 extending through each drain-side select gate electrode 46D is a non-integer number greater than zero.

[0104] The columns of the memory opening-fill structure 58 have a pitch "V" along the first horizontal direction, such as Figure 12B As shown. In one embodiment, the alternating stack (32, 46) comprises memory blocks MB, and at least two drain-side selected gate electrodes 46D are present at each vertical level in the memory blocks MB.

[0105] exist Figure 12B In one embodiment shown, a pair of adjacent drain-side select electrodes in the drain-side select electrode 46D (located in adjacent MSGs, such as MSG1 and MSG2) are laterally separated from each other along a second horizontal direction hd2 by a drain-select-level dielectric isolation structure 72. The average number of complete memory opening-fill structures (not cut by the drain-select-level dielectric isolation structure 72) in each column of memory opening-fill structures 58 extending through each drain-side select gate electrode in the drain-side select gate electrode 46D is a non-integer number greater than zero.

[0106] In one implementation, the column includes a repeating group of an X column containing C memory aperture filling structures 58 followed by a Y column containing C+1 or C-1 memory aperture filling structures 58, where C is an integer equal to or greater than 2, X is an integer equal to or greater than 2, and Y is an integer equal to or greater than 1. For example, as Figure 12B As shown, the group comprises four columns (e.g., columns 2, 3, 4, and 5). There are three columns (e.g., columns 2, 3, and 4) containing two memory opening fill structures 58 (i.e., C=2 and X=3), followed by a column (e.g., column 5) containing three memory opening fill structures (i.e., C+1=3 and Y=1). Figures 12C to 12G The diagram shows similar repeating groups of columns where the values ​​of C, X, and Y are different.

[0107] In one embodiment, each Nth memory opening fill structure within the row memory opening fill structure 58 belongs to a first memory string group, and all other memory opening structures within the row memory opening fill structure 58 belong to a second memory string group, where N is an integer greater than 1 and less than 13. In one embodiment, if the quantity M / K is an integer, then the integer N may be the same as M / K. Figure 12B In the example shown, M is 2, P is 4, K is 1, and the integer N is 2. Figure 12C In the example shown, M is 4, P is 4, K is 2, and the integer N is 2. Figure 12D In the example shown, M is 3, P is 4, K is 1, and the integer N is 3. Figure 12E In the example shown, M is 6, P is 4, K is 2, and the integer N is 3. Figure 12FIn the example shown, M is 3, P is 5, K is 1, and the integer N is 3. Figure 12G In the example shown, M is 6, P is 5, K is 2, and the integer N is 3.

[0108] In one embodiment, at least one drain-selective dielectric isolation structure 72 may consist of only one drain-selective dielectric isolation structure 72, and the non-zero fraction may be 1 / 2, such as... Figure 12B exemplified.

[0109] In one embodiment, M memory string groups are located in each memory block MB between the first lateral isolation trench fill structure 76 and the second lateral isolation trench fill structure 76, and at least one drain-select level dielectric isolation structure 72 includes (M-1) drain-select level dielectric isolation structures 72, where M is an integer greater than or equal to 2, for example, an integer greater than 2, such as... Figures 12C to 12G exemplified.

[0110] In one implementation, M is an odd number greater than 2, and each of the (M-1) drain-select-level dielectric isolation structures 72 meanders around the corresponding row memory aperture fill structure 58, such that a first non-zero fraction of the memory aperture fill structure 58 in the corresponding row is located on a first side of the corresponding drain-select-level dielectric isolation structure 72, and a second non-zero fraction of the memory aperture fill structure 58 is located on a second side of the corresponding drain-select-level dielectric isolation structure 72, as shown below. Figure 12D and Figure 12F exemplified.

[0111] In one embodiment, M is an even number greater than 3, and at least two, but less than (M-1), of the (M-1) drain-select-level dielectric isolation structures 72 meander around the corresponding row memory opening-fill structure 58, such that a first non-zero fraction of the memory opening-fill structure 58 in the corresponding row is located on a first side of the corresponding drain-select-level dielectric isolation structure 72, and a second non-zero fraction of the memory opening-fill structure 58 is located on a second side of the corresponding drain-select-level dielectric isolation structure 72; and at least one of the (M-1) drain-select-level dielectric isolation structures 72 extends laterally in a straight line along the first horizontal direction hd1, such as... Figure 12C , Figure 12E and Figure 12G exemplified.

[0112] In one implementation, M memory string groups are located in each memory block MB between the first lateral isolation trench filling structure 76 and the second lateral isolation trench filling structure 76, and for two memory string groups in the M memory string groups, a non-zero fraction is given by K / M, where M is an integer greater than 1 and less than 13, and K is a positive integer less than M.

[0113] In one embodiment, each row of memory aperture fill structure 58 includes Q memory aperture fill structures 58; and each memory string group includes (P+K / M)×Q memory aperture fill structures 58, where P is an integer greater than 1, M is an integer greater than 1 and less than 13, and K is a positive integer less than M. In one embodiment, each memory aperture fill structure in the memory aperture fill structure 58 includes a vertical semiconductor channel 60, a vertical stack of memory elements (e.g., portions of memory film 50), and a drain region 63; and the memory device also includes bit lines 128 (described below) that extend laterally along a second horizontal direction hd2 and are electrically connected to a corresponding subgroup of the drain regions 63 of the memory aperture fill structure 58.

[0114] Figure 13A This is a vertical cross-sectional view of an exemplary structure following the formation of the layer contact via structure 86 and the drain contact via structure 88, according to an embodiment of this disclosure. Figure 13B yes Figure 13A A top view of an exemplary structure. Vertical plane AA is... Figure 13A A cross-sectional view of the vertical cross section. Figures 13C to 13G Is Figure 13A and Figure 13B A top view of an alternative configuration of the exemplary structure at the processing steps.

[0115] refer to Figures 13A to 13G Contact via structures (88, 86) can be formed through the contact-level dielectric layer 80 and optionally through the stepped dielectric material portion 65. For example, a drain contact via structure 88 can be formed through the contact-level dielectric layer 80 on each drain region 63. A layer contact via structure 86 can be formed on the conductive layer 46 through the contact-level dielectric layer 80 and through the stepped dielectric material portion 65.

[0116] Figure 14A This is a vertical cross-sectional view of an exemplary structure after the formation of the connecting via structure and bit line 128, according to an embodiment of the present disclosure. Figure 14B yes Figure 14A A top view of an exemplary structure. Vertical plane AA is... Figure 14A A cross-sectional view of the vertical cross section. Figures 14C to 14G Is Figure 14A and Figure 14BA top view of an alternative configuration of the exemplary structure at the processing steps.

[0117] refer to Figures 14A to 14G A connection-level dielectric layer 90 may be formed on top of the contact-level dielectric layer 80. A connection via cavity may be formed through the connection-level dielectric layer 90 and may be filled with at least one conductive material to form a connection-level via structure (98, 96). The connection-level via structures (98, 96) include a drain connection via structure 98 of a corresponding drain contact via structure in the contact-drain contact via structures 88, and a layer connection via structure 96 of a corresponding layer contact via structure in the contact-layer contact via structures 86.

[0118] Bit-line level dielectric layer 120 may be formed on interconnect level dielectric layer 90. Bit-line level cavities may be formed through bit-line level dielectric layer 120 and may be filled with at least one conductive material (which may include at least one metallic material) to form bit-line level metal lines (128, 126). Bit-line level metal lines 128 may include bit lines 128 extending laterally along a second horizontal direction hd2, and bit-line level interconnect metal lines 126 that can be used to provide electrical connections to layer interconnect via structure 96.

[0119] In one embodiment, a two-dimensional array of drain connection via structures 98 may be located within each memory block MB (e.g., in each repeating cell RU) between regions of an adjacent pair of lateral isolation trench filling structures 76. The two-dimensional array of drain connection via structures 98 may include or may consist of M×P+K rows of drain connection via structures 98. M is an integer greater than 1 and less than 13, P is an integer greater than 1 and less than 9, and K is a positive integer less than M. In one embodiment, each row of drain connection via structures 98 may include Q drain connection via structures 98. The integer Q may be 2^30 ... 4 Up to 2 16 Such as 2 6 Up to 2 13 Within a certain range, but smaller or larger quantities can also be used. Figure 14B In the example shown, M is 2, P is 4, and K is 1. Figure 14C In the example shown, M is 4, P is 4, and K is 2. Figure 14D In the example shown, M is 3, P is 4, and K is 1. Figure 14E In the example shown, M is 6, P is 4, and K is 2. Figure 14F In the example shown, M is 3, P is 5, and K is 1. Figure 14G In the example shown, M is 6, P is 5, and K is 2.

[0120] In one embodiment, the total number of bit lines 128 in the memory array region 100 may not exceed (P+1)×Q. In one embodiment, P is an even number; and for each of the M memory string groups in each memory block MB between the first lateral isolation trench fill structure 76 and the second lateral isolation trench fill structure 76, a first subgroup of bit lines 128 is electrically connected to a corresponding drain region 63 within the memory string group, and a second subgroup of bit lines 128 is electrically isolated from each drain region 63 within the memory string group. In one embodiment, for each of the M memory string groups, the total number of bit lines 128 electrically connected to the drain regions 63 within that memory string group is the same as the total number of drain regions 63 within that memory string group. The total number of memory strings in a memory block MB located between adjacent pairs of lateral isolation trench fill structures 76 may be Q×(M×P+K). Therefore, the average number of memory strings electrically connected to a single bit line 128 in all memory strings of the memory block is given by Q×(M×P+K) divided by (P+1)×Q (which is M-(MK) / (P+1)). Generally, the first subgroup of bit line 128 is electrically connected to M memory strings within the memory block MB, and the second subgroup of bit line 128 is electrically connected to (M-1) memory strings.

[0121] In one embodiment, bit line 128 extends along the second horizontal direction hd2 and is electrically connected to a corresponding drain region 63 in the memory aperture-filled structure 58. For example... Figure 14B As shown, bit line 128 has a pitch W along a first horizontal direction, which is equal to the memory opening fill structure 58. Figure 12B The column (as shown) is divided by the pitch V along the first horizontal direction hd1 by an odd integer.

[0122] refer to Figure 15 Additional dielectric material layers and additional metal interconnect structures may be formed above the contact-level dielectric layer 80. The additional dielectric material layer may include at least one via-level dielectric layer, at least one additional line-level dielectric layer, and / or at least one additional line and via-level dielectric layer. The additional metal interconnect structures may include metal via structures, metal line structures, and / or integrated metal line and via structures. The additional dielectric material layer formed above the contact-level dielectric layer 80 is referred to herein as the memory-side dielectric material layer 960. The additional metal interconnect structures are collectively referred to as the memory-side dielectric material layer 960. The memory-side dielectric material layer 960 includes bit-line level dielectric material layers with embedded bit lines, which are subgroups of the memory-side metal interconnect structures 980.

[0123] Metal bonding pads (referred to herein as memory-side bonding pads 988) may be formed at the topmost layer of the memory-side dielectric material layer 960. The memory-side bonding pads 988 may be electrically connected to various nodes of the memory-side metal interconnect structure 980 and the three-dimensional memory array, including the conductive layer 46 and the memory opening fill structure 58. Thus, a memory die 900 may be provided.

[0124] A memory-side dielectric layer 960 is formed over alternating stacks (32, 46). A memory-side metal interconnect structure 980 is embedded in the memory-side dielectric layer 960. Memory-side bonding pads 988 may be embedded within the memory-side dielectric layer 960, and specifically embedded in the topmost layer of the memory-side dielectric layer 960. The memory-side bonding pads 988 may be electrically connected to the memory-side metal interconnect structure 980.

[0125] In one embodiment, the memory die 900 may include: a three-dimensional memory array located beneath the first dielectric material layer 110 and comprising alternating stacks (32, 46) of insulating layer 32 and conductive layer 46; a two-dimensional array of memory openings 49 extending vertically through the alternating stacks (32, 46); a two-dimensional array of memory opening-filling structures 58 located within the two-dimensional array of memory openings 49 and comprising corresponding vertical stacks of memory elements and corresponding vertical semiconductor channels 60; and a two-dimensional array of contact via structures (such as drain contact via structure 88) overlying the three-dimensional memory array and electrically connected to a corresponding vertical semiconductor channel in the vertical semiconductor channel 60.

[0126] refer to Figure 16 A logic die 700 can be provided. The logic die 700 includes a logic-side substrate 709, peripheral circuitry 720 located on the logic-side substrate 709 and including logic-side semiconductor devices (such as field-effect transistors), a logic-side metal interconnect structure 780 embedded within a logic-side dielectric layer 760, and logic-side bonding pads 788. The peripheral circuitry 720 can be configured to control the operation of a memory array within the memory die 900. Specifically, the peripheral circuitry 720 can be configured to drive various electrical components within the memory array, including (but not limited to) a conductive layer 46, a drain region 63, and subsequently formed source contact structures. The peripheral circuitry 720 can be configured to control the vertical stacking of memory elements in the memory array within the memory die 900.

[0127] The logic die 700 can be attached to the memory die 900, for example, by bonding logic-side bonding pads 788 to memory-side bonding pads 988 at a bonding interface. The bonding between the memory die 900 and the logic die 700 can be performed using a wafer-to-wafer bonding process (in which a two-dimensional array of memory dies 900 is bonded to a two-dimensional array of logic dies 700), a die-to-die bonding process, or a die-to-die bonding process. The logic-side bonding pads 788 within each logic die 700 can be bonded to the memory-side bonding pads 988 within the corresponding memory die 900.

[0128] refer to Figure 17A and Figure 17B The substrate 9 can be removed, for example, by grinding, polishing, pyrolysis, isotropic etching, anisotropic etching, and / or combinations thereof. If a chemical mechanical polishing or etching process is used as the final step for removing the substrate 9, the bottom insulating layer 32B can be used as a polishing stop or an etching stop, respectively.

[0129] In one embodiment, at least one final step of the at least one removal process for removing the carrier substrate 9 may include a selective wet etching process that selectively etches the material of the carrier substrate 9 (such as the semiconductor material of the carrier substrate 9) relative to the dielectric material of the memory film 50. In an exemplary example, if the carrier substrate 9 comprises a semiconductor material, the final step of the at least one removal process may include a wet etching process using thermally heated trimethyl-2-hydroxyethyl ammonium hydroxide (“thermal TMY”) or tetramethylammonium hydroxide (TMAH). The entire carrier substrate 9 can be removed by a selective wet etching process. The back-side end surface of the support pillar structure 20 may be physically exposed after the carrier substrate 9 has been removed.

[0130] refer to Figure 18 The end portions of each memory film 50 can be removed by performing a series of wet etching processes. In one embodiment, the series of wet etching processes may include a first wet etching process that selectively etches the material of the blocking dielectric layer 52 relative to the material of the memory material layer 54, a second wet etching process that selectively etches the material of the memory material layer 54 relative to the material of the dielectric liner 56, and a third wet etching process that selectively etches the material of the dielectric liner 56 relative to the material of the vertical semiconductor channel 60. During the removal of the end portions of the memory film 50, the end portions of each vertical semiconductor channel 60 may be physically exposed.

[0131] refer to Figure 19A and Figure 18B. Source layer 22 may be formed on the physically exposed end surface of the vertical semiconductor channel 60. Source layer 22 may include heavily doped semiconductor material and / or at least one metal material. Back-side dielectric layer 26 may be formed above source layer, and various back-side contact via structures, such as source contact structure 6, may be formed through back-side dielectric layer 26.

[0132] Referring to all the accompanying drawings and various embodiments of the present disclosure, a memory device is provided comprising: an alternating stack (32, 46) of an insulating layer 32 and a conductive layer 46, wherein the alternating stack (32, 46) 46) Located between a first lateral isolation trench fill structure 76 and a second lateral isolation trench fill structure 76, the first and second lateral isolation trench fill structures extending laterally along a first horizontal direction hd1 and laterally spaced apart from each other along a second horizontal direction hd2, wherein the conductive layer 46 includes a word line 46W extending laterally from the first lateral isolation trench fill structure 76 to the second lateral isolation trench fill structure 76, and further includes a drain-side selected gate electrode 46D overlying the word line 46W, wherein each drain-side selected gate electrode 46D includes a corresponding plurality of drain-side selected gate electrodes, the corresponding plurality of drain-side selected gate electrodes being laterally spaced apart from each other along the second horizontal direction hd2 by at least one drain-select level dielectric isolation structure 72 extending generally along the first horizontal direction hd1; a memory opening 49 extending vertically through alternating stacks (32, 46) and arranged in multiple rows such that each row of the multiple rows is arranged along a first horizontal direction hd1, and adjacent rows of the multiple rows are laterally spaced from each other along a second horizontal direction hd2; and memory opening fill structure 58, which is located in memory opening 49, wherein each set of memory opening fill structures 58 extending vertically between a corresponding adjacent pair of isolation structures (72, 76) selected from a first lateral isolation trench fill structure 76, a second lateral isolation trench fill structure 76 and at least one drain selection level dielectric isolation structure 72 defines a memory string group, and each memory string group includes all memory opening fill structures 58 within a corresponding set of each row of memory opening fill structures 58, and includes a non-zero fraction of memory opening fill structures 58 within a corresponding additional row of memory opening fill structures 58, the non-zero fraction being smaller than the total number of memory opening fill structures 58 within the corresponding additional row.

[0133] Various embodiments of this disclosure include column memory aperture fill structures having a non-integer average number of memory aperture fill structures and memory string groups comprising a fractional number of row memory strings. This configuration provides an optimal combination of the pitch W of the bit line 128 along the first horizontal direction hd1 with the array size and device response speed, the pitch W being implementable using photolithography methods, the device response speed varying with the length of the word line 46 along the first horizontal direction hd1.

[0134] While the foregoing relates to specific preferred embodiments, it should be understood that this disclosure is not limited thereto. Those skilled in the art will envision various modifications that can be made to the disclosed embodiments, and such modifications are intended to fall within the scope of this disclosure. Compatibility is assumed between all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words “comprising” or “including” contemplate that the words “consistently consisting of” or “comprises of” replace all embodiments for which the words “comprising” or “including” are used. Whenever two or more elements are listed as alternatives in the same paragraph or different paragraphs, a Markush group comprising the list of two or more elements is also implicitly disclosed. Whenever the auxiliary verb “capable” is used in this disclosure to describe the formation of an element or the execution of a processing step, it is also clearly envisioned that embodiments in which such element or such processing step is not performed are included, provided that the resulting apparatus or device is capable of providing equivalent results. Therefore, whenever omitting such an element or the formation of such a processing step can provide the same or equivalent result, the auxiliary verb "can" applied to the formation of an element or the execution of a processing step should also be interpreted as "can" or "may, or may not," with these equivalent results including slightly superior and slightly inferior results. Where embodiments employing specific structures and / or configurations are illustrated in this disclosure, it should be understood that this disclosure can be practiced with any other functionally equivalent compatible structures and / or configurations, provided that such substitutions are not expressly prohibited or otherwise known to be impossible for a person skilled in the art. If any publications, patent applications, and / or patents are cited herein, each of such documents is incorporated herein by reference in its entirety.

Claims

1. A memory device, the memory device comprising: Alternating stacks of insulating and conductive layers, the alternating stacks extending along a first horizontal direction, wherein the conductive layer includes word lines and drain-side selected gate electrodes covering the word lines; and A memory aperture fill structure, the memory aperture fill structure extending vertically through the alternating stack, wherein each memory aperture fill structure in the memory aperture fill structure includes a vertical stack of memory elements and a vertical semiconductor channel; in: The memory opening filling structure is arranged in columns extending in a second horizontal direction perpendicular to the first horizontal direction; and The average number of memory opening fill structures extending through each of the drain-side selected gate electrodes in the drain-side selected gate electrodes is a non-integer greater than zero.

2. The memory device according to claim 1, wherein: A pair of adjacent drain-side select electrodes are laterally separated from each other along the second horizontal direction by a drain-selection stage dielectric isolation structure; and The average number of complete memory opening-fill structures in each column of the memory opening-fill structures that are not cut by the drain-select-level dielectric isolation structure, extending through each drain-side selected-gate electrode in the drain-side selected-gate electrode, is a non-integer greater than zero.

3. The memory device of claim 1, wherein the column comprises a repeating group of an X column containing C memory opening fill structures followed by a Y column containing C+1 or C-1 memory opening fill structures, wherein C is an integer equal to or greater than 2, X is an integer equal to or greater than 2, and Y is an integer equal to or greater than 1.

4. The memory device of claim 1, further comprising a plurality of bit lines extending in the second horizontal direction and electrically connected to corresponding drain regions in the memory aperture fill structure, wherein the bit lines have a pitch along the first horizontal direction, the pitch being equal to the pitch of the column of the memory aperture fill structure along the first horizontal direction hd1 divided by an odd integer.

5. The memory device of claim 1, wherein the alternating stack comprises memory blocks, and at least two drain-side selected gate electrodes are present at each vertical level of the memory blocks.

6. The memory device according to claim 5, wherein: The alternating stack is located between a first lateral isolation trench filling structure and a second lateral isolation trench filling structure, the first and second lateral isolation trench filling structures extending laterally along a first horizontal direction and laterally spaced apart from each other along a second horizontal direction. The word line extends laterally from the first lateral isolation trench filling structure to the second lateral isolation trench filling structure; The drain-side selected gate electrodes are laterally spaced from each other along the second horizontal direction by at least one drain-select level dielectric isolation structure that extends generally along the first horizontal direction. The memory openings extend vertically through the alternating stacks and are arranged in multiple rows, which extend along the first horizontal direction and are laterally spaced from each other along the second horizontal direction; The memory opening filling structure is located in the memory opening; Each set of memory opening filling structures, extending vertically between corresponding adjacent pairs of isolation structures selected from the first lateral isolation trench filling structure, the second lateral isolation trench filling structure, and the at least one drain selection level dielectric isolation structure, defines a memory string group. and Each memory string group includes all memory opening fill structures within a corresponding set of memory opening fill structures in each row, and includes a non-zero fraction of memory opening fill structures within a corresponding additional row memory opening fill structure, the non-zero fraction being smaller than the total number of memory opening fill structures in the corresponding additional row.

7. The memory device of claim 6, wherein at least one of the drain select level dielectric isolation structures has a lateral undulation along the second horizontal direction.

8. The memory device according to claim 7, wherein: The drain-selective dielectric isolation structure in the at least one drain-selective dielectric isolation structure is located between an adjacent pair of memory strings, including a first memory string and a second memory string; and The drain-select-level dielectric isolation structure in the at least one drain-select-level dielectric isolation structure meanders around the additional row memory opening-fill structure, such that a first subgroup of the memory opening-fill structure within the row memory opening-fill structure belongs to the first memory string group, and a second subgroup of the memory opening-fill structure belongs to the second memory string group.

9. The memory device of claim 8, wherein each Nth memory opening fill structure within the row memory opening fill structure belongs to the first memory string group, and all other memory opening structures within the row memory opening fill structure belong to the second memory string group, wherein N is an integer greater than 1 and less than 13.

10. The memory device according to claim 7, wherein: The at least one drain-selective dielectric isolation structure is composed of a single drain-selective dielectric isolation structure; and The non-zero fraction is 1 / 2.

11. The memory device according to claim 7, wherein: M memory string groups are located between the first lateral isolation trench filling structure and the second lateral isolation trench filling structure; The at least one drain-selective dielectric isolation structure comprises (M-1) drain-selective dielectric isolation structures; and M is an integer equal to or greater than 2.

12. The memory device of claim 11, wherein: M is an odd number greater than 2; and Each of the (M-1) drain-select-level dielectric isolation structures meanders around the corresponding row memory opening-fill structure, such that a first non-zero fraction of the memory opening-fill structure in the corresponding row is located on a first side of the corresponding drain-select-level dielectric isolation structure, and a second non-zero fraction of the memory opening-fill structure is located on a second side of the corresponding drain-select-level dielectric isolation structure.

13. The memory device according to claim 11, wherein: M is an even number greater than 3; At least two, and less than (M-1), of the (M-1) drain-selection dielectric isolation structures meander around the corresponding row memory opening-fill structure, such that a first non-zero fraction of the memory opening-fill structures in the corresponding row are located on the first side of the corresponding drain-selection dielectric isolation structure, and a second non-zero fraction of the memory opening-fill structures are located on the second side of the corresponding drain-selection dielectric isolation structure; and At least one of the (M-1) drain-selection dielectric isolation structures extends laterally in a straight line along the first horizontal direction.

14. The memory device according to claim 6, wherein: M memory string groups are located between the first lateral isolation trench filling structure and the second lateral isolation trench filling structure; and For two memory string groups among the M memory string groups, the non-zero fraction is given by K / M, where M is an integer greater than 1 and less than 13, and K is a positive integer less than M.

15. The memory device according to claim 6, wherein: Each row of memory slot fill structures includes Q memory slot fill structures; and each memory string group includes (P+K / M)×Q memory slot fill structures, where P is an integer greater than 1, M is an integer greater than 1 and less than 13, and K is a positive integer less than M.

16. The memory device of claim 15, further comprising bit lines extending laterally along the second horizontal direction and electrically connected to corresponding subgroups of the drain regions of the memory aperture-filled structure.

17. The memory device of claim 16, wherein: P is an even number; For each of the M memory string groups, the first subgroup of the bit lines is electrically connected to the corresponding drain region within the memory string group, and the second subgroup of the bit lines is electrically isolated from each drain region within the memory string group. and The total number of bit lines electrically connected to the drain regions within the memory string is the same as the total number of drain regions within the memory string.

18. The memory device of claim 16, wherein the total number of bit lines is (P+1)×Q.

19. A memory device, the memory device comprising: An alternating stack of insulating and conductive layers, wherein the alternating stack is located between a first lateral isolation trench fill structure and a second lateral isolation trench fill structure, the first and second lateral isolation trench fill structures extending laterally along a first horizontal direction and laterally spaced apart from each other along a second horizontal direction, wherein the conductive layer includes word lines extending laterally from the first lateral isolation trench fill structure to the second lateral isolation trench fill structure, and further includes at least one drain select electrode layer overlying the word lines, wherein each of the at least one drain select electrode layer includes a corresponding plurality of drain select electrode strips, the corresponding plurality of drain select electrode strips being laterally spaced apart from each other along the second horizontal direction by at least one drain select level dielectric isolation structure extending generally along the first horizontal direction; A memory opening extends vertically through the alternating stack and is arranged in multiple rows such that each of the multiple rows is arranged along the first horizontal direction and adjacent rows are laterally spaced from each other along the second horizontal direction. and A memory aperture filling structure is located in the memory aperture, wherein each set of memory aperture filling structures extending vertically between a corresponding adjacent pair of isolation structures selected from the first lateral isolation trench filling structure, the second lateral isolation trench filling structure, and the at least one drain selection level dielectric isolation structure defines a memory string group, and each memory string group includes all memory aperture filling structures within a corresponding set of each row of memory aperture filling structures, and includes a non-zero fraction of memory aperture filling structures within a corresponding additional row of memory aperture filling structures, the non-zero fraction being smaller than the total number of memory aperture filling structures within the corresponding additional row.

20. The memory device of claim 19, wherein: One of the at least one drain-selection dielectric isolation structures has a lateral undulation along the second horizontal direction; The drain-selective dielectric isolation structure in the at least one drain-selective dielectric isolation structure is located between an adjacent pair of memory strings, including a first memory string and a second memory string; and The drain-selection dielectric isolation structure in the at least one drain-selection dielectric isolation structure meanders around a row of memory aperture filling structures, such that a first subgroup of the memory aperture filling structures within the row of memory aperture filling structures belongs to the first memory string group, and a second subgroup of the memory aperture filling structures belongs to the second memory string group.

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