High-precision low-ripple current sampling circuit applied to battery management chip
By introducing a three-input pair chopper operational amplifier and a ripple suppression circuit into the battery management chip, the problem of ripple influence in the current sampling circuit is solved, achieving high-precision current sampling and improving the accuracy and stability of current sampling.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- XIAN UNIV OF TECH
- Filing Date
- 2026-01-23
- Publication Date
- 2026-04-24
AI Technical Summary
Existing battery management chips have a problem with current sampling circuits where ripple affects current sampling accuracy. In particular, the ripple at the output of the chopper operational amplifier increases the performance requirements of the subsequent low-pass filter, thus limiting the accuracy of current sampling.
A three-input pair chopper operational amplifier and ripple suppression circuit are used. The voltage signal multiple is restored by adjusting the resistor ratio in the high-pass filter. The high-frequency ripple signal is demodulated synchronously using a Gilbert unit. The loop is transferred from the continuous time domain to the discrete time domain by a discrete integrator. Combined with circuit timing control, the transconductance stage offset voltage is compensated.
It significantly improves current sampling accuracy, effectively suppresses ripple, prevents output saturation, reduces circuit design complexity, and enhances current sampling accuracy.
Smart Images
Figure CN121917830A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of battery management chip technology and relates to a high-precision, low-ripple current sampling circuit for use in battery management chips. Background Technology
[0002] As humanity enters a new phase of rapid development, the pursuit of quality of life continues to rise, and the functional requirements of various electronic products are constantly upgrading, placing increasingly stringent demands on battery performance. Among the many types of batteries, lithium batteries have been widely used in various intelligent devices due to their numerous outstanding advantages. They not only possess high energy density, stable operating voltage, and long service life, but also offer advantages such as being environmentally friendly, having high charging efficiency, and being lightweight, perfectly meeting the development needs of modern intelligent devices. However, they also pose significant safety hazards. During charging and discharging, lithium batteries may experience overcharging, over-discharging, or short circuits, leading to overheating, expansion, or even explosion, damaging battery performance and lifespan. Therefore, battery management chips are needed to monitor the charging and discharging current of the battery pack.
[0003] Since the total voltage of a multi-cell series-connected lithium battery pack can reach tens of volts, to avoid using high-voltage MOSFETs and save chip area, the battery current sampling circuit typically uses low-side current sampling, such as... Figure 1 As shown, the sensing resistor is placed between the load and ground. The voltage difference across the sensing resistor is sampled by the current sampling circuit and amplified to the quantization range of the subsequent ADC.
[0004] In circuit design, due to the small voltage difference across the sensing resistor, the offset voltage of the op-amp will cause a non-negligible accuracy error in the current sampling circuit during voltage amplification. To eliminate the influence of the op-amp offset voltage, chopping technology is used. However, ripple caused by offset voltage and flicker noise will be generated at the op-amp output, which seriously affects the accuracy of the current sampling circuit. Summary of the Invention
[0005] The purpose of this invention is to provide a high-precision, low-ripple current sampling circuit for battery management chips, which solves the problem in the prior art where the output of the chopper operational amplifier has large ripple, which increases the performance requirements of the subsequent low-pass filter and thus restricts the accuracy of the current sampling circuit.
[0006] The technical solution adopted in this invention is a high-precision, low-ripple current sampling circuit for battery management chips, including a three-input pair chopper operational amplifier op1. The input terminal of the three-input pair chopper operational amplifier op1 is connected to the differential voltage signal on the current sensing resistor through a chopper switch CH1. The output terminal of the three-input pair chopper operational amplifier op1 is connected to the input terminal of a low-pass filter LPF. The output of the low-pass filter LPF is the sampling result Vout.
[0007] The invention is further characterized by:
[0008] The output of the three-input transistor chopper op-amp ... The output of the three-input transistor chopper op-amp ... The output of the three-input transistor chopper op-amp ...
[0009] The three-input pair transistor chopper operational amplifier OP1 includes an input stage circuit, an intermediate stage circuit, and an output stage circuit connected in sequence. The input stage circuit includes the Gm1 circuit, the Gm2 circuit, and the Gm3 circuit. The Gm1 circuit includes transistors Mp2 and Mp3. The gates of transistors Mp2 and Mp3 are connected to the input signals Vin+ and Vin- respectively via chopper switch CH1. The sources of transistors Mp2 and Mp3 are connected to the drain of transistor Mp1. The gate of transistor Mp1 is connected to the bias voltage Vb1, and the source of transistor Mp1 is connected to the power supply voltage VDD. The source of transistor Mp2 is connected to the drain of transistor Mn1, and the drain of transistor Mp3 is connected to the drain of transistor Mn2.
[0010] The Gm2 circuit includes transistors Mp5 and Mp6. The gates of transistors Mp5 and Mp6 are connected to signals Vo and VA respectively via chopper switch CH2. The sources of transistors Mp5 and Mp6 are connected to the drain of transistor Mp4. The gate of transistor Mp4 is connected to the bias voltage Vb1, and the source of transistor Mp4 is connected to the power supply voltage VDD. The source of transistor Mp5 is connected to the drain of transistor Mn1, and the drain of transistor Mp6 is connected to the drain of transistor Mn2.
[0011] The Gm3 circuit includes transistors Mp15 and Mp16. The gates of transistors Mp15 and Mp16 are connected to signals Vaz+ and Vaz-, respectively. The sources of transistors Mp15 and Mp16 are connected to the drain of transistor Mp14. The gate of transistor Mp14 is connected to the bias voltage Vb1, and the source of transistor Mp14 is connected to the power supply voltage VDD. The source of transistor Mp15 is connected to the drain of transistor Mn2, and the drain of transistor Mp16 is connected to the drain of transistor Mn1.
[0012] The intermediate stage circuit includes transistors Mn1 and Mn2. The source of transistor Mn1 and the source of transistor Mn2 are grounded. The drain of transistor Mn1 is connected to the source of transistor Mn3 through chopper switch CH3. The drain of transistor Mn2 is connected to the source of transistor Mn4 through chopper switch CH3. The drain of transistor Mn3 is connected to the source of transistor Mn5 and the drain of transistor Mp11. The drain of transistor Mn5 and the source of transistor Mp11 are connected to the drain of transistor Mp9. The source of transistor Mp9 is connected to the drain of transistor Mp7 through chopper switch CH4. The source of transistor Mp7 is connected to the power supply voltage VDD. The gate of transistor Mp7 is connected to the gate of transistor Mp8. The drain of transistor Mn4 is connected to the source of transistor Mn6, the drain of transistor Mp12, and the gate of transistor Mn7. The drain of transistor Mn6 and the source of transistor Mp12 are connected to the drain of transistor Mp10 and the gate of transistor Mp13. The source of transistor Mp10 is connected to the drain of transistor Mp8 through chopper switch CH4. The source of transistor Mp8 is connected to the power supply voltage VDD. The gates of transistor Mp7 and Mp8 are connected to the drain of transistor Mp9 through chopper switch CH4. The gates of transistors Mn1 and Mn2 are connected to the bias voltage Vb6; the gates of transistors Mn3 and Mn4 are connected to the bias voltage Vb5; the gates of transistors Mn5 and Mn6 are connected to the bias voltage Vb3; the gates of transistors Mp9 and Mp10 are connected to the bias voltage Vb2; and the gates of transistors Mp11 and Mp12 are connected to the bias voltage Vb4.
[0013] The output stage circuit includes transistor Mn7, the source of transistor Mn7 is grounded, the drain of transistor Mn7 is connected to the drain of transistor Mp13, and the source of transistor Mp13 is connected to the power supply voltage VDD. The drain of transistor Mn7 and the drain of transistor Mp13 are connected to one end of capacitor C2. The other end of capacitor C2 is connected to one end of resistor R5. The other end of resistor R5 is connected to the drain of transistor Mp10, the gate of transistor Mp13, the source of transistor Mn6, and the drain of transistor Mp12. The drain of transistor Mn7 and the drain of transistor Mp13 are connected to one end of capacitor C3. The other end of capacitor C3 is connected to one end of resistor R6. The other end of resistor R6 is connected to the drain of transistor Mn6, the source of transistor Mp12, the drain of transistor Mn4, and the gate of transistor Mn7.
[0014] The input terminal of the low-pass filter LPF is connected to the drain of transistor Mn7 and the drain of transistor Mp13. The low-pass filter LPF includes a resistor R7. One end of the resistor R7 is connected to the drain of transistor Mn7 and the drain of transistor Mp13. The other end of the resistor R7 is connected to one end of capacitor C4. The other end of capacitor C4 is grounded. The connection between resistor R7 and capacitor C4 is the output terminal of the low-pass filter LPF.
[0015] The ripple suppression circuit includes a high-pass filter, a Gilbert unit, and a switched capacitor integrator connected in sequence. The high-pass filter includes a capacitor C1, a resistor R3, and a resistor R4 connected in sequence. The end of capacitor C1 away from resistor R3 is connected to the signal Vo. The end of resistor R4 away from resistor R3 is grounded. The end of resistor R3 and resistor R4 connected to one input terminal of the Gilbert cell, the common-mode level VCM. The other input terminal of the Gilbert cell is connected to the common-mode level VCM. The Gilbert cell is connected to the control signals VLO+ and VLO- respectively.
[0016] The switched capacitor integrator includes switches S1 and S2; one end of switch S1 is connected to the non-inverting output terminal VO1 of the Gilbert unit, the other end of switch S1 is connected to one end of switch S3 and one end of sampling capacitor Cs1, the other end of switch S3 is connected to the common-mode level VCM, the other end of sampling capacitor Cs1 is connected to one end of switch S5 and one end of switch S7, the other end of switch S5 is connected to the common-mode level VCM, the other end of switch S7 is connected to one end of switch S9, one end of integrating capacitor Cf1 and the non-inverting input terminal of operational amplifier op2, the other end of switch S9 is connected to the common-mode level VCM, and the other end of integrating capacitor Cf1 is connected to the inverting output terminal of operational amplifier op2 and the signal Vaz-. One end of switch S2 is connected to the non-inverting output terminal VO2 of the Gilbert unit. The other end of switch S2 is connected to one end of switch S4 and one end of sampling capacitor Cs2. The other end of switch S4 is connected to the common-mode level VCM. The other end of sampling capacitor Cs2 is connected to one end of switch S6 and one end of switch S8. The other end of switch S6 is connected to the common-mode level VCM. The other end of switch S8 is connected to one end of switch S10, one end of integrating capacitor Cf2, and the inverting input terminal of operational amplifier op2. The other end of switch S10 is connected to the common-mode level VCM. The other end of integrating capacitor Cf2 is connected to the non-inverting output terminal of operational amplifier op2 and the signal Vaz+.
[0017] The beneficial effects of this invention are as follows: This invention restores the voltage signal multiple by adjusting the resistor ratio in the high-pass filter, uses the Gilbert unit to synchronously complete the demodulation of high-frequency ripple signals and the conversion from single-ended input to double-ended output, and uses a discrete integrator to transfer the loop from the continuous time domain to the discrete time domain, fundamentally avoiding the stability problem of continuous loops. It also allows the detection point to be placed directly at the output of the chopper operational amplifier, thereby completely capturing the original ripple information and significantly improving the effective suppression of ripple. At the same time, the circuit timing control solves the offset voltage of the transconductance stage Gm3, improving the current sampling accuracy. Attached Figure Description
[0018] Figure 1 This is a schematic diagram of a low-side current sampling scheme used in existing battery management chips. Figure 2 This is a schematic diagram of the overall structure of the high-precision, low-ripple current sampling circuit of the present invention applied to a battery management chip; Figure 3 This is a schematic diagram of the circuit structure of the three-input pair chopper operational amplifier op1 in this invention; Figure 4 This is a schematic diagram of the circuit structure of the ripple suppression loop in this invention; Figure 5 This is a schematic diagram of the working timing of the high-precision, low-ripple current sampling circuit applied to a battery management chip according to the present invention. Detailed Implementation
[0019] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.
[0020] Example 1 This embodiment proposes a high-precision, low-ripple current sampling circuit for battery management chips, including a three-input transistor chopper operational amplifier (op1). The input terminal of op1 is connected to the differential voltage signal across the current sensing resistor via a chopper switch CH1. The output terminal of op1 is connected to the input terminal of a low-pass filter (LPF), and the output of LPF is the sampling result Vout. The output terminal of op1 is connected to its input terminal via a ripple suppression circuit. The output terminal of op1 is also connected to its input terminal via a chopper switch CH2. Furthermore, the output terminal of op1 is connected to its input terminal sequentially via an adjusting resistor R1 and the chopper switch CH2. One end of the adjusting resistor R1 away from the output terminal of op1 is connected to one end of the adjusting resistor R2, and the other end of the adjusting resistor R2 is connected to the reference voltage Vref.
[0021] Example 2 Based on Example 1, this example proposes a three-input pair transistor chopper operational amplifier op1, which includes an input stage circuit, an intermediate stage circuit, and an output stage circuit connected in sequence. The input stage circuit includes Gm1 circuit, Gm2 circuit, and Gm3 circuit. The Gm1 circuit includes transistors Mp2 and Mp3. The gates of transistors Mp2 and Mp3 are connected to the input signals Vin+ and Vin- respectively via chopper switch CH1. The sources of transistors Mp2 and Mp3 are connected to the drain of transistor Mp1. The gate of transistor Mp1 is connected to the bias voltage Vb1, and the source of transistor Mp1 is connected to the power supply voltage VDD. The source of transistor Mp2 is connected to the drain of transistor Mn1, and the drain of transistor Mp3 is connected to the drain of transistor Mn2.
[0022] The Gm2 circuit includes transistors Mp5 and Mp6. The gates of transistors Mp5 and Mp6 are connected to signals Vo and VA respectively via chopper switch CH2. The sources of transistors Mp5 and Mp6 are connected to the drain of transistor Mp4. The gate of transistor Mp4 is connected to the bias voltage Vb1, and the source of transistor Mp4 is connected to the power supply voltage VDD. The source of transistor Mp5 is connected to the drain of transistor Mn1, and the drain of transistor Mp6 is connected to the drain of transistor Mn2.
[0023] The Gm3 circuit includes transistors Mp15 and Mp16. The gates of transistors Mp15 and Mp16 are connected to signals Vaz+ and Vaz-, respectively. The sources of transistors Mp15 and Mp16 are connected to the drain of transistor Mp14. The gate of transistor Mp14 is connected to the bias voltage Vb1, and the source of transistor Mp14 is connected to the power supply voltage VDD. The source of transistor Mp15 is connected to the drain of transistor Mn2, and the drain of transistor Mp16 is connected to the drain of transistor Mn1.
[0024] Example 3 Based on Example 2, this example proposes an intermediate stage circuit including transistors Mn1 and Mn2. The sources of transistors Mn1 and Mn2 are grounded. The drain of transistor Mn1 is connected to the source of transistor Mn3 via chopper switch CH3. The drain of transistor Mn2 is connected to the source of transistor Mn4 via chopper switch CH3. The drain of transistor Mn3 is connected to the source of transistor Mn5 and the drain of transistor Mp11. The drains of transistor Mn5 and the source of transistor Mp11 are connected to the drain of transistor Mp9. The source of transistor Mp9 is connected to the drain of transistor Mp7 via chopper switch CH4. The source of transistor Mp7 is connected to the power supply voltage VDD. The gate of transistor Mp7 is connected to the gate of transistor Mp8. The drain of transistor Mn4 is connected to the source of transistor Mn6, the drain of transistor Mp12, and the drain of transistor Mn4. The gate of transistor Mp7 is connected to the drain of transistor Mn6, the source of transistor Mp12 is connected to the drain of transistor Mp10, and the gate of transistor Mp13 is connected to the drain of transistor Mp8 via chopper switch CH4. The source of transistor Mp8 is connected to the power supply voltage VDD. The gates of transistor Mp7 and Mp8 are connected to the drain of transistor Mp9 via chopper switch CH4. The gates of transistor Mn1 and Mn2 are connected to the bias voltage Vb6. The gates of transistor Mn3 and Mn4 are connected to the bias voltage Vb5. The gates of transistor Mn5 and Mn6 are connected to the bias voltage Vb3. The gates of transistor Mp9 and Mp10 are connected to the bias voltage Vb2. The gates of transistor Mp11 and Mp12 are connected to the bias voltage Vb4.
[0025] Example 4 Based on Embodiment 3, this embodiment proposes an output stage circuit including transistor Mn7, with the source of transistor Mn7 grounded, the drain of transistor Mn7 connected to the drain of transistor Mp13, and the source of transistor Mp13 connected to the power supply voltage VDD; the drains of transistor Mn7 and Mp13 are connected to one end of capacitor C2, the other end of capacitor C2 is connected to one end of resistor R5, and the other end of resistor R5 is connected to the drain of transistor Mp10, the gate of transistor Mp13, the source of transistor Mn6, and the drain of transistor Mp12; the drains of transistor Mn7 and Mp13 are connected to one end of capacitor C3, the other end of capacitor C3 is connected to one end of resistor R6, and the other end of resistor R6 is connected to the drain of transistor Mn6, the source of transistor Mp12, the drain of transistor Mn4, and the gate of transistor Mn7.
[0026] Example 5 Based on Example 4, this example proposes that the input terminal of the low-pass filter LPF is connected to the drain of transistor Mn7 and the drain of transistor Mp13. The low-pass filter LPF includes a resistor R7, one end of which is connected to the drain of transistor Mn7 and the drain of transistor Mp13, and the other end of which is connected to one end of capacitor C4. The other end of capacitor C4 is grounded, and the connection between resistor R7 and capacitor C4 is the output terminal of the low-pass filter LPF.
[0027] Example 6 Based on Example 5, this example proposes a ripple suppression circuit comprising a high-pass filter, a Gilbert unit, and a switched capacitor integrator connected in sequence. The high-pass filter includes a capacitor C1, a resistor R3, and a resistor R4 connected in sequence. The end of capacitor C1 away from resistor R3 is connected to the signal Vo. The end of resistor R4 away from resistor R3 is grounded. The end of resistor R3 and resistor R4 connected to one input terminal of the Gilbert cell, the common-mode level VCM. The other input terminal of the Gilbert cell is connected to the common-mode level VCM. The Gilbert cell is connected to the control signals VLO+ and VLO- respectively.
[0028] The switched-capacitor integrator includes switches S1 and S2. One end of switch S1 is connected to the non-inverting output VO1 of the Gilbert unit. The other end of switch S1 is connected to one end of switch S3 and one end of sampling capacitor Cs1. The other end of switch S3 is connected to the common-mode level VCM. The other end of sampling capacitor Cs1 is connected to one end of switch S5 and one end of switch S7. The other end of switch S5 is connected to the common-mode level VCM. The other end of switch S7 is connected to one end of switch S9, one end of integrating capacitor Cf1, and the non-inverting input of operational amplifier op2. The other end of switch S9 is connected to the common-mode level VCM. The other end of integrating capacitor Cf1 is connected to the inverting output of operational amplifier op2. Signal Vaz- is connected; one end of switch S2 is connected to the non-inverting output terminal VO2 of the Gilbert unit, the other end of switch S2 is connected to one end of switch S4 and one end of sampling capacitor Cs2, the other end of switch S4 is connected to the common-mode level VCM, the other end of sampling capacitor Cs2 is connected to one end of switch S6 and one end of switch S8, the other end of switch S6 is connected to the common-mode level VCM, the other end of switch S8 is connected to one end of switch S10, one end of integrating capacitor Cf2, and the inverting input terminal of operational amplifier op2, the other end of switch S10 is connected to the common-mode level VCM, the other end of integrating capacitor Cf2 is connected to the non-inverting output terminal of operational amplifier op2 and signal Vaz+.
[0029] This invention adds an input pair to the traditional DDA circuit. A differential voltage signal with the same amplitude but opposite phase as the ripple is generated by the ripple suppression loop. This input pair is converted into a compensation current to suppress ripple inside the operational amplifier, thereby reducing output ripple and improving current sampling accuracy.
[0030] like Figure 2 As shown, the high-precision low-ripple current sampling circuit of the present invention applied to the battery management chip includes a three-input pair transistor chopper operational amplifier op1, a low-pass filter, and a ripple suppression loop. The output of the low-pass filter is used as the sampling result Vout of the final current sampling circuit.
[0031] This invention uses a three-input transistor chopper operational amplifier op1 as the main operational amplifier of the current detection circuit, such as... Figure 3 As shown, the three-input pair chopper op-amp op-amp op-amp includes: Transistors Mp1, Mp2, and Mp3 form the Gm1 input pair. Input signals Vin+ and Vin- are connected to the gates of transistors Mp2 and Mp3, respectively. The sources of transistors Mp2 and Mp3 are simultaneously connected to the drain of transistor Mp1. The source of Mp1 is connected to the power supply voltage VDD. The drain of transistor Mp2 is connected to the drain of Mn1, and the drain of transistor Mp3 is connected to the drain of Mn2.
[0032] Transistors Mp4, Mp5, and Mp6 form the Gm2 input pair. Signals Vo and VA are connected to the gates of transistors MP5 and MP6, respectively. The sources of transistors Mp5 and Mp6 are simultaneously connected to the drain of transistor Mp4. The source of Mp4 is connected to the power supply voltage VDD. The drain of transistor Mp5 is connected to the drain of Mn1, and the drain of transistor Mp6 is connected to the drain of Mn2.
[0033] Transistors Mp14, Mp15, and Mp16 form the Gm3 input pair. Signals Vaz+ and Vaz- are connected to the gates of transistors MP15 and MP16, respectively. The sources of transistors Mp15 and Mp16 are simultaneously connected to the drain of transistor Mp14. The source of Mp14 is connected to the power supply voltage VDD. The drain of transistor Mp15 is connected to the drain of Mn2, and the drain of transistor Mp16 is connected to the drain of Mn1.
[0034] The sources of transistors Mn1 and Mn2 are grounded simultaneously. The gates of transistors Mp1, Mp4, and Mp14 are connected to the same bias voltage Vb1 to ensure that the load current of each input pair is equal. The sources of transistors Mn1 and Mn2 are grounded simultaneously. Resistors R5 and R6, capacitor C2, and resistor C3 constitute a frequency compensation module. During the reset phase of the switched capacitor integrator, switches S1~S8 are open and S9~S10 are closed. Operational amplifier op2 is connected to the common-mode input level VCM, generating a common-mode output level of equal magnitude and constant value. The non-inverting output terminal of op2 is connected to the gate of transistor Mp15, and the inverting output terminal is connected to the gate of transistor Mp16, thereby ensuring that the transconductance stage Gm3 operates at the set static operating point. During this period, transconductance stages Gm1 and Gm2 complete the sampling of the charging and discharging current signal, and finally generate an amplified DC signal at the output Vo. This signal contains the ripple components introduced by the offset voltage and flicker noise present in the transconductance stages Gm1, Gm2, Gm3 and intermediate stage circuits. The sampling phase completes the sampling of the ripple amplitude. During the holding phase, a differential voltage signal with the same amplitude and opposite direction as the ripple is generated at the output of op2. This signal is converted into a compensation current injected into the intermediate stage circuit through the transconductance stage Gm3, thereby effectively suppressing the ripple at the output Vo.
[0035] The transconductance stages Gm1 and Gm2, the intermediate stage circuit, and the output stage circuit form the main signal path. The differential voltage sampling signals Vin+ and Vin- across the current sensing resistor are summed at the output after passing through the transconductance stages Gm1 and Gm2, and then amplified by the intermediate and output stage circuits to obtain the final output voltage Vo. By adjusting the resistance ratio of resistors R1 and R2 and the value of the reference voltage Vref, the voltage sampling signal can be boosted and amplified. This can be achieved from the voltage divider relationship. However, the offset voltage and flicker noise present in the main path are reflected on the output Vo through chopper modulation, manifesting as output ripple. Assuming that there is an input offset voltage Vos in the transconductance stages Gm1 and Gm2, the actual output voltage... The offset voltage is amplified. To suppress output ripple, a low-pass filter (LPF) is typically introduced. However, in high-precision sampling applications, the performance requirements for the low-pass filter are quite stringent to effectively filter out this ripple. This often necessitates the use of extremely large resistors and capacitors to lower the cutoff frequency, thereby ensuring the system's accuracy and stability.
[0036] To reduce the impact of output ripple on current sampling accuracy, a ripple suppression loop is designed. By employing a switched-capacitor integrator and placing the loop in the discrete-time domain, precise circuit timing control achieves deep ripple suppression, preventing operational amplifier output saturation. Figure 4As shown, the ripple suppression loop consists of a high-pass filter, a Gilbert cell, and a switched-capacitor integrator. The high-pass filter (HPF) includes a capacitor C1 and two resistors R3 and R4. The upper stage of capacitor C1 is connected to the output of the chopper operational amplifier, and the lower stage is connected to one end of resistor R3. Resistor R4 is connected in series with R3, and the other end is grounded. This circuit couples out the ripple from the output of the chopper operational amplifier. By adjusting the resistance ratio of R3 and R4, the voltage signal amplified by the chopper operational amplifier is restored to the required multiple. The voltage divider node of the resistor series is used as the input node of the next stage. After passing through the Gilbert cell, the control signal VLO+ of the Gilbert cell is in phase and frequency with the chopper signal, while VLO- is out of phase and frequency with the chopper signal. Using this phase relationship, the high-frequency ripple signal is demodulated and restored to a low-frequency DC signal, simultaneously realizing the conversion from single-ended input to double-ended output.
[0037] The switched-capacitor integrator includes six MOS switches, two sampling capacitors Cs1 and Cs2, two integrating capacitors Cf1 and Cf2, and an operational amplifier op2. The input of switch S1 is connected to the non-inverting output VO1 of the previous stage, and its output is connected to the upper stage board of sampling capacitor Cs1. The upper stage board of sampling capacitor Cs1 is also connected to the output of switch S3, and the input of switch S3 is connected to the common-mode level VCM. The lower stage board of Cs1 is connected to both the output of switch S5 and the input of switch S7, and the input of switch S5 is connected to the common-mode level VCM. The output of switch S7 is simultaneously connected to the output of switch S9, the non-inverting input of op2, and the upper stage board of integrating capacitor Cf1. The input of switch S9 is connected to VCM. The lower stage board of integrating capacitor Cf1 is connected to the inverting output of op2. The input of switch S2 is connected to the inverting output VO2 of the previous stage, and its output is connected to the upper stage board of sampling capacitor Cs2. The upper stage board of sampling capacitor Cs2 is also connected to the output of switch S4. The input of switch S4 is connected to the common-mode level VCM. The lower stage board of Cs2 is connected to both the output of switch S6 and the input of switch S8. The input of switch S6 is connected to the common-mode level VCM. The output of switch S8 is simultaneously connected to the output of switch S10, the inverting input of operational amplifier op2, and the upper stage board of integrating capacitor Cf2. The input of switch S10 is connected to VCM. The lower stage board of integrating capacitor Cf2 is connected to the non-inverting output of operational amplifier op2. The integrator integrates the differential voltage signal to generate a compensation signal with the same amplitude but opposite phase to the ripple. By employing a discrete integrator, the ripple suppression loop is shifted from the continuous-time domain to the discrete-time domain, fundamentally avoiding the loop stability problem in continuous ripple suppression loop design. This not only reduces the complexity of circuit design but also allows the detection point to be placed directly at the output of the chopper operational amplifier, thus completely capturing the original ripple information. This significantly improves the effective ripple suppression depth and prevents output saturation caused by excessive ripple amplitude.
[0038] The current sampling circuit of this invention is used as follows: Step 1: Switches S1~S8 of the switched capacitor integrator are open, and S9~S10 are closed. The integrator is in the reset stage. The input terminal of op-amp op2 is connected to the common-mode level VCM. By designing the internal common-mode feedback circuit of op-amp, a common-mode output level of equal magnitude and specificity is generated to ensure that the compensation transconductance stage Gm3 is at the static operating point and no differential current flows into the intermediate stage circuit. In this process, the voltage signals Vin+ and Vin- across the current sensing resistor Rsense are first modulated into high-frequency signals by chopper switch CH1, and then input together with the low-frequency offset voltage Vos1 to the transconductance stage Gm1 for amplification. Simultaneously, the output signal Vo of operational amplifier op1 and the feedback voltage VA are modulated into high-frequency signals by chopper switch CH2, and amplified together with the low-frequency offset voltage signal Vos2 by the transconductance stage Gm2. These two sets of signals are summed at the output of the transconductance stage, and then demodulated into low-frequency DC signals by chopper switch CH3. The offset voltages Vos1 and Vos2 are modulated into high-frequency signals. Furthermore, chopper switch CH4 controls the current mirrors Mp7 and Mp... The offset present in step 8 is also modulated into a high-frequency component. The final signal, after processing by the intermediate and output stage circuits, appears as a low-frequency DC signal with superimposed high-frequency ripple at the output Vout. Simultaneously, due to limitations in manufacturing processes and device characteristics, the input pair Mp15 and Mp15 in the introduced transconductance stage Gm3 also exhibit device mismatch. This mismatch is equivalent to an offset voltage Vos3 at the output. This offset voltage is also converted into an offset current through the transconductance stage Gm3, flowing into the main path and subsequently modulated into a high-frequency signal by the chopper switch CH3. Ultimately, this results in ripple at the output Vo. Due to the connection relationship between the transconductance stage Gm3 and the main path, the magnitude of the ripple amplitude at the Vo end during the reset phase can actually be expressed as… .
[0039] Step 2: Switches S1, S2, S5, and S6 of the switched-capacitor integrator are closed, while S3, S4, S7, and S8 are open, putting the integrator in the sampling phase. The high-pass filter (HPF) includes a capacitor C1 and two resistors R3 and R4. The upper stage of capacitor C1 is connected to the output of the chopper operational amplifier, and the lower stage is connected to one end of resistor R3. Resistor R4 is connected in series with R3, and the other end is grounded. The high-frequency ripple signal at the output is sampled by the high-pass filter. By adjusting the resistance ratio of R3 and R4, the ripple signal amplified by the chopper operational amplifier is restored to the required multiple. The voltage divider node of resistors R3 and R4 is used as the input node of the next stage. After passing through the Girbert cell, the control signal VLO+ of the Girbert cell is in phase and frequency with the chopper signal, while VLO- is out of phase and frequency with the chopper signal. Using this phase relationship, the high-frequency ripple signal is demodulated and restored to a low-frequency DC signal, simultaneously realizing the conversion from single-ended input to double-ended output. Integrating capacitors Cs1 and Cs2 are connected to the output of the Girbert cell to sample the amplitude of the ripple voltage.
[0040] Step 3: Switches S1, S2, S5, S6, S9, and S10 of the switched capacitor integrator are open, while S3, S4, S7, and S8 are closed, putting the integrator in the integration phase. By setting the capacitance ratio of the sampling capacitor Cs to the integrating capacitor Cf to 1:1, capacitors Cf1 and Cf2 complete the integration of the ripple voltage amplitude. This results in the integrator's output terminal Vaz being superimposed with a differential voltage signal equal to the ripple voltage amplitude at the common-mode output level. This differential signal is directly sent to the input terminal of the transconductance stage Gm3 for voltage-to-current conversion. Specifically, Vaz+ is connected to the gate of the input pair transistor Mp15 of Gm3, and Vaz- is connected to the gate of Mp15. The transconductance stage Gm3 converts this differential voltage into a compensation current, which is injected into the main path to suppress the ripple component.
[0041] During the reset phase of this invention, the integrator operates at its static operating point, with no differential current flowing into the intermediate stage circuit. In this process, the voltage signals Vin+ and Vin- across the current sensing resistor Rsense are first modulated into high-frequency signals by chopper switch CH1, and then input together with the low-frequency offset voltage Vos1 to the transconductance stage Gm1 for amplification. Simultaneously, the output signal Vo of operational amplifier op1 and the feedback voltage VA are modulated into high-frequency signals by chopper switch CH2, and amplified together with the low-frequency offset voltage signal Vos2 by the transconductance stage Gm2. These two sets of signals are summed at the output of the transconductance stage, and then demodulated into low-frequency DC signals by chopper switch CH3. The offset voltages Vos1 and Vos2 are modulated into high-frequency signals. Furthermore, chopper switch CH4 also modulates the offset present in the current mirrors Mp7 and Mp8 into high-frequency components. The final signal is processed by the intermediate stage and output stage circuits, and at the output Vout, it appears as a low-frequency DC signal superimposed with high-frequency ripple. During the sampling stage, the sampling capacitors Cs1 and Cs2 in the integrator sample the ripple signal output by the Girbert cell. During the integration stage, capacitors Cf1 and Cf2 integrate the amplitude of the ripple voltage. The final result is that at the output Vaz of the integrator, a differential voltage signal with a magnitude approximately equal to the amplitude of the ripple voltage is superimposed on the common-mode output level. This differential signal is directly sent to the input of the transconductance stage Gm3 for voltage-to-current conversion. This current is injected into the main path to resolve most of the offset voltage. The residual offset is further suppressed by the chopper operational amplifier and low-pass filter, improving the current sampling accuracy.
[0042] This invention introduces precise timing control. During the reset phase of the switched-capacitor integrator, the equivalent input offset voltage Vos3 is converted into an offset current through Gm3 and flows into the main path. Subsequently, it is modulated into a high-frequency signal by the chopper switch CH3, ultimately manifesting as ripple at the output Vo of the chopper operational amplifier. Due to the connection relationship between the transconductance stage Gm3 and the main path, the magnitude of the ripple amplitude at the Vo terminal during the reset phase can be expressed as follows: Therefore, during the sampling phase, the ripple information at the Vo terminal (including the ripple caused by Vos3) is sampled by sampling capacitors Cs1 and Cs2. During the integration phase, this sampled charge is integrated by integrating capacitors Cf1 and Cf2, generating a corresponding compensation voltage at the output of the integrator. This compensation voltage is superimposed on the common-mode output level of the integrator in the form of a differential signal, and flows into the main path through the transconductance stage Gm3 to convert the compensation current, thereby effectively offsetting the influence introduced by the mismatch between the Gm3 input pair and the transistor.
[0043] In the reset phase of the integrator, the input of operational amplifier op2 is connected to a common-mode level VCM. An internal common-mode feedback circuit is designed to generate a specific common-mode output level of equal magnitude, providing static bias to the transconductance stage Gm3. No differential current flows into the intermediate stage circuit. However, due to limitations in manufacturing process and device characteristics, this mismatch is equivalent to an offset voltage Vos3 at the output. This offset voltage is converted into an offset current flowing into the main path through the transconductance stage Gm3. During this process, the voltage signals Vin+ and Vin- across the current sensing resistor Rsense are first modulated into high-frequency signals by chopper switch CH1, and then input together with the low-frequency offset voltage Vos1 to the main circuit. The transconductance stage Gm1 amplifies the signal. Simultaneously, the output signal Vo of operational amplifier op1 and the feedback voltage VA are modulated into a high-frequency signal by chopper switch CH2. This high-frequency signal, along with the low-frequency offset voltage signal Vos2, is amplified by the transconductance stage Gm2. These three signals are summed at the output of the transconductance stage. Then, the input signal is demodulated into a low-frequency DC signal by chopper switch CH3, and the offset voltages Vos1, Vos2, and Vos3 are modulated into high-frequency signals. Furthermore, chopper switch CH4 modulates the offset present in current mirror tubes Mp7 and Mp8 into high-frequency components. Finally, the signal is processed by the intermediate stage and output stage circuits, resulting in a low-frequency DC signal with superimposed high-frequency ripple at the output Vout. + The ripple amplitude is During the sampling phase, the high-frequency ripple signal at the output terminal is sampled through a high-pass filter. The resistance ratio of R3 and R4 is adjusted to restore the ripple signal amplified by the chopper operational amplifier to the required multiple. Passing through the Girbert cell, the control signal VLO+ of the Girbert cell is in phase and frequency with the chopper signal, while VLO- is out of phase and frequency with the chopper signal. Utilizing this phase relationship, the high-frequency ripple signal is demodulated and restored to a low-frequency DC signal, simultaneously achieving the conversion from single-ended input to dual-ended output. Integrating capacitors Cs1 and Cs2 are connected to the output of the Girbert cell to sample the ripple voltage amplitude. During the integration phase, through charge transfer, capacitors Cf1 and Cf2 integrate the ripple voltage amplitude. Ultimately, the output Vaz of the integrator is superimposed with a differential voltage signal equal to the ripple voltage amplitude. This differential signal is directly sent to the input of the transconductance stage Gm3 for voltage-to-current conversion, generating a current signal opposite in phase to the offset current, which flows into the main path. Deep ripple suppression is achieved through precise circuit timing control.
[0044] This invention designs a ripple suppression loop that matches the characteristics of a current sampling circuit. The ripple suppression loop generates a compensation voltage, which is converted into a compensation current flowing into the main path through the transconductance stage Gm3, thus achieving output ripple suppression. By employing a discrete integrator, the loop is shifted from the continuous-time domain to the discrete-time domain, fundamentally avoiding the stability problems of continuous-time loops. Furthermore, this structure allows the loop detection point to be directly set at the output of the chopper operational amplifier, thereby obtaining the original ripple information, significantly improving the effective ripple suppression, effectively preventing chopper operational amplifier output saturation, and reducing the performance requirements of the subsequent low-pass filter (LPF). In addition, through precise circuit timing control, this invention can effectively solve the offset voltage problem existing in the compensation transconductance stage Gm3, further improving the overall accuracy of current sampling.
Claims
1. A high-precision, low-ripple current sampling circuit for battery management chips, characterized in that, It includes a three-input pair chopper operational amplifier op1. The input terminal of the three-input pair chopper operational amplifier op1 is connected to the differential voltage signal on the current sensing resistor through a chopper switch CH1. The output terminal of the three-input pair chopper operational amplifier op1 is connected to the input terminal of a low-pass filter LPF. The output of the low-pass filter LPF is the sampling result Vout.
2. The high-precision, low-ripple current sampling circuit for battery management chips according to claim 1, characterized in that, The output terminal of the three-input transistor chopper op-amp ... The output terminal of the three-input pair chopper operational amplifier op1 is connected to the input terminal of the three-input pair chopper operational amplifier op1 through chopper switch CH2; The output terminal of the three-input pair chopper op-amp ...
3. The high-precision, low-ripple current sampling circuit for battery management chips according to claim 2, characterized in that, The three-input pair chopper operational amplifier op1 includes an input stage circuit, an intermediate stage circuit, and an output stage circuit connected in sequence. The input stage circuit includes Gm1 circuit, Gm2 circuit, and Gm3 circuit. The Gm1 circuit includes transistors Mp2 and Mp3. The gates of transistors Mp2 and Mp3 are connected to the input signals Vin+ and Vin- respectively via chopper switch CH1. The sources of transistors Mp2 and Mp3 are connected to the drain of transistor Mp1. The gate of transistor Mp1 is connected to the bias voltage Vb1, and the source of transistor Mp1 is connected to the power supply voltage VDD. The source of transistor Mp2 is connected to the drain of transistor Mn1, and the drain of transistor Mp3 is connected to the drain of transistor Mn2.
4. The high-precision, low-ripple current sampling circuit for battery management chips according to claim 3, characterized in that, The Gm2 circuit includes transistors Mp5 and Mp6. The gates of transistors Mp5 and Mp6 are connected to signals Vo and VA respectively via chopper switch CH2. The sources of transistors Mp5 and Mp6 are connected to the drain of transistor Mp4. The gate of transistor Mp4 is connected to the bias voltage Vb1, and the source of transistor Mp4 is connected to the power supply voltage VDD. The source of transistor Mp5 is connected to the drain of transistor Mn1, and the drain of transistor Mp6 is connected to the drain of transistor Mn2.
5. The high-precision, low-ripple current sampling circuit for battery management chips according to claim 4, characterized in that, The Gm3 circuit includes transistors Mp15 and Mp16. The gates of transistors Mp15 and Mp16 are connected to signals Vaz+ and Vaz-, respectively. The sources of transistors Mp15 and Mp16 are connected to the drain of transistor Mp14. The gate of transistor Mp14 is connected to a bias voltage Vb1, and the source of transistor Mp14 is connected to a power supply voltage VDD. The source of transistor Mp15 is connected to the drain of transistor Mn2, and the drain of transistor Mp16 is connected to the drain of transistor Mn1.
6. The high-precision, low-ripple current sampling circuit for battery management chips according to claim 5, characterized in that, The intermediate stage circuit includes transistors Mn1 and Mn2. The source of transistor Mn1 and the source of transistor Mn2 are grounded. The drain of transistor Mn1 is connected to the source of transistor Mn3 through chopper switch CH3. The drain of transistor Mn2 is connected to the source of transistor Mn4 through chopper switch CH3. The drain of transistor Mn3 is connected to the source of transistor Mn5 and the drain of transistor Mp11. The drain of transistor Mn5 and the source of transistor Mp11 are connected to the drain of transistor Mp9. The source of transistor Mp9 is connected to the drain of transistor Mp7 through chopper switch CH4. The source of transistor Mp7 is connected to the power supply voltage VDD. The gate of transistor Mp7 is connected to the gate of transistor Mp8. The drain of transistor Mn4 is connected to the source of transistor Mn6, the drain of transistor Mp12, and the gate of transistor Mn7. The drain of transistor Mn6 and the source of transistor Mp12 are connected to the drain of transistor Mp10 and the gate of transistor Mp13. The source of transistor Mp10 is connected to the drain of transistor Mp8 via chopper switch CH4. The source of transistor Mp8 is connected to the power supply voltage VDD. The gates of transistor Mp7 and Mp8 are connected to the drain of transistor Mp9 via chopper switch CH4. The gates of transistors Mn1 and Mn2 are connected to the bias voltage Vb6. The gates of transistors Mn3 and Mn4 are connected to the bias voltage Vb5; the gates of transistors Mn5 and Mn6 are connected to the bias voltage Vb3. The gates of transistors Mp9 and Mp10 are connected to the bias voltage Vb2. The gates of transistors Mp11 and Mp12 are connected to the bias voltage Vb4.
7. The high-precision, low-ripple current sampling circuit for battery management chips according to claim 6, characterized in that, The output stage circuit includes transistor Mn7, the source of transistor Mn7 is grounded, the drain of transistor Mn7 is connected to the drain of transistor Mp13, and the source of transistor Mp13 is connected to the power supply voltage VDD. The drain of transistor Mn7 and the drain of transistor Mp13 are connected to one end of capacitor C2. The other end of capacitor C2 is connected to one end of resistor R5. The other end of resistor R5 is connected to the drain of transistor Mp10, the gate of transistor Mp13, the source of transistor Mn6, and the drain of transistor Mp12. The drain of transistor Mn7 and the drain of transistor Mp13 are connected to one end of capacitor C3. The other end of capacitor C3 is connected to one end of resistor R6. The other end of resistor R6 is connected to the drain of transistor Mn6, the source of transistor Mp12, the drain of transistor Mn4, and the gate of transistor Mn7.
8. The high-precision, low-ripple current sampling circuit for battery management chips according to claim 7, characterized in that, The input terminal of the low-pass filter LPF is connected to the drain of transistor Mn7 and the drain of transistor Mp13. The low-pass filter LPF includes a resistor R7, one end of which is connected to the drain of transistor Mn7 and the drain of transistor Mp13, and the other end of which is connected to one end of capacitor C4. The other end of capacitor C4 is grounded, and the connection point between resistor R7 and capacitor C4 is the output terminal of the low-pass filter LPF.
9. The high-precision, low-ripple current sampling circuit for battery management chips according to claim 8, characterized in that, The ripple suppression circuit includes a high-pass filter, a Gilbert unit, and a switched capacitor integrator connected in sequence. The high-pass filter includes a capacitor C1, a resistor R3, and a resistor R4 connected in sequence. The end of capacitor C1 away from resistor R3 is connected to the signal Vo. The end of resistor R4 away from resistor R3 is grounded. The end where resistor R3 and resistor R4 are connected is connected to one input terminal of the Gilbert unit and the common-mode level VCM. The other input terminal of the Gilbert unit is connected to the common-mode level VCM. The Gilbert unit is connected to the control signal VLO+ and the control signal VLO-, respectively.
10. The high-precision, low-ripple current sampling circuit for battery management chips according to claim 9, characterized in that, The switched capacitor integrator includes switches S1 and S2; one end of switch S1 is connected to the non-inverting output terminal VO1 of the Gilbert unit, the other end of switch S1 is connected to one end of switch S3 and one end of sampling capacitor Cs1, the other end of switch S3 is connected to the common-mode level VCM, the other end of sampling capacitor Cs1 is connected to one end of switch S5 and one end of switch S7, the other end of switch S5 is connected to the common-mode level VCM, the other end of switch S7 is connected to one end of switch S9, one end of integrating capacitor Cf1 and the non-inverting input terminal of operational amplifier op2, the other end of switch S9 is connected to the common-mode level VCM, and the other end of integrating capacitor Cf1 is connected to the inverting output terminal of operational amplifier op2 and the signal Vaz-. One end of switch S2 is connected to the non-inverting output terminal VO2 of the Gilbert unit. The other end of switch S2 is connected to one end of switch S4 and one end of sampling capacitor Cs2. The other end of switch S4 is connected to the common-mode level VCM. The other end of sampling capacitor Cs2 is connected to one end of switch S6 and one end of switch S8. The other end of switch S6 is connected to the common-mode level VCM. The other end of switch S8 is connected to one end of switch S10, one end of integrating capacitor Cf2, and the inverting input terminal of operational amplifier op2. The other end of switch S10 is connected to the common-mode level VCM. The other end of integrating capacitor Cf2 is connected to the non-inverting output terminal of operational amplifier op2 and the signal Vaz+.