Domain management apparatus for allocating super blocks and method of operating domain management

Abstract

Disclosed are a domain management apparatus for allocating a super block and a method of operating the domain management apparatus for allocating a super block. The method includes: counting a number of initial bad blocks in a plurality of memory chips included in a first domain of the nonvolatile memory device, respectively; selecting a first memory chip among the plurality of memory chips based on the number of initial bad blocks; replacing the first memory chip of the first domain with a second memory chip of a second domain of the non-volatile memory device; and allocating at least one super block of the reserved area to the excess configuration area in the first domain including the replaced second memory chip.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0146270, filed on October 24, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The embodiments of this disclosure described herein relate to methods for managing non-volatile memory devices, and more specifically, to a domain management device for allocating superblocks and a method for operating the domain management device for allocating superblocks. Background Technology

[0003] Memory devices store data in response to write requests and output the data stored therein in response to read requests. For example, memory devices are classified as volatile memory devices (such as dynamic random access memory (RAM) (DRAM) devices or static RAM (SRAM) devices) that lose data stored therein when power is disconnected, or as non-volatile memory devices (such as flash memory devices, phase-change RAM (PRAM), magnetic RAM (MRAM), or resistive RAM (RRAM)) that retain data stored therein even when power is disconnected.

[0004] Non-volatile memory devices may include multiple memory chips. Each of the multiple memory chips may include multiple memory blocks. A portion of the multiple memory blocks may be initially bad blocks due to the manufacturing process. The multiple memory chips may be managed on a domain basis. A domain may allocate reserved areas based on the initial bad blocks. Reserved areas may not store data. Summary of the Invention

[0005] Embodiments of this disclosure provide a domain management device for allocating superblocks and a method for operating the domain management device for allocating superblocks.

[0006] According to one aspect of this disclosure, a method of operating a domain management device that communicates with a non-volatile memory device may include: counting the number of initial bad blocks in a plurality of memory chips included in a first domain of the non-volatile memory device; selecting a first memory chip among the plurality of memory chips based on the number of initial bad blocks; replacing the first memory chip in the first domain with a second memory chip in a second domain of the non-volatile memory device; and allocating at least one superblock of a reserved region to an over-allocation region in the first domain including the replaced second memory chip.

[0007] According to another aspect of this disclosure, a method for operating a domain management device that communicates with a non-volatile memory device may include: counting the number of initial bad blocks in a plurality of memory chips included in a first domain and a second domain of the non-volatile memory device; distributing a plurality of bad memory chips identified from the plurality of memory chips between the first and second domains based on the number of initial bad blocks; performing a disk formatting operation on the first and second domains to which the plurality of bad memory chips are distributed; and after the disk formatting operation, allocating superblocks in reserved areas of the first and second domains to over-allocation areas; classifying superblocks into a first type supporting full superblock functionality and a second type supporting partial superblock functionality; and using either the first superblock classified as the first type or the second superblock classified as the second type based on the workload of the non-volatile memory device.

[0008] According to another aspect of this disclosure, a domain management apparatus may include: a memory chip information table configured to store first domain chip information and second domain chip information respectively included in a first domain and a second domain in a non-volatile memory device; and at least one processor configured to: count the number of initial bad blocks in a plurality of memory chips respectively included in a first domain; update the first domain chip information based on the counted number of initial bad blocks; select a first memory chip from a plurality of memory chips in the first domain and select a second memory chip from a plurality of memory chips in the second domain based on the first domain chip information and the second domain chip information; replace the first memory chip in the first domain with the second memory chip; update the first domain chip information and the second domain chip information to reflect the result of replacing the first memory chip with the second memory chip; and allocate at least one superblock of a reserved region to an over-allocation region in the first domain including the replaced second memory chip. Attached Figure Description

[0009] The above and other objects and features of this disclosure will become clear from the detailed description of embodiments thereof with reference to the accompanying drawings.

[0010] Figure 1 This is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0011] Figure 2 This describes some embodiments according to the present disclosure. Figure 1 Block diagram of a non-volatile memory device.

[0012] Figure 3 This describes some embodiments according to the present disclosure. Figure 1 A diagram of the domain.

[0013] Figure 4 It is a graph depicting the trend of memory chips and initial bad blocks according to some embodiments of the present disclosure.

[0014] Figure 5A This is a diagram illustrating the default domain settings of a domain according to some embodiments of the present disclosure.

[0015] Figure 5B This is a diagram illustrating an optimized domain configuration according to some embodiments of the present disclosure.

[0016] Figure 6A This is a diagram illustrating the default domain settings of multiple domains according to some embodiments of the present disclosure.

[0017] Figure 6B This is a diagram illustrating an optimized domain setup for multiple domains according to some embodiments of the present disclosure.

[0018] Figure 6C This is a diagram illustrating an optimized domain setup with switching functionality for multiple domains according to some embodiments of the present disclosure.

[0019] Figure 7 This is a diagram illustrating a method of operating an electronic device according to some embodiments of the present disclosure.

[0020] Figure 8 This is a flowchart describing a method of operating an electronic device according to some embodiments of the present disclosure.

[0021] Figure 9 This is a block diagram of an electronic device according to some embodiments of the present disclosure.

[0022] Figure 10 This is a block diagram of an electronic device according to some embodiments of the present disclosure.

[0023] Figure 11 This describes some embodiments according to the present disclosure. Figure 10 A block diagram of an electronic device.

[0024] Figure 12 This is a flowchart describing a method of operating an electronic device according to some embodiments of the present disclosure. Detailed Implementation

[0025] The embodiments of this disclosure will now be described in detail and clearly to the extent that those skilled in the art can readily implement the embodiments of this disclosure.

[0026] Figure 1 This is a block diagram of an electronic device according to embodiments of the present disclosure. (Refer to...) Figure 1 The electronic device 100 may include a domain management device 110 and a non-volatile memory device 120. The electronic device 100 may be a semiconductor manufacturing system for manufacturing the non-volatile memory device 120. Optionally, the electronic device 100 may be a storage device including the non-volatile memory device 120.

[0027] Domain management device 110 can communicate with non-volatile memory device 120. Domain management device 110 may include memory chip analysis device 111, domain reconstruction device 112, and domain setting device 113.

[0028] Domain management device 110 can manage domains (e.g., a first domain DO1 and a second domain DO2) of non-volatile memory device 120 and can be implemented by one or more processors. A domain can represent multiple memory chips (MCs). A memory chip (MC) can include multiple memory blocks. A memory block can include multiple memory cells (e.g., memory cell transistors) storing data. A domain can support superblock functionality for parallel (e.g., simultaneous or partially simultaneous) access to memory blocks respectively included in their respective memory chips (MCs). A superblock (SB) can represent a set of memory blocks that can be accessed in parallel.

[0029] Domain management device 110 may be implemented by hardware, software, or a combination thereof. For example, domain management device 110 may be implemented using a separate hardware device for managing a domain of non-volatile memory device 120. As another example, a non-transitory computer-readable storage medium may store instructions corresponding to domain management device 110. When a processor loads and executes the loaded instructions, the instructions may allow the processor to perform at least a portion of the functions corresponding to domain management device 110.

[0030] The memory chip analysis apparatus 111 can analyze the memory chips MC of a domain of the non-volatile memory device 120. For example, a portion of the memory blocks corresponding to the memory chip MC may be initial bad blocks, and other memory blocks corresponding to the memory chip MC may be normal blocks. The memory chip analysis apparatus 111 can count the number of initial bad blocks in the memory chip MC and can store information about the number of initial bad blocks in the non-volatile memory device 120. Initial bad blocks may represent memory blocks that include permanent defects that may be caused by the manufacturing process of the non-volatile memory device 120. Initial bad blocks may be unable to store or retrieve data due to defects or faults. Normal blocks may represent memory blocks that can normally store and retrieve data.

[0031] A memory chip MC that includes initial bad blocks (the number of initial bad blocks exceeding a predetermined chip threshold number) may be referred to as a "bad memory chip". The chip threshold number may be predetermined by various factors, such as the standards of the non-volatile memory device 120, the performance of the domain, and the number of memory blocks included in the memory chip MC. A memory chip MC that includes initial bad blocks (the number of initial bad blocks is less than or equal to the predetermined chip threshold number) or does not include initial bad blocks may be referred to as a "normal memory chip". In this disclosure, bad blocks and bad memory chips may also be referred to as faulty blocks and faulty memory chips, respectively.

[0032] Domain reconstruction device 112 can reconstruct the domains of non-volatile memory device 120 such that bad memory chips are uniformly or nearly uniformly distributed. For example, domain reconstruction device 112 can identify domains containing many bad memory chips, identify domains containing few bad memory chips, and can exchange bad memory chips in domains containing more bad memory chips with normal memory chips in domains containing few bad memory chips. Exchange can mean replacing memory chips with each other.

[0033] In some embodiments, memory chips may be replaced or swapped using physical methods as part of the manufacturing process. (See also...) Figure 9 This will be described in detail.

[0034] In some embodiments, a logical approach may be used to replace or swap the memory chips of a domain, the logical approach involving changing the mapping relationship between the domain and the memory chips by means of a memory controller configured to manage or control the non-volatile memory device 120. (Refer to...) Figure 10 and Figure 11 This will be described in detail.

[0035] Domain setting device 113 can manage user areas and reserved areas of a domain. User areas can represent logical space used for storing data or performing data-related operations. Reserved areas can represent unused logical space that has been initially allocated.

[0036] The domain setting device 113 can set the ratio of user area to reserved area based on the number of initial bad blocks in the memory chip MC corresponding to the domain. After the domain is reconstructed by the domain reconstruction device 112, the domain setting device 113 can set the ratio of user area to reserved area again based on the number of initial bad blocks in the memory chip MC after such change.

[0037] Non-volatile memory device 120 can store data. Non-volatile memory device 120 may include data input / output (I / O) circuitry 121, a first domain DO1, and a second domain DO2. Each of the first domain DO1 and the second domain DO2 may include multiple memory chips MC. The first domain DO1 and the second domain DO2 have been described for better understanding of this disclosure, but non-volatile memory device 120 may include three or more domains.

[0038] For example, the non-volatile memory device 120 may be NAND flash memory. However, this disclosure is not limited thereto, and the non-volatile memory device 120 may be implemented using one of various storage devices (such as phase-change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), and ferroelectric random access memory (FRAM)) that can retain the data stored therein even when power is disconnected.

[0039] Data I / O circuit 121 can receive data from an external device (e.g., a host device or a storage controller). Data I / O circuit 121 can provide data to a first domain DO1 or a second domain DO2. Data I / O circuit 121 can receive data from a first domain DO1 or a second domain DO2. Data I / O circuit 121 can provide data to an external device (e.g., a host device or a storage controller).

[0040] In some embodiments, the data I / O circuit 121 may communicate with the domain on a superblock basis. For example, the data I / O circuit 121 may provide data in parallel to memory blocks respectively included in the memory chip MC of the first domain DO1, or may receive data in parallel from memory blocks respectively included in the memory chip MC of the first domain DO1.

[0041] Figure 2 This describes some embodiments according to the present disclosure. Figure 1 A block diagram of a non-volatile memory device. (Refer to...) Figure 1 and Figure 2 The non-volatile memory device 120 may include data I / O circuitry 121, control logic circuitry 122, and memory chip region 123. The non-volatile memory device 120 can manage data under the control of a memory controller.

[0042] Under the control of the control logic circuit 122, the data I / O circuit 121 can provide data received from the memory controller to the memory chip area 123, or it can provide data received from the memory chip area 123 to the memory controller.

[0043] Control logic circuitry 122 can receive commands and addresses from the memory controller. Commands can be used to indicate the operation to be performed in the non-volatile memory device 120. Addresses can be used to identify the memory chip or memory block in which the operation corresponding to the command will be performed. Control logic circuitry 122 can control data I / O circuitry 121 and memory chip region 123 based on commands and addresses.

[0044] Memory chip region 123 may include a first domain DO1 and a second domain DO2. The first domain DO1 may include first memory chips MC1 through fourth memory chips MC1, MC2, MC3, and MC4. The first memory chip MC1 may include memory blocks BLK11, BLK12, BLK13, and BLK14. The second memory chip MC2 may include memory blocks BLK21, BLK22, BLK23, and BLK24. The third memory chip MC3 may include memory blocks BLK31, BLK32, BLK33, and BLK34. The fourth memory chip MC4 may include memory blocks BLK41, BLK42, BLK43, and BLK44.

[0045] Memory blocks BLK11, BLK21, BLK31, and BLK41 can be collectively referred to as "First Superblock SB1". As described above, memory blocks BLK12, BLK22, BLK32, and BLK42 can be collectively referred to as "Second Superblock SB2", memory blocks BLK13, BLK23, BLK33, and BLK43 can be collectively referred to as "Third Superblock SB3", and memory blocks BLK14, BLK24, BLK34, and BLK44 can be collectively referred to as "Fourth Superblock SB4".

[0046] The second domain DO2 may include the fifth through eighth memory chips MC5, MC6, MC7, and MC8. The fifth memory chip MC5 may include memory blocks BLK51, BLK52, BLK53, and BLK54. The sixth memory chip MC6 may include memory blocks BLK61, BLK62, BLK63, and BLK64. The seventh memory chip MC7 may include memory blocks BLK71, BLK72, BLK73, and BLK74. The eighth memory chip MC8 may include memory blocks BLK81, BLK82, BLK83, and BLK84.

[0047] Memory blocks BLK51, BLK61, BLK71, and BLK81 can be collectively referred to as "Superblock 5 SB5". As described above, memory blocks BLK52, BLK62, BLK72, and BLK82 can be collectively referred to as "Superblock 6 SB6", memory blocks BLK53, BLK63, BLK73, and BLK83 can be collectively referred to as "Superblock 7 SB7", and memory blocks BLK54, BLK64, BLK74, and BLK84 can be collectively referred to as "Superblock 8 SB8".

[0048] The first field DO1 and the second field DO2 can support super block functions. A super block function can represent the parallel output of data through a memory block corresponding to the super block, or the parallel storage of data in a memory block corresponding to the super block. Super block functions can include full super block functions and partial super block functions.

[0049] A full superblock function allows for parallel access to all memory blocks corresponding to a superblock. For example, when all memory blocks BLK11, BLK21, BLK31, and BLK41 corresponding to the first superblock SB1 are normal blocks, the first domain DO1 can support a full superblock function for parallel access to memory blocks BLK11, BLK21, BLK31, and BLK41 respectively included in the first to fourth memory chips MC1, MC2, MC3, and MC4. The full superblock function can offer wide data bandwidth and low latency.

[0050] A partial superblock function can represent parallel access to some normal blocks within the memory block corresponding to the superblock. For example, when a portion of the memory blocks BLK11, BLK21, BLK31, and BLK41 corresponding to the first superblock SB1 are initial bad blocks, and when the number of initial bad blocks is less than the function threshold, the first domain DO1 can support a partial superblock function for parallel access to the remaining normal blocks (i.e., other memory blocks) within memory blocks BLK11, BLK21, BLK31, and BLK41 respectively included in the first to fourth memory chips MC1, MC2, MC3, and MC4. The data bandwidth of the partial superblock function may be narrower than that of the full superblock function, and the latency of the partial superblock function may be higher than that of the full superblock function.

[0051] As another example, when a portion of the memory blocks BLK11, BLK21, BLK31, and BLK41 corresponding to the first superblock SB1 are initial bad blocks and when the number of initial bad blocks is equal to or greater than the functional threshold number, the first domain DO1 may not support the superblock functionality in the first superblock SB1. Normal blocks in the first superblock SB1 may be treated as redundant memory blocks (e.g., spare memory blocks that do not contribute to data storage).

[0052] For a better understanding of this disclosure, it is described that each of the first domain DO1 and the second domain DO2 includes four memory chips and the memory chips include four memory blocks, but this disclosure is not limited thereto. The number of memory chips included in a domain may be more or less than "4". The number of memory blocks included in a memory chip may be more or less than "4". In addition, the non-volatile memory device 120 may include one or more other domains (e.g., a third domain) besides the first domain DO1 and the second domain DO2.

[0053] Figure 3 This describes some embodiments according to the present disclosure. Figure 1 A diagram of the domain. (Refer to...) Figure 1 and Figure 3 The first domain DO1 may include multiple memory chips MC. The multiple memory chips MC may include multiple memory blocks BLK. A portion of the multiple memory blocks BLK may be initial bad blocks IBB, and the other memory blocks in the multiple memory blocks BLK may be normal blocks. The initial bad blocks IBB may be generated by a process used to manufacture the non-volatile memory device 120.

[0054] The first domain DO1 contains multiple memory blocks (BLKs) that can provide user areas and reserved areas. Within the logical space available to the first domain DO1, the remaining space, excluding reserved areas, can be allocated as user areas. User areas may include metadata areas, user data areas, and over-provisioning areas.

[0055] The metadata area stores metadata used for user data. Metadata may include information describing the user data. For example, metadata may include the following information about the file corresponding to the user data: the time when the file was created, the location where the file was created, the location where the file was stored, the writer, and the revision time.

[0056] The user data area can store user data. User data may include information about content to be provided to the user on the non-volatile memory device 120. For example, user data may include image data, video data, text data, and application information.

[0057] The over-provisioning area can be used to securely manage user data and metadata, and to perform background operations to improve the durability of the device (e.g., non-volatile memory device 120). The over-provisioning area may not be identifiable by the user of the non-volatile memory device 120. The over-provisioning area may be set up separately from the user data area. For example, the over-provisioning area can provide storage space for garbage collection or wear leveling operations associated with user data and metadata.

[0058] When the over-provisioned area is insufficient, garbage collection or wear leveling operations may fail to perform properly. In this case, the performance of the non-volatile memory device 120 (e.g., storage capacity, read speed, write speed, and reliability of stored data) may be degraded. To guarantee the required performance of the non-volatile memory device 120, a portion of a given size or larger is required as an over-provisioned area within the entire first domain DO1.

[0059] Reserved areas can be allocated based on initial bad block IBBs. For example, a reserved area can be allocated based on the maximum number of initial bad block IBBs that can be generated from multiple memory blocks BLKs in the first domain DO1. Reserved areas may include memory blocks BLKs that are not initial bad block IBBs. (See reference...) Figure 4 This will be described in detail.

[0060] Figure 4 This is a graph depicting the trends of memory chips and initial bad blocks according to some embodiments of this disclosure. (Refer to...) Figure 1 and Figure 4 The relationship between the memory chip MC and the initial bad block IBB is described. Figure 4 In the diagram, the horizontal axis represents the number of initial bad blocks (IBB) in each memory chip (MC), and the vertical axis represents the number of memory chips (MC).

[0061] Due to process variations or physical limitations, the number of initial bad blocks (IBBs) can vary depending on the memory chips (MCs) of the non-volatile memory device 120. According to some embodiments, in 90% of the memory chips (MCs) of the non-volatile memory device 120, the number of initial bad blocks (IBBs) for each memory chip (MC) can be between "0" and a first initial bad block value (IBBV1). In 10% of the memory chips (MCs) of the non-volatile memory device 120, the number of initial bad blocks (IBBs) for each memory chip (MC) can be between the first initial bad block value (IBBV1) and a second initial bad block value (IBBV2) (which is the maximum initial bad block value (max)).

[0062] In the first domain DO1 and the second domain DO2, the reserved area can be widely allocated based on a second initial bad block value IBBV2. Widely allocated reserved areas can result in a reduction of the user area. However, most memory chip MCs (e.g., approximately 90% of memory chip MCs) include an initial bad block value IBB, the number of which is less than the first initial bad block value IBBV1. As a result, the reserved area can randomly (or typically) include many normal blocks. The domain setting device 113 can increase the user area by allocating one or more normal blocks from the reserved area to the user area.

[0063] Figure 5A This is a diagram illustrating the default domain settings of a domain according to some embodiments of the present disclosure. Reference will be made to... Figure 5A The first domain DO1, which has a default domain setting, is described. The first domain DO1 may include first memory chips through fourth memory chips MC1, MC2, MC3, and MC4. The first memory chip MC1 may include memory blocks BLK11, BLK12, BLK13, BLK14, BLK15, BLK16, BLK17, and BLK18. The second memory chip MC2 may include memory blocks BLK21, BLK22, BLK23, BLK24, BLK25, BLK26, BLK27, and BLK28. The third memory chip MC3 may include memory blocks BLK31, BLK32, BLK33, BLK34, BLK35, BLK36, BLK37, and BLK38. The fourth memory chip MC4 may include memory blocks BLK41, BLK42, BLK43, BLK44, BLK45, BLK46, BLK47, and BLK48.

[0064] The first superblock SB1 may include memory blocks BLK11, BLK21, BLK31, and BLK41. As described above, the second superblock SB2 may include memory blocks BLK12, BLK22, BLK32, and BLK42; the third superblock SB3 may include memory blocks BLK13, BLK23, BLK33, and BLK43; the fourth superblock SB4 may include memory blocks BLK14, BLK24, BLK34, and BLK44; the fifth superblock SB5 may include memory blocks BLK15, BLK25, BLK35, and BLK45; the sixth superblock SB6 may include memory blocks BLK16, BLK26, BLK36, and BLK46; the seventh superblock SB7 may include memory blocks BLK17, BLK27, BLK37, and BLK47; and the eighth superblock SB8 may include memory blocks BLK18, BLK28, BLK38, and BLK48.

[0065] Superblocks SB5 through SB8 can be allocated to reserved areas based on the maximum number of initial bad blocks (e.g., 16 initial bad blocks) that can be generated in the first domain DO1. The number of initial bad blocks in the first domain DO1 (e.g., ten) can be less than the maximum number of initial bad blocks that can be generated (e.g., 16). Superblocks SB1 through SB4, which are not allocated to reserved areas, can be allocated to user areas. User areas may include over-allocated areas. For ease of description, user areas are not shaded, reserved areas are shaded, and initial bad blocks are marked with "x".

[0066] Superblocks SB1 through SB4 can support full superblock functionality. For example, superblocks SB1 through SB2 can exclude initial bad blocks. Because all memory blocks in superblocks SB1 through SB4 are normal blocks capable of storing data, full superblock functionality can be available in superblocks SB1 through SB2.

[0067] Superblock SB5 and Superblock SB6 can support some superblock functionality. For example, the function threshold number for some superblock functionality can be "3". Because Superblock SB5 includes one initial bad block (i.e., memory block BLK45) (the number of initial bad blocks (i.e., memory block BLK45) is less than "3" as the function threshold number), Superblock SB5 can support some superblock functionality. Because Superblock SB6 includes two initial bad blocks (i.e., memory blocks BLK36 and BLK46) (the number of two initial bad blocks (i.e., memory blocks BLK36 and BLK46) is less than "3" as the function threshold number), Superblock SB6 can support some superblock functionality. In other words, Superblock SB5 and Superblock SB6 can support some superblock functionality.

[0068] Superblock 7 (SB7) and Superblock 8 (SB8) may not support superblock functionality. For example, the function threshold number for some superblock functionality can be "3". Because Superblock 7 (SB7) includes three initial bad blocks (i.e., memory blocks BLK27, BLK37, and BLK47) (the number of the three initial bad blocks (i.e., memory blocks BLK27, BLK37, and BLK47) is not less than "3" as the function threshold number), Superblock 7 (SB7) may not support some superblock functionality. Because Superblock 8 (SB8) includes four initial bad blocks (i.e., memory blocks BLK18, BLK28, BLK38, and BLK48) (the number of the four initial bad blocks (i.e., memory blocks BLK18, BLK28, BLK38, and BLK48) is not less than "3" as the function threshold number, Superblock 8 (SB8) may not support some superblock functionality. In other words, superblock functionality may be unavailable in Superblock 7 (SB7) and Superblock 8 (SB8).

[0069] Domain DO1 can operate according to the default domain settings. In the default domain settings, because superblocks SB5 and SB6 are allocated to reserved areas, they may not be able to contribute to data storage. In other words, superblocks SB5 and SB6, which support some superblock functionality, may not be utilized in domain DO1.

[0070] Figure 5B This is a diagram illustrating an optimized domain setup according to some embodiments of the present disclosure. Reference will be made to... Figure 5B The first domain DO1 with optimized domain settings is described. Figure 1 The domain setting device 113 can assign optimized domain settings to the first domain DO1. The correspondence and reference between domain DO1, memory chips MC1, MC2, MC3 and MC4, memory blocks BLK11 to BLK48, and superblocks SB5 and SB6 are as follows. Figure 5A The correspondences described are similar; therefore, additional descriptions will be omitted to avoid redundancy.

[0071] Superblock SB5 and Superblock SB6 can support some superblock functionality. Allocating Superblock SB5 and Superblock SB6 to reserved areas can lead to a waste of storage capacity. Figure 1 The domain setting device 113 can assign optimized domain settings to the first domain DO1 by allocating the fifth superblock SB5 and the sixth superblock SB6 of the reserved area to the user area (e.g., the over-configuration area).

[0072] In an optimized domain setup, the fifth superblock SB5 and the sixth superblock SB6 can be allocated to user areas (e.g., over-allocation areas). Based on partial superblock functionality, the fifth superblock SB5 and the sixth superblock SB6 can store metadata, store user data, or provide over-allocation areas. The storage capacity of the first domain DO1 can be increased by adding the fifth superblock SB5 and the sixth superblock SB6, which support partial superblock functionality, to user areas (e.g., over-allocation areas).

[0073] Figure 6A This is a diagram illustrating the default domain settings of multiple domains according to some embodiments of the present disclosure. Reference will be made to... Figure 6A Describe the first domain DO1 and the second domain DO2, which have default domain settings.

[0074] The first domain DO1 may include first memory chips to fourth memory chips MC1, MC2, MC3, and MC4. The first memory chip MC1 may include memory blocks BLK11, BLK12, BLK13, BLK14, BLK15, BLK16, BLK17, and BLK18. The second memory chip MC2 may include memory blocks BLK21, BLK22, BLK23, BLK24, BLK25, BLK26, BLK27, and BLK28. The third memory chip MC3 may include memory blocks BLK31, BLK32, BLK33, BLK34, BLK35, BLK36, BLK37, and BLK38. The fourth memory chip MC4 may include memory blocks BLK41, BLK42, BLK43, BLK44, BLK45, BLK46, BLK47, and BLK48.

[0075] In the first field DO1, a group of memory blocks located on the same row can be referred to as a "superblock". For example, memory blocks BLK11, BLK21, BLK31, and BLK41 can be referred to as "superblocks". As described above, memory blocks BLK12, BLK22, BLK32, and BLK42 can be referred to as "superblocks".

[0076] The second domain DO2 may include the fifth through eighth memory chips MC5, MC6, MC7, and MC8. The fifth memory chip MC5 may include memory blocks BLK51, BLK52, BLK53, BLK54, BLK55, BLK56, BLK57, and BLK58. The sixth memory chip MC6 may include memory blocks BLK61, BLK62, BLK63, BLK64, BLK65, BLK66, BLK67, and BLK68. The seventh memory chip MC7 may include memory blocks BLK71, BLK72, BLK73, BLK74, BLK75, BLK76, BLK77, and BLK78. The eighth memory chip MC8 may include memory blocks BLK81, BLK82, BLK83, BLK84, BLK85, BLK86, BLK87, and BLK88.

[0077] In the second field DO2, a group of memory blocks located on the same row can be referred to as a "superblock". For example, memory blocks BLK51, BLK61, BLK71, and BLK81 can be referred to as a "superblock". As described above, memory blocks BLK52, BLK62, BLK72, and BLK82 can be referred to as a "superblock".

[0078] Memory blocks BLK11 to BLK88 in the first domain DO1 and the second domain DO2 can be allocated to user areas or reserved areas. User areas may include over-allocated areas. Some of the memory blocks BLK11 to BLK88 may be initial bad blocks. For ease of description, user areas are not shaded, reserved areas are shaded, and initial bad blocks are marked with "x".

[0079] Referring to the reserved area of ​​the first domain DO1, the superblocks including memory blocks BLK15, BLK25, BLK35, and BLK45 can support some superblock functions. The superblocks including memory blocks BLK16, BLK26, BLK36, and BLK46 can also support some superblock functions.

[0080] Referring to the reserved area of ​​the second domain DO2, superblocks including memory blocks BLK55, BLK65, BLK75, and BLK85 support full superblock functionality. Superblocks including memory blocks BLK56, BLK66, BLK76, and BLK86 support full superblock functionality. Superblocks including memory blocks BLK57, BLK67, BLK77, and BLK87 support partial superblock functionality.

[0081] Because superblocks that support partial or full superblock functionality are allocated to reserved areas, optimized domain settings for extending user areas (e.g., over-configured areas) may be required.

[0082] Figure 6B This is a diagram illustrating an optimized domain setup for multiple domains according to some embodiments of the present disclosure. Reference will be made to... Figure 6B The first domain DO1 and the second domain DO2, which have optimized domain settings that do not have switching functionality, are described. Figure 1 The domain setting device 113 can assign optimized domain settings without switching functionality to the first domain DO1 and the second domain DO2. The correspondence and reference between domains DO1 and DO2, memory chips MC1 to MC8, memory blocks BLK11 to BLK88, and the superblock... Figure 6A The correspondences described are similar; therefore, additional descriptions will be omitted to avoid redundancy.

[0083] Referring to the first domain DO1, a superblock comprising memory blocks BLK15, BLK25, BLK35, and BLK45 may be allocated to a user area (e.g., an over-provisioned area). A superblock comprising memory blocks BLK16, BLK26, BLK36, and BLK46 may be allocated to a user area (e.g., an over-provisioned area).

[0084] Referring to the second domain DO2, a superblock comprising memory blocks BLK55, BLK65, BLK75, and BLK85 may be allocated to a user area (e.g., an over-provisioned area). A superblock comprising memory blocks BLK56, BLK66, BLK76, and BLK86 may be allocated to a user area (e.g., an over-provisioned area). A superblock comprising memory blocks BLK57, BLK67, BLK77, and BLK87 may be allocated to a user area (e.g., an over-provisioned area).

[0085] In other words, since optimized domain configurations without switching capabilities are assigned to the first domain DO1 and the second domain DO2, five superblocks can be further provided to user areas (e.g., over-provisioned areas). However, when memory chip swapping in the first domain DO1 and the second domain DO2 is permitted, superblocks supporting superblock functionality can be further allocated to user areas (e.g., over-provisioned areas). (See also...) Figure 6C This will be described in detail.

[0086] Figure 6C This is a diagram illustrating an optimized domain setup with switching functionality across multiple domains according to some embodiments of the present disclosure. Reference will be made to... Figure 6C The first domain DO1 and the second domain DO2, which have optimized domain settings and switching capabilities, are described. Figure 1The domain reconstruction device 112 and the domain setting device 113 can assign optimized domain settings and switching functions to the first domain DO1 and the second domain DO2. The correspondence and reference between domains DO1 and DO2, memory chips MC1 to MC8, memory blocks BLK11 to BLK88, and the superblock... Figure 6A The correspondences described are similar; therefore, additional descriptions will be omitted to avoid redundancy.

[0087] Figure 1 The domain reconfiguration device 112 can swap the third memory chip MC3 of the first domain DO1 with the seventh memory chip MC7 of the second domain DO2. That is, the third memory chip MC3 of the first domain DO1 can be replaced by the seventh memory chip MC7, and the seventh memory chip MC7 of the second domain DO2 can be replaced by the third memory chip MC3. After the swap, the first domain DO1 may include the first memory chip MC1, the second memory chip MC2, the fourth memory chip MC4, and the seventh memory chip MC7. The second domain DO2 may include the third memory chip MC3, the fifth memory chip MC5, the sixth memory chip MC6, and the eighth memory chip MC8.

[0088] Referring to the first domain DO1 of the replaced seventh memory chip MC7, the superblock including memory blocks BLK15, BLK25, BLK75, and BLK45 can support partial superblock functionality. The superblock including memory blocks BLK16, BLK26, BLK76, and BLK46 can support partial superblock functionality. The superblock including memory blocks BLK17, BLK27, BLK77, and BLK47 can support partial superblock functionality. Figure 1 The domain setting device 113 can allocate superblocks that support superblock functionality to user regions (e.g., over-configured regions).

[0089] Referring to the second domain DO2 of the replaced third memory chip MC3, the superblock including memory blocks BLK55, BLK65, BLK35, and BLK85 supports full superblock functionality. The superblock including memory blocks BLK56, BLK66, BLK36, and BLK86 supports partial superblock functionality. The superblock including memory blocks BLK57, BLK67, BLK37, and BLK87 supports partial superblock functionality. Figure 1 The domain setting device 113 can allocate superblocks that support superblock functionality to user regions (e.g., over-configured regions).

[0090] In other words, after swapping the third memory chip MC3 of the first domain DO1 with the seventh memory chip MC7 of the second domain DO2 via the swapping function, the superblocks supporting the superblock function of the first domain DO1 and the second domain DO2 can be allocated to user areas (e.g., over-provisioned areas). Therefore, six superblocks can be further provided to user areas (e.g., over-provisioned areas). See reference. Figure 6B and Figure 6C When the switching function is permitted, the number of superblocks provided to user areas (e.g., over-configured areas) can be increased.

[0091] In some embodiments, Figure 1 The domain reconstruction device 112 can distribute faulty memory chips uniformly or nearly uniformly in a multi-domain environment. For example, before swapping, the first domain DO1 may include first memory chips to fourth memory chips MC1, MC2, MC3 and MC4, and the second domain DO2 may include fifth memory chips to eighth memory chips MC5, MC6, MC7 and MC8.

[0092] In one embodiment, the third memory chip MC3 and the fourth memory chip MC4, which include an initial number of bad blocks exceeding "2" as a chip threshold number, among the first memory chips MC1 to the eighth memory chips MC8, may be referred to as "bad memory chips". Before the swap, the first domain DO1 may include two bad memory chips, and the second domain DO2 may not include bad memory chips. That is, bad memory chips may be concentrated on the first domain DO1.

[0093] Figure 1 The domain reconstruction device 112 can select a third memory chip MC3, which includes the second largest number of initial bad blocks, from the bad memory chips in the first domain DO1, and a seventh memory chip MC7, which is one of the normal memory chips in the second domain DO2. It can also swap the third memory chip MC3 with the seventh memory chip MC7. Based on the above description, the two bad memory chips concentrated in the first domain DO1 can be evenly distributed between the first domain DO1 and the second domain DO2.

[0094] Because the faulty memory chips are evenly distributed across the first domain DO1 and the second domain DO2, a superblock supporting superblock functionality can be secured by attaching it within the reserved areas of the first domain DO1 and the second domain DO2. Figure 1 The domain setting device 113 allocates additional secured superblocks to user zones (e.g., over-configured zones), increasing... Figure 1 It is feasible to increase the storage capacity of the non-volatile memory device 120 and ensure the required performance of the non-volatile memory device 120.

[0095] Figure 7 This is a diagram illustrating a method of operating an electronic device according to some embodiments of the present disclosure. (Refer to...) Figure 7 The electronic device 100 may include a domain management device 110 and a non-volatile memory device 120. The domain management device 110 may communicate with the non-volatile memory device 120.

[0096] The non-volatile memory device 120 may include a first domain DO1 and a second domain DO2. The first domain DO1 may include a first memory chip to an Nth memory chip, and the second domain DO2 may include an (N+1)th memory chip to a 2Nth memory chip. “N” may indicate the number of memory chips allocated to the domain. “N” is any natural number greater than 0. For example, “N” may be “4”.

[0097] Domain management device 110 can manage a first domain DO1 and a second domain DO2 of non-volatile memory device 120. Domain management device 110 may include memory chip analysis device 111, domain reconstruction device 112, domain setting device 113, and memory chip information table 114.

[0098] The memory chip analysis device 111 can analyze the first memory chips MC1 to the eighth memory chips MC8 of the non-volatile memory device 120, and can store the first initial bad block count INUM1 to the eighth initial bad block count INUM8 of the first memory chips MC1 to the eighth memory chips MC8 in the memory chip information table 114. The initial bad block count (INUM) indicates the number of initial bad blocks counted in the corresponding memory chip.

[0099] Domain reconstruction device 112 can change the memory chip included in the first domain DO1 of the non-volatile memory device 120. Domain reconstruction device 112 can also change the memory chip included in the second domain DO2 of the non-volatile memory device 120.

[0100] Domain setting device 113 can set the user area and reserved area of ​​the first domain DO1. Domain setting device 113 can set the user area and reserved area of ​​the second domain DO2.

[0101] The memory chip information table 114 can store the first to fourth memory chip information (or first domain chip information) corresponding to the first to fourth memory chips MC1, MC2, MC3 and MC4 of the first domain DO1, respectively. The memory chip information table 114 can also store the fifth to eighth memory chip information (or second domain chip information) corresponding to the fifth to eighth memory chips MC5, MC6, MC7 and MC8 of the second domain DO2, respectively.

[0102] The memory chip information may include a domain index value, a memory chip index value, and an initial bad block count. For example, the first memory chip information may include a domain index value "1" indicating the first domain DO1 to which the first memory chip MC1 belongs, a memory chip index value "1" used to identify the first memory chip MC1, and a first initial bad block count INUM1 indicating the number of initial bad blocks of the first memory chip MC1.

[0103] The method of operating the electronic device 100 will now be described.

[0104] In operation S110, the memory chip analysis device 111 can count the number of first initial bad blocks to the number of fourth initial bad blocks corresponding to the first memory chip to the Nth memory chip in the first domain DO1, and can update the information of the first memory chip to the Nth memory chip in the memory chip information table 114 based on the number of first initial bad blocks to the number of fourth initial bad blocks.

[0105] For example, N can be "4". The memory chip analysis device 111 can count the first initial bad block number to the fourth initial bad block number INUM1, INUM2, INUM3 and INUM4 corresponding to the first memory chips MC1 to MC2, MC3 and MC4 respectively in the first domain DO1. The first initial bad block number to the fourth initial bad block number INUM1, INUM2, INUM3 and INUM4 can be "1", "2", "3" and "4" respectively. The memory chip analysis device 111 can update the first memory chip information to the fourth memory chip information in the memory chip information table 114 based on the first initial bad block number to the fourth initial bad block number INUM1, INUM2, INUM3 and INUM4.

[0106] In some embodiments, independent of operation S110 and before operation S120, the memory chip analysis device 111 may count the number of initial bad blocks from the (N+1)th to the 2Nth memory chips corresponding to the second domain DO2, and may update the memory chip information from the (N+1)th to the 2Nth memory chips in the memory chip information table 114 based on the number of initial bad blocks from the (N+1)th to the 2Nth memory chips.

[0107] In operation S120, the domain reconstruction device 112 can select one of the first memory chip to the Nth memory chip based on the first initial bad block number to the Nth initial bad block number corresponding to the first domain DO1. The domain reconstruction device 112 can select one of the (N+1)th memory chip to the 2Nth memory chip based on the (N+1)th initial bad block number to the 2Nth initial bad block number corresponding to the second domain DO2.

[0108] For example, the domain reconstruction device 112 can select a third memory chip MC3 from the first to fourth memory chips MC1, MC2, MC3, and MC4 based on the first to fourth memory chip information in the memory chip information table 114, specifically the first initial bad block numbers INUM1 to INUM2, INUM3, and INUM4. Similarly, the domain reconstruction device 112 can select a seventh memory chip MC7 from the fifth to eighth memory chips MC5, MC6, MC7, and MC8 based on the fifth to eighth initial bad block numbers INUM5, INUM6, INUM7, and INUM8 in the memory chip information table 114.

[0109] In some embodiments, the domain reconstruction device 112 can distribute bad memory chips uniformly or nearly uniformly in a multi-domain environment. For example, a multi-domain environment including a first domain DO1 and a second domain DO2 may include first memory chips MC1 to eighth memory chips MC8. Third memory chip MC3 and fourth memory chip MC4, each comprising an initial bad block exceeding a chip threshold number "2", from the first memory chips MC1 to the eighth memory chips MC8, may be referred to as "bad memory chips". The first domain DO1 may include two bad memory chips, and the second domain DO2 may not include any bad memory chips.

[0110] In order to distribute the bad memory chips concentrated on the first domain DO1 to the first domain DO1 and the second domain DO2, the domain reconstruction device 112 can select a third memory chip MC3 from the first memory chips MC1 to the fourth memory chips MC1, MC2, MC3 and MC4 based on the first initial bad block number to the fourth initial bad block number INUM1, INUM2, INUM3 and INUM4 corresponding to the first domain DO1, and can select a seventh memory chip MC7 from the fifth memory chips to the eighth memory chips MC5, MC6, MC7 and MC8 based on the fifth initial bad block number to the eighth initial bad block number INUM5, INUM6, INUM7 and INUM8 corresponding to the second domain DO2.

[0111] In detail, the domain reconstruction device 112 can select a third initial bad block number INUM3 and a fourth initial bad block number INUM4 corresponding to bad memory chips from the first initial bad block number to the fourth initial bad block number INUM1, INUM2, INUM3 and INUM4, respectively. It can select a third initial bad block number INUM3 as the second largest number from the selected third initial bad block number INUM3 and the fourth initial bad block number INUM4, and can select a third memory chip MC3 corresponding to the third initial bad block number INUM3.

[0112] The domain reconstruction device 112 can select from the fifth to the eighth initial bad block numbers INUM5, INUM6, INUM7 and INUM8 respectively, which correspond to normal memory chips. It can also select from the selected fifth to the eighth initial bad block numbers INUM5, INUM6, INUM7 and INUM8 as the seventh initial bad block number, and can select the seventh memory chip MC7 corresponding to the seventh initial bad block number INUM7.

[0113] In operation S130, the domain reconstruction device 112 may replace the third memory chip MC3 of the first domain DO1 with the seventh memory chip MC7 of the second domain DO2. The seventh initial bad block number INUM7 (e.g., "1") corresponding to the seventh memory chip MC7 may be less than the third initial bad block number INUM3 (e.g., "3") corresponding to the third memory chip MC3. For example, the domain reconstruction device 112 may swap the third memory chip MC3 with the seventh memory chip MC7.

[0114] In some embodiments, a physical method or a logical method may be used as part of a manufacturing process to replace the third memory chip MC3 of the first domain DO1 with the seventh memory chip MC7 of the second domain DO2 or to exchange the third memory chip MC3 of the first domain DO1 with the seventh memory chip MC7 of the second domain DO2. This involves changing the mapping relationship between domains and memory chips by controlling the memory controller of the non-volatile memory device 120.

[0115] Based on the above description, the first domain DO1 may include a first memory chip MC1, a second memory chip MC2, a fourth memory chip MC4, and a seventh memory chip MC7. The second domain DO2 may include a third memory chip MC3, a fifth memory chip MC5, a sixth memory chip MC6, and an eighth memory chip MC8. In the first domain DO1, the number of superblocks supporting superblock functionality can be increased by replacing the third memory chip MC3 (which is a faulty memory chip) with the seventh memory chip MC7. In the second domain DO2, even if the seventh memory chip MC7 is replaced with the third memory chip MC3 (which is a faulty memory chip), the number of superblocks supporting superblock functionality can be maintained.

[0116] In other words, in a multi-domain environment that includes the first domain DO1 and the second domain DO2, the number of superblocks supporting superblock functionality can be increased.

[0117] In some embodiments, the domain reconstruction device 112 may update the memory chip information in the memory chip information table 114 corresponding to the replaced memory chip. For example, the domain reconstruction device 112 may replace the third memory chip MC3 of the first domain DO1 with the seventh memory chip MC7 of the second domain DO2, and then update the third memory chip information and the seventh memory chip information corresponding to the third memory chip MC3 and the seventh memory chip MC7 in the memory chip information table 114 (e.g., to reflect the result of replacing the third memory chip MC3 with the seventh memory chip MC7).

[0118] In detail, the updated third memory chip information may include a field index value "2" indicating the second field DO2, a memory chip index value "3" for identifying the third memory chip MC3, and a third initial bad block number INUM3. As described above, the updated seventh memory chip information may include a field index value "1" indicating the first field DO1, a memory chip index value "7" for identifying the seventh memory chip MC7, and a seventh initial bad block number INUM7.

[0119] In operation S140, in the first domain DO1, which includes the replaced seventh memory chip MC7, the domain setting device 113 can allocate at least one superblock from the reserved region's superblocks to the user region (e.g., an over-configuration region). In the second domain DO2, which includes the replaced third memory chip MC3, the domain setting device 113 can allocate at least one superblock from the reserved region's superblocks to the user region (e.g., an over-configuration region).

[0120] For example, based on the memory chip information table 114 (i.e., based on the first memory chip information, second memory chip information, fourth memory chip information and seventh memory chip information corresponding to the first domain DO1), the domain setting device 113 can identify at least one superblock that supports the superblock function from the superblocks in the reserved area, and can allocate the identified at least one superblock to the user area (e.g., the over-configuration area).

[0121] Similarly, based on the memory chip information table 114 (i.e., based on the third memory chip information, fifth memory chip information, sixth memory chip information and eighth memory chip information corresponding to the second domain DO2), the domain setting device 113 can identify at least one superblock that supports the superblock function from the superblocks in the reserved area, and can allocate the identified at least one superblock to the user area (e.g., the over-configuration area).

[0122] Figure 8 This is a flowchart describing a method of operating an electronic device according to some embodiments of the present disclosure. (See also...) Figure 8Electronic devices may include domain management devices and non-volatile memory devices.

[0123] In operation S210, the domain management device can count the first initial bad block count INUM1 to the second initial bad block count INUM2N corresponding to the first memory chip to the second N memory chip, respectively. The non-volatile memory device may include a first domain DO1 and a second domain DO2. The first domain DO1 may include the first memory chip to the Nth memory chip. Each of the first initial bad block count INUM1 to the Nth initial bad block count INUMN may indicate the number of initial bad blocks for each of the first memory chip to the Nth memory chip. The second domain DO2 may include the (N+1)th memory chip to the second Nth memory chip. Each of the (N+1)th initial bad block count INUM(N+1) to the second initial bad block count INUM2N may indicate the number of initial bad blocks for each of the (N+1)th memory chip to the second Nth memory chip.

[0124] In some embodiments, the domain management device may identify bad memory chips among the first to the 2Nth memory chips based on a first initial bad block count INUM1 to a 2Nth initial bad block count INUM2N. A bad memory chip may represent a memory chip corresponding to an initial bad block count exceeding a chip threshold.

[0125] In operation S220, the domain management device can identify bad memory chips among the first memory chips to the 2Nth memory chips based on the first initial bad block number INUM1 to the 2Nth initial bad block number INUM2N, and can distribute the identified bad memory chips to the first domain DO1 and the second domain DO2.

[0126] For example, the distribution of bad memory chips may include selecting a first memory chip in the first domain DO1, selecting a (N+1)th memory chip in the second domain DO2, and swapping the first memory chip and the (N+1)th memory chip.

[0127] In some embodiments, the domain management device can identify a domain having a number of bad memory chips that is higher than the average bad memory chip count across multiple domains, and can distribute bad memory chips from the identified domain to other domains.

[0128] For example, a domain management device can identify memory chips from the first to the Nth memory chips in a first domain DO1 as bad memory chips, corresponding to an initial number of bad blocks exceeding a chip threshold. The first memory chip may be a bad memory chip. The domain management device can determine whether the number of bad memory chips in the first domain DO1 exceeds "M". In one embodiment, "M" may indicate the average number of bad memory chips in each domain in a multi-domain environment including the first domain DO1 and the second domain DO2.

[0129] In one embodiment, the number of faulty memory chips in the first domain DO1 may exceed "M", and the number of faulty memory chips in the second domain DO2 may be less than "M". The domain management device may select a first memory chip in the first domain DO1 in response to determining that the number of faulty memory chips in the first domain DO1 exceeds "M". The first memory chip may be a faulty memory chip. The domain management device may select a (N+1)th memory chip from the (N+1)th to the 2Nth memory chips in the second domain DO2. The (N+1)th memory chip may be a normal memory chip. The domain management device may swap the first memory chip with the (N+1)th memory chip.

[0130] In some embodiments, the domain management device may distribute bad memory chips uniformly or nearly uniformly between a first domain DO1 and a second domain DO2. For example, the domain management device may identify memory chips from the first to the 2Nth memory chips that have an initial number of bad blocks exceeding a chip threshold as bad memory chips. The domain management device may distribute or allocate half of the bad memory chips to the first domain DO1 and the remaining half to the second domain DO2.

[0131] In operation S230, the domain management device can perform a disk formatting operation including a first domain DO1 and a second domain DO2, which consist of multiple bad memory chips after distribution.

[0132] After the domain management device performs a disk formatting operation, in operation S240, the domain management device may allocate at least one superblock from the reserved superblocks of the first domain DO1 and the second domain DO2 to a user region (e.g., an over-provisioned region) (e.g., allocating at least one superblock from the reserved superblocks of the first domain DO1 to a user region (e.g., an over-provisioned region) and at least one superblock from the reserved superblocks of the second domain DO2 to a user region (e.g., an over-provisioned region)). For example, the domain management device may identify at least one superblock supporting superblock functionality from the superblocks of the reserved regions and may allocate the identified at least one superblock to a user region (e.g., an over-provisioned region). Superblock functionality may include full superblock functionality and partial superblock functionality.

[0133] In operation S250, the domain management device can classify the allocated superblocks. For example, each of the allocated superblocks may support full superblock functionality or partial superblock functionality. The domain management device can classify the allocated superblocks into a first type that supports full superblock functionality and a second type that supports partial superblock functionality.

[0134] In operation S260, the domain management device may use a first superblock classified as a first type or a second superblock classified as a second type, depending on the workload of the non-volatile memory device. For example, the workload may be suitable for at least one of a user data area, a metadata area, and an over-provisioning area. The domain management device may select the first type or the second type based on the workload. For the user data area, the metadata area, and the over-provisioning area, the domain management device may use the first superblock corresponding to the first type or the second superblock corresponding to the second type. That is, the domain management device may use a superblock whose type is suitable for the workload.

[0135] Figure 9 This is a block diagram of an electronic device according to some embodiments of the present disclosure. (See also...) Figure 9 The electronic device 200 may include a domain management device 210, a non-volatile memory device 220, and a semiconductor manufacturing equipment 230. The electronic device 200 may be referred to as a "semiconductor manufacturing system".

[0136] Domain management device 210 may include memory chip analysis device 211, domain reconstruction device 212, domain setting device 213, and memory chip information table 214. The memory chip analysis device 211, domain reconstruction device 212, domain setting device 213, and memory chip information table 214 are similar to those of memory chip analysis device 111, domain reconstruction device 112, domain setting device 113, and memory chip information table 114; therefore, additional descriptions will be omitted to avoid redundancy.

[0137] The non-volatile memory device 220 may include a first domain DO1 and a second domain DO2. Each of the first domain DO1 and the second domain DO2 may include a plurality of memory chips MC. The memory chips MC of the first domain DO1 may include a first memory chip to an Nth memory chip. The memory chips MC of the second domain DO2 may include an (N+1)th memory chip to a 2Nth memory chip.

[0138] Semiconductor manufacturing equipment 230 can manufacture non-volatile memory device 220. Semiconductor manufacturing equipment 230 may include processor 231, memory device 232, and packaging equipment 233. In one example, semiconductor manufacturing equipment 230 may include domain management device 210. Semiconductor manufacturing equipment 230 can implement domain management device 210 as a software module. For example, processor 231 can implement (or interoperate with) domain management device 210 by loading instructions stored in memory device 232 and executing the loaded instructions.

[0139] In some embodiments, the memory chips of the switching domain can be implemented through a physical method as part of a manufacturing process. For example, a first domain DO1 may include first memory chips to the Nth memory chip. A second domain DO2 may include (N+1)th memory chips to the 2Nth memory chip. Domain reconstruction device 212 may select the first memory chip of the first domain DO1 and the (N+1)th memory chip of the second domain DO2. Then, domain reconstruction device 212 may be configured to control packaging equipment 233 such that the second memory chips to the Nth memory chip and the (N+1)th memory chip are packaged. This may mean that the second memory chips to the Nth memory chip and the (N+1)th memory chip constitute the first domain DO1. Domain reconstruction device 212 may be configured to control packaging equipment 233 such that the first memory chip and the (N+2)th memory chip to the 2Nth memory chip are packaged. This may mean that the first memory chip and the (N+2)th memory chip to the 2Nth memory chip constitute the second domain DO2.

[0140] Figure 10 This is a block diagram of an electronic device according to some embodiments of the present disclosure. (See also...) Figure 10 The electronic device 300 may include a domain management device 310, a non-volatile memory device 320, and a memory controller 330. The electronic device 300 may be referred to as a "memory device".

[0141] Domain management device 310 may include memory chip analysis device 311, domain reconstruction device 312, domain setting device 313, and memory chip information table 314. The memory chip analysis device 311, domain reconstruction device 312, domain setting device 313, and memory chip information table 314 are similar to those of memory chip analysis device 111, domain reconstruction device 112, domain setting device 113, and memory chip information table 114; therefore, additional descriptions will be omitted to avoid redundancy.

[0142] The non-volatile memory device 320 may include a first domain DO1 and a second domain DO2. Each of the first domain DO1 and the second domain DO2 may include a plurality of memory chips MC. The memory chips MC of the first domain DO1 may include a first memory chip to an Nth memory chip. The memory chips MC of the second domain DO2 may include an (N+1)th memory chip to a 2Nth memory chip.

[0143] The storage controller 330 can control the non-volatile memory device 320. For example, upon a request from an external host device, the storage controller 330 can store data received from the external host device in the non-volatile memory device 320, provide the data stored in the non-volatile memory device 320 to the external host device, or delete the data stored in the non-volatile memory device 320.

[0144] The storage controller 330 may include a processor 331 and a memory device 332. The storage controller 330 may implement a domain management device 310, which may be implemented as a software module or a firmware module. For example, the processor 331 may implement (or interoperate with) the domain management device 310 by loading instructions stored in the memory device 332 and executing the loaded instructions.

[0145] In some embodiments, the memory chip swapping of domains can be implemented via a logical method that changes the mapping relationship between domains and memory chips through a memory controller 330 controlling the non-volatile memory device 320. (Refer to...) Figure 11 Provide a detailed description of the logical methods.

[0146] Figure 11 This describes some embodiments according to the present disclosure. Figure 10 A block diagram of the electronic device. (Refer to...) Figure 10 and Figure 11 The electronic device 300 may include a domain management device 310 and a non-volatile memory device 320. The domain management device 310 may include a domain reconfiguration device 312 and a memory chip information table 314. The non-volatile memory device 320 may include data I / O circuitry 321 and multiple physical domains. To better understand this disclosure, an embodiment of one physical domain will be described.

[0147] A physical domain may include first memory chips MC1 through sixteenth memory chips MC16. Each of the first memory chips MC1 through sixteenth memory chips MC16 may include multiple memory blocks BLK. The number of memory chips in a physical domain is provided as an example, and the number of memory chips in a physical domain may be more or less than 16.

[0148] The first memory chip MC1 through the sixteenth memory chip MC16 of the physical domain can be identified as multiple virtual domains. For example, the first memory chip MC1 and the second memory chip MC2 can be assigned to the first virtual domain. The third memory chip MC3 and the fourth memory chip MC4 can be assigned to the second virtual domain. The number of memory chips assigned to virtual domains is provided as an example, and a virtual domain may include two or more memory chips. Virtual domains can be associated with... Figure 10 The first field DO1 corresponds to the second field DO2.

[0149] The memory chip information table 314 can store the first memory chip information to the sixteenth memory chip information corresponding to the first memory chip MC1 to the sixteenth memory chip MC16 included in the physical domain, respectively.

[0150] The memory chip information may include a virtual domain index value, a memory chip index value, and an initial bad block count. For example, the first memory chip information may include a virtual domain index value "1" indicating the first virtual domain to which the first memory chip MC1 belongs, a memory chip index value "1" used to identify the first memory chip MC1, and a first initial bad block count INUM1 for the first memory chip MC1.

[0151] In some embodiments, the domain reconfiguration device 312 can swap the memory chips of a domain using logical methods. For example, the non-volatile memory device 320 may include a physical domain. The physical domain may include first memory chips through second-N memory chips. The first memory chips through third-N memory chips may be allocated to a first virtual domain. The (N+1)th memory chip through second-Nth memory chips may be allocated to a second virtual domain.

[0152] For the purpose of the exchange, the domain reconstruction device 312 can select the first memory chip of the first virtual domain and the (N+1)th memory chip of the second virtual domain. Then, the domain reconstruction device 312 can set the virtual domain index value corresponding to the first memory chip in the memory chip information table 314 to a value indicating the second virtual domain instead of the first virtual domain, and can update the first memory chip information corresponding to the first memory chip.

[0153] As described above, the domain reconstruction device 312 can set the virtual domain index value corresponding to the (N+1)th memory chip in the memory chip information table 314 to a value indicating the first virtual domain instead of the second virtual domain, and can update the information of the (N+1)th memory chip corresponding to the (N+1)th memory chip.

[0154] Figure 12 This is a flowchart describing a method of operating an electronic device according to some embodiments of the present disclosure. (See also...) Figure 12 The electronic device may include a domain management device and a non-volatile memory device. The domain management device may communicate with the non-volatile memory device. The non-volatile memory device may include a first domain DO1 and a second domain DO2. The first domain DO1 may include first memory chips MC1 to Nth memory chips MCN. The second domain DO2 may include (N+1)th memory chips MC(N+1) to 2Nth memory chips MC2N. In one embodiment, "N" may be any natural number greater than 0 indicating the number of memory blocks included in the domain.

[0155] In operation S310, the domain management device can count the first initial bad block number INUM1 to the Nth initial bad block number INUMN corresponding to the first memory chip MC1 to the Nth memory chip MCN of the first domain DO1, respectively.

[0156] In operation S320, the domain management device can select the first memory chip MC1 from the first memory chips MC1 to the Nth memory chip MCN in the first domain DO1 based on the first initial bad block number INUM1 to the Nth initial bad block number INUMN. For example, the first initial bad block number INUM1 may exceed the chip threshold number. The first memory chip MC1 may be selected as the bad memory chip.

[0157] In operation S330, the domain management device can replace the first memory chip MC1 of the first domain DO1 with the (N+1)th memory chip MC(N+1) of the second domain DO2. The (N+1)th initial bad block number INUM(N+1) corresponding to the (N+1)th memory chip MC(N+1) can be less than the first initial bad block number INUM1. For example, the (N+1)th initial bad block number INUM(N+1) can not exceed the chip threshold number. The (N+1)th memory chip MC(N+1) can be a normal memory chip.

[0158] In operation S340, in the first domain DO1, which includes the (N+1)th memory chip MC(N+1) to be replaced, the domain management device can allocate at least one superblock from the superblocks of the reserved area to the user area (e.g., the over-configuration area). Therefore, the storage capacity of the non-volatile memory device can be increased.

[0159] According to embodiments of this disclosure, a domain management device for allocating superblocks and a method for operating the domain management device for allocating superblocks are provided.

[0160] Furthermore, because faulty memory chips are evenly distributed in a multi-domain environment, superblocks destined for over-provisioned regions can be additionally secured. Therefore, the storage capacity of non-volatile memory devices can be increased.

[0161] Although this disclosure has been described with reference to embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of this disclosure as set forth in the appended claims.

Claims

1. A method of operating a domain management device, the domain management device communicating with a non-volatile memory device, the method comprising: The number of initial bad blocks in a plurality of memory chips included in a first domain of a non-volatile memory device is counted respectively; The first memory chip is selected from the plurality of memory chips based on the number of initial bad blocks. The first memory chip of the first domain is replaced by the second memory chip of the second domain of the non-volatile memory device. as well as In the first domain, which includes the replacement second memory chip, at least one superblock from the reserved region is allocated to the over-configuration region.

2. The method according to claim 1, wherein, The first domain is configured to support: Full superblock functionality for parallel access to memory blocks of each of the multiple memory chips; and Partial superblock functionality for parallel access to some of the memory blocks.

3. The method according to claim 1, wherein, An initial bad block includes at least one memory block having defects caused by the manufacturing process of a non-volatile memory device.

4. The method according to claim 1, wherein, The steps for selecting the first memory chip include: Among the plurality of memory chips in the first domain, memory chips whose number of initial bad blocks exceeds a chip threshold number are identified as bad memory chips, and a first memory chip is selected in response to the number of bad memory chips in the first domain exceeding a first value. Among them, the number of initial bad blocks in the first memory chip exceeds the chip's threshold number, and The first value corresponds to the average number of bad memory chips in multiple domains, including the first domain and the second domain.

5. The method according to claim 4, wherein, The number of bad memory chips in the second domain is less than the first value, and The number of initial bad blocks in the second memory chip is less than the chip threshold number.

6. The method according to claim 1, wherein, The steps for selecting the first memory chip include: Among the plurality of memory chips in the first domain, select the first memory chip with the second largest number of initial bad blocks.

7. The method according to claim 1, wherein, Domain management devices are included in semiconductor manufacturing equipment configured to manufacture non-volatile memory devices. Semiconductor manufacturing equipment includes processors and memory devices, and The processor is configured to operate as a domain management device or interoperate with a domain management device by loading instructions stored in a memory device and executing the loaded instructions.

8. The method according to claim 7, wherein, Semiconductor manufacturing equipment also includes packaging equipment, and The step of replacing the first memory chip of the first domain with the second memory chip of the second domain of the non-volatile memory device includes: The control packaging equipment packages memory chips, excluding the first memory chip, and a replacement second memory chip from the plurality of memory chips in the first domain into the first domain.

9. The method according to claim 1, wherein, Storage devices include storage controllers and non-volatile memory devices. The storage controller includes a processor and a memory device, and The processor is configured to operate as a domain management device or interoperate with a domain management device by loading instructions stored in a memory device and executing the loaded instructions.

10. The method according to claim 9, wherein, Non-volatile memory devices include physical domains, The physical domain includes the plurality of memory chips in the first domain and the second memory chip in the second domain. The step of replacing the first memory chip of the first domain with the second memory chip of the second domain of the non-volatile memory device includes: Set the virtual domain index value corresponding to the first memory chip to the value indicating the second domain; and Set the virtual domain index value corresponding to the second memory chip to the value indicating the first domain.

11. The method according to claim 1, wherein, The over-configuration area provides storage space for waste collection or wear leveling operations.

12. The method according to any one of claims 1 to 11, wherein, The at least one superblock allocated includes multiple superblocks, and The method further includes: The multiple superblocks are classified into a first type that supports full superblock functionality and a second type that supports partial superblock functionality. Choose between Type 1 or Type 2 based on workload; and The first superblock corresponding to the first type or the second superblock corresponding to the second type will be used for the user data area, metadata area, or over-configuration area.

13. A method of operating a domain management device, the domain management device communicating with a non-volatile memory device, the method comprising: The number of initial bad blocks in multiple memory chips included in the first and second domains of the non-volatile memory device is counted respectively; Multiple bad memory chips identified from the plurality of memory chips based on the distribution of the number of initial bad blocks between the first and second domains; Perform disk formatting operations on the first and second domains to which the plurality of faulty memory chips are distributed; After the disk formatting operation, at least one superblock from the reserved areas of the first and second domains is allocated to the over-configured area; The at least one superblock is classified into a first type that supports full superblock functionality and a second type that supports partial superblock functionality; as well as Workloads based on non-volatile memory devices use either a first superblock classified as type one or a second superblock classified as type two.

14. The method according to claim 13, wherein, The steps of distributing the plurality of bad memory chips identified from the plurality of memory chips include: Among the plurality of memory chips, memory chips whose number of initial bad blocks exceeds a chip threshold number are identified as the plurality of bad memory chips; Distribute half of the plurality of faulty memory chips into the first domain; and The remaining half of the plurality of faulty memory chips are distributed to the second domain.

15. The method according to claim 13, wherein, The steps for a workload based on a non-volatile memory device to use a first superblock classified as type one or a second superblock classified as type two include: Choose between Type 1 or Type 2 based on workload; and The first superblock corresponding to the first type or the second superblock corresponding to the second type will be used for the user data area, metadata area, or over-configuration area.

16. A domain management device, comprising: The memory chip information table is configured to store first-domain chip information and second-domain chip information respectively included in the first and second domains of the non-volatile memory device; as well as At least one processor is configured as follows: The number of initial bad blocks in the multiple memory chips respectively included in the first domain is counted; The first domain chip information is updated based on the initial number of bad blocks counted. Based on the chip information in the first domain and the chip information in the second domain, a first memory chip is selected from multiple memory chips in the first domain and a second memory chip is selected from multiple memory chips in the second domain. Replace the first memory chip of the first domain with the second memory chip; Update the first domain chip information and the second domain chip information to reflect the result of replacing the first memory chip with the second memory chip; as well as In the first domain, which includes the replacement second memory chip, at least one superblock from the reserved region is allocated to the over-configuration region.

17. The domain management device according to claim 16, wherein, Semiconductor manufacturing equipment for producing non-volatile memory devices includes processors and memory devices, and The processor is configured to operate as or interoperate with the domain management device by loading instructions stored in a memory device and executing the loaded instructions.

18. The domain management device according to claim 16, wherein, Storage devices include storage controllers and non-volatile memory devices. The storage controller includes a processor and a memory device, and The processor is configured to operate as or interoperate with the domain management device by loading instructions stored in a memory device and executing the loaded instructions.

19. The domain management device according to any one of claims 16 to 18, wherein, The over-configuration area provides storage space for waste collection or wear leveling operations.

20. The domain management device according to any one of claims 16 to 18, wherein, An initial bad block includes at least one memory block having defects caused by the manufacturing process of a non-volatile memory device.

Images