Artificial intelligence memory architecture systems and methods

Abstract

The embodiment of the invention relates to an artificial intelligence memory architecture system and method. A system and method for providing a neural network model to an artificial intelligence (AI) field programmable gate array (FPGA) is provided. The flash memory stores a neural network model. A tunnel is created between a flash memory and a random access memory (RAM) through a multi-wire serial peripheral interface (QSPI) interface. Using the tunnel, the RAM reads one or more layers of the neural network model from the flash memory and writes the one or more layers to a page in the RAM. The AI FPGA reads the one or more layers of the neural network model from the RAM over a wide input / output interface, and executes the one or more layers.

Description

Technical Field

[0001] This disclosure generally relates to an architecture that facilitates the storage and execution of neural network models, and more specifically to an artificial intelligence core-coupled memory using multi-chip module packaging technology, which has a field-programmable gate array and a memory die. Background Technology

[0002] Memory availability and bandwidth are bottlenecks during AI inference tasks. In typical edge AI applications, neural network models are stored in non-volatile flash memory, which has low bandwidth access to the AI ​​computing engine, such as a compute engine on a field-programmable gate array (FPGA). During execution, one or more layers of the neural network model are fed to the AI ​​computing engine. During this time, the AI ​​computing engine typically stalls while waiting for memory to fetch the layers containing the neural network model parameters, including both code and parameters. These stalls create idle cycles, reduce overall computational efficiency, and cause power loss. Summary of the Invention

[0003] In one or more embodiments, a system is provided, comprising: flash memory configured to store a neural network model; random access memory (RAM) configured to read one or more layers of the neural network model from the flash memory via a first interface; and an artificial intelligence (AI) field-programmable gate array (FPGA) and / or application-specific integrated circuit (ASIC) configured to read the one or more layers of the neural network model from the RAM via a second interface and execute the one or more layers.

[0004] In one or more embodiments, a method is provided, comprising: reading one or more layers of a neural network model from flash memory via a first interface; writing the one or more layers of the neural network model into random access memory (RAM) via the first interface; reading the one or more layers of the neural network model from the RAM into an artificial intelligence (AI) field-programmable gate array (FPGA) and / or application-specific integrated circuit (ASIC) via a second interface; and executing the one or more layers of the neural network model using the computing engine of the AI ​​FPGA. Attached Figure Description

[0005] Figure 1 A block diagram of a programmable logic device (PLD) according to an embodiment is shown.

[0006] Figure 2 A block diagram of an example memory and PLD architecture according to some embodiments is shown.

[0007] Figure 3 This is a flowchart of an exemplary method for storing and executing a neural network model using a memory and PLD architecture, according to some embodiments.

[0008] Figures 4A to 4B The diagram illustrates the layout of a multi-chip module package on a chip, including a memory and PLD architecture, according to some embodiments.

[0009] Figure 5 The illustration shows a computing device including a multi-chip module package according to some embodiments.

[0010] Figures 6A to 6B This is a diagram illustrating timing for a conventional embodiment of acquiring and executing a neural network model, according to some embodiments.

[0011] Figure 6C This is a diagram illustrating the timing of an example memory and PLD architecture for acquiring and executing a neural network model according to some embodiments.

[0012] The embodiments and advantages of this disclosure are best understood by referring to the following detailed description. It should be understood that similar reference numerals are used to identify one or more similar elements illustrated in the figures. Detailed Implementation

[0013] The embodiments involve creating a background tunnel between memory devices coupled to the AI ​​core (such as flash memory, e.g., SPI flash (Serial Peripheral Interface flash)) and RAM (Random Access Memory) (such as HyperRAM, DRAM, MRAM, etc.). The flash memory may include a DMA (Direct Memory Access) controller, which can be configured by the AI ​​FPGA via descriptor commands. Descriptor commands can be received and / or sent via an SPI / QSPI interface. The DMA controller can create parallel memory interfaces, such as DMA channels, for reading data from the flash memory and writing data to the RAM. The data may include neural network models and / or neural network model components, such as individual neural network layers, code within layers, and parameters. The RAM can provide write channel access to the flash memory and manage arbitration between write accesses from the AI ​​FPGA and regular memory accesses. In some cases, the AI ​​FPGA may perform power gating during this process.

[0014] Figure 1 A block diagram of a programmable logic device (PLD) 100 according to an embodiment of the present disclosure is illustrated. The PLD 100 (e.g., a field-programmable gate array (FPGA), a complex programmable logic device (CPLD), a field-programmable system-on-a-chip (FPSC), or other types of programmable devices) typically includes an input / output (I / O) block 102 and a logic block 104 (e.g., also referred to as a programmable logic block (PLB), a programmable functional unit (PFU), or a programmable logic unit (PLC)).

[0015] I / O block 102 provides I / O functionality to PLD 100 (e.g., support for one or more I / O and / or memory interface standards), while programmable logic block 104 provides logical functionality to PLD 100 (e.g., LUT-based logic or gate array-based logic). Serializer / deserializer (SerDes) block 150 and Physical Coding Sublayer (PCS) block 152 can provide additional I / O functionality. PLD 100 may also include a hard intellectual property core (IP) block 160 to provide additional functionality (e.g., substantially predetermined functionality provided in hardware, which can be configured with less programming than logic block 104).

[0016] PLD 100 may also include memory blocks 106 (e.g., EEPROM blocks, SRAM blocks, and / or flash memory), clock-related circuitry 108 (e.g., clock sources, PLL circuitry, and / or DLL circuitry), and / or various routing resources 180 (e.g., interconnects and appropriate switching logic to provide paths for routing signals throughout PLD 100, such as for clock signals, data signals, or others), as appropriate. Typically, various elements of PLD 100 can be used to implement their intended functions for the desired application, as will be understood by those skilled in the art.

[0017] For example, certain I / O blocks 102 may be used to program memory 106 or to transmit information (such as various types of user data and / or control signals) to / from PLD 100. Other I / O blocks 102 include a first programming port (which may represent a central processing unit (CPU) port, peripheral data port, SPI interface, and / or sysCONFIG programming port) and / or a second programming port, such as a Joint Test Action Group (JTAG) port (e.g., by adopting standards such as IEEE 1149.1 or 1532). In various embodiments, I / O blocks 102 may be included to receive configuration data and commands (e.g., via one or more connections 140) to configure PLD 100 for its intended use, and to support serial or parallel device configuration and information transmission using SerDes block 150, PCS block 152, hard IP block 160, and / or logic block 104, as appropriate.

[0018] It should be understood that the number and placement of various components are not limiting and can depend on the desired application. For example, various components may not be required for the desired application or design specifications (such as the type of programmable device chosen).

[0019] Furthermore, it should be understood that, for clarity, components are illustrated in block form, and various components are typically distributed throughout the PLD 100, such as in and between logic block 104, hard IP block 160, and routing resources 180, to perform their general functions (e.g., storing configuration data for configuring the PLD 100 or providing interconnection structures within the PLD 100). It should also be understood that the various embodiments disclosed herein are not limited to programmable logic devices such as the PLD 100, and can be applied to a variety of other types of programmable and non-programmable devices (e.g., application-specific integrated circuits (ASICs)), as will be understood by those skilled in the art.

[0020] External system 130 can be used to create the desired user configuration or design for PLD 100 and generate corresponding configuration data to program (e.g., configure) PLD 100. For example, system 130 can provide this configuration data to one or more I / O blocks 102, SerDes blocks 150, and / or other parts of PLD 100. As a result, programmable logic blocks 104, various routing resources, and any other appropriate components of PLD 100 can be configured to operate according to the user-specified application.

[0021] In the illustrated embodiment, system 130 is implemented as a computer system. In this respect, system 130 includes, for example, one or more processors 132, which can be configured to execute instructions, such as software instructions, provided in one or more memories 134 and / or stored in non-transitory form in one or more non-transitory machine-readable media 136 (e.g., internal or external to system 130). For example, in some embodiments, system 130 can run PLD configuration software, such as Lattice Diamond System Planner software available from Lattice Semiconductor, to allow a user to create a desired configuration and generate corresponding configuration data to program PLD 100.

[0022] System 130 also includes, for example, a user interface 135 (e.g., a screen or display) for displaying information to the user and one or more user input devices 137 (e.g., a keyboard, mouse, trackball, touchscreen and / or other devices) for receiving user commands or design inputs to prepare the desired configuration of PLD 100.

[0023] The PLD 100 can be an Artificial Intelligence FPGA (AI FPGA), which may facilitate the processing of data input using the code and parameters of a neural network model. In some instances, for efficient data input processing, the PLD 100 can be communicatively coupled and packaged with flash memory that can store the neural network model and random access memory (RAM) that can read layers of the neural network model from the flash memory during initialization, startup, power-on, etc., or it can execute the code and parameters in other layers of the neural network model in parallel with the AI ​​FPGA.

[0024] Figure 2 A block diagram 200 illustrating an example memory and PLD architecture according to some embodiments is shown. Figure 2 The memory and PLD architecture 202 includes flash memory 204, RAM 206, and AI FPGA 208 (which may be PLD 100). Although not shown, the embodiment may also be applied to an AI ASIC instead of AI FPGA 208, or applied in conjunction with AI FPGA 208.

[0025] Flash memory can be a non-volatile storage technology that retains data even when the power is off. Some examples of flash memory include NOR flash, SPI flash, and NAND flash.

[0026] RAM 206 can be a type of volatile memory used in computers and other electronic devices to store data that the computing engine is actively using or processing. Unlike flash memory 204, which retains data when the power is off, RAM typically requires power to maintain the stored information. Furthermore, when the computing device is turned off, and therefore the power is turned off, the data stored in RAM 206 is lost. RAM 206 can be UltraRAM, DRAM (Dynamic RAM), etc. DRAM is high-performance, low-power RAM designed for embedded systems and Internet of Things (IoT) applications. UltraRAM is a variant of DRAM that offers a balance between speed, power consumption, and cost.

[0027] The AI ​​FPGA 208 is a field-programmable gate array designed for artificial intelligence (AI) and machine learning (ML) applications. In some instances, the AI ​​FPGA 208 may be or include components of the PLD 100 discussed above. The AI ​​FPGA 208 comprises one or more integrated circuits, configured with inputs provided by the customer or designer after manufacturing, and consists of an array of programmable logic blocks and a hierarchy of reconfigurable interconnects that can be customized for specific computing tasks.

[0028] In some embodiments, the flash memory 204 and the AI ​​FPGA 208 can communicate via interface 210. Example interface 210 may be a multi-wire serial peripheral interface (SPI), such as a quad SPI (QSPI) interface, octal SPI, etc. QSPI and octal SPI can be extensions of SPI, designed to achieve higher data transfer rates by using four data lines instead of one.

[0029] Similarly, Flash 204 and RAM 206 can communicate via interface 212. Interface 212 can also be QSPI and can be used as a tunnel to transfer data between Flash 204 and RAM 206.

[0030] RAM 206 and AI FPGA 208 can communicate via interface 214. Interface 214 can be a wide input / output (I / O) interface, such as DDR or HyperBus. In some instances, a DDR interface can be used for small language model (SLM) or optimized large language model applications, while a HyperBus interface can be used for low-power edge applications. Interface 214 can be used to fetch data from RAM 206 for execution on AI FPGA 208.

[0031] The AI ​​FPGA 208 can be configured with flash memory 204 using a DMA controller 218. The DMA controller 218 of flash memory 204 can facilitate data transfers from flash memory 204 to RAM 206 without involving the computation engine of the AI ​​FPGA 208. For example, the AI ​​FPGA 208 may include a CCM prefetcher 215, which can send Closed Coupled Memory (CCM) commands to flash memory 204 via interface 210. The CCM commands can be a reduced instruction set computer language, such as RISC-V. The CCM commands can be interpreted by a CCM CMD decoder 216 of flash memory 204, enabling the DMA controller 218 to create a prefetch DMA path between flash memory 204 and RAM 206 via interface 212. This DMA path will facilitate reading data from flash memory 204 and writing data to RAM 206.

[0032] Flash memory 204 can store neural network model 220. Neural network model 220 may include multiple layers, each containing parameters and code. In some instances, neural network model 220 may be 5MB or larger and may have millions or billions of parameters. Example neural network model 220 may be a large language model, a bidirectional encoder representation (BERT) model from a transformer, or another large neural network model. Example layers may be convolutional neural network layers, normalization layers, pooling layers, etc. Additionally, each layer of neural network model 220 may include one or more sublayers, each designed to perform data transformation on the input passed through neural network model 220.

[0033] The layers of neural network model 220 can be written to RAM 206 via interface 212 through a DMA path. In some instances, neural network model 220 can be written for read access.

[0034] RAM 206 may also include multiple pages 222. Layers of the neural network model 220 can be written to pages 222. These layers can be written one at a time or as a group. In some instances, the entire neural network model 220 can also be loaded into RAM 206, provided that the size of the neural network model 220 fits into RAM 206.

[0035] In some instances, the AI ​​FPGA 208 may sleep and not process data when layers of the neural network model 220 are written from flash memory 204 to RAM 206. This could occur during the initialization, power-on, pre-boot, or boot of the computing device. In other instances, the AIFPGA 208 can read layers of the neural network model 220 from some pages 222 using interface 214 when other layers of the neural network model 220 are written to other pages 222 via interface 212. It is worth noting that the neural network model 220 can be loaded into RAM 206 multiple times from flash memory 204 because RAM 206 is not persistent storage and typically does not retain state or data once the computer device is turned off.

[0036] In some instances, the AI ​​FPGA 208 may be power-gated when the neural network model 220 is written to RAM 206.

[0037] In some instances, RAM 206 can manage arbitration between writing data to page 222 and regular memory access from AI FPGA 208.

[0038] In some instances, RAM may retain memory and enter a deep sleep state to conserve energy. Magnetoresistive RAM (MRAM) can be an example of this type of RAM.

[0039] The AI ​​FPGA 208 may include a computing engine 224. The computing engine 224 can read pages 222 from RAM 206, including pages 222 storing layers of the neural network model 220 via interface 214. As discussed above, interface 214 is a wide input / output interface. Once read, the computing engine 224 can execute the layers of the neural network model 220. In some instances, the AI ​​FPGA 208 can read data from RAM 206, such as pages 222 of the neural network model 220, when flash memory 204 writes the layers of the neural network model 220 to pages 222 of RAM 206.

[0040] The above embodiments illustrate improvements over conventional techniques, where the neural network model 220 is not preloaded into RAM 206. The improvement lies in RAM 206 acting as a local cache memory for the AI ​​FPGA 208, which reduces or eliminates the time spent fetching layers of the neural network model 220 from flash memory 204, during which the conventional computing engine might stall. The improvement also involves preloading one or more layers of the neural network model 220 from flash memory 204 into RAM 206 during initialization, power-on, and / or boot times, enabling the AI ​​FPGA 208 to fetch layers of the neural network model 220 from page 222 in RAM 206 without additional fetch time. As a result, fetching data from flash memory 204 is no longer a bottleneck for the AI ​​FPGA 208.

[0041] Although the embodiments discussed above relate to reading, writing, and executing neural network model 220, these embodiments are also applicable to reading, writing, and executing other types of structures, including the data, layers, and parameters of these structures.

[0042] Figure 3 This is a flowchart of an exemplary method 300 for storing and executing a neural network model using flash memory, RAM memory, and an AI FPGA, according to some embodiments. It is worth noting that method 300 is exemplary, and other methods may also be used. Operations 302 to 306 in method 300 can be used... Figures 1 to 2 The hardware circuitry discussed herein shall be used to implement this. Note that one or more operations may be deleted, combined, or performed in different orders, depending on the circumstances.

[0043] In operation 302, a DMA controller is set up in the flash memory. For example, the AI ​​FPGA 208 can issue a CCM command via interface 210, which sets up the DMA controller 218 in flash memory 204. As discussed above, interface 210 can be an SPI interface. In some instances, the AI ​​FPGA 208 can issue the CCM command during initialization, boot-up, power-on, etc. The DMA controller 218 can create a tunnel between flash memory 204 and RAM 206 to read and write data.

[0044] In operation 304, layers of the neural network model, including code and parameters, are read from flash memory and written to RAM via tunneling. For example, by creating a tunnel via interface 212, DMA controller 218 can cause layers of the neural network, including code and parameters, to be read from flash memory 204 and written to RAM 206. Typically, each layer can be stored in one or more pages 222 of RAM 206. During operation 304, AI FPGA 208 can sleep or can read data from other pages 222 in RAM 206 (e.g., pages 222 where parameters and code have not been written from flash memory 204).

[0045] In operation 306, neural network code and / or data are read via a wide I / O interface from RAM to the AI ​​FPGA. For example, the AI ​​FPGA 208 can read layers of the neural network model 220, including parameters and code, via interface 214, which can be a wide I / O interface. In some instances, the parameters and code of the neural network model 220 can be read from one or more pages 222 in RAM 206.

[0046] In operation 308, layers of the neural network, including code and / or parameters, are executed. For example, the computation engine 224 of the AI ​​FPGA 208 can execute the code and parameters of the neural network model 220 to process data inputs, such as inputs from a camera, dataset, etc.

[0047] Figures 4A to 4B Figures 400A to 400B are shown in some embodiments of a multi-chip module package on a chip. Figures 4A to 4B The illustration shows a multi-chip module (MCP) package (POC) (also known as MCP POC402) according to some embodiments, which includes flash memory 204, RAM 206, and AI FPGA 208. Notably, flash memory 204 is adjacent to RAM 206 (e.g., within 308.75 mm), and RAM 206 is adjacent to AI FPGA 208 (e.g., within 308.75 mm) to improve data transfer speeds using interfaces 212 and 214 (not shown). Furthermore, as... Figure 4B As illustrated, flash memory 204, RAM 206, and AI FPGA 208 are situated on die 404, which facilitates faster data transfers between flash memory 204 and RAM 206 via interface 212 and between RAM 206 and AI FPGA 208 via interface 214. In some instances, flash memory 204, RAM 206, and AI FPGA 208 can communicate using a direct die-to-die bonding interface (not shown) or an interposer (not shown), which can further increase bandwidth via parallel connectivity. The interposer may be an electrical conduit, may connect components in a multi-chip module package on the chip, and may be made of silicon or another organic material.

[0048] Figure 5 Figure 500 illustrates a computing device with an AI FPGA according to an embodiment. Figure 5 The illustration shows a computing device 502, which can be a laptop computer, smartphone, tablet computer, desktop computer, etc. Although only the AI ​​FPGA 208 is shown in computing device 502, computing device 502 also includes... Figures 4A to 4B The MCP POC 402 discussed herein. In some embodiments, the AI ​​FPGA 208 may receive input from various input devices in the computing device 502. For example, Figure 5 The illustration shows an embodiment where the AIFPGA 208 receives input from a camera 504 via an interface 506, which may be a MIPI CSI. For example, the input may be an image, for which the AI ​​FPGA 208 can use a neural network model (such as one loaded into RAM 206 and acquired by the AI ​​FPGA 208) Figure 2 (As discussed in the text) to determine the objects displayed in the image.

[0049] Figures 6A to 6B The timing diagrams 600A to 600B are conventionally designed according to some embodiments, and Figure 6C This is the timing diagram for MCPPOC 402. Figures 6A to 6C The illustration shows an improvement of the MCP POC 402 compared to a conventional design according to some embodiments. Figure 6A The illustration depicts a conventional embodiment where each layer of the neural network model is read directly from flash memory and then executed. These layers are read serially, with a conventional AI FPGA performing fetch 602A to retrieve a portion of the first layer of the neural network model, followed by execution 604A, which executes the retrieved portion of the first layer. Then, the conventional AI FPGA performs fetch 602B to retrieve another portion of the first layer, followed by execution 604B for that portion of the first layer. It is worth noting that... Figure 6AThe process described is highly serialized, causing the AI ​​FPGA's computing engine to be in a dormant state and not processing data during fetching 602A and 602B. Furthermore, although the AI ​​FPGA may have local memory within the AI ​​FPGA, the local memory is insufficient to store the layers of the neural network model, causing the AI ​​FPGA to use serialized fetching (such as fetching 602A and 602B) to retrieve the layer from flash memory (not shown).

[0050] Figure 6B The illustration depicts a conventional embodiment where neural network layers can be acquired at the node and / or instruction level as acquisitions 606A and 606B. Once acquisition of 606A is complete, the AI ​​FPGA can execute the first node's execution 608A, and once acquisition of 606B is complete, it can execute the second node's execution 608B. Figure 6A The implementation methods differ. Figure 6B The embodiments in the example are not serialized because the acquisition 606B of the second node can be performed in parallel with the execution 608A of the first node.

[0051] Figure 6C The diagram shows Figures 1 to 5 The embodiment discussed above. As discussed above, RAM 206 acts as a local cache memory for the AI ​​FPGA 208, without increasing fetch time because the layers in page 222 can be fetched via the wide I / O interface 214. As a result, fetching the layers of the neural network model 220 from flash memory 204 is no longer a bottleneck because these layers are pre-written into RAM 206. Figure 6C In this context, the efficiency of executing neural network model 220 depends on the capacity of the silicon device.

[0052] Where applicable, the various embodiments provided by this disclosure may be implemented using hardware, software, firmware, or a combination of hardware, software, and firmware. Furthermore, where applicable, the various hardware and / or software components described herein may be combined into composite components comprising software, hardware, and / or both, without departing from the spirit of this disclosure. Where applicable, the various hardware and / or software components described herein may be separated into sub-components comprising software, hardware, and / or both, without departing from the spirit of this disclosure. Additionally, where applicable, it is contemplated that software components may be implemented as hardware components, and vice versa.

[0053] The software (such as program code and / or data) according to this disclosure may be stored on one or more non-transitory machine-readable media. It is also contemplated that the software identified herein may be implemented using one or more networked and / or other general-purpose or special-purpose computers and / or computer systems. Where applicable, the order of the various steps described herein may be changed, combined into compound steps, and / or separated into sub-steps to provide the features described herein.

[0054] The above embodiments are illustrated but do not limit the invention. It should also be understood that many modifications and variations are possible based on the principles of the invention. Therefore, the scope of the invention is defined only by the following claims.

Claims

1. A system comprising: Flash memory is configured to store neural network models; Random access memory (RAM) is configured to read one or more layers of the neural network model from the flash memory via a first interface; as well as Artificial intelligence (AI) field-programmable gate arrays (FPGAs) and / or application-specific integrated circuits (ASICs) are configured to read one or more layers of the neural network model from the RAM via a second interface and execute the one or more layers.

2. The system of claim 1, wherein the AI ​​FPGA is further configured to issue a Closed Coupled Memory (CCM) command to the flash memory via a third interface, wherein the CCM command enables a Direct Memory Access (DMA) controller at the flash memory.

3. The system according to claim 2, wherein the third interface is a multi-wire serial peripheral interface (QSPI).

4. The system of claim 2, wherein the DMA controller is configured to create a tunnel through the first interface to read one or more layers of the neural network model from the flash memory and write one or more layers of the neural network model into the RAM.

5. The system according to claim 1, wherein the first interface is a multi-wire SPI interface.

6. The system of claim 1, wherein one or more layers of the neural network model are written to multiple pages in the RAM.

7. The system of claim 6, wherein the AI ​​FPGA is further configured to read a first layer of the neural network model stored in a first page from the plurality of pages via the second interface, while the RAM is configured to write a second layer from the flash memory to a second page of the plurality of pages.

8. The system of claim 1, wherein the second interface is a wide input / output interface.

9. The system of claim 1, wherein the RAM is further configured to read and write one or more layers of the neural network model via the first interface during startup of the computing device.

10. The system of claim 1, wherein in a multi-chip module package on a chip, the flash memory is adjacent to the RAM, and the RAM is adjacent to the AI ​​FPGA.

11. A method comprising: One or more layers of the neural network model are read from flash memory via the first interface; The first interface is used to write one or more layers of the neural network model into the random access memory (RAM). The second interface is used to read one or more layers of the neural network model from the RAM into an artificial intelligence field-programmable gate array (FPGA) and / or application-specific integrated circuit (ASIC); as well as The computational engine of the AI ​​FPGA is used to execute one or more layers of the neural network model.

12. The method of claim 11, further comprising: The AI ​​FPGA sends Closed Coupled Memory (CCM) commands to the flash memory via a third interface. as well as Use the CCM command to enable the Direct Memory Access (DMA) controller at the flash memory.

13. The method according to claim 12, wherein the first interface and / or the third interface is a multi-wire SPI interface or a direct die-to-die interface.

14. The method of claim 12, further comprising: Using the DMA controller, a tunnel is created through the first interface to read one or more layers of the neural network model from the flash memory and write one or more layers of the neural network model into the RAM.

15. The method of claim 11, wherein the one or more layers of the neural network model are written to a plurality of pages in the RAM.

16. The method of claim 15, further comprising: The AI ​​FPGA reads the first layer of the neural network model stored in the first page from the plurality of pages through the second interface, while the RAM writes the second layer from the flash memory to the second page of the plurality of pages.

17. The method of claim 11, wherein the second interface is a wide input / output interface or a direct die-to-die interface.

18. The method of claim 11, wherein the reading and writing of one or more layers of the neural network model in the RAM occur during the initialization of the computing device.

19. The method of claim 11, wherein in a multi-chip module package on a chip, the flash memory is adjacent to the RAM, and the RAM is adjacent to the AI ​​FPGA.

20. A system comprising: Flash memory is configured to store data structures; Random access memory (RAM) is configured to load a portion of the data structure from the flash memory via a first interface; as well as Artificial intelligence (AI) field-programmable gate arrays (FPGAs) and / or application-specific integrated circuits (ASICs) are configured to read a portion of the data structure from the RAM via a second interface and execute that portion of the data structure.

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