FFT (Fast Fourier Transform) inverted sequence processing method and device, radar receiver and memory

Abstract

The invention discloses an FFT (Fast Fourier Transform) inverse sequence processing method and device and a radar receiver, which support parallel inverse sequence processing of FFT of multiple paths of data, meet the real-time processing requirement of data, realize efficient completion of inverse sequence conversion of input data and reduce resources. Furthermore, ping-pong cache is used in the system to improve the data access efficiency, and parallel processing between inverted conversion and storage and subsequent butterfly operation is added, so that the processing delay is really reduced, and the performance of the system is optimized.

Description

Technical Field

[0001] This application relates to, but is not limited to, digital signal processing technology, and particularly to an FFT reverse processing method and apparatus, a radar receiver, and a memory. Background Technology

[0002] In radar baseband signal processing, especially for Decimation in Time (DIT) structures using Fast Fourier Transform (FFT) (referred to as DIT-FFT), reversing the order of the input data is a crucial step. Due to the nature of the FFT algorithm itself, in DIT-FFT, the order of the input data needs to be reversed before entering the FFT process to ensure the correctness and efficiency of subsequent processing.

[0003] DIT-FFT is widely used in radar signal processing. In DIT-FFT, the input data needs to be reverse-ordered before FFT processing. How to efficiently perform this reverse-ordering of the input data is a crucial problem that needs to be solved in DIT-FFT processing. Summary of the Invention

[0004] This application provides an FFT reverse processing method and apparatus, a radar receiver, and a memory, which can meet the needs of real-time data processing and reduce resource consumption.

[0005] This invention provides an FFT inversion processing method, including:

[0006] Acquire one or more channels of data that require FFT processing;

[0007] Perform parallel reverse processing on more than one stream of data;

[0008] Perform FFT processing on the data to be processed after reversing the order of the data.

[0009] In one exemplary instance, prior to the reverse order processing, the process further includes:

[0010] Zero-padding is performed on the data to be processed in one or more channels so that the length of the data to be processed in one or more channels is the same as the number of FFT points.

[0011] In one exemplary instance, the parallel reverse processing of more than one stream of data includes:

[0012] The parallel reverse processing is performed in real time during the transmission of the above-mentioned data.

[0013] In one exemplary instance, the parallel reverse processing of more than one stream of data includes:

[0014] The parallel reverse processing is performed in real time during the input buffering of the data to be processed in one or more channels, so that the data stored in the input buffer is arranged in reverse order.

[0015] In one exemplary instance, the input buffer is a memory employing a ping-pong mode.

[0016] In one exemplary instance, the data to be processed, including one or more channels, is obtained through any one or any combination of the following interfaces:

[0017] Analog-to-digital converter interface, direct memory access interface, and universal asynchronous transceiver interface.

[0018] In one exemplary instance, it also includes:

[0019] When reverse processing is not required, the obtained data that needs to be processed by FFT is output to other non-FFT processing.

[0020] In one exemplary instance, the FFT processing includes FFTs of different cardinality types;

[0021] The different cardinality types of FFT include radix-2, radix-3, radix-4, or radix-8.

[0022] In one exemplary instance, prior to the reverse processing, the data to be processed is further subjected to one or any combination of the following processes: data decompression or data type conversion, data masking, and data scattering.

[0023] This application also provides a computer-readable storage medium storing computer-executable instructions for executing the FFT inversion processing method described in any of the above claims.

[0024] This application embodiment further provides a computer device, including a memory and a processor, wherein the memory stores the following instructions executable by the processor: steps for performing the FFT reversal processing method described in any of the above claims.

[0025] This application embodiment further provides an FFT inversion processing apparatus, including: an acquisition module, an inversion processing module, and an FFT processing module; wherein,

[0026] The acquisition module is used to acquire one or more channels of data that need to be processed by FFT.

[0027] The reverse processing module is used to perform parallel reverse processing on more than one stream of data.

[0028] The FFT processing module is used to perform FFT processing on data to be processed in one or more channels after reverse processing.

[0029] In one exemplary instance, it also includes: an input cache module and an output cache module, wherein,

[0030] An input cache module is used to store the data after the reverse processing;

[0031] An output buffer module is used to store the data processed by the FFT.

[0032] In one exemplary instance, the input cache module and / or the output cache module employ a distributed-aggregated data read / write method.

[0033] In one exemplary instance, the input cache module and / or the output cache module are memories employing a ping-pong mode.

[0034] In one exemplary instance, a switch module is also included, configured to: when reverse processing is required, output the obtained data to be processed (one or more channels) to the reverse processing module; and when reverse processing is not required, output the obtained data to be processed (one or more channels) to other non-FFT processing modules.

[0035] In one exemplary instance, the acquisition module includes an analog-to-digital converter interface, a direct memory access interface, a serial peripheral interface, an integrated circuit interconnect interface, and a universal asynchronous transceiver interface.

[0036] This application also provides a radar receiver, including the FFT reverse processing apparatus described in any of the above claims.

[0037] This application embodiment further provides a memory, including: an interface module, a processing module, and a cache module; wherein,

[0038] The interface module is used to input the data to be processed;

[0039] The processing module is used to enable or disable real-time processing functions according to user configuration, and to process the input data to be processed through the enabled real-time processing functions; wherein, the real-time processing functions include one or any combination of the following: zero padding, address inversion, data decompression or data type conversion, data masking, and data scattering;

[0040] The caching module is used to write data that has been processed by the processing module.

[0041] In one exemplary instance, the interface module includes: an ADC interface and a DMA interface.

[0042] In one exemplary instance, the interface module is further configured to output data read from the cache module; correspondingly,

[0043] The real-time processing functions in the processing module include one or any combination of the following: data aggregation, data compression, or data type conversion.

[0044] The FFT inversion processing method and apparatus provided in this application support parallel inversion processing of multi-channel data, meeting the requirements of real-time data processing, achieving efficient inversion of input data, and reducing resources. Furthermore, the system uses ping-pong caching to improve data access efficiency, and the parallel processing between inversion transformation, storage, and subsequent butterfly operations truly reduces processing latency and optimizes system performance.

[0045] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description, claims and drawings. Attached Figure Description

[0046] The accompanying drawings are used to provide a further understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0047] Figure 1 This is a schematic diagram illustrating the reverse order of input data for a 16-point DIT-FFT in related technologies.

[0048] Figure 2 This is a schematic diagram illustrating the process of data interaction between the data source and the DIT-FFT module in related technologies;

[0049] Figure 3 This is a flowchart illustrating the FFT inversion processing method in the embodiments of this application;

[0050] Figure 4 This is a schematic diagram of a parallel reverse processing procedure in an embodiment of this application;

[0051] Figure 5 This is a schematic diagram illustrating the process of data interaction between the data source and the DIT-FFT module in an embodiment of this application;

[0052] Figure 6 This is a schematic diagram illustrating the process of reverse processing implemented during the input buffering of data to be processed in the embodiments of this application;

[0053] Figure 7 This is a schematic diagram illustrating the process of the distributed-aggregated data read / write method in the embodiments of this application;

[0054] Figure 8 A schematic diagram illustrating the application of the FFT inversion processing method provided in this application embodiment to PBUF;

[0055] Figure 9 This is a schematic diagram of the composition of the FFT reverse processing device in the embodiments of this application. Detailed Implementation

[0056] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0057] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be more thorough and complete.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0059] It is understood that the terms "first" and "second" used in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0060] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0061] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0062] Figure 1 This is a schematic diagram illustrating the reverse order of input data for a 16-point DIT-FFT in related technologies, such as... Figure 1 As shown, before performing FFT calculations, the original input data can be reversed according to the requirements of the DIT algorithm by performing bit reversal. Figure 1 The data displayed on the left shows the numerical order obtained by reversing the original input data (i.e., the data source) from 0 to 15. The reversed data then enters each butterfly stage of the FFT, where it is weighted, combined, and updated according to specific rules. After multiple butterfly operations, the final output data order will be arranged according to the FFT calculation results. Figure 1 On the right side, each output data point corresponds to a component in the frequency domain. This reverse order is crucial in DIT-FFT because it ensures that the input data is processed in the correct order, enabling the FFT calculation to correctly generate the frequency domain signal.

[0063] To improve data processing efficiency, the data source and the DIT-FFT module interact through a ping-pong cache. This method minimizes waiting time during data input and output and makes data processing more continuous and efficient. Figure 2 This is a schematic diagram illustrating the process of data interaction between the data source and the DIT-FFT module in related technologies, such as... Figure 2 As shown, data is input from the data source into the input buffer (Input Memory). The Input Memory uses a ping-pong mode, meaning that while processing a portion of the data, the next portion can be prepared in the background. This way, when the current batch of data is finished, the next batch is already ready, reducing processing downtime. The input data enters the FFT module in sequence (0,1,2,...). First, this data undergoes reverse sorting processing by the first reverse module. The first reverse module is responsible for reversing the input data according to the FFT requirements, ensuring the correctness of subsequent calculations. Next, the reversed data (referred to as reversed data) is written into an internal memory module, which can be understood as a temporary storage for the reversed data. Then, the reversed data in the memory module is read in a predetermined order and sent to each stage of the FFT calculation to begin the butterfly operation. Each butterfly stage (e.g., ...) Figure 2The butterfly stage 0, butterfly stage 1, and so on, perform successive Fourier transform operations on the data to ultimately generate a frequency domain signal. Finally, the result of the FFT processing is written to the output memory, which also uses a ping-pong mode. This ensures that while one batch of data is being processed and output, the processing of the next batch of data has already begun or is ready, further improving the system's efficiency.

[0064] It should be noted that the above description only uses the radar baseband signal processing architecture using FFT-DIT as an example, but it is not intended to limit the application scope of this application. The embodiments of this application can be applied to other scenarios that require fast Fourier transform, because in these scenarios, the speed and efficiency of data processing are also crucial.

[0065] from Figure 2 As shown in the diagram, the data interacts with the data source and the DIT-FFT module. After passing through the first inversion module, the data is written to memory. This data interaction method indicates that the inversion transformation is a separate process before the data enters the FFT processing, rather than being completed in real time during data transmission. This may result in additional latency between the inversion transformation and storage. Figure 2 In this system, the reverse transformation, storage, and subsequent butterfly operation form a sequential processing flow. This means that data must first be reverse-transformed, then stored, and finally subjected to the FFT butterfly operation. This sequential processing method limits real-time processing capabilities, especially at high data rates, where this structure may not meet real-time requirements. Furthermore, although the system uses a ping-pong cache to improve data access efficiency, because the reverse transformation, storage, and subsequent butterfly operation are sequential processes, the ping-pong cache can only partially alleviate the data transmission bottleneck and cannot solve the latency problem inherent in the reverse transformation itself.

[0066] This application provides an embodiment of an FFT inversion processing method, such as... Figure 3 As shown, it may include:

[0067] Step 300: Obtain one or more channels of data to be processed that require FFT processing.

[0068] In one exemplary instance, the data to be processed may include one, two, or multiple channels. The data to be processed can be acquired through various types of input interfaces, including but not limited to analog-to-digital converter (ADC) interfaces, direct memory access (DMA) interfaces, universal asynchronous transmitter (UART) interfaces, serial peripheral interface (SPI), integrated circuit interconnect (I2C) interfaces, etc.

[0069] Step 301: Perform parallel reverse processing on more than one channel of data to be processed.

[0070] In one exemplary instance, the functionality supporting multi-channel parallel reverse processing can be implemented through hardware, software, or a combination of both. For example, dedicated hardware circuits or field-programmable gate arrays (FPGAs) can be designed to implement multi-channel parallel address reverse processing. Another example is in a multi-core processor or multi-threaded environment, where parallel algorithms are written in software to utilize multiple threads or tasks to process address reverse operations on multiple data streams. Yet another example is that critical reverse processing operations can be accelerated by hardware, while overall control and task management are implemented in software. For instance, an FPGA can be used to implement the core parallel reverse processing logic, while an embedded processor runs control software to manage data flow and system operations.

[0071] In one exemplary instance, the reverse processing in step 301 can be completed in real time during the data transmission process, without storing the data in a separate buffer. This approach is suitable for scenarios requiring high processing speeds and real-time processing capabilities.

[0072] In one exemplary instance, the reverse order processing in step 301 can be implemented during the input buffering of the data to be processed, so that the data to be processed is already in reverse order when stored in the input buffer. In one embodiment, the buffer can be a ping-pong mode memory.

[0073] Figure 4 This is a schematic diagram of a parallel reverse processing procedure in an embodiment of this application, as shown below. Figure 4 As shown, the data to be processed, i.e., the data source, is multi-channel ADC data, such as... Figure 4 The system contains five ADC data channels: ADC channel 0, ADC channel 1, ADC channel 2, ADC channel 3, and ADC channel 4. Each ADC data channel will subsequently undergo independent FFT operations. This embodiment uses a radar signal processing scenario as an example, where each ADC data channel will be used independently for range-dimensional FFT operations. Therefore, before each ADC data channel is used independently for range-dimensional FFT operations, it will be processed in parallel according to step 301 of the FFT inversion processing method provided in this embodiment.

[0074] It should be noted that, Figure 4The illustrated embodiment is merely an example; the data source is not limited to ADC data and can also be DMA or other data sources. For instance, in radar signal processing, during velocity-dimensional FFT processing, data is often moved from DMA to a buffer using a ping-pong mode. In this case, step 301 of the FFT reverse processing method provided in this application embodiment can be used to perform real-time reverse processing on the data moved from DMA to the buffer, so that the data stored in the buffer is the data after reverse processing.

[0075] The reverse processing in this embodiment supports parallel processing of multiple data streams, which means that the reverse conversion of multiple FFT input data streams can be completed simultaneously, thus achieving efficient reverse conversion of input data.

[0076] In one exemplary instance, when the reverse processing is implemented using hardware or a combination of hardware and software, to better adapt to more application scenarios and increase system flexibility, the process before step 301 may further include: determining whether reverse processing is required; if required, continuing the reverse processing in step 301; if not required, exiting the application process and proceeding to other non-FFT processing, such as filtering, modulation / demodulation, correlation accumulation, or non-correlation accumulation. This means the system can perform different types of signal processing operations as needed, no longer limited to FFT operations. Taking hardware implementation of reverse processing as an example, the reverse function can be enabled or disabled via a switch configuration. This allows the same data source to be used in different applications without necessarily performing FFT operations on the data source, improving the compatibility of the embodiments of this application and expanding the application scope of the embodiments of this application.

[0077] In one exemplary instance, to ensure that the length of the data entering the FFT process is consistent with the number of FFT points to meet the requirements of the FFT algorithm, when the length of the input data to be processed is less than the number of FFT points, step 301 may further include:

[0078] Before reversing the order, zero-padding can be performed on the data to be processed, including leading zeros and / or trailing zeros, so that the length of the data to be processed is the same as the number of FFT points.

[0079] The FFT point count refers to the number of input data samples required by the FFT algorithm, typically a power of 2, such as 64, 128, 256, 512, 1024, etc. These point counts correspond to the length of the input data, that is, the length of the data sequence processed by the FFT algorithm.

[0080] In this embodiment of the application, the parallel processing of multiple data streams enables real-time reverse processing of FFT for multiple data streams simultaneously. For example, four data streams, each with 1024 points, will all undergo 1024-point FFT after reverse processing.

[0081] Step 302: Perform FFT processing on the data to be processed after reversing the order of one or more channels.

[0082] In one exemplary instance, FFT processing may include, but is not limited to, FFTs of different radix types, such as radix-2, radix-3, radix-4, and radix-8. That is, the reverse processing in this embodiment supports reverse processing of FFTs of different radix types.

[0083] radix-2, radix-3, radix-4, and radix-8 are radixes in different FFT algorithms, referring to the number of points involved in each butterfly operation. radix-2 FFT is the most commonly used FFT algorithm, processing two data points at a time, resulting in high computational efficiency. radix-3 FFT processes three data points at a time, suitable for multiples of three. radix-4 FFT processes four data points at a time, reducing the number of multiplication operations compared to radix-2. radix-8 FFT processes eight data points at a time, further optimizing computational efficiency in larger-scale FFTs. Supporting FFT reversal processing with these different radixes means the system can handle multiple different FFT algorithms and can reverse the input or output data in each FFT algorithm.

[0084] The FFT algorithm computes the entire FFT by decomposing it into multiple smaller radixes. For example, a 1024-point FFT can be decomposed into 10 levels of butterfly operations using radix-2 (1024 = 2^32). 10 It can also be decomposed into 5 levels of butterfly operations using radix-4 (1024 = 4). 5 ).

[0085] Figure 5 This is a schematic diagram illustrating the data interaction process between the data source and the DIT-FFT module in this embodiment of the application. The InputMemory and OutputMemory use a ping-pong mode, such as... Figure 5 As shown, before the data is input from the data source into the Input Memory, the inversion module performs reverse processing in real time. This eliminates the need for memory allocation within the FFT module to temporarily store the reverse processing results. Furthermore, the inversion module supports parallel processing of multiple data streams, enabling simultaneous inversion of multiple FFT input data streams. Additionally, the inversion module supports on / off configuration, allowing users to enable or disable the reverse processing function based on different application scenarios, facilitating subsequent data processing needs such as FFT operations or non-FFT operations. Figure 5 As shown in the example, the embodiments of this application support parallel reverse processing of FFT for multi-channel data, which meets the real-time data processing requirements, achieves efficient reverse transformation of input data, and reduces resources. At the same time, the system uses ping-pong caching to improve the efficiency of data access. In addition, the parallel processing between reverse transformation and storage and subsequent butterfly operations truly reduces processing latency and optimizes system performance.

[0086] In one exemplary instance, where reverse processing is implemented during the input buffering of the data to be processed, reverse FFT processing is enabled during the input buffering process, and the data is distributed and written to different storage spaces in the input buffer to further improve data processing efficiency. For example, in radar signal processing, during velocity-dimensional FFT processing, data is moved from direct memory access (DMA) to a ping-pong mode memory. Figure 6 As shown, during data transfer, DMA distributes data across different storage spaces. Furthermore, enabling FFT address reversal processing further improves data processing efficiency. Figure 6 As shown, this embodiment includes 16 DMA packages, each containing a set of data. This data is transferred from the source location to RAM via the DMA controller, and is processed in reverse order during the transfer. During the data distribution phase, i.e., when writing data, the data in each DMA package (e.g., A1, A2, A3, A4, etc.) is not stored contiguously in the input buffer, but is distributed to different memory addresses according to specific mapping rules, such as... Figure 6 As shown, data blocks A1, A2, A3, A4, etc., are allocated to different storage units in the input cache, such as RAM. This optimizes memory usage and improves data access efficiency. During the data aggregation phase, i.e., when reading data, the memory controller extracts data from different storage units according to the previous mapping rules and recombines them into a meaningful dataset.

[0087] In one embodiment, the process of the distributed-aggregated data read / write method is illustrated as follows: Figure 7 As shown, in this embodiment, it is assumed that the source data includes 16 data packets, i.e. Figure 7 The first through sixteenth data packets in the memory are each containing several data elements. For example, the first data packet includes A1, A2, A3…A16, the second data packet includes B1, B2, B3…B4, etc. These data elements are arranged in different address spaces. The target memory (RAM) is divided into 16 storage unit blocks. For example… Figure 7As shown, during the data scattering phase, when metadata is written to RAM, data packets from different sources are scattered and written to different storage blocks in the target RAM. This means that elements in each data packet are not stored sequentially in memory, but are allocated to different storage blocks according to pre-set address mapping rules. For example, A1, A2, A3, and A4 are allocated to different columns in RAM, while B1, C1, D1, and E1 are allocated to the same storage block as A1. During the data aggregation phase, when data is read from RAM, the data elements scattered in memory are re-aggregated according to the previously pre-set address mapping rules. That is, data from different storage blocks is read and reorganized into a continuous data stream. The scatter-aggregate data read / write method optimizes memory usage, enabling efficient access to different storage blocks and improving the parallelism of data transmission and processing efficiency, especially in systems that require processing large amounts of data, such as image processing, real-time signal processing, and high-performance computing applications.

[0088] This application also provides a computer-readable storage medium storing computer-executable instructions for performing the FFT reversal processing method described in any of the above claims.

[0089] This application further provides a computer device, including a memory and a processor, wherein the memory stores the following instructions executable by the processor: steps for performing the FFT reversal processing method described in any of the preceding claims.

[0090] Figure 8 A schematic diagram illustrating the application of the FFT reverse processing method provided in this application embodiment to the Ping Pong Buffer (PBUF) microarchitecture is shown below. Figure 8As shown, MBUF and SBUF are two buffer areas. MBUF is divided into 32 columns (columns 0-31), storing data from different input sources, such as DMA channels or ADC converters. SBUF is divided into 32 columns (columns 32-63), each used to process different data paths. RO indicates a read-only operation, meaning that data read from PBUF will not be modified; the read data may be directly used for subsequent calculations or forwarded to other processing units. WO indicates a write-only operation, used in scenarios where data needs to be temporarily stored for later processing. RW indicates a read-write operation, where data can be read and written, allowing modification or updates during processing. The Address Reverse module, used to implement the reverse processing in this embodiment, is a key module in the PBUF microarchitecture, especially for FFT operations. Since the FFT algorithm requires the input data to be arranged in reverse bit order, the address reversal module is responsible for performing this reversal operation in real time during data writing. By reversing the address order during data writing, an additional reversal operation is avoided during FFT calculation, thus saving time and resources and improving the overall efficiency of the system. Figure 7 The data aggregation shown is Scatter. Figure 7 The diagram illustrates the dispersion. Zero padding is used to pad the data to be processed with zeros as needed before reverse processing, including leading and / or trailing zeros, so that the length of the data to be processed is the same as the number of FFT points. Other methods include: Data masking, which is used to mask invalid bits or noise in the data, ensuring that only valid data is processed. This is especially important in FFT and other sensitive signal processing tasks. Data decompression / data compression (CPS / DCP) or type conversion can be used to convert data from one format to another, or to perform digital-to-analog / analog-to-digital conversion, to ensure that the data is compatible between different processing units and maintains consistency in different computational processes. Figure 8In the FFT engine, interfaces supporting FFT Address Reverse include DMA0, DMA2, ADC, and STATS_RLT. DMA0 and DMA2 interfaces are used for efficient data transfer; integrating FFT Address Reverse ensures that data transferred from DMA0 and DMA2 to the FFT engine is bit-reversed, requiring no additional processing. The ADC interface converts analog signals to digital signals; integrating address reversal means that the ADC output data can directly enter FFT processing without additional reversal processing. The STATS_RLT module can be used to process statistical results or real-time data; integrating address reversal ensures that statistical data or real-time data is bit-reversed before entering the FFT engine, optimizing the efficiency of real-time data processing.

[0091] The following two examples from radar signal processing demonstrate how to perform operations such as zero padding, data masking, and address reversal on data in real-time processing to optimize the FFT processing flow.

[0092] In one embodiment, writing ADC data to the PBUF buffer is taken as an example. In this example, the system processes ADC data and writes it to the PBUF. During this process, there are two real-time processing functions that can be enabled or disabled: First, when the ADC data is insufficient to meet the number of points required for FFT, the system will pad the data with zeros. For example, if the original number of points in the ADC data is 500, but the system needs to perform a 512-point FFT, the system will add 12 zeros to the end of the ADC data to ensure that the number of points in the input data matches the requirements of the FFT processing. Second, the FFT algorithm usually requires the input data to be arranged in reverse bit order to improve computational efficiency. Therefore, before performing FFT processing, the system will reverse the address of the ADC data to prepare for the execution of FFT. The address reversal operation rearranges the data according to the number of data points to ensure that it meets the requirements of the FFT algorithm. In one embodiment, the user can configure through the user interface to choose to enable or disable one or more real-time processing functions.

[0093] For example, when ADC data (500 points) is written to PBUF, during real-time processing, zero padding is used to fill in zeros to 512 points, and address reversal is performed using the address reversal module. Then, the data is written to PBUF via a Word operation for subsequent FFT processing.

[0094] In one embodiment, the example of moving external data into the PBUF cache via a Direct Memory Access (DMA) interface is used. In this example, external data is moved into the PBUF cache via the DMA interface. During this process, four real-time processing functions can be enabled or disabled: First, data decompression (DCP) or type conversion (Type Conversion) is performed to make the external data type consistent with the data types of the PBUF and subsequent modules. For example, if the external data is in a compressed format or its data type differs from the format required by the PBUF (e.g., 8-bit or 16-bit data), the data will be decompressed or converted to the data format required by the PBUF and subsequent processing modules. Second, a data mask is used to select (or filter) data, allowing the selection of some data while discarding unnecessary data. By applying a data mask, the system can filter out data that needs further processing, thereby reducing the amount of data written to the PBUF and optimizing cache utilization and processing efficiency. Third, data scattering is used to distribute and organize continuous data into different data blocks to adapt to subsequent processing of the same data. Distributing data is very useful when processing large-scale datasets, especially when the next step requires processing the data in chunks. This prepares the data for subsequent parallel processing. Fourth, address reversal prepares the data for subsequent FFT processing. Similar to the example of writing ADC data to the PBUF buffer, the address reversal function reverses the data addresses to prepare for FFT processing. In one embodiment, the user can configure the interface to enable or disable one or more real-time processing functions.

[0095] For example, after the ADC data completes the first FFT processing (called range-dimensional FFT), the result is usually stored in compressed form outside the PBUF. The next step in radar processing is to perform a second FFT (also called velocity-dimensional FFT). At this point, the range-dimensional FFT data is moved into the PBUF via a DMA interface. During this process, the data first needs to be decompressed to adapt to the PBUF and subsequent FFT processing data formats. After decompression, multiple data points are obtained. Optionally, some range-dimensional data can be retained, such as selecting one or several range data points to keep in the PBUF. Then, based on the data processing dimension, the data is distributed into different data blocks to meet the data block processing requirements of the velocity-dimensional FFT. Finally, address reversal is performed to prepare for the second FFT.

[0096] Figure 8The memory shown may also include other functional modules, such as: the stats_rlt module and the stats_dat module, which are used to process statistically related results or data, respectively; the ccmb0_dat module and the ccmb1_dat module, which are data for the combined module; the fft_dat module, which is used for FFT-related data processing; and the User module, which represents a custom or user-defined module. The implementation of these modules is common to those skilled in the art, and the specific implementation is not intended to limit the scope of protection of this application, and will not be described in detail here.

[0097] Figure 8 The PBUF architecture shown integrates real-time address reversal functionality, enabling data preprocessing before it enters the FFT engine, thus significantly optimizing FFT computation efficiency. All interfaces supporting FFT Address Reverse (such as DMA0, DMA2, ADC, and STATS_RLT) ensure optimal data transmission and processing, reducing system latency and improving resource utilization.

[0098] This application embodiment also provides a memory, combined with Figure 8 It includes at least: an interface module, a processing module, and a caching module; among which,

[0099] An interface module is used to input data to be processed. In one embodiment, the interface module may include various types, such as, but not limited to, ADC interfaces, DMA interfaces, etc.

[0100] The processing module is used to enable or disable real-time processing functions according to user configuration, and to process the input data to be processed through the enabled real-time processing functions; wherein, the real-time processing functions include one or any combination of the following: zero padding, address inversion, data decompression or data type conversion, data masking, and data scattering.

[0101] The caching module is used to write data that has been processed by the processing module.

[0102] In one exemplary instance, the interface module is also used to output data read from the caching module. Accordingly, the real-time processing functions in the processing module include one or any combination of the following: data aggregation, data compression, or data type conversion.

[0103] The memory provided in this application embodiment integrates a real-time address reversal function, which preprocesses the data before it enters the FFT engine, thus ensuring a significant optimization of the efficiency of FFT calculation.

[0104] Figure 9 This is a schematic diagram of the composition structure of the FFT reverse processing device in the embodiments of this application, as shown below. Figure 9As shown, it includes at least: an acquisition module, a reverse processing module, and an FFT processing module; wherein,

[0105] The acquisition module is used to acquire one or more channels of data that need to be processed by FFT.

[0106] The reverse processing module is used to perform parallel reverse processing on more than one stream of data.

[0107] The FFT processing module is used to perform FFT processing on data to be processed in one or more channels after reverse processing.

[0108] The FFT inversion processing apparatus provided in this application supports parallel processing of multiple data streams, enabling simultaneous inversion of multiple FFT input data streams and achieving efficient inversion of input data.

[0109] In one exemplary instance, an input caching module and an output caching module are also included, wherein...

[0110] The input cache module is used to store the data after reverse processing;

[0111] The output buffer module is used to store the data after FFT processing.

[0112] In one embodiment, the input cache module and / or output cache module employ a distributed-aggregated data read / write method.

[0113] In one exemplary instance, the input cache module is a ping-pong mode memory, and the output cache module is a ping-pong mode storage.

[0114] In one embodiment, the acquisition module may include, but is not limited to, an analog-to-digital converter (ADC) interface, a direct memory access (DMA) interface, a serial peripheral interface (SPI), an integrated circuit interconnect (I2C) interface, a universal asynchronous transceiver (UART) interface, etc.

[0115] In one exemplary embodiment, a switching module is also included, used to output one or more channels of data to be processed that require FFT processing to the reverse processing module when reverse processing is required; and to output one or more channels of data to be processed that require FFT processing to other non-FFT processing modules (not shown in the figure), such as filtering or modulation / demodulation, when reverse processing is not required. In this way, the FFT reverse processing apparatus provided in this application embodiment can use the same data source in different applications without necessarily performing FFT operations on the data source, improving the compatibility of this application embodiment and expanding its application scope.

[0116] This application also provides a radar receiver, including the FFT reverse processing apparatus described in any of the above claims.

[0117] Although the embodiments disclosed in this application are as described above, the content described is merely for the purpose of understanding this application and is not intended to limit this application. Any person skilled in the art to which this application pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application; however, the scope of patent protection of this application shall still be determined by the scope defined in the appended claims.

Claims

1. A method for reversing FFT, characterized in that, include: Acquire one or more channels of data that require FFT processing; Perform parallel reverse processing on more than one stream of data; Perform FFT processing on the data to be processed after reversing the order of the data.

2. The FFT inversion processing method according to claim 1, further comprising, before the inversion processing: Zero-padding is performed on the data to be processed in one or more channels so that the length of the data to be processed in one or more channels is the same as the number of FFT points.

3. The FFT inversion processing method according to claim 1 or 2, wherein, The parallel reverse processing of more than one channel of data includes: The parallel reverse processing is performed in real time during the transmission of the above-mentioned data.

4. The FFT inversion processing method according to claim 1 or 2, wherein, The parallel reverse processing of more than one channel of data includes: The parallel reverse processing is performed in real time during the input buffering of the data to be processed in one or more channels, so that the data stored in the input buffer is arranged in reverse order.

5. The FFT inversion processing method according to claim 4, wherein, The input buffer is a ping-pong mode memory.

6. The FFT inversion processing method according to claim 1 or 2, wherein, The data to be processed, including one or more channels, can be obtained through any one or any combination of the following interfaces: Analog-to-digital converter interface, direct memory access interface, and universal asynchronous transceiver interface.

7. The FFT inversion processing method according to claim 1 or 2, further comprising: When reverse processing is not required, the obtained data that needs to be processed by FFT is output to other non-FFT processing.

8. The FFT inversion processing method according to claim 1, wherein, The FFT processing includes FFTs with different cardinality types; The different cardinality types of FFT include radix-2, radix-3, radix-4, or radix-8.

9. The FFT inversion processing method according to claim 1 or 2, further comprising, before the inversion processing: The data to be processed may be subjected to one or any combination of the following processes: data decompression or data type conversion, data masking, and data scattering.

10. A computer-readable storage medium storing computer-executable instructions for performing the FFT reversal processing method according to any one of claims 1-9.

11. A computer device comprising a memory and a processor, wherein, The memory stores the following instructions that can be executed by a processor: for performing the steps of the FFT reversal processing method according to any one of claims 1-9.

12. An FFT reverse processing apparatus, characterized in that, include: The module consists of an acquisition module, a reverse processing module, and an FFT processing module; among which, The acquisition module is used to acquire one or more channels of data that need to be processed by FFT. The reverse processing module is used to perform parallel reverse processing on more than one stream of data. The FFT processing module is used to perform FFT processing on data to be processed in one or more channels after reverse processing.

13. The FFT inversion processing apparatus according to claim 12, further comprising: Input caching module, output caching module, where, An input cache module is used to store the data after the reverse processing; An output buffer module is used to store the data processed by the FFT.

14. The FFT inversion processing apparatus according to claim 13, wherein, The input cache module and / or the output cache module adopt a distributed-aggregated data read / write method.

15. The FFT inversion processing apparatus according to claim 13, wherein, The input cache module and / or the output cache module are memory modules using a ping-pong mode.

16. The FFT reverse processing apparatus according to claim 12 further includes a switching module, configured to: when reverse processing is required, output the obtained data to be processed (one or more channels) to the reverse processing module; and when reverse processing is not required, output the obtained data to be processed (one or more channels) to other non-FFT processing modules.

17. The FFT inversion processing apparatus according to any one of claims 12-16, wherein, The acquisition module includes an analog-to-digital converter interface, a direct memory access interface, a serial peripheral interface, an integrated circuit interconnect interface, and a universal asynchronous transceiver interface.

18. A radar receiver, characterized in that, Includes the FFT inversion processing apparatus according to any one of claims 12-17.

19. A memory, characterized in that, include: The system includes an interface module, a processing module, and a caching module; among them, The interface module is used to input the data to be processed; The processing module is used to enable or disable real-time processing functions according to user configuration, and to process the input data to be processed through the enabled real-time processing functions; wherein, the real-time processing functions include one or any combination of the following: zero padding, address inversion, data decompression or data type conversion, data masking, and data scattering; The caching module is used to write data that has been processed by the processing module.

20. The memory according to claim 19, wherein, The interface module includes: ADC interface and DMA interface.

21. The memory according to claim 19 or 20, wherein, The interface module is also used to output data read from the cache module; correspondingly, The real-time processing functions in the processing module include one or any combination of the following: data aggregation, data compression, or data type conversion.

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