Method and system for generating netlist based on circuit diagram identification

Abstract

The invention discloses a netlist generation method and system based on circuit diagram recognition, and relates to the technical field of circuit diagram recognition, semantic segmentation of a circuit diagram is triggered according to contents of a plurality of feature categories and corresponding positions, a corresponding binary mask is output, a corresponding connection line pixel is marked in the traversing process of the binary mask, and a netlist is generated. The method comprises the following steps of: acquiring a connecting line pixel, and performing recursive search on a peripheral position along the connecting line pixel until a boundary of the connecting line pixel cluster is found so as to determine a complete connected region, thereby realizing image recognition of the circuit diagram, introducing semantic segmentation of the circuit diagram, improving the accuracy of a binary mask, further improving the accuracy of the connected region, and further improving the accuracy of the connected region. The connection relation in the netlist is determined according to each continuous wire and the element mask, the element list in the netlist is determined according to recognition of the binary mask, and the element list and the connection relation are summarized to generate the netlist in a standard format, so that the accuracy of the netlist is improved.

Description

Technical Field

[0001] This invention relates to the technical field of circuit diagram recognition, and more particularly to a method and system for generating netlists based on circuit diagram recognition. Background Technology

[0002] Circuit diagrams are core technical documents in the field of electronic design that describe the connection relationships of circuits. With the development of electronic design automation (EDA) technology, how to convert existing paper or image-format circuit diagrams into computer-readable netlists for subsequent simulation, revision and archiving has become a research hotspot.

[0003] Existing circuit diagram recognition and netlist generation technologies typically employ traditional image processing methods. In the image recognition stage, traditional methods are mostly based on simple binarization or edge detection algorithms, lacking a deep understanding of the semantic information of the image. The lines of wires, components, and text annotations intersect, resulting in low accuracy of the generated connection masks. Furthermore, it is impossible to control multiple continuous wires, leading to low accuracy of the netlist. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art. This invention provides a method and system for generating netlists based on circuit diagram recognition.

[0005] This invention provides a method for generating a netlist based on circuit diagram recognition, comprising: The circuit diagram is acquired, image recognition is performed on the circuit diagram, and multiple feature categories are determined in the image recognition. Based on the content and corresponding position of the multiple feature categories, semantic segmentation of the circuit diagram is triggered, and the corresponding binary mask is output. The binary mask includes the connection mask, component mask and annotation mask. The binary mask is traversed, and the corresponding connected pixels are marked during the traversal. The surrounding positions are recursively searched along the connected pixels until the boundary of the connected pixel cluster is found to determine a complete connected region. Each connected region corresponds to a continuous wire in the circuit diagram. In each connected region, the connected region is refined into a skeleton line with a width of one pixel. The corresponding endpoints and intersections are determined based on the detection of the skeleton lines. Multiple continuous wires of the connected region are determined based on the endpoints and intersections, and the multiple continuous wires are in an independent state. Multiple continuous wires are marked, and the connection relationships in the netlist are determined based on each continuous wire and component mask. At the same time, the component list in the netlist is determined based on the identification of the binary mask, and the component list and connection relationships are summarized to generate a netlist in a standard format. In the netlist, each electronic component lists the node number or name it is connected to.

[0006] This invention provides a netlist generation system based on circuit diagram recognition, which is applied to the aforementioned netlist generation method based on circuit diagram recognition; the netlist generation system based on circuit diagram recognition includes: The image recognition module is used to acquire circuit diagrams, perform image recognition on the circuit diagrams, determine multiple feature categories in the image recognition, trigger semantic segmentation of the circuit diagrams based on the content and corresponding positions of multiple feature categories, and output corresponding binary masks. The binary masks include connection masks, component masks and annotation masks. The connected region module is used to traverse the binary mask, mark the corresponding connected pixels during the traversal, and recursively search the surrounding positions along the connected pixels until the boundary of the connected pixel cluster is found to determine a complete connected region; each connected region corresponds to a continuous wire in the circuit diagram. The continuous wire module is used to refine the connected regions into skeleton lines with a width of one pixel in each connected region, determine the corresponding endpoints and intersections based on the detection of the skeleton lines, and determine multiple continuous wires in the connected region based on the endpoints and intersections. The multiple continuous wires are in an independent state. The netlist module is used to mark multiple continuous wires, determine the connection relationships in the netlist based on each continuous wire and component mask, and determine the component list in the netlist based on the identification of the binary mask. The component list and connection relationships are then summarized to generate a netlist in a standard format. In the netlist, each electronic component lists the node number or name to which it is connected.

[0007] Compared with the prior art, the beneficial effects of the present invention are: (1) Acquire circuit diagrams, perform image recognition on the circuit diagrams, and determine multiple feature categories in the image recognition. Based on the content and corresponding position of multiple feature categories, trigger semantic segmentation of the circuit diagrams and output the corresponding binary masks. The binary masks cover connection masks, component masks and annotation masks. Traverse the binary masks and mark the corresponding connection pixels during the traversal. Recursively search the surrounding positions along the connection pixels until the boundary of the connection pixel cluster is found to determine a complete connected region. Each connected region corresponds to a continuous wire in the circuit diagram. This realizes the image recognition of the circuit diagrams and introduces the semantic segmentation of the circuit diagrams, which improves the accuracy of the binary masks and further improves the accuracy of the connected regions.

[0008] (2) In each connected region, the connected region is refined into a skeleton line with a width of one pixel. The corresponding endpoints and intersections are determined based on the detection of the skeleton line. Multiple continuous wires in the connected region are determined based on the endpoints and intersections. The multiple continuous wires are in an independent state. Multiple continuous wires are marked. The connection relationship in the netlist is determined based on each continuous wire and the component mask. At the same time, the component list in the netlist is determined based on the recognition of the binary mask. The component list and connection relationship are summarized to generate a netlist in a standard format. In the netlist, each electronic component lists the node number or name it is connected to. The detection of each connected region is introduced, multiple continuous wires are controlled, and the component list and connection relationship are considered as a whole, which improves the accuracy of the netlist. Attached Figure Description

[0009] Figure 1 This is a schematic flowchart of the netlist generation method based on circuit diagram recognition in an embodiment of the present invention; Figure 2 This is a flowchart illustrating step S11 in the method for generating a netlist based on circuit diagram recognition in an embodiment of the present invention. Figure 3 This is a flowchart illustrating step S12 in the method for generating a netlist based on circuit diagram recognition in an embodiment of the present invention. Figure 4 This is a flowchart illustrating step S13 in the method for generating a netlist based on circuit diagram recognition in an embodiment of the present invention. Figure 5 This is a flowchart illustrating step S14 of the method for generating a netlist based on circuit diagram recognition in an embodiment of the present invention. Figure 6 This is a schematic diagram of the structural composition of the netlist generation system based on circuit diagram recognition in an embodiment of the present invention. Detailed Implementation

[0010] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0011] Please see Figures 1 to 6 A method for generating a netlist based on circuit diagram recognition, applied to circuit diagram recognition scenarios; the method for generating a netlist based on circuit diagram recognition includes: Step S11: Acquire the circuit diagram, perform image recognition on the circuit diagram, determine multiple feature categories in the image recognition, trigger semantic segmentation of the circuit diagram based on the content and corresponding position of multiple feature categories, and output the corresponding binary mask. The binary mask covers the connection mask, component mask and annotation mask. Step S12: Traverse the binary mask and mark the corresponding connected pixels during the traversal. Recursively search the surrounding positions along the connected pixels until the boundary of the connected pixel cluster is found to determine a complete connected region. Each connected region corresponds to a continuous wire in the circuit diagram. Step S13: In each connected region, the connected region is refined into a skeleton line with a width of one pixel. Based on the detection of the skeleton line, the corresponding endpoints and intersections are determined. Based on the endpoints and intersections, multiple continuous wires of the connected region are determined. The multiple continuous wires are in an independent state. Step S14: Mark multiple continuous wires, determine the connection relationship in the netlist based on each continuous wire and component mask, and determine the component list in the netlist based on the identification of the binary mask. Then, summarize the component list and connection relationship to generate a netlist in a standard format. In the netlist, each electronic component lists the node number or name it is connected to.

[0012] refer to Figure 2 In step S11, the specific steps are as follows: S111: Obtain the corresponding circuit diagram based on the circuit diagram database, input the circuit diagram into the preset image recognition model, and trigger the image recognition of the circuit diagram to mark multiple pixels in the circuit diagram. Based on the matching of each pixel, determine the corresponding feature category to mark multiple feature categories. S112: Determine the corresponding content based on the recognition of each feature category, and mark the position of each feature category. Based on the content and corresponding position of multiple feature categories, trigger semantic segmentation of the circuit diagram. At this time, perform semantic segmentation on the circuit diagram, and determine whether each pixel belongs to a connection by combining the context relationship, and output the corresponding binary mask. Based on the recognition of the binary mask, determine the connection mask, component mask and annotation mask. The connection mask highlights all pixels in the circuit diagram that belong to wires, the component mask marks all symbol areas, and the annotation mask corresponds to the text or annotation area.

[0013] In the embodiments of this application, the corresponding circuit diagram is obtained based on the circuit diagram database, the circuit diagram is input into the preset image recognition model, and the image recognition of the circuit diagram is triggered to mark multiple pixels in the circuit diagram. Based on the matching of each pixel, the corresponding feature category is determined to mark multiple feature categories, which takes into account the overall consideration of each pixel and ensures the accuracy of the corresponding feature category.

[0014] At this point, the system retrieves the circuit diagram image file to be processed from the circuit diagram database. Considering that the circuit diagram may come from scanned documents or electronic design screenshots, the system needs to perform standardized preprocessing on the acquired image, including resolution unification and grayscale normalization, to ensure the consistency of subsequent model input. This process ensures that the image data can be correctly read by the preset image recognition model, preparing for pixel-level fine recognition.

[0015] The preprocessed circuit diagram is input into a preset image recognition model, which is preferably a deep learning model based on a convolutional neural network (CNN) architecture (such as the U-Net structure). After triggering image recognition, the model performs multi-layer feature abstraction on the image through convolutional layers, extracting high-dimensional semantic features of each pixel and its neighborhood. This process is no longer a simple color or brightness judgment, but a deep analysis combined with contextual information. For example, the model can distinguish whether a line in the image is a "wire" with electrical properties or a "frame line" that only serves a decorative purpose.

[0016] The model performs classification prediction for each pixel in the image at the output layer. Based on the extracted high-dimensional features, the model matches the feature vector of each pixel with a preset feature category space. In the scenario of a circuit diagram, the feature category space mainly includes four categories: "connection", "component", "label", and "background". The system calculates the probability of each pixel belonging to each category and selects the category with the highest probability as the final label for that pixel. For example, for pixels representing electrical connections, the model labels them as "connection"; for pixels representing symbols such as resistors and capacitors, they are labeled as "component"; and for text pixels representing network labels or parameter values, they are labeled as "label". In this way, the feature category labeling of all pixels in the entire image is completed.

[0017] Specifically, taking a specific circuit diagram as an example, the diagram contains a resistor symbol, a horizontal wire, and the character "VDD" marked next to the wire; the system retrieves the image matrix of the circuit diagram from the database and feeds it into the pre-trained convolutional neural network model.

[0018] When the model scans the image area containing the resistor symbol, it identifies that the pixels in that area have specific geometric and topological features, matches their feature vectors to the "component" category, and marks these pixels as "components". When the model scans the horizontal lines connecting the two ends of the resistor, it identifies that these pixels are continuous lines with electrical connection characteristics, matches them to the "connection" category, and marks them as "connection". At the same time, when the model scans the "VDD" lettering above the lines, it identifies that these pixels conform to the features of text characters, matches them to the "label" category, and marks them as "label".

[0019] After the above steps, the pixels of the entire circuit diagram are accurately classified and labeled, forming a category matrix with the same size as the original image. This provides a direct decision basis for generating the connection mask, component mask and annotation mask in the subsequent step S112, ensuring that the underlying image data source required for netlist generation is accurate.

[0020] Furthermore, the corresponding content is determined based on the recognition of each feature category, and the position of each feature category is marked. Based on the content and corresponding position of multiple feature categories, semantic segmentation of the circuit diagram is triggered. At this time, semantic segmentation of the circuit diagram is performed, and the context relationship is combined to determine whether each pixel belongs to a connection. The corresponding binary mask is output. Based on the recognition of the binary mask, the connection mask, component mask, and annotation mask are determined. The connection mask highlights all pixels in the circuit diagram that belong to wires, the component mask marks all symbol areas, and the annotation mask corresponds to the text or annotation area. This overall consideration of the recognition of the binary mask is compatible, ensuring the accuracy of the connection mask, component mask, and annotation mask.

[0021] At this point, after completing the initial pixel feature matching in step S111, the system further confirms and precisely locates the identified feature categories. For the "component" category, the system analyzes its specific geometric contour and determines its minimum bounding rectangle in the image coordinate system. For the "label" category, the system locks the pixel area range of the text characters. This process transforms the abstract category label into specific image area location information, providing a spatial index basis for subsequent semantic segmentation.

[0022] Based on the determined location information, semantic segmentation processing for the entire image is triggered. This process is not a simple pixel classification, but rather uses a deep learning model (such as U-Net) to perform deep reasoning in conjunction with the contextual relationships of the image. The model corrects and confirms the preliminary recognition results by analyzing the neighborhood information around the pixel. For example, when determining whether a pixel belongs to the "connection" category, the model not only relies on the grayscale features of the pixel itself, but also combines the connectivity and direction of its neighboring pixels to identify whether it has the topological features of an electrical wire, thereby effectively distinguishing wires from interference items such as frame lines and decorative lines, ensuring the accuracy of segmentation.

[0023] After semantic segmentation is completed, the system generates and outputs multiple binary masks based on the segmentation results. Each mask is a binary image with the same size as the original image, used to represent the distribution area of ​​a specific category. For the connection mask, all pixels that are determined to be of the "connection" category are extracted and highlighted in the mask image (e.g., pixel value of 255), while the remaining areas are set as background (e.g., pixel value of 0), thereby independently mapping out the distribution areas of all electrical wires in the circuit diagram.

[0024] For the component mask, all pixel areas identified as "component" symbols (such as resistors, capacitors, chips, etc.) are highlighted to form a component mask, clearly marking the symbol areas of all electronic components in the circuit diagram; at the same time, for the annotation mask, all text labels or annotation areas are extracted to generate an annotation mask, which is used for subsequent OCR text recognition and node name extraction.

[0025] Specifically, the system identifies the "resistance" feature category, determines its specific location coordinates in the image (such as a bounding box), and parses its internal geometry into the content of a resistance symbol; for the character "VDD", the system locks the pixel range of its text area; for horizontal lines, the system locates their start and end coordinates.

[0026] After triggering semantic segmentation, the model performs pixel-by-pixel analysis on the image. When processing the horizontal wire region, the model combines the context to determine that the line pixels are continuous and both ends extend to the resistor pin region, which has electrical connection attributes, so it is confirmed as the "connection" category. When processing the "VDD" character, the model confirms it as the "label" category based on its arrangement characteristics and its proximity to the wire.

[0027] Wiring Mask: At this stage, the pixel positions corresponding to horizontal wires in the mask image are highlighted (appearing as white lines), while the resistor symbol area and character area are set to a black background, clearly revealing the electrical connection topology; Component Mask: In this mask image, only the pixel area where the resistor symbol is located is highlighted, while the wire and text areas are in the background color, accurately indicating the physical range of the component symbol; Simultaneously, Label Mask: In this mask image, only the pixel area where the "VDD" character is located is highlighted, providing an accurate input source for subsequent extraction of the network name using OCR technology; The image information of the circuit diagram is structurally parsed into three independent levels: wiring, components, and labels, laying a solid data foundation for the subsequent generation of an accurate netlist.

[0028] refer to Figure 3 In step S12, the specific steps are as follows: S121: In the binary mask, the binary mask is traversed accordingly, and the traversal process of the binary mask is monitored in real time. Based on the recognition of the traversal process, the corresponding connecting pixels are determined, and the corresponding connecting pixels are identified and displayed. S122: Determine the corresponding peripheral position based on the peripheral detection of the connected pixels, and trigger the corresponding recursive search along the peripheral position to include the adjacent connected pixels around the connected pixel into the set one by one until the boundary of the connected pixel cluster is found to determine a complete connected region; in the connected region, each connected pixel presents the corresponding color and presents the corresponding continuous wire.

[0029] In the embodiments of this application, the binary mask is traversed accordingly, and the traversal process of the binary mask is monitored in real time. Based on the recognition of the traversal process, the corresponding connecting pixels are determined, and the corresponding connecting pixels are identified and displayed. This approach takes into account the overall consideration of the recognition of the traversal process and ensures the accuracy of the corresponding connecting pixels.

[0030] At this point, the system calls the connection mask generated in step S112 as input data; adopting a raster scanning strategy, it traverses the entire image from the top left corner of the mask image, row by row to the right and row by row downward; during the traversal, the system monitors the changes in pixel values ​​in real time. Since the connection mask is a binary image, the system sets the highlight pixel value (such as "1" or "255") as the target feature value, representing the potential connection pixels; background pixel values ​​(such as "0") are ignored.

[0031] During the traversal, when the scanning pointer moves to a certain coordinate position, the system reads the pixel value at that position in real time. If the pixel value is detected as being in a highlighted state, the position is determined to be a valid "connected pixel". At this time, the system immediately records the specific coordinate information of the pixel and marks it as visited to prevent subsequent repeated recognition. This process realizes the extraction of dynamic connected pixel points from static image data.

[0032] Once a connected pixel is identified, the system triggers the visualization module to highlight the pixel in the monitoring interface or cache layer (e.g., by marking it with a specific color such as red or green) to create a sharp contrast with the background and visually demonstrate the recognition progress. At the same time, the system locks the pixel's position, confirming it as the starting node for subsequent connected component searches. By displaying the connected pixels in real time, the observability of the traversal process is ensured, and an accurate starting point is provided for determining the complete connected region.

[0033] Specifically, the system loads the connection mask output from step S112; in this mask, the resistor symbol and the "VDD" character area are black backgrounds, and only the horizontal wire area is presented as a white highlight strip; the system scans line by line starting from the upper left corner of the mask; when the scan reaches the line containing the horizontal wire, the system monitors in real time that the pixel value at a certain coordinate is 255 (white), and determines that the point is a "connection pixel"; the system immediately records the specific coordinates of the pixel.

[0034] The system marks the pixel at that coordinate in the processing cache and highlights it in the visualization window to confirm that the point is part of a potential traverse. The system then uses this pixel as the starting point to prepare to perform the next recursive search operation to capture the connected region of the entire horizontal traverse.

[0035] Furthermore, based on the perimeter detection of connected pixels, the corresponding perimeter position is determined, and a recursive search is triggered along the perimeter position to include the adjacent connected pixels around the connected pixel into the set one by one until the boundary of the connected pixel cluster is found to determine a complete connected region. In the connected region, each connected pixel presents the corresponding color and presents the corresponding continuous wire, which is compatible with the overall consideration of perimeter detection of connected pixels and ensures the accuracy of the corresponding perimeter position. At the same time, image recognition of circuit diagrams is realized, and semantic segmentation of circuit diagrams is introduced, which improves the accuracy of binary masks and further improves the accuracy of connected regions.

[0036] At this point, based on the starting connected pixel identified in step S121, the system immediately starts the surrounding detection mechanism; using 8-neighbor or 4-neighbor detection, it locates the adjacent positions of the starting pixel in the horizontal, vertical and diagonal directions; the system detects the pixel values ​​of these surrounding positions one by one to determine whether they also belong to the "connected pixels" in the highlighted state. This process transforms the local point information of the image into neighborhood association information, laying the foundation for connectivity analysis.

[0037] Once a new connected pixel is detected in the surrounding area, the system immediately triggers a recursive search logic (preferably using breadth-first search (BFS)). The system adds the newly detected connected pixel to the current pixel set and uses this new pixel as the new center point to repeatedly perform the surrounding detection operation. This process spreads outward from the starting point like a ripple, automatically tracing the direction of the wire. The system continuously adds adjacent connected pixels to the set one by one, building an ever-expanding pixel cluster to ensure that no breakpoints in the wire network are missed.

[0038] During the recursive search, the system monitors the search status in real time. When there are no more highlighted connected pixels in the surrounding area in a certain direction (i.e., encountering background pixels, image boundaries, or non-connected areas), it is determined that the boundary of the wire has been reached in that direction. When all search paths have reached the boundary and there are no new pixels to be included, the recursive process ends. At this time, all the pixels included in the set constitute a complete connected region, which corresponds to a complete potential electrical wire network in the circuit diagram.

[0039] To visually demonstrate the results of connected component analysis, the system performs uniform coloring on the extracted complete connected regions. The system assigns a unique color (such as red, blue, or green) from a preset color map and updates the display value of all pixels within the connected region to that color. In this way, different connected regions can be visually distinguished, and the original black and white binary mask is transformed into a colored connected component distribution map, clearly presenting the shape of continuous wires.

[0040] Specifically, the system takes the starting pixel of the horizontal wire identified in step S121 as the center and scans its eight neighboring positions (left, right, top, and bottom). It detects that the adjacent pixel to its right is also a highlight value, confirming it as a connected pixel. The system recursively advances to the right along the horizontal direction, adding each pixel on the wire to the "current wire set" in turn. Since the wire is horizontal and not connected to other components (the resistor symbol is in the component mask, and only the connection mask is processed here), the search process proceeds quickly along a straight line.

[0041] When the search reaches the right end of the wire, the system finds that the neighboring pixels on the right are the background color (black) and there are no other branch paths, indicating that the boundary has been reached; the recursion ends, confirming that the horizontal strip is a complete connected region; the system marks all pixels corresponding to this horizontal wire segment in green in the output image; on the visualization interface, the user can clearly see a continuous green line, which represents an identified independent net, clearly distinguishing it from the unconnected "VDD" character area (belonging to the label mask and ignored in this step) and the resistor symbol (belonging to the component mask and ignored in this step).

[0042] refer to Figure 4 In step S13, the specific steps are as follows: S131: Real-time monitoring of each connected region, refinement of the lines of the connected region into skeleton lines with a width of one pixel, dynamic detection of the skeleton lines, marking multiple point features during detection, and determining the corresponding endpoints and intersections based on the recognition of multiple point features. The endpoints are the pixels where the line segment terminates; the intersections are the pixels where the line segment forks or intersects. S132: For intersections, when four line segments extend from a point on the skeleton line and no element or connection point symbol is detected above that point, it is determined that this is the intersection of two wires but not connected. At the intersection, the original connected domain is divided into two segments and split into two independent continuous wires. S133: If a connection point symbol is detected at a wire intersection or the intersection happens to be the pin overlap of a component, it is determined to be an electrical connection and should be retained as the same continuous wire; at the same time, for "T" or "cross" type connections, the connectivity is determined by analyzing the orientation angle of each line segment at the intersection and grouping the line segments on opposite sides into pairs; in the case of a cross intersection, if there is no node mark, a pair of line segments in the horizontal direction are interconnected, a pair of line segments in the vertical direction are interconnected, and there is no connection between the horizontal and vertical directions.

[0043] In the embodiments of this application, each connected region is monitored in real time, and the lines of the connected region are refined into skeleton lines with a width of one pixel. The skeleton lines are dynamically detected, and multiple point features are marked during the detection. The corresponding endpoints and intersections are determined based on the recognition of multiple point features. The endpoint is the pixel where the line segment terminates; the intersection is the pixel where the line segment forks or intersects. This approach takes into account the overall consideration of recognizing multiple point features and ensures the accuracy of the corresponding endpoints and intersections.

[0044] At this point, the system marks all pixels corresponding to the horizontal conductor segment as green in the output image; on the visualization interface, the user can clearly see a continuous green line, which represents an identified independent net, clearly distinguishing it from the adjacent unconnected "VDD" character area (belonging to the annotation mask and ignored in this step) and the resistor symbol (belonging to the component mask and ignored in this step).

[0045] The system employs skeleton extraction technology from image morphology to refine the lines of connected regions. By peeling away pixels from the edges of the conductor layer by layer while preserving its topological features, the connected regions of the conductor, which originally had a certain width (possibly several pixels wide), are gradually shrunk and finally refined into skeleton lines with only a single pixel width. This step is crucial, as it transforms complex strip-shaped regions into easily analyzable geometric curves, removes the influence of line width variations on topological recognition, and accurately restores the centerline path of the conductor.

[0046] After obtaining the skeleton line with a width of one pixel, the system initiates a dynamic detection mechanism to traverse along the skeleton line path. During the traversal, the system marks multiple point features based on neighborhood connectivity analysis. Specifically, the system calculates the number of connected pixels in the 8-neighborhood of each pixel on the skeleton line. If there is only one connected pixel in the neighborhood of a pixel, it is marked as an "endpoint feature," representing the termination position of the line segment. If there are three or four connected pixels in the neighborhood of a pixel, it is marked as an "intersection feature," representing the fork or intersection position of the line segment.

[0047] Based on the characteristics of the marked points, the system ultimately determines the endpoints and intersections. The endpoints are defined as the pixels where the line segment terminates, marking the electrical connection boundary of the wire segment. The intersections are defined as the pixels where the line segment forks or intersects, marking the possible T-shaped connections or cross-shaped intersections of the wire. The identification of these key points provides an accurate geometric basis for subsequent judgments on whether the wire is connected or needs to be split. Specifically, the system locks the connected region of the green horizontal guideline identified in step S122; the system performs morphological refinement on this horizontal guideline region; assuming the guideline width in the original image is 5 pixels, after refinement, the guideline becomes a horizontal straight line (i.e., skeleton line) only 1 pixel wide, located at the center of the original guideline; at the same time, the system scans along this single-pixel-wide horizontal skeleton line; in the middle part of the guideline, each pixel has a neighboring pixel on the left and right, which are ordinary path points.

[0048] When scanning to the leftmost end of the skeleton line, the system found that the pixel had only one neighboring pixel to its right, while the left and top and bottom were all background. Therefore, the system determined that the point was an endpoint (the pixel where the line segment ends). Similarly, an endpoint was also identified at the rightmost end. Since the horizontal wire had no branches, the system did not detect any intersections (pixels where the line segment forks or intersects). Thus, the system accurately extracted the two electrical boundary points of the wire segment, preparing for the subsequent determination of its connection relationship with resistors or other components.

[0049] Furthermore, regarding intersections, when four line segments extend from a point on the skeleton line and no element or connection point symbol is detected above that point, it is determined that this is the intersection of two wires but not connected. At this intersection, the original connected domain is divided into two segments, split into two independent continuous wires, thus introducing the splitting into two independent continuous wires.

[0050] At this point, the system performs deep topology analysis on the intersection points identified in step S131; detects the local connection pattern of the intersection point on the skeleton line, and counts the number of line segments extending from the point; if it detects that a point has exactly four line segments extending in a "cross" or "X" shape, the system initially determines it as a potential crossing intersection node. This process excludes cases that are confirmed as physical connections, such as "T" type connections (usually three lines extending), and focuses on special scenarios that may have visual overlap but electrical separation.

[0051] After confirming that the geometry is a four-line intersection, the system immediately calls the context semantic information for verification; the system retrieves the corresponding position of the intersection point in the original image and its neighborhood, and checks whether there are connection point symbols (such as solid circles) or component symbols covering it; if no node symbol representing an electrical connection is detected above the point or in the local area, and no component pins overlap at this point, the system determines according to the circuit drawing specifications that this intersection point is only a graphic crossing of two wires, and not an electrical connection node.

[0052] Based on the above determination results, the system performs a connected component splitting operation. Logically, the system breaks the connected component that was originally considered as a whole at the intersection point. Specifically, according to the direction of the skeleton lines, the system divides the four intersecting line segments into two groups of opposite edges (for example, a pair of line segments in the horizontal direction is divided into one group, and a pair of line segments in the vertical direction is divided into another group), and cuts off the pixel connection path between them at the intersection point. As a result, the original connected region is split into two electrically independent continuous wire network segments, ensuring the accuracy of subsequent netlist generation and avoiding short-circuit errors.

[0053] Specifically, when scanning the intersection of horizontal and vertical wires, the system detected an intersection point on the skeleton line. Analysis showed that there were exactly four line segments extending from this point in the left, right, up, and down directions, which conforms to the geometric feature of "four lines extending". The system further called the component mask and annotation mask generated in step S11 for verification. The detection found that there were no solid circles (connection point symbols) at the coordinate position of the intersection point and its neighborhood, and no resistors or chip pins overlapped at this point. Based on this, the system determined that this point was "the intersection of two wires but not connected", that is, the horizontal and vertical wires are only crossing each other in the drawing and are not electrically connected.

[0054] The system then executes the split command, severing the connection between the horizontal and vertical skeleton lines at the intersection coordinates. The system identifies the horizontal line segment as an independent continuous wire (net segment A) and the vertical line segment as another independent continuous wire (net segment B). After this step, the area that was originally connected due to pixel intersections is successfully separated into two independent electrical networks, providing an accurate topology basis for generating the correct netlist.

[0055] Therefore, if a connection point symbol is detected at a wire intersection or the intersection happens to be the pin overlap of a component, it is determined to be an electrical connection and should be retained as the same continuous wire. At the same time, for "T" or "cross" type connections, the connectivity is determined by analyzing the orientation angle of each line segment at the intersection and grouping the line segments on opposite sides into pairs. In the case of a cross intersection, if there is no node mark, a pair of line segments in the horizontal direction are interconnected, and a pair of line segments in the vertical direction are interconnected, and there is no connection between the horizontal and vertical directions, thus introducing a disconnect between the horizontal and vertical directions.

[0056] At this point, the system performs a secondary semantic check on the intersection points identified in step S131. If a specific electrical symbol (such as a standard solid dot connector) is detected above or in a local area of ​​the wire intersection, or if the coordinates of the intersection point coincide with the pin position of a component in the component mask identified in step S11, the system determines that this is a valid electrical connection node. Under this determination, the intersection point and its connected branch wires are considered as a single entity in electrical logic and retained as the same continuous wire network without being split.

[0057] For complex "T" or "cross" shaped connections without explicit connection point symbols, the system initiates topology analysis. The system calculates the extension direction (orientation angle) of each branch segment of the skeleton line at the intersection point. Based on geometric topology rules, the system groups the segments in opposite directions into pairs. For example, in the case of a cross intersection, the system identifies horizontal (0° and 180°) segments as one group and vertical (90° and 270°) segments as another group. This grouping strategy is used to determine which segments are physically directly connected and which are crossing relationships.

[0058] In the special case of a cross intersection without node markers (no solid dots), the system performs connectivity determination based on the grouping results. Due to the lack of electrical connection symbols, the system defaults to the intersection as a physical crossing rather than an electrical connection. Therefore, it determines that a pair of interconnected line segments in the horizontal direction forms an independent horizontal continuous conductor, and a pair of interconnected line segments in the vertical direction forms an independent vertical continuous conductor. The horizontal and vertical directions are determined to be disconnected. Based on this, the system logically splits the intersection into two independent electrical nodes to ensure the correctness of the netlist logic.

[0059] Specifically, suppose there is another scenario in the diagram: a vertical wire intersects the aforementioned horizontal wire, and a solid dot is drawn at the intersection point; the system scans the intersection of the horizontal and vertical wires; in the local image area of ​​the intersection point, the system detects a set of highlighted solid dot pixels (connection point symbol); according to the rules, the system determines that this is an electrical connection; therefore, the horizontal and vertical wires are logically confirmed to be connected together and retained as the same connected network. In the subsequently generated netlist, they will belong to the same node name.

[0060] Conversely, if no solid dot is detected at the intersection, the system will initiate angle analysis. The system identifies that horizontal line segments face left and right, and vertical line segments face up and down. Based on the rule of "horizontal interconnection, vertical interconnection, and no connection between horizontal and vertical lines", the system determines that this is a crossing rather than a connection. At this time, the horizontal conductor is determined to be an independent continuous conductor (maintaining its original electrical path), and the vertical conductor is determined to be another independent continuous conductor. The two correspond to different node numbers in the netlist, thus achieving accurate parsing of complex drawing logic.

[0061] refer to Figure 5 In step S14, the specific steps are as follows: S141: Real-time monitoring of multiple continuous wires, feature extraction of component masks, extraction of the bounding box position and type information of each component symbol, and pre-determining the pin area of ​​each component in combination with the component type features. For each component pin area, it is detected whether a pixel of a certain continuous wire passes through its position or is close to the end of the continuous wire, and then the connection relationship between the component pin and the continuous wire is established. S142: Extract node name text using a label mask, compare the text identifiers of adjacent continuous conductors, and automatically merge the corresponding continuous conductors into the same node if the labels have the same name; for standard power and ground symbols, once the same type is detected, merge the continuous conductors connected to them to construct a component list; summarize the component list and connection relationships to generate a netlist in a standard format; each electronic component in the netlist lists the node number or name it is connected to, and the generated netlist is output after verification and directly used for layout reconstruction.

[0062] In the embodiments of this application, multiple continuous wires are monitored in real time, and feature extraction is performed on the component mask. The bounding box position and type information of each component symbol are extracted, and the pin area of ​​each component is pre-determined in combination with the component type features. For each component pin area, it is detected whether a pixel of a certain continuous wire passes through its position or is close to the end of the continuous wire. Then, the connection relationship between the component pin and the continuous wire is established. This approach combines the overall consideration of the component type features in advance and ensures the accuracy of each component pin area.

[0063] At this point, the system performs real-time status monitoring on the multiple continuous wires (segments) determined in step S13; establishes a wire topology index, and records the unique identifier, pixel coordinate set, and endpoint location information of each continuous wire. This process ensures that when associating components later, the relevant wire segments can be quickly retrieved and the progress of connection establishment can be tracked in real time.

[0064] The system calls the component mask generated in step S11 and extracts features from the mask; it uses connected component analysis or contour detection technology to identify each independent component symbol region in the mask; for each identified component symbol, the system calculates its minimum bounding rectangle, obtains the bounding box position coordinates, and determines the type information of the component (such as resistor, capacitor, integrated circuit, etc.) based on the pre-trained classification model.

[0065] Based on the determination of component type and location, the system combines the component type feature library to pre-determine the pin area of ​​each component. For discrete components (such as resistors), the pin area is usually predicted to be the midpoint of the left and right sides of the symbol rectangle boundary. For integrated circuits or multi-pin components, the pin distribution is predicted to be at a specific position on the edge of the component according to standard packaging rules. The system defines a search neighborhood within an allowable error range for each predicted pin area.

[0066] The system performs spatial mapping detection on the predicted component pin area and the coordinate set of the interconnect mask or continuous wire; specifically, it detects whether there are pixels of continuous wire passing through the search neighborhood of the pin, or whether the distance between the pin position and the endpoint of a continuous wire is less than a preset threshold; if one of the above conditions is met, the system determines that the pin and the continuous wire are in physical contact.

[0067] Once the physical contact between the pin and the wire is confirmed, the system establishes a mapping relationship between the component pin and the continuous wire (network segment) at the data level. The system binds the unique identifier of the component with the network identifier of the corresponding continuous wire, and records which specific electrical node the pin is connected to, thereby completing the conversion from graphic recognition to electrical logic connection.

[0068] Specifically, the system monitors the identified horizontal continuous wires in real time and extracts features from the component mask; the system identifies a rectangular region in the image whose aspect ratio matches the characteristics of a resistor symbol, determines that the region is a "resistor element", and calculates its rectangular bounding box coordinates.

[0069] Based on the characteristics of the resistor element, the system predicts that the midpoints of the left and right boundaries of the resistor symbol are the left and right pin regions, respectively. For example, a tiny rectangular search box is drawn at the midpoint of the left boundary of the resistor symbol as the left pin detection area. The system detects the pixel status within the left pin search area. Since the horizontal wire connects to the left side of the resistor in the graphic, the system finds that there are pixels belonging to the horizontal continuous wire in this area, and the endpoint of the wire is very close to the pin center.

[0070] Based on the detection results, the system determines that the left pin of the resistor has established an electrical connection with the horizontal continuous wire; the system then generates a record in the database indicating that "pin 1 of resistor R1 is connected to network Net_A (horizontal wire)"; similarly, if another wire is connected to the right side of the resistor, a corresponding connection will also be established, providing core data support for the final generation of an accurate netlist.

[0071] Furthermore, node name text is extracted using a label mask, and the text identifiers of adjacent continuous wires are compared. For markers with the same name, the corresponding continuous wires are automatically merged into the same node. For standard power and ground symbols, once the same type is detected, the continuous wires connected to them are merged to construct a component list. The component list and connection relationships are summarized to generate a netlist in a standard format. Each electronic component in the netlist lists the node number or name it is connected to. The generated netlist is output after verification and is directly used for layout reconstruction. This introduces the detection of each connected region, manages multiple continuous wires, and considers the component list and connection relationships as a whole, thus improving the accuracy of the netlist.

[0072] At this point, the system calls the annotation mask generated in step S11 to locate the text region in the image; using optical character recognition (OCR) technology, the pixel graphics in the annotation mask are converted into string text; the system focuses on identifying labels with electrical meaning, such as network names "VDD", "GND" or specific signal names; the extracted text strings and their coordinate positions in the image are stored as a node name text dataset.

[0073] The system performs spatial correlation analysis between the extracted text identifiers and the continuous conductors (network segments) determined in step S13; the system detects whether there are text identifiers near each continuous conductor; if multiple scattered continuous conductors are found to have text markers with the same name in their vicinity (e.g., multiple conductors are marked with "VDD"), the system determines that these conductors are logically at the same potential according to electrical connection rules; the system automatically merges these continuous conductors with the same name into the same electrical node, thereby eliminating node duplication caused by scattered drawing and ensuring the consistency of global electrical connections.

[0074] For standard power symbols (such as positive power symbols) and ground symbols (such as inverted T-shaped ground symbols) in circuit diagrams, the system executes special component identification logic; the system detects the type of these special symbols in the component mask, and once multiple symbols of the same type are detected (such as multiple ground symbols), it is determined that they are electrically interconnected; the system automatically merges all continuous wires connected to these special symbols into one (for example, all wires connected to the ground symbol are eventually merged into a node named "GND"), constructing a complete electrical node network.

[0075] The system integrates the above processing results to construct the final circuit data model; it summarizes all identified electronic component information (including component type, number, and parameter value) to form a component list; it summarizes all continuous wires and their merged node information to form a connection relationship table; the system matches and maps the component list with the connection relationships to generate a netlist file that conforms to a standard format (such as SPICE format); in the netlist, each electronic component clearly lists the node number or specific name to which its pins are connected.

[0076] The generated netlist text undergoes logical checks by the system's built-in verification module, focusing on verifying whether nodes are isolated (unconnected) or component pins are floating (unconnected). After verification, the netlist is officially output as a machine-readable text file, which can be directly imported into subsequent EDA (Electronic Design Automation) tools for circuit simulation, design rule checking, or layout reconstruction, thus realizing a closed loop from image to digital design.

[0077] Specifically, the system identifies text in the pixel area above the conductor in the annotation mask, which is then confirmed by OCR as the string "VDD". The system detects that there is a "VDD" label near the horizontal conductor. Assuming there is another vertical conductor in another part of the drawing, which is also labeled "VDD", the system compares the two conductors and finds that the adjacent text labels have the same name. It determines that the two are electrically equivalent and automatically merges the two conductors into the same "VDD" node, even though they may not be directly connected in the drawing.

[0078] If the drawing contains two independent grounding symbols, the system recognizes both as "ground" type and automatically merges their connected wires (if any) into a single "GND" node. The system summarizes the information and generates a netlist file. The file contains a record: "R1net_VDDnet_210k", indicating that one end of resistor R1 is connected to the VDD node (i.e., the aforementioned horizontal wire), and the other end is connected to the net_2 node. The system verifies that both pins of R1 are connected and that a valid path exists in the VDD node. Finally, the netlist file is output, which can be directly called by layout reconstruction software to restore the circuit design data.

[0079] Please see Figure 6 , Figure 6 This is a schematic diagram of the structure of a netlist generation system based on circuit diagram recognition according to an embodiment of the present invention; the netlist generation system based on circuit diagram recognition is applied to the above-described netlist generation method based on circuit diagram recognition; the netlist generation system based on circuit diagram recognition includes: The image recognition module 21 is used to acquire circuit diagrams, perform image recognition on circuit diagrams, determine multiple feature categories in image recognition, trigger semantic segmentation of circuit diagrams based on the content and corresponding positions of multiple feature categories, and output corresponding binary masks. The binary masks cover connection masks, component masks and annotation masks. The connected region module 22 is used to traverse the binary mask, mark the corresponding connected pixels during the traversal, and recursively search the surrounding positions along the connected pixels until the boundary of the connected pixel cluster is found to determine a complete connected region; each connected region corresponds to a continuous wire in the circuit diagram. The continuous wire module 23 is used to refine the connected regions into skeleton lines with a width of one pixel in each connected region, determine the corresponding endpoints and intersections based on the detection of the skeleton lines, and determine multiple continuous wires in the connected region based on the endpoints and intersections. The multiple continuous wires are in an independent state. Netlist module 24 is used to mark multiple continuous wires, determine the connection relationship in the netlist based on each continuous wire and component mask, and determine the component list in the netlist based on the identification of the binary mask. The component list and connection relationship are summarized to generate a netlist in a standard format. In the netlist, each electronic component lists the node number or name to which it is connected.

[0080] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A method for generating a netlist based on circuit diagram recognition, characterized in that, include: The circuit diagram is acquired, image recognition is performed on the circuit diagram, and multiple feature categories are determined in the image recognition. Based on the content and corresponding position of the multiple feature categories, semantic segmentation of the circuit diagram is triggered, and the corresponding binary mask is output. The binary mask includes the connection mask, component mask and annotation mask. The binary mask is traversed, and the corresponding connected pixels are marked during the traversal. The surrounding positions are recursively searched along the connected pixels until the boundary of the connected pixel cluster is found to determine a complete connected region. Each connected region corresponds to a continuous wire in the circuit diagram. In each connected region, the connected region is refined into a skeleton line with a width of one pixel. The corresponding endpoints and intersections are determined based on the detection of the skeleton lines. Multiple continuous wires of the connected region are determined based on the endpoints and intersections, and the multiple continuous wires are in an independent state. Multiple continuous wires are marked, and the connection relationships in the netlist are determined based on each continuous wire and component mask. At the same time, the component list in the netlist is determined based on the identification of the binary mask, and the component list and connection relationships are summarized to generate a netlist in a standard format. In the netlist, each electronic component lists the node number or name to which it is connected.

2. The method for generating a netlist based on circuit diagram recognition according to claim 1, characterized in that, The acquired circuit diagram undergoes image recognition, identifying multiple feature categories. Based on the content and corresponding positions of these feature categories, semantic segmentation of the circuit diagram is triggered, and a corresponding binary mask is output. This binary mask encompasses connection masks, component masks, and annotation masks, including: Obtain the corresponding circuit diagram from the circuit diagram database, input the circuit diagram into the preset image recognition model, and trigger the image recognition of the circuit diagram to mark multiple pixels in the circuit diagram. Based on the matching of each pixel, determine the corresponding feature category to mark multiple feature categories.

3. The method for generating a netlist based on circuit diagram recognition according to claim 2, characterized in that, The acquired circuit diagram undergoes image recognition, identifying multiple feature categories. Based on the content and corresponding positions of these feature categories, semantic segmentation of the circuit diagram is triggered, and a corresponding binary mask is output. This binary mask encompasses connection masks, component masks, and annotation masks, and also includes: The corresponding content is determined based on the identification of each feature category, and the position of each feature category is marked. Based on the content and corresponding position of multiple feature categories, semantic segmentation of the circuit diagram is triggered. At this time, semantic segmentation of the circuit diagram is performed, and the context relationship is combined to determine whether each pixel belongs to a connection. The corresponding binary mask is output. Based on the identification of the binary mask, the connection mask, component mask and annotation mask are determined. The connection mask highlights all pixels in the circuit diagram that belong to wires, the component mask marks all symbol areas, and the annotation mask corresponds to the text or annotation area.

4. The method for generating a netlist based on circuit diagram recognition according to claim 1, characterized in that, The binary mask is traversed, and corresponding connected pixels are marked during the traversal. A recursive search is then performed along these connected pixels to locate the surrounding area until the boundary of the pixel cluster is found, thus determining a complete connected region. Each connected region corresponds to a continuous wire segment in the circuit diagram, including: In this binary mask, the binary mask is traversed accordingly, and the traversal process of the binary mask is monitored in real time. Based on the recognition of the traversal process, the corresponding connecting pixels are determined, and the corresponding connecting pixels are identified and displayed.

5. The method for generating a netlist based on circuit diagram recognition according to claim 4, characterized in that, The binary mask is traversed, and the corresponding connected pixels are marked during the traversal. The surrounding positions are recursively searched along the connected pixels until the boundary of the connected pixel cluster is found, so as to determine a complete connected region. Each connected region corresponds to a continuous wire segment in the circuit diagram, and also includes: The corresponding surrounding position is determined based on the surrounding detection of the connected pixels, and a recursive search is triggered along the surrounding position to include the adjacent connected pixels around the connected pixel into the set one by one until the boundary of the connected pixel cluster is found to determine a complete connected region; in the connected region, each connected pixel presents the corresponding color and presents the corresponding continuous wire.

6. The method for generating a netlist based on circuit diagram recognition according to claim 1, characterized in that, In each connected region, the connected region is refined into a skeleton line with a width of one pixel. Based on the detection of the skeleton line, the corresponding endpoints and intersections are determined. Multiple continuous wires are then determined for that connected region based on the endpoints and intersections. These multiple continuous wires are independent and include: Real-time monitoring of each connected region is performed, and the lines of the connected region are refined into skeleton lines with a width of one pixel. The skeleton lines are dynamically detected, and multiple point features are marked during the detection. Based on the recognition of multiple point features, the corresponding endpoints and intersections are determined. The endpoints are the pixels where the line segment terminates; the intersections are the pixels where the line segment forks or intersects.

7. The method for generating a netlist based on circuit diagram recognition according to claim 6, characterized in that, In each connected region, the connected region is refined into a skeleton line with a width of one pixel. Based on the detection of the skeleton line, the corresponding endpoints and intersections are determined. Based on the endpoints and intersections, multiple continuous wires are determined for the connected region, and the multiple continuous wires are in an independent state. The method also includes: For intersections, when four line segments extend from a point on the skeleton line and no element or connection point symbol is detected above that point, it is determined that this is the intersection of two wires but not connected. At the intersection, the original connected domain is divided into two segments and split into two independent continuous wires. If a connection point symbol is detected at a wire intersection or the intersection happens to be where a component pin overlaps, it is considered an electrical connection and should be retained as the same continuous wire. At the same time, for "T" or "cross" type connections, the connectivity is determined by analyzing the orientation angle of each line segment at the intersection and grouping the line segments on opposite sides into pairs. In the case of a cross intersection, if there is no node mark, a pair of line segments in the horizontal direction are interconnected, a pair of line segments in the vertical direction are interconnected, and there is no connection between the horizontal and vertical directions.

8. The method for generating a netlist based on circuit diagram recognition according to claim 1, characterized in that, The method involves marking multiple continuous wires, determining the connection relationships in the netlist based on each continuous wire and the component mask, and simultaneously determining the component list in the netlist based on the identification of the binary mask. The component list and connection relationships are then summarized to generate a netlist in a standard format. In the netlist, each electronic component lists the node number or name to which it is connected, including: The system monitors multiple continuous wires in real time, extracts features from the component mask, extracts the bounding box position and type information of each component symbol, and pre-determines the pin area of ​​each component based on the component type features. For each component pin area, it detects whether a pixel of a certain continuous wire passes through its position or is close to the end of the continuous wire, and then establishes the connection relationship between the component pin and the continuous wire.

9. The method for generating a netlist based on circuit diagram recognition according to claim 8, characterized in that, The method involves marking multiple continuous wires, determining the connection relationships in the netlist based on each continuous wire and the component mask, and simultaneously determining the component list in the netlist based on the identification of the binary mask. The component list and connection relationships are then summarized to generate a netlist in a standard format. In the netlist, each electronic component lists the node number or name it is connected to, and also includes: The node name text is extracted using a label mask. The text labels of adjacent continuous wires are compared. If the labels have the same name, the corresponding continuous wires are automatically merged into the same node. For standard power and ground symbols, once the same type is detected, the continuous wires connected to them are merged to build a component list. The component list and connection relationships are summarized to generate a standard format netlist. Each electronic component in the netlist lists the node number or name it is connected to. The generated netlist is output after verification and can be directly used for layout reconstruction.

10. A netlist generation system based on circuit diagram recognition, characterized in that, The netlist generation system based on circuit diagram recognition is applied to the netlist generation method based on circuit diagram recognition as described in any one of claims 1-9; The netlist generation system based on circuit diagram recognition includes: The image recognition module is used to acquire circuit diagrams, perform image recognition on the circuit diagrams, determine multiple feature categories in the image recognition, trigger semantic segmentation of the circuit diagrams based on the content and corresponding positions of multiple feature categories, and output corresponding binary masks. The binary masks include connection masks, component masks and annotation masks. The connected region module is used to traverse the binary mask, mark the corresponding connected pixels during the traversal, and recursively search the surrounding positions along the connected pixels until the boundary of the connected pixel cluster is found to determine a complete connected region; each connected region corresponds to a continuous wire in the circuit diagram. The continuous wire module is used to refine the connected regions into skeleton lines with a width of one pixel in each connected region, determine the corresponding endpoints and intersections based on the detection of the skeleton lines, and determine multiple continuous wires in the connected region based on the endpoints and intersections. The multiple continuous wires are in an independent state. The netlist module is used to mark multiple continuous wires, determine the connection relationships in the netlist based on each continuous wire and component mask, and determine the component list in the netlist based on the identification of the binary mask. The component list and connection relationships are then summarized to generate a netlist in a standard format. In the netlist, each electronic component lists the node number or name to which it is connected.

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