High-voltage Geiger mode avalanche photodiode quenching circuit

Abstract

The invention discloses a high-voltage Geiger mode avalanche photodiode quenching circuit, which comprises an avalanche photodiode D1, and further comprises a quenching and resetting unit for realizing quenching and resetting of the avalanche photodiode D1 in response to a quenching control signal and a resetting control signal; the voltage reduction unit is used for reducing the voltage of the cathode of the avalanche photodiode D1 to be within the input range allowed by the control unit step by step; and the control unit is used for generating a corresponding quenching control signal and a corresponding resetting control signal according to the voltage change caused by the avalanche of the avalanche photodiode D1 so as to drive the quenching and resetting unit. The high-voltage Geiger mode avalanche photodiode quenching circuit provided by the invention is small in area, high in speed and high in reliability.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a high-voltage Geiger mode avalanche photodiode quenching circuit. Background Technology

[0002] Geiger-mode avalanche photodiodes (APDs) operate under high bias and have single-photon detection capabilities. Due to their advantages such as high sensitivity, high quantum efficiency, and ease of integration, they have been widely used in fields such as laser ranging, lidar 3D imaging, environmental detection, and medical testing.

[0003] Increasing the bias voltage of an avalanche photodiode can improve its sensitivity and efficiency, but it also presents challenges for the design of its readout circuit. If the quenching circuit of the avalanche photodiode is designed entirely with high-voltage MOSFETs, it will affect its response speed and occupy more area. If a DC blocking capacitor is added to isolate the avalanche photodiode from the circuit and an AC coupling scheme is used, then there is not enough space on either the detector chip or the circuit chip to design such a large DC blocking capacitor.

[0004] Therefore, it is urgently needed to be able to quench and reset high-voltage Geiger mode avalanche photodiodes without using DC blocking capacitors and with only a few high-voltage tubes. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the technical problem to be solved by the present invention is to provide a high-voltage Geiger mode avalanche photodiode quenching circuit that does not use DC blocking capacitors and only uses a small number of high-voltage tubes.

[0006] To solve the above-mentioned technical problems, one technical solution adopted by the present invention is: to provide a high-voltage Geiger mode avalanche photodiode quenching circuit, comprising: The quenching and reset unit is used to respond to the quenching control signal and the reset control signal to realize the quenching and reset of the avalanche photodiode D1; A step-down unit is used to progressively reduce the voltage at the cathode of the avalanche photodiode D1 to the input range allowed by the control unit; and The control unit is used to generate corresponding quenching control signals and reset control signals based on the voltage changes caused by the avalanche photodiode D1, so as to drive the quenching and reset unit.

[0007] Furthermore, the control unit includes: An amplification subunit is used to detect the voltage change caused by avalanche in the avalanche photodiode D1 and amplify it into a recognizable pulse voltage; A comparison subunit is configured to compare the pulse voltage output by the amplification subunit with a reference voltage, and generate a digital trigger signal when the pulse voltage is greater than the reference voltage; and The digital logic control module is used to respond to the digital trigger signal, generate a valid quenching control signal when the digital trigger signal is detected to be valid, and generate a valid reset control signal after the preset quenching time has elapsed.

[0008] Furthermore, the anode of the avalanche photodiode D1 is grounded, and the cathode of the avalanche photodiode D1 is electrically connected to the output terminal of the quenching and reset unit.

[0009] Furthermore, the quenching and reset unit includes a high-voltage PMOS transistor SPLD1 and a high-voltage NMOS transistor SNLD1. The source of the high-voltage PMOS transistor SPLD1 is connected to a high-voltage power supply HVDD, and the gate of the high-voltage PMOS transistor SPLD1 is connected to the reset control signal. The gate of the high-voltage NMOS transistor SNLD1 is connected to the quenching control signal, and the source of the high-voltage NMOS transistor SNLD1 is grounded. The drain of the high-voltage PMOS transistor SPLD1 and the drain of the high-voltage NMOS transistor SNLD1 are electrically connected as the output terminal of the quenching and reset unit and are electrically connected to the cathode of the avalanche photodiode D1.

[0010] Furthermore, the quenching and reset unit also includes a first level conversion subunit and a second level conversion subunit; the input terminal of the first level conversion subunit is connected to the reset control signal, and the output terminal of the first level conversion subunit is electrically connected to the gate of the high-voltage PMOS transistor SPLD1; the input terminal of the second level conversion subunit is connected to the quenching control signal, and the output terminal of the second level conversion subunit is electrically connected to the gate of the high-voltage NMOS transistor SNLD1.

[0011] Furthermore, the buck unit includes at least two PMOS transistors connected in series; wherein, the source of the first-stage PMOS transistor serves as the input terminal of the buck unit and is electrically connected to the cathode of the avalanche photodiode D1, and its gate is electrically connected to its drain and the source of the next-stage PMOS transistor; the source of the last-stage PMOS transistor is electrically connected to the drain of the previous-stage PMOS transistor and serves as the output terminal of the buck unit, electrically connected to the control unit; when the buck unit includes three or more PMOS transistors, the PMOS transistor connected in series between the first-stage PMOS transistor and the last-stage PMOS transistor is an intermediate-stage PMOS transistor, the source of each intermediate-stage PMOS transistor is electrically connected to the drain of the previous-stage PMOS transistor, and the source of each intermediate-stage PMOS transistor is electrically connected to its drain and the source of the next-stage PMOS transistor.

[0012] Furthermore, the buck unit includes four PMOS transistors connected in series.

[0013] Furthermore, the step-down unit also includes at least one step-down resistor R, which is connected in series between two adjacent PMOS transistors.

[0014] Furthermore, the amplification subunit is configured as an amplifier, and the comparison subunit is configured as a comparator; the input terminal of the amplifier is electrically connected to the output terminal of the buck unit, the output terminal of the amplifier is electrically connected to the non-inverting input terminal of the comparator, the inverting input terminal of the comparator is connected to the reference voltage, the output terminal of the comparator is electrically connected to the input terminal of the digital logic control module, the first output terminal of the digital logic control module outputs the reset control signal, and the second output terminal of the digital logic control module outputs the quenching control signal.

[0015] Furthermore, the digital logic control module controls the generation time of the reset control signal to be later than the generation time of the quench control signal.

[0016] The high-voltage Geiger mode avalanche photodiode quenching circuit of the present invention has at least the following beneficial effects: The present invention replaces the traditional large-capacity DC blocking capacitor with a step-down unit, achieving safe isolation between the high-voltage avalanche photodiode and the low-voltage control unit. This eliminates the need for a large area of ​​DC blocking capacitor and the use of all high-voltage transistors, significantly reducing chip area and facilitating monolithic integration. The control unit uses low-voltage devices, resulting in fast response speed. Simultaneously, the digital logic control module delays the reset control signal compared to the quenching control signal, achieving rapid and reliable quenching and reset of the avalanche photodiode, effectively improving single-photon detection efficiency. The number of PMOS transistors and the optional series resistor in the step-down unit provide flexible step-down adjustment capabilities, enabling the circuit to adapt to avalanche photodiodes with different operating voltages. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a schematic diagram of the high-voltage Geiger mode avalanche photodiode quenching circuit of the present invention.

[0018] Figure 2 This is a circuit diagram of one embodiment of the high-voltage Geiger mode avalanche photodiode quenching circuit of the present invention.

[0019] Figure 3 for Figure 2 The waveform diagram shown is of the high-voltage Geiger mode avalanche photodiode quenching circuit.

[0020] Figure 4 This is a circuit diagram of another embodiment of the high-voltage Geiger mode avalanche photodiode quenching circuit of the present invention. Detailed Implementation

[0021] The invention will now be further described with reference to the accompanying drawings.

[0022] Please see Figure 1 The high-voltage Geiger-mode avalanche photodiode quenching circuit of the present invention includes a quenching and reset unit 100, a step-down unit 200, and a control unit 300. The quenching and reset unit 100 is used to quench and reset the avalanche photodiode D1 in response to a quenching control signal SW and a reset control signal SWN. The step-down unit 200 is used to gradually reduce the voltage of the cathode of the avalanche photodiode D1 to the input range allowed by the control unit 300. The control unit 300 is used to generate corresponding quenching control signals SW and SWN according to the voltage changes caused by the avalanche of the avalanche photodiode D1, so as to drive the quenching and reset unit 100.

[0023] The anode of the avalanche photodiode D1 is grounded, and the cathode of the avalanche photodiode D1 is electrically connected to the output terminal of the quenching and reset unit 100.

[0024] The quenching and reset unit 100 includes a high-voltage PMOS transistor SPLD1 and a high-voltage NMOS transistor SNLD1. The source of the high-voltage PMOS transistor SPLD1 is connected to a high-voltage power supply HVDD, and the gate of the high-voltage PMOS transistor SPLD1 is connected to the reset control signal SWN. The gate of the high-voltage NMOS transistor SNLD1 is connected to the quenching control signal SW, and the source of the high-voltage NMOS transistor SNLD1 is grounded. The drain of the high-voltage PMOS transistor SPLD1 and the drain of the high-voltage NMOS transistor SNLD1 are electrically connected as the output terminal of the quenching and reset unit 100 and are electrically connected to the cathode of the avalanche photodiode D1.

[0025] To convert the low-voltage control signal generated by the control unit 300 into a high-voltage control signal capable of effectively controlling the high-voltage PMOS transistor SPLD1 and the high-voltage NMOS transistor SNLD1, the quenching and reset unit 100 further includes a first level conversion subunit 110 and a second level conversion subunit 120. The input terminal of the first level conversion subunit 110 is connected to the reset control signal SWN, and the output terminal of the first level conversion subunit 110 is electrically connected to the gate of the high-voltage PMOS transistor SPLD1. The input terminal of the second level conversion subunit 120 is connected to the quenching control signal SW, and the output terminal of the second level conversion subunit 120 is electrically connected to the gate of the high-voltage NMOS transistor SNLD1.

[0026] To protect the low-voltage devices in the control unit 300 and provide safety isolation, a step-down unit 200 is provided between the quenching and reset unit 100 and the control unit 300. The step-down unit 200 includes at least two PMOS transistors connected in series. The source of the first-stage PMOS transistor serves as the input terminal of the step-down unit 200 and is electrically connected to the cathode of the avalanche photodiode D1. Its gate, drain, and the source of the next-stage PMOS transistor are electrically connected. The source of the last-stage PMOS transistor is electrically connected to the drain of the previous-stage PMOS transistor and serves as the output terminal of the step-down unit 200, electrically connected to the control unit 300. When the step-down unit 200 includes three or more PMOS transistors, the PMOS transistor connected in series between the first-stage and last-stage PMOS transistors is an intermediate-stage PMOS transistor. The source of each intermediate-stage PMOS transistor is electrically connected to the drain of the previous-stage PMOS transistor, and the source of each intermediate-stage PMOS transistor is electrically connected to its drain and the source of the next-stage PMOS transistor. Figure 1 It is known that the step-down unit 200 may include PMOS transistors PM1, PM2, ..., PMn-1, PMn. The number n of PMOS transistors can be selected according to the actual step-down requirements. The gate voltage of these PMOS transistors gradually decreases from HVDD to GND.

[0027] Please see Figure 2 In this embodiment, the buck converter 200 includes four PMOS transistors connected in series: a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, and a fourth PMOS transistor PM4. The source of the first PMOS transistor PM1 is electrically connected to the cathode of the avalanche photodiode D1, and the gate of the first PMOS transistor PM1 is electrically connected to its drain. The drain of the first PMOS transistor PM1 is electrically connected to the source of the second PMOS transistor PM2. The gate of the second PMOS transistor PM2 is electrically connected to its drain, and the drain of the second PMOS transistor PM2 is electrically connected to the source of the third PMOS transistor PM3. The gate of the third PMOS transistor PM3 is electrically connected to its drain, serving as the output terminal of the buck converter 200, and is connected to the control unit 300. The drain of the third PMOS transistor PM3 is electrically connected to the source of the fourth PMOS transistor PM4. The gate of the fourth PMOS transistor PM4 is electrically connected to the drain of the fourth PMOS transistor PM4, and the drain of the fourth PMOS transistor PM4 is grounded.

[0028] The control unit 300 includes an amplification subunit 310, a comparison subunit 320, and a digital logic control module 330. The amplification subunit 310 detects the voltage change caused by the avalanche of the avalanche photodiode D1 and amplifies it into a recognizable pulse voltage VPULSE. The comparison subunit 320 compares the pulse voltage VPULSE output by the amplification subunit 310 with a reference voltage VREF. When the pulse voltage VPULSE is greater than the reference voltage VREF, a digital trigger signal CMPOUT is generated. The digital logic control module 330 responds to the digital trigger signal CMPOUT by generating a valid quenching control signal SW when the CMPOUT is detected to be valid, and generating a valid reset control signal SWN after a preset quenching time.

[0029] The amplification subunit 310 is configured as an amplifier, and the comparator subunit 320 is configured as a comparator. The input terminal of the amplifier is electrically connected to the output terminal of the buck unit 200, the output terminal of the amplifier is electrically connected to the non-inverting input terminal of the comparator, the inverting input terminal of the comparator is connected to the reference voltage VREF, and the output terminal of the comparator is electrically connected to the input terminal of the digital logic control module 330. The first output terminal of the digital logic control module 330 outputs the reset control signal SWN, and the second output terminal of the digital logic control module 330 outputs the quenching control signal SW.

[0030] Please see Figure 3The process of generating the quench control signal SW and the reset control signal SWN is the result of the internal state transition of the digital logic control module 330 according to a preset timing sequence. The specific process is as follows: When the input digital trigger signal CMPOUT is low, it is determined that the digital trigger signal CMPOUT is invalid. At this time, the digital logic control module 330 is in the initial state after reset, and the output quench control signal SW is low (i.e., the quench control signal SW is invalid), and the reset control signal SWN is low (i.e., the reset control signal SWN is invalid). At this time, both the high-voltage PMOS transistor SPLD1 and the high-voltage NMOS transistor SNLD1 are turned off, and the cathode of the avalanche photodiode D1 maintains a high voltage, in a detectable state. When the rising edge of the digital trigger signal CMPOUT is detected, it is determined that the digital trigger signal CMPOUT is valid, confirming that the avalanche photodiode D1 has avalanched. The digital logic control module 330 immediately switches to the quench state, and the output quench control signal SW immediately becomes high (i.e., the quench control signal SW is valid), while the reset control signal SWN remains low. At this time, the high-voltage NMOS transistor SNLD1 is turned on, rapidly pulling down the cathode voltage of the avalanche photodiode D1, thus quenching it. The quenching state is maintained until the preset quenching time ends, ensuring sufficient time for the charge carriers inside the avalanche photodiode D1 to dissipate, completely extinguishing the avalanche process. After the preset quenching time ends, the digital logic control module 330 switches to the reset state, the output quenching control signal SW becomes low, and the reset control signal SWN becomes high (i.e., the reset control signal SWN is active). The high-voltage PMOS transistor SPLD1 is turned on, rapidly pulling the cathode voltage of the avalanche photodiode D1 back to the high-voltage HVDD, achieving a reset. When the avalanche photodiode D1 is fully reset, both the quenching control signal SW and the reset control signal SWN output by the digital logic control module 330 return to low, preparing to respond to the next avalanche event.

[0031] Please see Figure 2 and Figure 3The working cycle of the high-voltage Geiger mode avalanche photodiode quenching circuit is as follows: Node VIN (i.e., the cathode of avalanche photodiode D1) is first reset to high voltage HVDD. At this time, avalanche photodiode D1 is in Geiger mode, waiting for photon incidence. Since the gate voltages of PMOS transistors PM1 to PM4 in the buck unit 200 decrease sequentially, even though node VIN is at high voltage, the gate voltage of the third PMOS transistor PM3 is at a lower voltage value and can be connected to the input of the amplifier. When a photon is incident on avalanche photodiode D1, avalanche photodiode D1 generates an avalanche current, causing the voltage of node VIN to decrease slowly. At the same time, the gate voltage of the third PMOS transistor PM3 also decreases accordingly. After amplification, it is converted into a rising pulse voltage VPULSE. When the pulse voltage VPULSE is greater than the reference voltage VREF, the comparator flips. The digital logic control module 330 generates a high-level quenching control signal SW and a reset control signal SWN based on the rising edge of this flip signal (digital trigger signal CMPOUT). Both the quenching control signal SW and the reset control signal SWN are low-voltage control signals. After being converted by the first and second level conversion units, they are transformed into appropriate high-voltage control signals to control the high-voltage PMOS transistor SPLD1 and the high-voltage NMOS transistor SNLD1. The reset control signal SWN is delayed compared to the quenching control signal SW, allowing the avalanche photodiode D1 to remain quenched for a certain period before being reset. When the quenching control signal SW is high, SNLD1 conducts, causing the voltage at node VIN to drop rapidly, achieving quenching. When the reset control signal SWN is high, the voltage at point VIN is reset to the high voltage HVDD, awaiting the next photon incident response.

[0032] To work in conjunction with the PMOS transistors to achieve both voltage reduction and current limiting, in a preferred embodiment, the voltage reduction unit 200 may further include at least one voltage reduction resistor R, which is connected in series between two adjacent PMOS transistors. Specifically, the two ends of the voltage reduction resistor R are electrically connected to the drain of the preceding PMOS transistor and the source of the following PMOS transistor, respectively. Please refer to [link to relevant documentation]. Figure 4 In this embodiment, the step-down unit 200 further includes a step-down resistor R, one end of which is electrically connected to the drain of the second PMOS transistor PM2, and the other end of which is electrically connected to the source of the third PMOS transistor PM3.

[0033] This invention replaces the traditional large-capacity DC blocking capacitor with a step-down unit, achieving safe isolation between the high-voltage avalanche photodiode and the low-voltage control unit. It eliminates the need for a large DC blocking capacitor and all-high-voltage transistors, significantly reducing chip area and facilitating monolithic integration. The control unit uses low-voltage devices, resulting in fast response. Simultaneously, the digital logic control module delays the reset control signal compared to the quench control signal, enabling rapid and reliable quenching and reset of the avalanche photodiode, effectively improving single-photon detection efficiency. The number of PMOS transistors and the optional series resistor in the step-down unit provide flexible voltage adjustment capabilities, allowing the circuit to adapt to avalanche photodiodes with different operating voltages.

[0034] The above description merely illustrates preferred embodiments of the present invention and is quite specific and detailed; however, it should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept, and these all fall within the scope of protection of the present invention. Therefore, the scope of protection of this invention should be determined by the appended claims.

Claims

1. A high-voltage Geiger mode avalanche photodiode quenching circuit, characterized in that, include: The quenching and reset unit is used to respond to the quenching control signal and the reset control signal to realize the quenching and reset of the avalanche photodiode D1; The step-down unit is used to gradually reduce the voltage of the cathode of the avalanche photodiode D1 to the input range allowed by the control unit; as well as The control unit is used to generate corresponding quenching control signals and reset control signals based on the voltage changes caused by the avalanche photodiode D1, so as to drive the quenching and reset unit.

2. The high-voltage Geiger mode APD quenching circuit according to claim 1, characterized in that, The control unit includes: An amplification subunit is used to detect the voltage change caused by avalanche in the avalanche photodiode D1 and amplify it into a recognizable pulse voltage; A comparison subunit is used to compare the pulse voltage output by the amplification subunit with a reference voltage, and generate a digital trigger signal when the pulse voltage is greater than the reference voltage; as well as The digital logic control module is used to respond to the digital trigger signal, generate a valid quenching control signal when the digital trigger signal is detected to be valid, and generate a valid reset control signal after the preset quenching time has elapsed.

3. The high-voltage Geiger mode avalanche photodiode quenching circuit as described in claim 1, characterized in that: The anode of the avalanche photodiode D1 is grounded, and the cathode of the avalanche photodiode D1 is electrically connected to the output terminal of the quenching and reset unit.

4. The high-voltage Geiger mode avalanche photodiode quenching circuit as described in claim 1, characterized in that: The quenching and reset unit includes a high-voltage PMOS transistor SPLD1 and a high-voltage NMOS transistor SNLD1. The source of the high-voltage PMOS transistor SPLD1 is connected to a high-voltage power supply HVDD, and the gate of the high-voltage PMOS transistor SPLD1 is connected to the reset control signal. The gate of the high-voltage NMOS transistor SNLD1 is connected to the quenching control signal, and the source of the high-voltage NMOS transistor SNLD1 is grounded. The drain of the high-voltage PMOS transistor SPLD1 and the drain of the high-voltage NMOS transistor SNLD1 are electrically connected as the output terminal of the quenching and reset unit and are electrically connected to the cathode of the avalanche photodiode D1.

5. The high-voltage Geiger mode avalanche photodiode quenching circuit as described in claim 4, characterized in that: The quenching and reset unit further includes a first level conversion subunit and a second level conversion subunit; the input terminal of the first level conversion subunit is connected to the reset control signal, and the output terminal of the first level conversion subunit is electrically connected to the gate of the high-voltage PMOS transistor SPLD1; the input terminal of the second level conversion subunit is connected to the quenching control signal, and the output terminal of the second level conversion subunit is electrically connected to the gate of the high-voltage NMOS transistor SNLD1.

6. The high-voltage Geiger mode avalanche photodiode quenching circuit as described in claim 1, characterized in that: The step-down unit includes at least two PMOS transistors connected in series. The source of the first-stage PMOS transistor serves as the input terminal of the step-down unit and is electrically connected to the cathode of the avalanche photodiode D1. Its gate is electrically connected to its drain and the source of the next-stage PMOS transistor. The source of the last-stage PMOS transistor is electrically connected to the drain of the previous-stage PMOS transistor and serves as the output terminal of the step-down unit, electrically connected to the control unit. When the step-down unit includes three or more PMOS transistors, the PMOS transistor connected in series between the first-stage and last-stage PMOS transistors is an intermediate-stage PMOS transistor. The source of each intermediate-stage PMOS transistor is electrically connected to the drain of the previous-stage PMOS transistor, and the source of each intermediate-stage PMOS transistor is electrically connected to its drain and the source of the next-stage PMOS transistor.

7. The high-voltage Geiger mode avalanche photodiode quenching circuit as described in claim 6, characterized in that: The step-down unit includes four PMOS transistors connected in series.

8. The high-voltage Geiger mode avalanche photodiode quenching circuit as described in claim 6, characterized in that: The step-down unit also includes at least one step-down resistor R, which is connected in series between two adjacent PMOS transistors.

9. The high-voltage Geiger mode avalanche photodiode quenching circuit as described in claim 2, characterized in that: The amplification subunit is configured as an amplifier, and the comparator subunit is configured as a comparator; the input terminal of the amplifier is electrically connected to the output terminal of the buck unit, the output terminal of the amplifier is electrically connected to the non-inverting input terminal of the comparator, the inverting input terminal of the comparator is connected to the reference voltage, the output terminal of the comparator is electrically connected to the input terminal of the digital logic control module, the first output terminal of the digital logic control module outputs the reset control signal, and the second output terminal of the digital logic control module outputs the quenching control signal.

10. The high-voltage Geiger mode APD quenching circuit according to claim 1, characterized in that: The digital logic control module controls the generation time of the reset control signal to be later than the generation time of the quench control signal.

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