Grid driving circuit using ideal diode circuit as bootstrap diode

Abstract

The invention discloses a gate drive circuit with an ideal diode circuit as a bootstrap diode. The gate drive circuit comprises an input logic circuit, a high-side drive circuit HSD, the ideal diode circuit, a low-side drive circuit LSD and a power supply circuit. The input logic circuit is used for performing level shift processing on a high-side input signal HI to generate a first control signal and performing level shift processing on a low-side input signal LI to generate a second control signal; the high-side driving circuit HSD is used for generating a high-side driving signal HO according to the first control signal; the ideal diode circuit is used for bootstrap boost of the high-side driving circuit; the low-side driving circuit LSD is used for generating a low-side driving signal LO according to the second control signal; and the power supply circuit is used for providing reference voltage and reference current for each module. During high-frequency work, electric leakage to ground is small, chip power consumption is low, chip temperature is low, high-side output voltage is high when VDD voltage is low, the driving capacity is high, and a high-side power MOSFET is not prone to being burnt out.

Description

Technical Field

[0001] This invention belongs to the field of electronic circuit technology and relates to a gate drive circuit for using an ideal diode circuit as a bootstrap diode. Background Technology

[0002] A gate driver circuit is a type of gate driver circuit, typically a half-bridge driver structure. It has a low-side drive circuit and a floating high-side drive circuit, used to drive a half-bridge driver composed of discrete power MOSFETs outside the chip. Both the high-side and low-side of the half-bridge driver are N-type power MOSFETs.

[0003] The gate drive circuit has two input drive signals, which are complementary and have a certain dead time. The external half-bridge power supply is VIN, connected to the drain of the high-side power MOSFET. The working principle of the gate drive circuit is as follows: When driving the low-side power MOSFET, the low-side output LO outputs a high level, the high-side output HO outputs a low level, and the half-bridge output HS is low. At this time, VDD charges the bootstrap capacitor connected between HB and HS through the bootstrap diode. Charging stops when the voltage on the bootstrap capacitor rises to VDD-0.7V, where 0.7V represents the forward voltage drop of the bootstrap diode in the PN junction. When the high-side drive HO outputs a high level and the low-side drive LO outputs a low level, the half-bridge output HS=VIN, HB=VDD-0.7V+VIN. At this time, the bootstrap diode is reverse-biased and cut off, and the high-side gate drive is powered by the bootstrap capacitor.

[0004] In medium- and high-voltage applications, the bootstrap diode in the gate drive circuit needs to have high forward current capability and high reverse withstand voltage. The bootstrap diode has a vertical parasitic SPNP in its device structure. When the bootstrap diode is forward-biased, the parasitic SPNP also conducts. A portion of the current flowing through the bootstrap diode flows to ground through the parasitic SPNP, and this portion can account for up to 40% of the total current. At high-frequency operation, this wasted current increases the power consumption and heat generation of the gate drive chip.

[0005] When the bootstrap diode is forward-biased, the voltage drop is 0.7V, causing the voltage VB across the bootstrap capacitor to be 0.7V lower than the voltage VDD. This 0.7V voltage drop reduces the drive capability of the HO (high-side MOSFET), resulting in the high-side HO output voltage being 0.7V lower than the low-side LO output voltage. This makes the high-side power MOSFET more prone to entering the saturation region, leading to greater heat generation. The heat generation phenomenon of the high-side power MOSFET entering the saturation region is more pronounced in applications with lower VDD voltages, and in severe cases, it can burn out the high-side power MOSFET.

[0006] In summary, bootstrap diodes have the following disadvantages: when operating at high frequencies, bootstrap diodes have a large leakage current to ground, resulting in high chip power consumption and a large temperature rise; when the VDD voltage is low, the high-side MOSFET generates a lot of heat and is prone to burnout. Summary of the Invention

[0007] To address at least one of the aforementioned problems, this invention proposes an ideal diode circuit as a gate drive circuit for a bootstrap diode. This circuit features low leakage current to ground, low chip power consumption, low chip temperature during high-frequency operation, high high-side output voltage at low VDD voltage, strong driving capability, and the high-side power MOSFET is less prone to burnout.

[0008] The technical solution adopted in this invention is as follows:

[0009] This application discloses a gate drive circuit for using an ideal diode circuit as a bootstrap diode, including an input logic circuit, a high-side drive circuit HSD, an ideal diode circuit, a low-side drive circuit LSD, and a power supply circuit. The first and second output terminals of the input logic circuit are respectively connected to the input terminals of the high-side drive circuit HSD and the low-side drive circuit LSD. The input logic circuit performs level shifting on the high-side input signal HI to generate a first control signal and performs level shifting on the low-side input signal LI to generate a second control signal. The high-side drive circuit HSD generates a high-side drive signal HO based on the first control signal. The ideal diode circuit provides bootstrap voltage boosting for the high-side drive circuit. The low-side drive circuit LSD generates a low-side drive signal LO based on the second control signal. The power supply circuit provides a reference voltage and a reference current to each module.

[0010] As an optional technical solution, the ideal diode circuit includes a comparator Comp, an inverter INV, and a high-voltage PLDMOS transistor; the non-inverting input of the comparator Comp is connected to the power supply pin VDD, the inverting input of the comparator Comp is connected to the floating power supply pin HB, the output of the comparator Comp is connected to the input of the inverter INV, the output of the inverter INV is connected to the gate of the high-voltage PLDMOS transistor, the drain of the high-voltage PLDMOS transistor is connected to the power supply pin VDD, and the source of the high-voltage PLDMOS transistor is connected to the floating power supply pin HB; a resistor R1 and a Zener diode D1 are also connected in parallel between the gate and source of the high-voltage PLDMOS transistor.

[0011] As an optional technical solution, the input logic circuit includes a first filter circuit, a first level shift circuit, and a first dead-time delay circuit connected in series, as well as a second filter circuit, a second level shift circuit, and a second dead-time delay circuit connected in series. The first filter circuit is used to filter the high-side input signal HI to remove glitches from the input signal HI. The first level shift circuit is used to perform level shifting processing on the glitched input signal HI to convert it into a first level shift signal for controlling the high-side drive circuit HSD. The first dead-time delay circuit is used to delay and invert the first level shift signal to generate the... A first control signal is sent to the first and second input terminals of the high-side drive circuit HSD; a second filter circuit is used to filter the low-side input signal L1 to remove glitches from the input signal L1; a second level shift circuit is used to perform level shift processing on the glitches-removed input signal L1 to convert it into a second level shift signal for controlling the low-side drive circuit LSD; a second dead-time delay circuit is used to delay and invert the second level shift signal to generate the second control signal, and the second control signal is sent to the first and second input terminals of the low-side drive circuit LSD.

[0012] As an optional technical solution, the high-side drive circuit HSD includes a high-voltage PLD1 transistor and a high-voltage NLD1 transistor for driving the load, a first inverter INV1, a second inverter INV2, and a third inverter INV3 connected in series, and a fourth inverter INV4, a fifth inverter INV5, and a sixth inverter INV6 connected in series. The input terminal of the first inverter INV1 serves as the first input terminal of the high-side drive circuit HSD and is connected to the output terminal of the first dead-time delay circuit. The output of the third inverter INV3... The terminal of the first inverter INV4 is connected to the gate of the high-voltage PLD1 transistor, and the source of the high-voltage PLD1 transistor is connected to the floating power supply pin HB; the input terminal of the fourth inverter INV4 is connected to the output terminal of the first dead-time delay circuit as the second input terminal of the high-side drive circuit HSD; the output terminal of the sixth inverter INV6 is connected to the gate of the high-voltage NLD1 transistor, and the source of the high-voltage NLD1 transistor is connected to the floating ground pin HS; the drain of the high-voltage PLD1 transistor is connected to the drain of the high-voltage NLD1 transistor, and then connected to the high-side output pin HO.

[0013] As an optional technical solution, the low-side drive circuit LSD includes a high-voltage PLD2 transistor and a high-voltage NLD2 transistor for driving the load, a seventh inverter INV7, an eighth inverter INV8, and a ninth inverter INV9 connected in series, and a tenth inverter INV10, an eleventh inverter INV11, and a twelfth inverter INV12 connected in series. The input terminal of the seventh inverter INV7 serves as the first input terminal of the low-side drive circuit LSD and is connected to the output terminal of the second dead-time delay circuit. The ninth inverter INV9... The output terminal is connected to the gate of the high-voltage PLD2 transistor, and the source of the high-voltage PLD2 transistor is connected to the power supply pin VDD; the input terminal of the tenth inverter INV10 serves as the second input terminal of the low-side drive circuit LSD and is connected to the output terminal of the second dead-time delay circuit; the output terminal of the twelfth inverter INV12 is connected to the gate of the high-voltage NLD2 transistor, and the source of the high-voltage NLD2 transistor is connected to the ground pin VSS; the drain of the high-voltage PLD2 transistor is connected to the drain of the high-voltage NLD2 transistor, and then connected to the low-side output pin LO.

[0014] As an optional technical solution, the power supply circuit includes a high-side floating power supply and a low-side power supply; the input terminal of the high-side floating power supply is connected to the floating power supply pin HB, and the high-side floating power supply includes two output terminals, namely the high-side floating ground output terminal VHPD and the high-side floating power supply output terminal VHPS; the input terminal of the low-side power supply is connected to the power supply pin VDD, and the low-side power supply includes two output terminals, namely the low-side floating ground output terminal VLPD and the low-side floating power supply output terminal VLPS.

[0015] The beneficial effects of this application are as follows:

[0016] 1. The present invention has low leakage current to ground when operating at high frequency, so the chip power consumption is low, the chip temperature is low, the standby power consumption of the application circuit is reduced, and the service life is extended.

[0017] 2. When this invention is working, the voltage difference between VDD and HB-HS is the offset voltage VOS. The VOS voltage is designed to be +0.2V to +0.4V to cut off the charging current in advance and prevent the current from flowing back into the bootstrap capacitor when HS rises. The offset voltage VOS of +0.2V to +0.4V is lower than the diode voltage drop of 0.7V in a typical gate drive circuit, so the high-side output voltage is high and the power MOSFET is not easy to burn out. Attached Figure Description

[0018] Figure 1 This is a circuit block diagram of an ideal diode circuit used as the gate drive circuit for a bootstrap diode in an exemplary embodiment.

[0019] Figure 2This is a circuit diagram of an ideal diode circuit in an exemplary embodiment.

[0020] Figure 3 yes Figure 1 A schematic diagram of an application of the center gate drive circuit.

[0021] Figure 4 This is a circuit block diagram of the input logic circuit in an exemplary embodiment.

[0022] Figure 5 This is a circuit schematic diagram of the first level shifting circuit in an exemplary embodiment.

[0023] Figure 6 This is a circuit schematic diagram of the second level shifting circuit in an exemplary embodiment.

[0024] Figure 7 This is a circuit schematic of the first dead-time delay circuit in an exemplary embodiment.

[0025] Figure 8 This is a circuit schematic of the second dead-time delay circuit in an exemplary embodiment.

[0026] Figure 9 This is a circuit schematic of the high-side drive circuit HSD in an exemplary embodiment.

[0027] Figure 10 This is a circuit schematic of the low-side drive circuit (LSD) in an exemplary embodiment.

[0028] Figure 11 This is a schematic diagram of the timing of each signal in an exemplary embodiment.

[0029] Figure 12 This is a circuit block diagram of a power supply circuit in an exemplary embodiment.

[0030] Figure 13 This is a circuit schematic diagram of a high-side floating power supply in an exemplary embodiment.

[0031] Figure 14 This is a circuit schematic of the low-side power supply in an exemplary embodiment. Detailed Implementation

[0032] The following embodiments are provided to better understand the present invention and are not limited to the following embodiments. They do not constitute a limitation on the content and scope of protection of the present invention. Any product that is the same as or similar to the present invention, derived by any person under the guidance of the present invention or by combining the features of the present invention with other prior art, falls within the protection scope of the present invention.

[0033] In the description of this invention, it should be noted that the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, the technical features involved in the different embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0034] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0035] Example

[0036] like Figure 1 As shown, the ideal diode circuit provided in this embodiment, used as a bootstrap diode gate drive circuit, comprises a total of 8 pins: one power supply pin VDD, one ground pin VSS, two input pins: high-side input HI and low-side input LI, two output pins: high-side output HO and low-side output LO, one floating power supply pin HB, and one floating ground pin HS. The entire circuit mainly consists of five modules: input logic circuit 101, power supply circuit 102, ideal diode circuit 103, high-side drive circuit HSD 104, and low-side drive circuit LSD 105. The input logic circuit 101 is used to process the input signal, the power supply circuit 102 is used to provide the reference voltage and reference current to the circuit, the ideal diode circuit 103 is used for bootstrap boosting of the high-side drive circuit, the ideal diode circuit 103 replaces the bootstrap diode in the conventional gate drive circuit, the ideal diode circuit 103 has the characteristics of low forward voltage drop, low leakage current to ground and high reverse withstand voltage, the high-side drive circuit HSD104 is used to drive the high-side power MOS, and the low-side drive circuit LSD105 is used to drive the low-side power MOS. Specifically, as an optional implementation, the first and second output terminals of the input logic circuit 101 are respectively connected to the input terminals of the high-side driving circuit HSD104 and the low-side driving circuit LSD105. The input logic circuit 101 is used to perform level shifting processing on the high-side input signal HI to generate a first control signal, and to perform level shifting processing on the low-side input signal LI to generate a second control signal. The high-side driving circuit HSD104 is used to generate a high-side driving signal HO according to the first control signal. The ideal diode circuit 103 is used to bootstrap the high-side driving circuit HSD104. The low-side driving circuit LSD105 is used to generate a low-side driving signal LO according to the second control signal. The power supply circuit 102 is used to provide a reference voltage and a reference current for each module.

[0037] As an optional implementation method, such as Figure 2As shown, the ideal diode circuit 103 includes a comparator Comp, an inverter INV, and a high-voltage PLDMOS transistor, which represents a high-DS-rated P-type lateral double-diffused MOS transistor. The non-inverting input of the comparator Comp is connected to the power supply pin VDD, the inverting input of the comparator Comp is connected to the floating power supply pin HB, the output of the comparator Comp is connected to the input of the inverter INV, the output of the inverter INV is connected to the gate of the high-voltage PLDMOS transistor, the drain of the high-voltage PLDMOS transistor is connected to the power supply pin VDD, and the source of the high-voltage PLDMOS transistor is connected to the floating power supply pin HB. A resistor R1 and a Zener diode D1 for protection are also connected in parallel between the gate and source of the high-voltage PLDMOS transistor. The positive terminal of the Zener diode D1 is connected to the gate of the high-voltage PLDMOS transistor, and the negative terminal of the Zener diode D1 is connected to the drain of the high-voltage PLDMOS transistor.

[0038] The ideal diode circuit 103 is equivalent to a diode with low forward voltage drop, low leakage current to ground, and high reverse withstand voltage. The working principle of the ideal diode circuit 103 is as follows: In one application embodiment, such as Figure 3 As shown, when the low-side output LO of the gate drive circuit is on and the high-side output HO is off, HS=0V, and the bootstrap capacitor between HB and HS begins to charge. At this time, VDD>VHB (VHB is the voltage at the HB pin), the comparator Comp outputs a high voltage, the inverter INV outputs a low voltage, and the high-voltage PLDMOS (i.e., Figure 2 When the high-voltage PLD is turned on, the ideal diode charges the bootstrap capacitor, and current flows from VDD through the high-voltage PLDMOS to the HB pin. The comparator Comp has an offset voltage VOS. When the bootstrap capacitor is almost fully charged (VDD - VHB = VOS), the COMP output flips to low, the INV output flips to high, and the high-voltage PLDMOS turns off. When the low-side output LO of the gate drive circuit is off and the high-side output HO is on, HS bootstraps to the VIN voltage. The bootstrap capacitor acts as the high-side power supply. At this time, the VHB voltage is much greater than the VDD voltage, the INV output follows HB, and the high-voltage PLDMOS turns off. When the low-side output LO turns on again in the next cycle, HS = 0V, and the ideal diode starts charging the bootstrap capacitor again.

[0039] As an optional implementation method, such as Figure 4As shown, the input logic circuit 101 includes a first filter circuit, a first level shift circuit, and a first dead-time delay circuit connected in series, as well as a second filter circuit, a second level shift circuit, and a second dead-time delay circuit connected in series. The first filter circuit is used to filter the high-side input signal HI to remove glitches from the input signal HI. The first level shift circuit is used to perform level shifting processing on the glitched input signal HI to convert it into a first level shift signal for controlling the high-side drive circuit HSD. The first dead-time delay circuit is used to delay the first level shift signal to generate a first control signal 1 and a first control signal 2. The first control signal 1 and the first control signal 2 are sent to the first input terminal and the second input terminal of the high-side drive circuit HSD; the second filter circuit is used to filter the low-side input signal L1 to remove glitches in the input signal L1; the second level shift circuit is used to perform level shift processing on the glitches-removed input signal L1 to convert it into a second level shift signal for controlling the low-side drive circuit LSD; the second dead-time delay circuit is used to delay the second level shift signal to generate the second control signal 1 and the second control signal 2; the second control signal 1 and the second control signal 2 are sent to the first input terminal and the second input terminal of the low-side drive circuit LSD.

[0040] Specifically, the first level shifting circuit is as follows: Figure 5 This includes a high-voltage NLD3 (high-voltage NLD indicates a high-DS withstand voltage N-type lateral double-diffused MOSFET), a thirteenth inverter INV13, a fourteenth inverter INV14, a fifteenth inverter INV15, a resistor R2, and a Zener diode D2. The gate of the high-voltage NLD3 receives the output signal of the first filter circuit, its source is grounded, and its drain is connected in series with the thirteenth inverter INV13, the fourteenth inverter INV14, and the fifteenth inverter INV15. The output of the fifteenth inverter INV15 outputs the output signal of the first level shift circuit. The resistor R2 and the Zener diode D2 are connected in parallel between pin HB and the drain of the high-voltage NLD3, and are used to clamp the input voltage of INV13. When the output signal of the first filter circuit is high, the high-voltage NLD3 is turned on, the input of the thirteenth inverter INV13 is low and the output is high, INV14 outputs low, and INV15 outputs high. The second level shift circuit is as follows: Figure 6 This includes high voltage NLD4, sixteenth inverter INV16, seventeenth inverter INV17, eighteenth inverter INV18, resistor R3, and Zener diode D3. The second level shift circuit is similar in structure and principle to the first level shift circuit. When the output signal of the second filter circuit is high, the eighteenth inverter INV18 outputs a high level.

[0041] Specifically, the first dead-time delay circuit is as follows: Figure 7 The circuit consists of, in series, the nineteenth inverter INV19, the twentieth inverter INV20, the twenty-first inverter INV21, the twenty-second inverter INV22, the twenty-third inverter INV23, the twenty-fourth inverter INV24, the twenty-fifth inverter INV25, and the twenty-sixth inverter INV26, as well as an NMOS transistor NM1, a first NAND gate NAND1, and a twenty-seventh inverter INV27. The source of NM1 is connected to the high-side floating ground output terminal VHPD, and the gate of NM1... The output signal of the first level shift circuit is connected to the output of the 21st inverter, INV21. The two inputs of the first NAND gate, NAND1, are connected to the output signals of the first level shift circuit and the 26th inverter, INV26, respectively. The output of the first NAND gate, NAND1, is connected to the input of the 27th inverter, INV27. The output of the 24th inverter, INV24, outputs the first control signal 2, and the output of the 27th inverter, INV27, outputs the first control signal 1. INV20 and INV21 form delay circuit 1 with a delay time of tF. INV25 and INV26 form delay circuit 2 with a delay time of tR. The working principle of the first dead-time delay circuit is to process the output signal of the first level shift circuit into the first control signal 1 and the first control signal 2. The high level output of the first control signal 1 is delayed by tR time compared to the high level output of the first level shift circuit, and the low level output of the first control signal 2 is delayed by tF time compared to the low level output of the first level shift circuit. The high and low levels output by the first control signal 1 are used to turn the high voltage PLD1 of the HSD on and off, respectively. The high and low levels output by the first control signal 2 are used to turn the high voltage NLD1 of the HSD on and off, respectively. The second dead-time delay circuit is as follows: Figure 8 The circuit includes inverters INV28-INV36, an NMOS transistor NM2, and a second NAND gate NAND2. The output signal of the second level shift circuit is input from the input terminal of the twenty-eighth inverter INV28. The generated second control signal 1 and second control signal 2 are output from the output terminals of the thirty-sixth inverter INV36 and the thirty-third inverter INV33, respectively. INV29 and INV30 form delay circuit 3 with a delay time of tF, and INV34 and INV35 form delay circuit 4 with a delay time of tR. The specific circuit structure and working principle of the second dead-time delay circuit are similar to those of the first dead-time delay circuit, and will not be described in detail here.

[0042] High-side drive circuit HSD (e.g.) Figure 9During operation, it is necessary to prevent high-voltage NLD1 and high-voltage PLD1 from turning on simultaneously, which could cause them to conduct together and burn out. The purpose of the dead-time delay circuit is to generate sufficient delay time to prevent high-voltage NLD1 and high-voltage PLD1 from turning on at the same time.

[0043] During operation, if the first level shift circuit outputs a high-level signal, the first control signal 2 immediately outputs a high-level signal, and the high-voltage NLD1 of the HSD will be turned off immediately. At this time, both high-voltage PLD1 and high-voltage NLD1 are in the off state. Then, after a time interval tR, the first control signal 1 outputs a high-level signal, thereby turning on the high-voltage PLD1 of the HSD. tR is called the high-side dead time. If the first level shift circuit outputs a low-level signal, the first control signal 1 immediately outputs a low-level signal, and the high-voltage PLD1 of the HSD will be turned off immediately. At this time, both high-voltage PLD1 and high-voltage NLD1 are in the off state. Then, after a time interval tF, the first control signal 2 outputs a low-level signal, thereby turning on the high-voltage NLD1. tF is called the low-side dead time. The timing diagram is as follows: Figure 11 .

[0044] As an optional implementation method, such as Figure 9 As shown, the high-side drive circuit HSD104 includes a high-voltage PLD1 transistor and a high-voltage NLD1 transistor (high-voltage NLD represents a high-DS withstand voltage N-type lateral double-diffused MOS transistor) for driving the load, a first inverter INV1, a second inverter INV2, and a third inverter INV3 connected in series, and a fourth inverter INV4, a fifth inverter INV5, and a sixth inverter INV6 connected in series. The input terminal of the first inverter INV1 receives a first control signal 1. The output terminal of the third inverter INV3 is connected to the gate of the high-voltage PLD1 transistor, and the source of the high-voltage PLD1 transistor is connected to the floating power supply pin HB. The input terminal of the fourth inverter INV4 receives a first control signal 2. The output terminal of the sixth inverter INV6 is connected to the gate of the high-voltage NLD1 transistor, and the source of the high-voltage NLD1 transistor is connected to the floating ground pin HS. The drain of the high-voltage PLD1 transistor is connected to the drain of the high-voltage NLD1 transistor, and then connected to the high-side output pin HO, for driving the high-side power load.

[0045] As an optional implementation method, such as Figure 10As shown, the low-side drive circuit LSD includes a high-voltage PLD2 transistor and a high-voltage NLD2 transistor for driving the load, a seventh inverter INV7, an eighth inverter INV8, and a ninth inverter INV9 connected in series, and a tenth inverter INV10, an eleventh inverter INV11, and a twelfth inverter INV12 connected in series. The input terminal of the seventh inverter INV7 receives a second control signal 1. The output terminal of the ninth inverter INV9 is connected to the gate of the high-voltage PLD2 transistor, and the source of the high-voltage PLD2 transistor is connected to the power supply VDD. The input terminal of the tenth inverter INV10 receives a second control signal 2. The output terminal of the twelfth inverter INV12 is connected to the gate of the high-voltage NLD2 transistor, and the source of the high-voltage NLD2 transistor is connected to the ground pin VSS. The drain of the high-voltage PLD2 transistor is connected to the drain of the high-voltage NLD2 transistor, and then connected to the low-side output pin LO, for driving the low-side power load.

[0046] As an optional implementation method, such as Figure 12 As shown, the power supply circuit includes a high-side floating power supply and a low-side power supply; the input terminal of the high-side floating power supply is connected to the floating power supply pin HB, and the high-side floating power supply includes two output terminals, namely the high-side floating ground output terminal VHPD and the high-side floating power supply output terminal VHPS; the input terminal of the low-side power supply is connected to the power supply VDD, and the low-side power supply includes two output terminals, namely the low-side floating ground output terminal VLPD and the low-side floating power supply output terminal VLPS.

[0047] Specifically, as an optional implementation method, such as Figure 13 As shown, the high-side floating power supply includes high voltage PLD3, high voltage PLD4, high voltage NLD5, high voltage NLD6, high voltage NLD7, Zener diodes DZ4-DZ7, resistors R4-R8, and two voltage output ports: high-side floating ground VHPD and high-side floating power supply VHPS. It also includes a power supply port HB and a reference ground port HS.

[0048] Specifically, as an optional implementation method, such as Figure 14 As shown, the low-side power supply includes high-voltage PLD5, high-voltage PLD6, high-voltage NLD8, high-voltage NLD9, high-voltage NLD10, Zener diodes DZ8-DZ12, resistors R9-R15, and two voltage output ports: low-side floating ground VLPD and low-side floating power supply VLPS. It also includes a power supply port VDD and a reference ground port VSS.

[0049] It should be noted that in this application, high voltage NLD represents a high DS withstand voltage N-type lateral double diffused MOSFET, and high voltage PLD represents a high DS withstand voltage P-type lateral double diffused MOSFET.

[0050] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. All technical solutions that fall within the scope of the claims of this invention are within the scope of protection of this invention.

Claims

1. A gate drive circuit for an ideal diode circuit as a bootstrap diode, characterized in that: The system includes an input logic circuit, a high-side drive circuit (HSD), an ideal diode circuit, a low-side drive circuit (LSD), and a power supply circuit. The first and second output terminals of the input logic circuit are connected to the input terminals of the HSD and LSD, respectively. The input logic circuit performs level shifting on the high-side input signal HI to generate a first control signal and performs level shifting on the low-side input signal LI to generate a second control signal. The HSD generates a high-side drive signal HO based on the first control signal. The ideal diode circuit provides bootstrapping for the high-side drive circuit. The LSD generates a low-side drive signal LO based on the second control signal. The power supply circuit provides a reference voltage and reference current to each module.

2. The ideal diode circuit according to claim 1, used as a gate drive circuit for a bootstrap diode, is characterized in that: The ideal diode circuit includes a comparator Comp, an inverter INV, and a high-voltage PLDMOS transistor. The non-inverting input of the comparator Comp is connected to the power supply pin VDD, the inverting input of the comparator Comp is connected to the floating power supply pin HB, the output of the comparator Comp is connected to the input of the inverter INV, the output of the inverter INV is connected to the gate of the high-voltage PLDMOS transistor, the drain of the high-voltage PLDMOS transistor is connected to the power supply pin VDD, and the source of the high-voltage PLDMOS transistor is connected to the floating power supply pin HB. A resistor R1 and a Zener diode D1 are also connected in parallel between the gate and source of the high-voltage PLDMOS transistor.

3. The ideal diode circuit described in claim 1 or 2, used as a gate drive circuit for a bootstrap diode, is characterized in that: The input logic circuit includes a first filter circuit, a first level shift circuit, and a first dead-time delay circuit connected in series, as well as a second filter circuit, a second level shift circuit, and a second dead-time delay circuit connected in series. The first filter circuit filters the high-side input signal HI to remove glitches. The first level shift circuit performs level shifting on the glitches-removed input signal HI to convert it into a first level shift signal for controlling the high-side drive circuit HSD. The first dead-time delay circuit delays and inverts the first level shift signal to generate the first control signal, which is then sent to the first and second input terminals of the high-side drive circuit HSD. The second filter circuit filters the low-side input signal L1 to remove glitches. The second level shift circuit performs level shifting on the glitches-removed input signal L1 to convert it into a second level shift signal for controlling the low-side drive circuit LSD. The second dead-time delay circuit delays and inverts the second level shift signal to generate the second control signal, which is then sent to the first and second input terminals of the low-side drive circuit LSD.

4. The ideal diode circuit described in claim 3, used as a gate drive circuit for a bootstrap diode, is characterized in that: The high-side drive circuit HSD includes a high-voltage PLD1 transistor and a high-voltage NLD1 transistor for driving the load, a first inverter INV1, a second inverter INV2, and a third inverter INV3 connected in series, and a fourth inverter INV4, a fifth inverter INV5, and a sixth inverter INV6 connected in series. The input terminal of the first inverter INV1 serves as the first input terminal of the high-side drive circuit HSD and is connected to the output terminal of the first dead-time delay circuit. The output terminal of the third inverter INV3 is connected to the gate of the high-voltage PLD1 transistor, and the source of the high-voltage PLD1 transistor is connected to the floating power supply pin HB. The input terminal of the fourth inverter INV4 serves as the second input terminal of the high-side drive circuit HSD and is connected to the output terminal of the first dead-time delay circuit. The output terminal of the sixth inverter INV6 is connected to the gate of the high-voltage NLD1 transistor, and the source of the high-voltage NLD1 transistor is connected to the floating ground pin HS. The drain of the high-voltage PLD1 transistor is connected to the drain of the high-voltage NLD1 transistor and then to the high-side output pin HO.

5. The ideal diode circuit according to claim 3, used as a gate drive circuit for a bootstrap diode, is characterized in that: The low-side drive circuit LSD includes a high-voltage PLD2 transistor and a high-voltage NLD2 transistor for driving the load, a seventh inverter INV7, an eighth inverter INV8, and a ninth inverter INV9 connected in series, and a tenth inverter INV10, an eleventh inverter INV11, and a twelfth inverter INV12 connected in series. The input terminal of the seventh inverter INV7 serves as the first input terminal of the low-side drive circuit LSD and is connected to the output terminal of the second dead-time delay circuit. The output terminal of the ninth inverter INV9 is connected to the... The gate of the high-voltage PLD2 transistor is connected to the power supply pin VDD; the input terminal of the tenth inverter INV10 is connected to the output terminal of the second dead-time delay circuit as the second input terminal of the low-side drive circuit LSD; the output terminal of the twelfth inverter INV12 is connected to the gate of the high-voltage NLD2 transistor; the source of the high-voltage NLD2 transistor is connected to the ground pin VSS; the drain of the high-voltage PLD2 transistor is connected to the drain of the high-voltage NLD2 transistor, and then connected to the low-side output pin LO.

6. The ideal diode circuit according to any one of claims 1-5 is used as the gate drive circuit for a bootstrap diode, characterized in that: The power supply circuit includes a high-side floating power supply and a low-side power supply. The input terminal of the high-side floating power supply is connected to the floating power supply pin HB, and the high-side floating power supply includes two output terminals, namely the high-side floating ground output terminal VHPD and the high-side floating power supply output terminal VHPS. The input terminal of the low-side power supply is connected to the power supply pin VDD, and the low-side power supply includes two output terminals, namely the low-side floating ground output terminal VLPD and the low-side floating power supply output terminal VLPS.

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