Chip packaging structure and electronic equipment

Abstract

The invention discloses a chip packaging structure and electronic equipment. The chip packaging structure comprises a chip, a lead frame and a packaging layer, the first surface of the chip is attached to the upper surface of the lead frame, and the chip is electrically connected with the lead frame; the packaging layer is attached to the upper surface of the lead frame, and the chip is wrapped by the packaging layer; at least part of target pins in the plurality of pins included in the lead frame extend out of the packaging layer, and the solder plating layer wraps the surfaces, extending out of the packaging layer, of the target pins. According to the invention, at least part of the target pins in the plurality of pins included in the lead frame extend out of the packaging layer, and the solder plating layer wraps the surfaces, extending out of the packaging layer, of the target pins, so that the solder plating layer can comprehensively and roundly wrap the surfaces, extending out of the packaging layer, of the target pins after SMT (Surface Mount Technology) welding. And the sharp appearance near the device side pin in the traditional packaging is avoided.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a chip packaging structure and an electronic device. Background Technology

[0002] With the rapid development of the electronics and information industry, semiconductor manufacturing processes are shrinking, leading to smaller pad sizes and new challenges to the reliability of board-level solder joints. Traditional leadless frame (QFN) packages, as surface-mount packaging structures, offer advantages such as small size, cost-effectiveness, and good production yield. However, existing QFN packages exhibit sharp morphologies near the device-side pads after SMT soldering during board-level mechanical shock and temperature cycling / shock tests. This leads to stress concentration and premature fracture at these locations, severely impacting the board-level reliability of the package. Summary of the Invention

[0003] In view of this, this application provides a chip packaging structure and an electronic device to solve the technical problem of heat dissipation in traditional chip packaging structures.

[0004] A first aspect of this application provides a chip packaging structure, comprising: a chip, a lead frame, and a packaging layer; a first surface of the chip is attached to the upper surface of the lead frame, and the chip is electrically connected to the lead frame; the packaging layer is attached to the upper surface of the lead frame, and the chip is covered by the packaging layer; at least a portion of target pins of a plurality of pins included in the lead frame extend out of the packaging layer, and a solder plating layer covers the surface of the target pins extending out of the packaging layer.

[0005] Optionally, the side of the solder plating layer is bonded to the encapsulation layer.

[0006] Optionally, the lead frame includes electrical pins and heat dissipation pins, wherein at least a portion of the electrical pins are the target pins.

[0007] Optionally, the heat dissipation pin is the target pin.

[0008] Optionally, the vertical distance between the lower surface of the target pin and the lower surface of the package layer ranges from [10um, 40um].

[0009] Optionally, the first surface of the chip is the back surface of the chip, the front surface of the chip is provided with a first pad, the lead frame is provided with an electrical pad, the first pad and the electrical pad are electrically connected by bonding wires, and the front surface and the back surface of the chip are opposite to each other.

[0010] Optionally, the first surface of the chip is the front side of the chip, and the front side of the chip is provided with a second pad, which is electrically connected to the lead frame through copper pillar bumps; the encapsulation layer covers at least a portion of the side surface and the back surface of the chip, and the front and back surfaces of the chip are opposite to each other.

[0011] Optionally, the first surface of the chip is bonded to the upper surface of the lead frame via an adhesive layer, the thickness of which is in the range of [10um, 30um].

[0012] Optionally, the lower surfaces of the target pins are in the same plane.

[0013] A second aspect of this application provides an electronic device, comprising: a chip package structure as described in any of the first aspects above.

[0014] The chip packaging structure provided in this application, by setting at least a portion of the target pins of the lead frame to extend out of the packaging layer, and the solder plating layer covering the surface of the target pins extending out of the packaging layer, allows the solder plating layer to fully and smoothly wrap the surface of the target pins extending out of the packaging layer after SMT (Surface Mount Technology) soldering, avoiding the sharp morphologies near the device-side pins in traditional packaging. The solder plating layer evenly distributes stress, avoiding the concentrated superposition of stress at sharp locations, and significantly reducing the risk of premature fracture of the solder plating layer. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0016] Figure 1 This is a schematic diagram of a chip packaging structure according to an embodiment of this application; Figure 2 This is a schematic diagram showing the soldering position of the target pin to the printed circuit board according to an embodiment of this application; Figure 3 This is a schematic diagram of a chip packaging structure according to another embodiment of this application; Figure 4 This is a schematic diagram of a chip packaging structure according to another embodiment of this application; Figure 5 This is a schematic diagram of a chip packaging structure according to another embodiment of this application; Figure 6 This is a bottom view of a chip packaging structure according to an embodiment of this application; Figure 7 This is a bottom view of a chip package structure according to another embodiment of this application; Figure 8 This is a schematic diagram of a chip packaging structure according to another embodiment of this application.

[0017] List of reference numerals in the attached diagram: Detailed Implementation

[0018] To enable those skilled in the art to better understand the technical solutions in the embodiments of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art should fall within the protection scope of the embodiments of this application.

[0019] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0020] It should be understood that although this application may use the terms first, second, third, etc., to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0021] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0022] In the semiconductor packaging field, with the rapid development of the electronics and information industry, semiconductor manufacturing processes are constantly iterating, and process dimensions are continuously shrinking. The corresponding pad sizes are also decreasing, posing a severe and complex technical challenge to the reliability of board-level solder joints. While traditional leadless frame packaging is widely used in surface mount packaging scenarios due to its advantages of small size, high cost-effectiveness, and good production yield, several core technical problems have been exposed in practical applications and reliability testing, severely limiting its technological upgrades and application expansion. For example, in traditional leadless frame packaging, the lower edge of the cupad (copper pad) and the EMC (epoxy molding compound) is designed to be flush (e.g., ...). Figure 1 (As shown). After SMT (Surface Mount Technology) soldering, the board-level solder joints near the device-side pads exhibit noticeable sharp morphologies. From a mechanical perspective, these sharp morphologies lead to a high concentration of stress in this area. When the package faces external environmental influences such as temperature changes and mechanical vibrations, the stress borne by the solder joints cannot be evenly distributed, concentrating on the sharp areas and causing premature solder joint fracture. This failure mode directly results in a significant decrease in the board-level reliability of the package, becoming a key hidden danger affecting product lifespan. Therefore, embodiments of this application provide a chip packaging structure and electronic device to at least partially solve the above-mentioned technical problems.

[0023] Figure 1 This is a schematic diagram of a chip packaging structure according to an embodiment of this application, as shown below. Figure 1 As shown, the chip package structure 1 includes a chip 11, a lead frame 12, and a package layer 13. A first surface of the chip 11 is attached to the upper surface of the lead frame 12, and the chip 11 is electrically connected to the lead frame 12. The package layer 13 is attached to the upper surface of the lead frame 12, and the chip 11 is covered by the package layer 13. At least a portion of the target pins of the plurality of pins 121 included in the lead frame 12 protrude from the package layer 13, and a solder plating layer 14 covers the surface of the target pins protruding from the package layer 13.

[0024] Therefore, in the chip package structure 1, the length of at least a portion of the target pins among the plurality of pins 121 included in the lead frame 12 can be extended, or the package layer 13 can be etched so that the lower end of the target pin extends out of the package layer 13. At this time, the surface of the target pin extending out of the package layer 13 is tin-plated so that during SMT, the surface of the target pin extending out of the package layer 13 is covered by the solder plating layer 14, such as... Figure 2 As shown, the solder plating layer 14 and the solder paste form a board-level solder joint 17. In addition to covering the lower surface of the target pin, the board-level solder joint 17 also covers the part of the side surface of the target pin that extends out of the package layer 13, thereby increasing the contact area between the board-level solder joint 17 and the target pin, and also changing the direction of the force exerted by the board-level solder joint 17 on the surface of the target pin when it is under stress.

[0025] It should be noted that, Figure 1 The chip package structure 1 shown is a standard chip package structure. The first surface of the chip 11 is the back surface of the chip 11. A first pad 111 is provided on the front surface of the chip 11, and an electrical pad 122 is provided on the lead frame 12. The first pad 111 and the electrical pad 122 are electrically connected by bonding wires 15. The front and back surfaces of the chip 11 are opposite to each other. However, the chip package structure 1 can also be a flip chip package structure, as long as at least some of the target pins of the multiple pins 121 included in the lead frame 12 extend out of the package layer 13, and the solder plating layer 14 covers the surface of the target pins extending out of the package layer 13. For example, as shown in the figure... Figure 3 As shown, the first surface of chip 11 is the front surface of chip 11. A second pad 112 is provided on the front surface of chip 11. The second pad 112 is electrically connected to the lead frame 12 through bumps 16. The bumps 16 can be copper pillar bumps or solder bumps. The encapsulation layer 13 covers at least a portion of the side surface and the back surface of chip 11, with the front and back surfaces of chip 11 facing each other.

[0026] In this embodiment, by setting at least a portion of the target pins of the multiple pins 121 included in the lead frame 12 to extend out of the package layer 13, and the solder plating layer 14 covering the surface of the target pins extending out of the package layer 13, after SMT (Surface Mount Technology) soldering, the solder plating layer 14 can fully and smoothly wrap the surface of the target pins extending out of the package layer 13, avoiding the sharp morphologies near the device-side pins in traditional packages. The solder plating layer 14 evenly disperses stress, avoiding the concentrated superposition of stress at sharp locations, and significantly reducing the risk of premature fracture of the solder plating layer 14.

[0027] Figure 4 This is a schematic diagram of a chip packaging structure according to another embodiment of this application, as shown below. Figure 4 As shown, the side of the solder plating layer 14 is bonded to the encapsulation layer 13.

[0028] In this embodiment, by setting the side of the solder plating layer 14 to be attached to the encapsulation layer 13, the stability of the chip packaging structure 1 can be further improved.

[0029] Figure 5 This is a schematic diagram of a chip packaging structure according to another embodiment of this application, as shown below. Figure 5 As shown, the lead frame 12 includes: electrical pins 1211 and heat dissipation pins 1212, at least some of the electrical pins 1211 being target pins.

[0030] Heat dissipation pin 1212 is disposed on the lower surface of heat dissipation pad 123, and chip 11 is disposed on the upper surface of heat dissipation pad 123.

[0031] In this embodiment, since the bottom area of ​​the heat dissipation pin 1212 is large, the area of ​​the solder plating layer 14 corresponding to the heat dissipation pin 1212 is large and relatively stable. Therefore, only at least some of the pins in the electrical pin 1211 can be extended out of the encapsulation layer 13, which reduces the manufacturing difficulty.

[0032] In one possible implementation, the vertical distance between the lower surface of the target pin and the lower surface of the package layer 13 ranges from [10um, 40um].

[0033] In this embodiment, the minimum controllable precision of processes such as film-assisted molding and laser / plasma etching in mass production scenarios is approximately ±2-3µm. A height setting of 10µm avoids actual protrusion height falling below the functional threshold due to process errors (e.g., with an error of -3µm, the actual height is still 7µm, close to the minimum functional requirement), ensuring consistency in mass production. If the protrusion height exceeds 40µm, two key issues arise: First, during SMT soldering, a large amount of solder is required to form the solder plating layer 14, easily leading to solder accumulation and excessively large solder joints, increasing the risk of bridging short circuits between adjacent solder plating layers 14. Second, an excessively high protrusion height may result in loose bonding between the chip package structure 1 and the PCB, creating gaps that affect heat dissipation efficiency. Furthermore, under mechanical impact, the leverage effect can increase the risk of solder plating layer 14 peeling off.

[0034] In one possible implementation, the first surface of the chip 11 is bonded to the upper surface of the lead frame 12 via an adhesive layer 20, the thickness of which is in the range of [10um, 30um].

[0035] In this embodiment, a thickness of 10-30µm ensures that the adhesive layer completely fills the tiny gap between the chip 11 and the lead frame 12, fully covering the bonding surface of the chip 11. The insulating / conductive film (containing microbubble structure) formed after heat curing forms a strong bond with the high-purity copper lead frame 12 and the surface of the chip 11, preventing the chip 11 from shifting or falling off during packaging, transportation, welding and use, and ensuring the mechanical stability of the chip packaging structure 1.

[0036] In one possible implementation, the lower surface of the target pin is in the same plane.

[0037] In this embodiment, by setting the lower surfaces of the target pins to be in the same plane, it can be ensured that the target pins extend from the package layer 13 at a consistent height, avoiding the problem of uneven mechanical stress on the solder plating layer 14 caused by uneven target pin heights. The coplanar design allows the solder plating layer 14 corresponding to all target pins to evenly distribute the external load, resulting in a more balanced stress distribution and significantly reducing the risk of package failure caused by local stress concentration.

[0038] Figure 6 This is a bottom view of a chip package structure according to an embodiment of this application, as shown below. Figure 3 and Figure 6 As shown, electrical pin 1211 within the dashed box is the target pin, meaning all electrical pins 1211 are target pins.

[0039] In this embodiment of the application, by setting all electrical pins 1211 located on the outer ring as target pins, it is easy to process, and a sufficient number of target pins can have a greater stress-relieving effect.

[0040] Figure 7 This is a bottom view of a chip package structure according to another embodiment of this application, as shown below. Figure 7 and Figure 8 As shown, the electrical pin 1211 within the dashed box is the target pin, that is, the electrical pin 1211 located in the area near the bottom four corners of the chip package structure 1 is the target pin.

[0041] According to board-level reliability test data, more than 90% of failures in traditional leadless packages are concentrated in the four corner areas. As the weak points of the package structure, the stress in the corners will increase exponentially as the package size increases, making them the highest risk areas for solder joint breakage. Furthermore, the breakage of electrical pins in the corners will directly lead to the open circuit of the core circuit, causing complete product failure. Therefore, electrical pins 1211 located near the four corners at the bottom of the chip package structure 1 can be set as target pins.

[0042] In this embodiment, by setting the electrical pins 1211 located near the four corners of the bottom of the chip package structure 1 as the target pins, the most critical failure problem is solved with the most precise design, which improves reliability and achieves the highest cost performance.

[0043] This application provides an electronic device, which includes a chip packaging structure as described in any of the foregoing embodiments. The electronic device may include one chip packaging structure or multiple chip packaging structures.

[0044] It should be noted that the electronic devices in this application are specific applications of the chip packaging structures in the foregoing embodiments in various electronic products (such as smartphones and tablets). For specific chip packaging structures in electronic devices, please refer to the description in the foregoing chip packaging structure embodiments, which will not be repeated here.

[0045] In this embodiment, the chip package structure includes a lead frame in which at least a portion of the target pins extend out of the package layer. A solder plating layer covers the surface of the target pins extending out of the package layer. After SMT (Surface Mount Technology) soldering, the solder plating layer can fully and smoothly wrap the surface of the target pins extending out of the package layer, avoiding the sharp morphologies near the device-side pins in traditional packages. The solder plating layer evenly distributes stress, avoiding stress concentration at sharp locations and significantly reducing the risk of premature solder plating fracture.

[0046] Although this application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on a reading and understanding of this specification and the accompanying drawings. This application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components, the terminology used to describe such components is intended to correspond to any component (unless otherwise indicated) that performs the specified function of said component (e.g., is functionally equivalent to it), even if structurally not equivalent to the disclosed structure performing the functions in the exemplary implementations of this specification shown herein.

[0047] That is, the above description is only an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, such as the combination of technical features between embodiments, or direct or indirect application in other related technical fields, are similarly included within the patent protection scope of this application.

[0048] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0049] The above description is provided to enable any person skilled in the art to implement and use this application. Various details are set forth in the above description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

[0050] It should be noted that, without conflict, the various embodiments and / or technical features described in this application can be arbitrarily combined with each other, and the resulting technical solutions should also fall within the protection scope of this application.

[0051] It should be understood that the specific examples in the embodiments of this application are only for the purpose of helping those skilled in the art to better understand the embodiments of this application, and are not intended to limit the scope of the embodiments of this application. Those skilled in the art can make various improvements and modifications based on the above embodiments, and all such improvements or modifications fall within the protection scope of this application.

[0052] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip packaging structure, characterized in that, include: Chip, lead frame, and packaging layer; The first surface of the chip is attached to the upper surface of the lead frame, and the chip is electrically connected to the lead frame. The encapsulation layer is attached to the upper surface of the lead frame, and the chip is encapsulated by the encapsulation layer; At least a portion of the target pins of the lead frame extend out of the package layer, and a solder plating layer covers the surface of the target pins extending out of the package layer.

2. The chip packaging structure according to claim 1, characterized in that, The side of the solder plating layer is attached to the encapsulation layer.

3. The chip packaging structure according to claim 1 or 2, characterized in that, The lead frame includes electrical pins and heat dissipation pins, wherein at least a portion of the electrical pins are the target pins.

4. The chip packaging structure according to claim 3, characterized in that, The heat dissipation pin is the target pin.

5. The chip packaging structure according to claim 1, characterized in that, The vertical distance between the lower surface of the target pin and the lower surface of the package layer ranges from [10um, 40um].

6. The chip packaging structure according to claim 1, characterized in that, The first surface of the chip is the back surface of the chip, the front surface of the chip is provided with a first pad, the lead frame is provided with an electrical pad, the first pad and the electrical pad are electrically connected by bonding wires, and the front surface and the back surface of the chip are opposite to each other.

7. The chip packaging structure according to claim 1, characterized in that, The first surface of the chip is the front surface of the chip, and a second pad is provided on the front surface of the chip. The second pad is electrically connected to the lead frame through copper pillar bumps. The encapsulation layer covers at least a portion of the side and back of the chip, with the front and back sides of the chip facing each other.

8. The chip packaging structure according to claim 1, characterized in that, The first surface of the chip is bonded to the upper surface of the lead frame via an adhesive layer, the thickness of which ranges from 10µm to 30µm.

9. The chip packaging structure according to claim 1, characterized in that, The lower surfaces of the target pins are in the same plane.

10. An electronic device, characterized in that, Includes the chip packaging structure as described in any one of claims 1-9.

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