Semiconductor packaging device, manufacturing method thereof and electronic equipment

Abstract

The invention relates to the field of semiconductors, and provides a semiconductor packaging device and a manufacturing method thereof, and electronic equipment, and the device comprises an electronic element which is fixed on the surface of a substrate; the first circuit structural member and the second circuit structural member are fixed on the surface; the first interconnection line is used for electrically connecting the input end of the electronic component and the first circuit structural component; the second interconnection line is used for electrically connecting the output end of the electronic component and the second circuit structural component; the substrate is provided with a groove group, the groove group comprises one or more grooves, the groove group comprises at least one of a first groove part and a second groove part, the first groove part is located between the electronic element and the first circuit structural member, and the second groove part is located between the electronic element and the second circuit structural member; the dielectric loss tangent value of the first groove part and the dielectric loss tangent value of the second groove part are both larger than the dielectric loss tangent value of the substrate. Therefore, the reverse isolation of the electronic component can be increased, the cost can be reduced, and the yield of the semiconductor packaging device can be improved.

Description

Technical Field

[0001] This application relates to the semiconductor field and discloses semiconductor packaging devices and their manufacturing methods, as well as electronic devices. Background Technology

[0002] For chip-packaged devices, the chip and signal transmission components are fixed on the upper surface of the substrate, and the chip is electrically connected to the substrate. When the chip operates at high frequency, the chip substrate forms a waveguide-like resonant cavity structure that couples energy in multiple propagation modes, causing the reverse isolation of the chip to deteriorate, increasing the risk of chip self-oscillation, and reducing operational stability.

[0003] To improve the reverse isolation of a chip, through-silicon via (TSV) technology can be used to create metallized vias on the chip substrate. These metallized vias are then grounded to cut off the active area of ​​the chip substrate, thereby increasing the propagation cutoff frequency and enhancing the reverse isolation. TSV technology involves vertically drilling holes in the chip substrate and filling them with conductive material. The TSV process is extremely complex, involving etching, insulating layer deposition, and electroplating, resulting in low yield and high cost.

[0004] Therefore, how to solve the above-mentioned technical problems should be a key focus for those skilled in the art. Summary of the Invention

[0005] This application discloses semiconductor packaging devices and their manufacturing methods, as well as electronic devices, to solve the technical problems of low yield and high cost caused by the complexity of fabricating through-silicon vias in chip substrates to increase reverse isolation.

[0006] In a first aspect, this application provides a semiconductor packaging device, comprising: an electronic component fixed to the surface of a substrate and electrically connected to the substrate via the surface; a first circuit structure and a second circuit structure fixed to the surface, the first circuit structure being used to transmit an input signal to the electronic component, and the second circuit structure being used to receive an output signal from the electronic component; a first interconnect and a second interconnect, the first interconnect being used to electrically connect an input terminal of the electronic component and the first circuit structure, and the second interconnect being used to electrically connect an output terminal of the electronic component and the second circuit structure; the substrate having a set of recesses, the set of recesses including one or more recesses extending from the surface toward the substrate in a direction away from the electronic component, the set of recesses including at least one of a first recess portion and a second recess portion, the first recess portion being located between the electronic component and the first circuit structure, and the second recess portion being located between the electronic component and the second circuit structure; the dielectric loss tangent of the first recess portion and the dielectric loss tangent of the second recess portion are both greater than the dielectric loss tangent of the substrate.

[0007] The semiconductor packaging device in this embodiment includes a substrate, electronic components, a first circuit structure and a second circuit structure fixed on the surface of the substrate, a first interconnect and a second interconnect. The electronic components, the first circuit structure and the second circuit structure are all fixed on the surface of the substrate. The input terminal of the electronic component is electrically connected to the circuit structure through the first interconnect, and the output terminal is electrically connected to the circuit structure through the second interconnect. The substrate has a groove group, which includes one or more grooves. The one or more grooves extend from the surface of the substrate in a direction away from the electronic components. The groove group includes at least one of a first groove portion and a second groove portion. The first groove portion is located between the electronic component and the first circuit structure, and the second groove portion is located between the electronic component and the second circuit structure. The dielectric loss tangent of the first groove portion and the dielectric loss tangent of the second groove portion are both greater than the dielectric loss tangent of the substrate. In this case, when the electrical signal is transmitted in the substrate, since the groove group includes at least one of the first groove portion and the second groove portion, and the dielectric loss tangent of the first groove portion and the dielectric loss tangent of the second groove portion are both greater than the dielectric loss tangent of the substrate, the electrical signal will be more easily dissipated in the first groove portion and / or the second groove portion, thereby increasing the reverse isolation of the electronic components; and the method of forming groove groups on the substrate is simple and mature, which helps to reduce costs and improve the yield of semiconductor packaging devices.

[0008] In one possible implementation, the groove group includes a first groove portion and a second groove portion. Thus, the groove group includes a first groove portion and a second groove portion. When an electrical signal is transmitted in the substrate, since the groove group includes a first groove portion and a second groove portion, and the dielectric loss tangent values ​​of both the first and second groove portions are greater than the dielectric loss tangent value of the substrate, the electrical signal will dissipate in the first and second groove portions. This helps to improve the dissipation degree of the electrical signal, thereby further increasing the reverse isolation of the electronic components.

[0009] In one possible implementation, the groove group includes a plurality of grooves, the plurality of grooves including a first groove portion and a second groove portion.

[0010] In this embodiment, the groove group is configured to include multiple grooves, and the multiple grooves include a first groove portion and a second groove portion. That is, the first groove portion corresponds to one groove, and the second groove portion corresponds to another groove. This enables the partial opening of grooves between electronic components and the first circuit structure, as well as the partial opening of grooves between electronic components and the second circuit structure, reducing the grooving process of the substrate and helping to reduce the impact of opening grooves on the mechanical properties of the substrate.

[0011] In one possible implementation, the plurality of grooves are two grooves, the two grooves being a first groove portion and a second groove portion, respectively.

[0012] In this embodiment, the substrate has two grooves, namely a first groove and a second groove. The grooves are only provided between the electronic components and the first circuit structure and between the electronic components and the second circuit structure. This can further reduce the grooving process of the substrate and help to further reduce the impact of the grooves on the mechanical properties of the substrate.

[0013] In one possible implementation, the groove assembly includes a groove surrounding the electronic component, and the groove includes a first groove portion and a second groove portion.

[0014] In this embodiment, a groove is provided around the electronic component, and this groove includes a first groove portion and a second groove portion. This satisfies the requirement of increasing the reverse isolation of the electronic component, and the groove can be made by only one cutting process, which can reduce the manufacturing difficulty.

[0015] In one possible implementation, it further includes: one or more fillers corresponding one-to-one with the one or more grooves, each filler being located in the corresponding groove, and the dielectric loss tangent of each filler being greater than the dielectric loss tangent of the substrate.

[0016] In this embodiment, a filler with a high dielectric loss tangent is provided in the groove to increase the reverse isolation of electronic components.

[0017] In one possible implementation, each filler is made of an absorbing material. Thus, by including an absorbing material in the filler, electrical signals are more easily dissipated within the filler, thereby further increasing the reverse isolation of electronic components. Furthermore, filling with a solid material like the absorbing material can improve the mechanical properties of the substrate, reduce the probability of damage to the substrate under external forces, and extend the lifespan of the semiconductor packaged device.

[0018] In one possible implementation, the microwave absorbing material includes at least one of graphene, graphite, carbon black, carbon fiber, carbon nanotubes, and ferrite. Thus, graphene, graphite, carbon black, carbon fiber, carbon nanotubes, and ferrite are all readily available or purchasable materials. Including at least one of these materials in the microwave absorbing material not only improves the mechanical properties of the substrate but also shortens the time required to prepare or purchase the microwave absorbing material, thereby increasing the manufacturing efficiency of semiconductor packaging devices.

[0019] In one possible implementation, the material of each filler also includes a carrier material. Thus, the material of each filler includes an absorbing material and a carrier material. The absorbing material helps dissipate electrical signals, and the carrier material can provide rigid support, thereby further increasing the reverse isolation of electronic components while enhancing the performance of the rigid support and further improving the mechanical properties of the substrate.

[0020] In one possible implementation, the first interconnect is connected to the input terminal by gold wire bonding or bridging; and / or, the second interconnect is connected to the output terminal by gold wire bonding or bridging.

[0021] In this embodiment, the gold wire bonding method uses gold wire, which has low resistivity, good conductivity, and is not easily oxidized, thus improving the reliability of long-term connections. The bridge bonding method uses flat copper strips as connecting wires. The flat strip structure has a larger cross-sectional area and a smaller skin effect, thus significantly reducing resistance and inductance, which can reduce power loss and signal distortion.

[0022] In one possible implementation, the projection of the first interconnect on the substrate at least partially overlaps with the first recess; and / or, the projection of the second interconnect on the substrate at least partially overlaps with the second recess.

[0023] In this embodiment, at least a portion of the first interconnects has a first groove directly below it, and at least a portion of the second interconnects has a second groove directly below it. The first groove and the second groove can cut off the coupling energy ground plane, reduce energy coupling, and thus further improve the reverse isolation.

[0024] In one possible implementation, the length of the first groove in a first direction is greater than or equal to the length of the projection of the first interconnect line onto the substrate in the first direction, wherein the first direction is the direction of the perpendicular line of the line connecting the connection point of the first interconnect line at the first circuit structure and the input terminal; and / or, the length of the second groove in a second direction is greater than or equal to the length of the projection of the second interconnect line onto the substrate in the second direction, wherein the second direction is the direction of the perpendicular line of the line connecting the connection point of the second interconnect line at the second circuit structure and the output terminal.

[0025] In this embodiment, the length of the projection of the first interconnect on the substrate in the first direction is less than or equal to the length of the first groove in the first direction. The first direction is the direction perpendicular to the line connecting the connection point of the first interconnect to the input terminal of the first circuit structure. Therefore, the first groove is located directly below the first interconnect, which can further reduce the reverse coupling of the first interconnect to the signal and improve the directional isolation of the electronic component. The length of the projection of the second interconnect on the substrate in the second direction is less than or equal to the length of the second groove in the second direction. The second direction is the direction perpendicular to the line connecting the connection point of the second interconnect to the output terminal of the second circuit structure. Therefore, the second groove is located directly below the second interconnect, which can further reduce the reverse coupling of the second interconnect to the signal and improve the directional isolation of the electronic component.

[0026] In one possible implementation, at least one of the grooves is parallel to at least a pair of opposing edges of its projection onto the surface.

[0027] This embodiment can reduce the difficulty of manufacturing the groove and reduce the manufacturing cost.

[0028] In one possible implementation, the projection is a parallelogram.

[0029] In this embodiment, the groove can be rectangular in shape, making the manufacturing process the simplest.

[0030] In one possible implementation, the substrate is a conductive substrate.

[0031] In this embodiment, the substrate is set as a conductive substrate, which can ground the electronic components, the first circuit structure and the second circuit structure, and shield the interference of external electromagnetic fields on the electronic components, the first circuit structure and the second circuit structure.

[0032] In one possible implementation, the projection of the first interconnect line on the substrate is located within the range of the first recess; and / or, the projection of the second interconnect line on the substrate is located within the range of the second recess.

[0033] In this embodiment, the projection of the first interconnect on the substrate is located within the range of the first groove portion; and / or, the projection of the second interconnect on the substrate is located within the range of the second groove portion, which can minimize energy coupling and improve reverse isolation.

[0034] In one possible implementation, the groove assembly is formed by CNC machine tool processing.

[0035] The CNC machine tool processing method used in this embodiment has a simple manufacturing process and can reduce costs.

[0036] Secondly, this application provides a method for manufacturing a semiconductor packaged device, comprising: A groove group is formed on a substrate, the groove group including one or more grooves, the one or more grooves extending from the surface of the substrate toward the interior of the substrate, the groove group including at least one of a first groove portion and a second groove portion, the dielectric loss tangent of the first groove portion and the dielectric loss tangent of the second groove portion are both greater than the dielectric loss tangent of the substrate. Electronic components are fixed on the surface and electrically connected to the substrate through the surface; A first circuit structure and a second circuit structure are fixed on the surface. The first circuit structure is used to transmit input signals to the electronic component, and the second circuit structure is used to receive output signals from the electronic component. The first groove is located between the electronic component and the first circuit structure, and the second groove is located between the electronic component and the second circuit structure. A first interconnect is electrically connected between the input terminal of the electronic component and the first circuit structure, and a second interconnect is electrically connected between the output terminal of the electronic component and the second circuit structure.

[0037] The semiconductor packaged device manufactured in this embodiment includes a substrate, electronic components fixed on the surface of the substrate, a first circuit structure and a second circuit structure, a first interconnect and a second interconnect; the input terminal of the electronic component is electrically connected to the circuit structure through the first interconnect, and the output terminal is electrically connected to the circuit structure through the second interconnect; the substrate has a groove group, the groove group includes one or more grooves, the one or more grooves extend from the surface of the substrate in a direction away from the electronic component, the groove group includes at least one of a first groove portion and a second groove portion, the first groove portion is located between the electronic component and the first circuit structure, the second groove portion is located between the electronic component and the second circuit structure, and the dielectric loss tangent of the first groove portion and the dielectric loss tangent of the second groove portion are both greater than the dielectric loss tangent of the substrate. In this case, when the electrical signal is transmitted in the substrate, since the groove group includes at least one of the first groove portion and the second groove portion, and the dielectric loss tangent of the first groove portion and the dielectric loss tangent of the second groove portion are both greater than the dielectric loss tangent of the substrate, the electrical signal will be more easily dissipated in the first groove portion and / or the second groove portion, thereby increasing the reverse isolation of the electronic components; and the method of forming groove groups on the substrate is simple and mature, which helps to reduce costs and improve the yield of semiconductor packaging devices.

[0038] Thirdly, this application provides an electronic device, including: any of the semiconductor packaged devices described above. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 A schematic cross-section of a semiconductor packaging device provided in an embodiment of this application. Figure 1 ; Figure 2 A top view of a semiconductor packaging device provided in an embodiment of this application. Figure 1 ; Figure 3 A top view of a semiconductor packaging device provided in an embodiment of this application. Figure 2 ; Figure 4 A schematic cross-section of a semiconductor packaging device provided in an embodiment of this application. Figure 2 .

[0041] Explanation of reference numerals in the attached figures: 10-Semiconductor package device; 101-Substrate; 1011-Groove assembly; 10111-Groove; 10112-First groove portion; 10113-Second groove portion; 102-First circuit structure; 103-Electronic component; 104-Second circuit structure; 105-Fill; 106-First interconnect; 107-Second interconnect. Detailed Implementation

[0042] This application provides an electronic device, which includes a semiconductor packaged device. This embodiment does not limit the type of electronic device; for example, the electronic device can be a smartphone, tablet computer, laptop computer, in-vehicle computer, smartwatch, or smart bracelet, etc.

[0043] Example 1

[0044] This embodiment provides a semiconductor packaged device 10. Please refer to [reference needed]. Figure 1 and Figure 2 The semiconductor package device 10 includes: an electronic component 103, a first circuit structure 102 and a second circuit structure 104, a first interconnect 106 and a second interconnect 107. The semiconductor package device 10 may also include a substrate 101.

[0045] Electronic component 103 is fixed to the surface of substrate 101 and electrically connected to substrate 101 via the surface.

[0046] The first circuit structure 102 and the second circuit structure 104 are fixed on the surface. The electronic component 103 is located between the first circuit structure 102 and the second circuit structure 104. The first circuit structure 102 is used to transmit input signals to the electronic component 103, and the second circuit structure 104 is used to receive output signals from the electronic component 103.

[0047] It should be understood that the positions of the first circuit structure 102 and the second circuit structure 104 are related to the positions of the input terminal and the output terminal of the electronic component 103. For example, as Figure 1 and Figure 2 As shown, the input terminal and the output terminal of electronic component 103 are located on opposite sides of the upper surface of electronic component 103, respectively. In this case, electronic component 103 is located between the first circuit structure 102 and the second circuit structure 104. Alternatively, if the input terminal and the output terminal of electronic component 103 are on the same side of the upper surface of electronic component 103, the first circuit structure 102 and the second circuit structure 104 can be arranged in the same direction relative to that side.

[0048] The first interconnect line 106 is used to electrically connect the input terminal of the electronic component 103 and the first circuit structure 102, and the second interconnect line 107 is used to electrically connect the output terminal of the electronic component 103 and the second circuit structure 104.

[0049] The substrate 101 has a groove group 1011, which includes one or more grooves 10111. The one or more grooves 10111 extend from the surface of the substrate 101 in a direction away from the electronic component 103. The groove group 1011 includes at least one of a first groove portion 10112 and a second groove portion 10113. The first groove portion 10112 is located between the electronic component 103 and the first circuit structure 102. The second groove portion 10113 is located between the electronic component 103 and the second circuit structure 104. The dielectric loss tangent of the first groove portion 10112 and the dielectric loss tangent of the second groove portion 10113 are both greater than the dielectric loss tangent of the substrate 101.

[0050] It should be understood that the dielectric loss tangent is a physical quantity that characterizes the magnitude of dielectric loss of a dielectric material after an electric field is applied. For example, the dielectric loss tangent can be represented by tanδ, where δ represents the dielectric loss angle. That is, the dielectric loss tangent of the first groove 10112 and the dielectric loss tangent of the second groove 10113 are both greater than the dielectric loss tangent of the substrate 101, meaning that the dissipation of the electrical signal in the first groove 10112 and the second groove 10113 is greater than the dissipation of the electrical signal in the substrate 101.

[0051] Thus, the semiconductor package device includes a substrate 101, an electronic component 103, a first circuit structure 102 and a second circuit structure 104 fixed on the surface of the substrate 101, a first interconnect and a second interconnect; the input terminal of the electronic component 103 is electrically connected to the circuit structure through the first interconnect, and the output terminal is electrically connected to the circuit structure through the second interconnect; the substrate 101 has a groove group 1011, the groove group 1011 includes one or more grooves, the one or more grooves extend from the surface of the substrate 101 in a direction away from the electronic component 103, the groove group 1011 includes at least one of a first groove portion 10112 and a second groove portion 10113, the first groove portion 10112 is located between the electronic component 103 and the first circuit structure 102, the second groove portion 10113 is located between the electronic component 103 and the second circuit structure 104, and the dielectric loss tangent of the first groove portion 10112 and the dielectric loss tangent of the second groove portion 10113 are both greater than the dielectric loss tangent of the substrate 101. In this case, when the electrical signal is transmitted in the substrate 101, since the groove group 1011 includes at least one of the first groove portion 10112 and the second groove portion 10113, and the dielectric loss tangent of the first groove portion 10112 and the dielectric loss tangent of the second groove portion 10113 are both greater than the dielectric loss tangent of the substrate 101, the electrical signal will be more easily dissipated in the first groove portion 10112 and / or the second groove portion 10113, thereby increasing the reverse isolation of the electronic component 103; and the method of forming the groove group 1011 on the substrate 101 is simple and mature, which helps to reduce costs and improve the yield of semiconductor packaging devices.

[0052] The type of substrate 101 is not limited in this application and can be set arbitrarily. For example, substrate 101 is a conductive substrate. Exemplarily, substrate 101 includes, but is not limited to, any one of the following: copper alloy substrate, aluminum alloy substrate, Kovar alloy substrate, ferrite material substrate, magnetic loss absorbing material substrate, and ceramic package shell. The ceramic package shell includes a ceramic sheet and a metal layer on the surface of the ceramic sheet. In this embodiment, substrate 101 is set as a conductive substrate, which allows the electronic component 103, the first circuit structure 102, and the second circuit structure 104 to be grounded, thus shielding them from interference from external electromagnetic fields. Electronic component 103 is electrically connected to substrate 101. First circuit structure 102 and second circuit structure 104 are electrically connected to substrate 101 respectively. Substrate 101 is a conductive substrate that grounds electronic component 103, first circuit structure 102 and second circuit structure 104, and provides mechanical support for electronic component 103, first circuit structure 102 and second circuit structure 104.

[0053] Electronic component 103 is provided with an input terminal and an output terminal. Electrical signals enter electronic component 103 through the input terminal and exit electronic component 103 through the output terminal. In some embodiments, electronic component 103 can be a passive device, an RF amplifier chip, or a mixer, etc. For example, a passive device can be a thin-film circuit or a micro-coaxial device; another example is that the RF amplifier chip can be a millimeter-wave power amplifier chip; yet another example is that the RF amplifier chip can be a low-noise amplifier (LNA), a power amplifier (PA), a driver amplifier, a variable gain amplifier, etc.

[0054] Thin-film circuits are integrated circuits fabricated by depositing conductive metal materials on a dielectric substrate using thin-film processes such as vacuum evaporation and cathode sputtering. They have a metal-dielectric-metal structure. The dielectric substrate can be a glass substrate or a ceramic substrate.

[0055] The input terminal of electronic component 103 is connected to the first circuit structure 102, and the output terminal of electronic component 103 is connected to the second circuit structure 104. The electrical signal enters electronic component 103 through the first circuit structure 102, flows through electronic component 103, and then enters the second circuit structure 104 through the output terminal of electronic component 103.

[0056] The circuit structure (including the first circuit structure 102 and the second circuit structure 104) serves to transmit electrical signals. It should be noted that the type of circuit structure is not limited in this application and can be set by the user.

[0057] The first circuit component 102 and the second circuit component 104 can be components with at least one function of attenuation, filtering, and impedance matching. As one possible implementation, the first circuit component 102 and the second circuit component 104 can be either a thin-film circuit or a PCB (Printed Circuit Board). For example, both the first circuit component 102 and the second circuit component 104 can be thin-film circuits. Because thin-film circuits have a flat, sheet-like structure, they have a larger cross-sectional area and a smaller skin effect, thus significantly reducing resistance and inductance, and reducing power loss and signal distortion.

[0058] In the semiconductor package device 10, there is also a situation where the electrical signal is transmitted in the substrate 101. In this embodiment, by providing a groove 10111 on the substrate 101, the high-frequency (e.g., frequency above 3MHz) electrical signal can be reflected in the groove 10111 and dissipated, thereby increasing the reverse isolation of the electronic component 103.

[0059] It should be understood that the groove group 1011 of the substrate refers to the groove formed by the substrate material itself.

[0060] The depth of the groove 10111 on the substrate 101 is not limited in this application and can be set by the user. The deeper the groove 10111, the better the dissipation effect of the electrical signal in the groove 10111, which helps to further increase the reverse isolation of the electronic component 103.

[0061] It should be noted that the method of manufacturing the groove group 1011 is not limited in this application, as long as the groove group 1011 can be formed on the substrate.

[0062] In one embodiment of this application, the groove group 1011 is formed by CNC machine tool processing. CNC machine tool processing is simple and can reduce costs.

[0063] In one possible implementation, the groove assembly 1011 includes a first groove portion 10112 and a second groove portion 10113. Thus, when an electrical signal is transmitted in the substrate 101, because the groove assembly 1011 includes the first groove portion 10112 and the second groove portion 10113, and the dielectric loss tangent of the first groove portion 10112 and the dielectric loss tangent of the second groove portion 10113 are both greater than the dielectric loss tangent of the substrate 101, the electrical signal will dissipate in the first groove portion 10112 and the second groove portion 10113. This helps to improve the degree of electrical signal dissipation, thereby further increasing the reverse isolation of the electronic component 103.

[0064] In one possible implementation, the groove assembly 1011 includes a plurality of grooves 10111, each groove 10111 including a first groove portion 10112 and a second groove portion 10113. The first groove portion 10112 and the second groove portion 10113 each constitute a groove 10111. For example, the plurality of grooves 10111 may also include a third groove portion, which can connect the first groove portion 10112 and the second groove portion 10113.

[0065] In this embodiment, the groove group 1011 is configured to include a plurality of grooves 10111, and the plurality of grooves 10111 includes a first groove portion 10112 and a second groove portion 10113. That is, the first groove portion 10112 corresponds to one groove 10111, and the second groove portion 10113 corresponds to another groove 10111. This allows for the partial opening of grooves 10111 between the electronic component 103 and the first circuit structure 102, as well as between the electronic component 103 and the second circuit structure 104. This reduces the grooving process on the substrate 101 and helps to reduce the impact of the grooves on the mechanical properties of the substrate 101.

[0066] It should be noted that the number of grooves 10111 is not limited in this application and can be set by the user.

[0067] like Figure 2 As shown, in one possible implementation, the plurality of grooves 10111 are divided into two grooves 10111, which are respectively the first groove portion 10112 and the second groove portion 10113. In this embodiment, the groove group 1011 of the substrate 101 consists of two grooves 10111, which are respectively the first groove portion 10112 and the second groove portion 10113. That is, the grooves 10111 are only provided between the electronic component 103 and the first circuit structure 102, and between the electronic component 103 and the second circuit structure 104. This can further reduce the grooving process of the substrate 101 and help to further reduce the impact of grooving on the mechanical properties of the substrate 101.

[0068] like Figure 3 As shown, in one possible implementation, the groove assembly 1011 includes a groove 10111 surrounding the electronic component 103. The groove 10111 includes a first groove portion 10112 and a second groove portion 10113.

[0069] A groove 10111 is provided around the electronic component 103. When cutting and making the groove 10111, only one cutting process is required to make the groove 10111, which can reduce the manufacturing difficulty.

[0070] It should be noted that this application does not limit the connection method between the first interconnect line 106 and the second interconnect line and the electronic component 103.

[0071] As one possible implementation, the first interconnect 106 is connected to the input terminal of the electronic component 103 by gold wire bonding or bridge soldering.

[0072] It can be understood that when one end of the first interconnect 106 is connected to the input terminal of the electronic component 103 by gold wire bonding, the other end of the first interconnect 106 is also connected to the circuit structure by gold wire bonding; when one end of the first interconnect 106 is connected to the input terminal of the electronic component 103 by bridge soldering, the other end of the first interconnect 106 is also connected to the circuit structure by bridge soldering.

[0073] As another possible implementation, the second interconnect 107 is connected to the output terminal of the electronic component 103 by gold wire bonding or bridge soldering.

[0074] It can be understood that when one end of the second interconnect 107 is connected to the output terminal of the electronic component 103 by gold wire bonding, the other end of the second interconnect 107 is also connected to the circuit structure by gold wire bonding; when one end of the second interconnect 107 is connected to the output terminal of the electronic component 103 by bridge soldering, the other end of the second interconnect 107 is also connected to the circuit structure by bridge soldering.

[0075] Gold wire bonding uses gold wire, which has low resistivity, good conductivity, and is not easily oxidized, thus improving the reliability of long-term connections.

[0076] Bridge soldering uses flat copper strips as connecting lines. The flat strip structure has a larger cross-sectional area and a smaller skin effect, thus significantly reducing resistance and inductance, which can reduce power loss and signal distortion.

[0077] In this embodiment, the semiconductor package device 10 can be an active device or a passive device. The active device includes, but is not limited to, any one of a low-noise amplifier, a power amplifier, a drive amplifier, a variable gain amplifier, and a mixer. The passive device can be a thin-film circuit or a micro coaxial device, etc.

[0078] Example 2

[0079] Based on the above embodiments, this embodiment provides a semiconductor packaging device 10, such as... Figure 4 As shown, it also includes: one or more fillers 105, corresponding one-to-one with one or more grooves 10111, each filler 105 being located in the corresponding groove 10111, and the dielectric loss tangent of each filler 105 being greater than the dielectric loss tangent of the substrate 101. For example, the filler 105 can be air.

[0080] Thus, by providing a filler 105 with a high dielectric loss tangent in the groove 10111, the reverse isolation of the electronic component 103 can be increased.

[0081] Because the substrate 101 has a groove 10111 extending from the surface of the substrate 101 in a direction away from the electronic component 103, the substrate 101 is prone to breakage or other damage at the location of the groove 10111 when subjected to external force. In this embodiment, a filler 105 with a high dielectric loss tangent is provided in the groove 10111, which can increase the reverse isolation of the electronic component 103.

[0082] As some implementations, the material of each filler 105 may include a microwave absorbing material. For example, the material of each filler 105 may include a combination of air and a microwave absorbing material.

[0083] It should be understood that microwave absorbing materials refer to a class of materials that can absorb or significantly reduce the electromagnetic wave energy received on their surface, thereby reducing electromagnetic wave interference.

[0084] Thus, the filler 105 is made of absorbing material, which makes it easier for electrical signals to dissipate in the filler 105, thereby further increasing the reverse isolation of the electronic component 103. In addition, the filling material, which is a solid material, can improve the mechanical properties of the substrate 101, reduce the probability of damage to the substrate 101 under external force, and improve the service life of the semiconductor packaged device.

[0085] As some implementation methods, the microwave absorbing material may include at least one of graphene, graphite, carbon black, carbon fiber, carbon nanotubes, and ferrite, and is not exhaustive. Thus, graphene, graphite, carbon black, carbon fiber, carbon nanotubes, and ferrite are all materials that are easy to prepare or purchase. Including at least one of these materials in the microwave absorbing material can not only improve the mechanical properties of the substrate 101, but also shorten the time for preparing or purchasing the microwave absorbing material and improve the manufacturing efficiency of semiconductor packaging devices.

[0086] In some implementations, the material of each filler 105 includes a microwave absorbing material and a carrier material. For example, the carrier material includes insulating adhesive or resin. For example, each filler 105 is obtained by mixing the microwave absorbing material with the carrier material. For example, the three-dimensional structure of each filler 105 can be adapted to the corresponding groove 10111 by a processing method such as injection molding.

[0087] Thus, the material of each filler 105 includes absorbing material and carrier material. The absorbing material helps dissipate electrical signals, and the carrier material can provide rigid support. This further increases the reverse isolation of electronic components 103, enhances the performance of rigid support, and further improves the mechanical properties of substrate 101.

[0088] Example 3

[0089] Based on the above embodiments, this embodiment provides a semiconductor package device 10, wherein the projection of the first interconnect 106 on the substrate 101 at least partially overlaps with the first recess 10112; and / or, the projection of the second interconnect 107 on the substrate 101 at least partially overlaps with the second recess 10113. For example, they may completely overlap.

[0090] The first interconnect 106 between the input terminal of electronic component 103 and the first circuit structure 102, and the second interconnect 107 between the output terminal of electronic component 103 and the second circuit structure 104, can induce directional coupling of electrical signals, causing a change in the reference ground plane of the output signal. The projection of the first interconnect 106 on the substrate 101 at least partially overlaps with the first recess 10112, that is, at least a portion of the first interconnect 106 is directly below the first recess 10112. The projection of the second interconnect 107 on the substrate 101 at least partially overlaps with the second recess 10113, that is, at least a portion of the second interconnect 107 is directly below the second recess 10113. The first recess 10112 and the second recess 10113 can cut off the coupling energy ground plane, reduce energy coupling, and thereby further improve the reverse isolation.

[0091] In this application, the relationship between the projections of the first interconnect line 106 and the second interconnect line 107 on the substrate 101 and the first groove portion 10112 and the second groove portion 10113 is not limited and can be set by the user.

[0092] In one possible implementation, the length of the first recess 10112 in the first direction is greater than or equal to the length of the projection of the first interconnect 106 onto the substrate 101 in the first direction, where the first direction is the direction perpendicular to the line connecting the connection point of the first interconnect 106 to the input terminal of the electronic component 103; and / or, the length of the second recess 10113 in the second direction is greater than or equal to the length of the projection of the second interconnect 107 onto the substrate in the second direction, where the second direction is the direction perpendicular to the line connecting the connection point of the second interconnect 107 to the output terminal of the electronic component 103.

[0093] The projection of the first interconnect 106 onto the substrate 101 has a length in a first direction that is less than or equal to the length of the first recess 10112 in the first direction. The first direction is the direction perpendicular to the line connecting the connection point of the first interconnect 106 to the input terminal of the first circuit structure 102. Consequently, the first recess 10112 is located directly below the first interconnect 106, thereby further reducing the reverse coupling of the first interconnect 106 to the signal and improving the directional isolation of the electronic component 103. Similarly, the projection of the second interconnect 107 onto the substrate 101 has a length in a second direction that is less than or equal to the length of the second recess 10113 in the second direction. The second direction is the direction perpendicular to the line connecting the connection point of the second interconnect 107 to the output terminal of the second circuit structure 104. Consequently, the second recess 10113 is located directly below the second interconnect 107, thereby further reducing the reverse coupling of the second interconnect 107 to the signal and improving the directional isolation of the electronic component 103.

[0094] like Figure 2 As shown, under certain circumstances, the first direction can be the same as the second direction, denoted as the Y direction.

[0095] For example, in specific cases: the projection of the side of the first circuit structure 102 relative to the electronic component 103 on the substrate 101 is parallel to the projection of the side of the electronic component 103 relative to the first circuit structure 102 on the substrate 101; the projection of the side of the second circuit structure 104 relative to the electronic component 103 on the substrate 101 is parallel to the projection of the side of the electronic component 103 relative to the second circuit structure 104 on the substrate 101; and the projection of the side of the electronic component 103 relative to the first circuit structure 102 on the substrate 101 is parallel to the projection of the side of the electronic component 103 relative to the second circuit structure 104 on the substrate 101.

[0096] The shape of the groove 10111 is not limited in this application and can be set by the user.

[0097] like Figure 2 As shown, in one possible implementation, at least a pair of opposite sides of the projection of at least one groove 10111 onto the surface are parallel, that is, the grooves have a structure of equal width in one direction, which can reduce the manufacturing difficulty of the groove 10111 and reduce the manufacturing cost.

[0098] In one embodiment of this application, at least one of the grooves 10111 is projected onto the surface as a parallelogram. In this case, the shape of the groove 10111 can be rectangular, which simplifies the manufacturing process.

[0099] When the first direction and the second direction are the same, as another possible implementation, the width W of the groove 10111 in the third direction X gradually changes along the first direction Y. For example, the width of the groove 10111 in the third direction X gradually decreases along the first direction Y, or the width W of the groove 10111 in the third direction X gradually increases along the first direction Y.

[0100] In this application, the length of the groove 10111 in the first direction Y is not limited and can be set by the user.

[0101] When the first direction and the second direction are the same, as an implementation method, the length L of the groove 10111 in the first direction Y is equal at all points in the third direction X. That is, the groove 10111 has a structure with equal length in the third direction X, which can reduce the manufacturing difficulty of the groove 10111 and reduce the manufacturing cost.

[0102] When the first direction and the second direction are the same, as another possible implementation, the length L of the groove 10111 in the first direction Y gradually changes along the third direction X. For example, the length L of the groove 10111 in the first direction Y gradually increases along the third direction X, or the length L of the groove 10111 in the first direction Y gradually decreases along the third direction X. The thickness direction of the semiconductor device is denoted as the Z direction.

[0103] As one possible implementation, the projection of the first interconnect 106 on the substrate 101 is located within the range of the first recess 10112; and / or, the projection of the second interconnect 107 on the substrate 101 is located within the range of the second recess 10113, which can minimize energy coupling and improve reverse isolation.

[0104] Example 4

[0105] This embodiment provides a method for manufacturing a semiconductor packaged device, including steps S101 to S104.

[0106] Step S101: A groove group is formed on the substrate. The groove group includes one or more grooves that extend from the surface of the substrate toward the interior of the substrate. The groove group includes at least one of a first groove portion and a second groove portion. The dielectric loss tangent of the first groove portion and the dielectric loss tangent of the second groove portion are both greater than the dielectric loss tangent of the substrate.

[0107] Step S102: Fix the electronic components on the surface of the substrate and electrically connect them to the substrate through the surface of the substrate.

[0108] Step S103: Fix the first circuit structure and the second circuit structure to the surface of the substrate. The first circuit structure is used to transmit input signals to the electronic components, and the second circuit structure is used to receive output signals from the electronic components. The first groove is located between the electronic components and the first circuit structure, and the second groove is located between the electronic components and the second circuit structure.

[0109] It should be understood that the positions of the first and second circuit components are related to the positions of the input and output terminals of the electronic component. For example, if the input and output terminals of the electronic component are located on opposite sides of the upper surface of the electronic component, the electronic component is positioned between the first and second circuit components. Alternatively, if the input and output terminals of the electronic component are on the same side of the upper surface of the electronic component, the first and second circuit components can be positioned opposite each other on that side.

[0110] Step S104: Electrically connect a first interconnecting line between the input terminal of the electronic component and the first circuit structure, and electrically connect a second interconnecting line between the output terminal of the electronic component and the second circuit structure.

[0111] The semiconductor packaged device manufactured in this embodiment includes a substrate, electronic components fixed on the surface of the substrate, a first circuit structure and a second circuit structure, a first interconnect and a second interconnect; the input terminal of the electronic component is electrically connected to the circuit structure through the first interconnect, and the output terminal is electrically connected to the circuit structure through the second interconnect; the substrate has a groove group, the groove group includes one or more grooves, the one or more grooves extend from the surface of the substrate in a direction away from the electronic component, the groove group includes at least one of a first groove portion and a second groove portion, the first groove portion is located between the electronic component and the first circuit structure, the second groove portion is located between the electronic component and the second circuit structure, and the dielectric loss tangent of the first groove portion and the dielectric loss tangent of the second groove portion are both greater than the dielectric loss tangent of the substrate. In this case, when the electrical signal is transmitted in the substrate, since the groove group includes at least one of the first groove portion and the second groove portion, and the dielectric loss tangent of the first groove portion and the dielectric loss tangent of the second groove portion are both greater than the dielectric loss tangent of the substrate, the electrical signal will be more easily dissipated in the first groove portion and / or the second groove portion, thereby increasing the reverse isolation of the electronic components; and the method of forming groove groups on the substrate is simple and mature, which helps to reduce costs and improve the yield of semiconductor packaging devices.

[0112] In one embodiment of this application, the groove group is formed by CNC machine tool processing, which is a simple manufacturing process.

[0113] It should be noted that this application does not limit the arrangement of the groove group.

[0114] In one possible implementation, the groove assembly includes a first groove portion and a second groove portion. Thus, when an electrical signal is transmitted in the substrate, because the groove assembly includes both the first and second groove portions, and the dielectric loss tangents of both the first and second groove portions are greater than the dielectric loss tangent of the substrate, the electrical signal will dissipate in the first and second groove portions. This helps to improve the dissipation of the electrical signal, thereby further increasing the reverse isolation of the electronic components.

[0115] As one possible implementation, the groove group includes multiple grooves, each groove including a first groove portion and a second groove portion, and the first groove portion corresponds to one groove, and the second groove portion corresponds to another groove. This allows for the partial opening of grooves between electronic components and first circuit structural components, as well as between electronic components and second circuit structural components, reducing the need for grooving the substrate and helping to reduce the impact of groove opening on the mechanical properties of the substrate.

[0116] In one embodiment of this application, the plurality of grooves are two grooves, namely a first groove portion and a second groove portion. In this embodiment, the groove group of the substrate is two grooves, namely a first groove portion and a second groove portion, that is, the groove portions are only provided between the electronic components and the first circuit structure and between the electronic components and the second circuit structure, which can further reduce the grooving process of the substrate and help to further reduce the impact of grooving on the mechanical properties of the substrate.

[0117] As another possible implementation, the groove assembly includes a groove surrounding the electronic component, and the groove includes a first groove portion and a second groove portion. By providing a ring of grooves around the electronic component, including a first groove portion and a second groove portion, the groove can be created with only one subsequent cutting process while simultaneously increasing the reverse isolation of the electronic component, thus reducing manufacturing difficulty.

[0118] In one embodiment of this application, the method for manufacturing a semiconductor packaged device may further include: One or more fillers are used, each corresponding to one or more grooves. Each filler is located in its corresponding groove, and the dielectric loss tangent of each filler is greater than the dielectric loss tangent of the substrate. For example, the filler can be air.

[0119] For example, the filling method of the filler can be deposition or scraping, etc., and no specific limitation is made in this application.

[0120] By filling the grooves with fillers that have a high dielectric loss tangent, the reverse isolation of electronic components can be increased.

[0121] The material of each filler includes, but is not limited to, absorbing materials. Thus, by including absorbing materials in the filler, electrical signals are more easily dissipated within the filler, thereby further increasing the reverse isolation of electronic components. Furthermore, filling with solid materials like absorbing materials can improve the mechanical properties of the substrate, reduce the probability of damage to the substrate under external forces, and extend the lifespan of semiconductor packaged devices. For example, the material of each filler may include a combination of air and absorbing materials.

[0122] This application does not specify any particular absorbing material; you may choose your own.

[0123] As some implementation methods, the microwave absorbing material may include at least one of graphene, graphite, carbon black, carbon fiber, carbon nanotubes, and ferrite, and the list is not exhaustive. Thus, graphene, graphite, carbon black, carbon fiber, carbon nanotubes, and ferrite are all materials that are easy to prepare or purchase. Including at least one of these materials in the microwave absorbing material can not only improve the mechanical properties of the substrate, but also shorten the time required to prepare or purchase the microwave absorbing material, thereby improving the manufacturing efficiency of semiconductor packaging devices.

[0124] In some implementations, each filler is made of a microwave absorbing material and a carrier material. For example, the carrier material may include an insulating adhesive or resin. For example, each filler may be obtained by mixing the microwave absorbing material with the carrier material. For example, the three-dimensional structure of each filler may be adapted to the corresponding groove by a processing method such as injection molding.

[0125] Thus, each filler consists of absorbing material and carrier material. The absorbing material helps dissipate electrical signals, while the carrier material provides rigid support. This further increases the reverse isolation of electronic components, enhances the performance of the rigid support, and further improves the mechanical properties of the substrate.

[0126] It should be noted that this application does not limit the connection method of the first interconnect line and the second interconnect line.

[0127] In one embodiment of this application, the first interconnect is connected to the input terminal of the electronic component by gold wire bonding or bridging; and / or, the second interconnect is connected to the output terminal of the electronic component by gold wire bonding or bridging.

[0128] Gold wire bonding uses gold wire, which has low resistivity, good conductivity, and is not easily oxidized, thus improving the reliability of long-term connections.

[0129] Bridge soldering uses flat copper strips as connecting lines. The flat strip structure has a larger cross-sectional area and a smaller skin effect, thus significantly reducing resistance and inductance, which can reduce power loss and signal distortion.

[0130] This application does not limit the relationship between the projections of the first interconnect line and the second interconnect line on the substrate and the first groove and the second groove, and can be set by the user.

[0131] In one embodiment of this application, the projection of the first interconnect on the substrate at least partially overlaps with the first groove; and / or, the projection of the second interconnect on the substrate at least partially overlaps with the second groove. In this case, the first groove and the second groove can cut off the coupling energy ground plane, reduce energy coupling, and thereby further improve the reverse isolation.

[0132] In one possible implementation, the length of the first groove portion in the first direction is greater than or equal to the length of the projection of the first interconnect line on the substrate in the first direction, where the first direction is the direction of the perpendicular line connecting the connection point of the first interconnect line to the input terminal of the first circuit structure; and / or, the length of the second groove portion in the second direction is greater than or equal to the length of the projection of the second interconnect line on the substrate in the second direction, where the second direction is the direction of the perpendicular line connecting the connection point of the second interconnect line to the output terminal of the second circuit structure.

[0133] The projection of the first interconnect on the substrate in a first direction has a length less than or equal to the length of the first recess in the first direction. The first direction is the direction perpendicular to the line connecting the connection point of the first interconnect to the input terminal of the first circuit structure. Therefore, the first recess is located directly below the first interconnect, which further reduces the reverse coupling of the first interconnect to the signal and improves the directional isolation of the electronic component. Similarly, the projection of the second interconnect on the substrate in a second direction has a length less than or equal to the length of the second recess in the second direction. The second direction is the direction perpendicular to the line connecting the connection point of the second interconnect to the output terminal of the second circuit structure. Therefore, the second recess is located directly below the second interconnect, which further reduces the reverse coupling of the second interconnect to the signal and improves the directional isolation of the electronic component.

[0134] The shape of the groove is not limited in this application and can be set by the user.

[0135] As one possible implementation, at least a pair of opposite sides of the projection of at least one of the grooves onto the surface are parallel, which can reduce the difficulty of manufacturing the grooves and reduce the manufacturing cost.

[0136] In one embodiment of this application, the projection is a parallelogram, and the shape of the groove can be rectangular, which simplifies the manufacturing process.

[0137] It should be noted that this application does not limit the positional relationship between the first interconnect and the first groove, or between the second interconnect and the second groove.

[0138] As one possible implementation, the projection of the first interconnect on the substrate is located within the range of the first groove portion; and / or, the projection of the second interconnect on the substrate is located within the range of the second groove portion, which can minimize energy coupling and improve reverse isolation.

[0139] It should be understood that the specific details of the semiconductor packaging device, substrate, groove group, groove, first groove portion, second groove portion, first circuit structure, electronic component, second circuit structure, filler, first interconnect and second interconnect mentioned in Embodiment 4 can be found in the corresponding descriptions of the semiconductor packaging device, substrate, groove group, groove, first groove portion, second groove portion, first circuit structure, electronic component, second circuit structure, filler, first interconnect and second interconnect in Embodiments 1 to 3, and will not be repeated here.

[0140] The above-described preferred embodiments have further illustrated the purpose, technical solutions, and advantages of the present invention. It should be understood that the above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A semiconductor packaged device, characterized in that, include: Electronic components are fixed to the surface of a substrate and electrically connected to the substrate via the surface; A first circuit structure and a second circuit structure are fixed on the surface. The first circuit structure is used to transmit input signals to the electronic component, and the second circuit structure is used to receive output signals from the electronic component. A first interconnect and a second interconnect, wherein the first interconnect is used to electrically connect the input terminal of the electronic component and the first circuit structure, and the second interconnect is used to electrically connect the output terminal of the electronic component and the second circuit structure; The substrate has a set of recesses, the set of recesses including one or more recesses, the one or more recesses extending from the surface toward the substrate in a direction away from the electronic component, the set of recesses including at least one of a first recess portion and a second recess portion, the first recess portion being located between the electronic component and the first circuit structure, and the second recess portion being located between the electronic component and the second circuit structure; the dielectric loss tangent of the first recess portion and the dielectric loss tangent of the second recess portion are both greater than the dielectric loss tangent of the substrate.

2. The semiconductor packaged device as claimed in claim 1, characterized in that, The groove group includes a first groove portion and a second groove portion.

3. The semiconductor packaged device as described in claim 1 or 2, characterized in that, The groove group includes multiple grooves, and the multiple grooves include a first groove portion and a second groove portion.

4. The semiconductor packaged device as described in claim 3, characterized in that, The plurality of grooves are two grooves, which are respectively a first groove portion and a second groove portion.

5. The semiconductor packaged device as described in claim 1 or 2, characterized in that, The groove assembly includes a groove surrounding the electronic component, and the groove includes a first groove portion and a second groove portion.

6. The semiconductor packaged device according to any one of claims 1 to 5, characterized in that, Also includes: One or more fillers correspond one-to-one with one or more grooves, each filler is located in the corresponding groove, and the dielectric loss tangent of each filler is greater than the dielectric loss tangent of the substrate.

7. The semiconductor packaged device as claimed in claim 6, characterized in that, Each filler is made of microwave absorbing material.

8. The semiconductor packaged device as claimed in claim 7, characterized in that, The microwave absorbing material includes at least one of graphene, graphite, carbon black, carbon fiber, carbon nanotubes, and ferrite.

9. The semiconductor packaged device as claimed in claim 7 or 8, characterized in that, The material of each filler also includes carrier material.

10. The semiconductor packaged device according to any one of claims 1-9, characterized in that, The first interconnect is connected to the input terminal by gold wire bonding or bridging; and / or, the second interconnect is connected to the output terminal by gold wire bonding or bridging.

11. The semiconductor packaged device as claimed in claim 1, characterized in that, The projection of the first interconnect line on the substrate at least partially overlaps with the first recess; and / or, the projection of the second interconnect line on the substrate at least partially overlaps with the second recess.

12. The semiconductor packaged device as claimed in claim 11, characterized in that, The length of the first groove in the first direction is greater than or equal to the length of the projection of the first interconnect line on the substrate in the first direction, where the first direction is the direction of the perpendicular line connecting the connection point of the first interconnect line at the first circuit structure and the input terminal. And / or, the length of the second groove portion in the second direction is greater than or equal to the length of the projection of the second interconnect line on the substrate in the second direction, where the second direction is the direction of the perpendicular line connecting the connection point of the second interconnect line at the second circuit structure and the output terminal.

13. The semiconductor packaged device according to any one of claims 1 to 12, characterized in that, At least one of the grooves in the one or more grooves has at least a pair of opposite sides of its projection onto the surface.

14. The semiconductor packaged device as claimed in claim 13, characterized in that, The projection is a parallelogram.

15. The semiconductor packaged device according to any one of claims 1 to 14, characterized in that, The substrate is a conductive substrate.

16. The semiconductor packaged device according to any one of claims 1 to 15, characterized in that, The projection of the first interconnect line on the substrate is located within the range of the first recess; and / or, the projection of the second interconnect line on the substrate is located within the range of the second recess.

17. The semiconductor packaged device according to any one of claims 1 to 16, characterized in that, The grooves are formed by CNC machine tool processing.

18. A method for manufacturing a semiconductor packaged device, characterized in that, include: A groove group is formed on a substrate, the groove group including one or more grooves, the one or more grooves extending from the surface of the substrate toward the interior of the substrate, the groove group including at least one of a first groove portion and a second groove portion, the dielectric loss tangent of the first groove portion and the dielectric loss tangent of the second groove portion are both greater than the dielectric loss tangent of the substrate. Electronic components are fixed on the surface and electrically connected to the substrate through the surface; A first circuit structure and a second circuit structure are fixed on the surface. The first circuit structure is used to transmit input signals to the electronic component, and the second circuit structure is used to receive output signals from the electronic component. The first groove is located between the electronic component and the first circuit structure, and the second groove is located between the electronic component and the second circuit structure. A first interconnect is electrically connected between the input terminal of the electronic component and the first circuit structure, and a second interconnect is electrically connected between the output terminal of the electronic component and the second circuit structure.

19. An electronic device, characterized in that, include: The semiconductor packaged device as described in any one of claims 1 to 17.

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