Refresh during power state change

Abstract

A data processor operable to couple to a memory includes an array of memory operations, a controller, a refresh logic circuit, and a selector. The memory operation array is to store memory operations for a first power state of the memory. The controller is responsive to the power state change request to perform a plurality of memory operations from the memory operation array when the first power state is selected. The refresh logic circuit periodically generates a refresh cycle for the memory. A selector is used to multiplex the refresh cycles with the memory operations during a change in power state to a first power state.

Description

Background Technology

[0001] Computer systems typically use inexpensive, high-density Dynamic Random Access Memory (DRAM) chips as main memory. Most DRAM chips sold today are compatible with various Double Data Rate (DDR) DRAM standards published by the Joint Electronic Equipment Commission (JEDEC). The data flow to and from the DRAM via the memory bus is typically managed by the memory controller. The memory controller receives memory access requests from the host system, stores them in a queue, and dispatches them to the DRAM in an order selected by an arbitrator to improve the efficiency of the memory bus. Attached Figure Description

[0002] Figure 1 A data processing system based on some specific implementations is illustrated in the form of a block diagram; Figure 2 The diagram illustrates, in the form of a block diagram, the possible uses of some specific implementations. Figure 1 The memory controller of the memory controller; Figure 3 The diagram illustrates, in the form of a block diagram, the possible uses of some specific implementations. Figure 2 The self-refreshing state machine and power engine; Figure 4 An example of a memory mapping showing the contents of the command section of a memory operation array is provided; Figure 5 The diagram illustrates, in the form of a block diagram, the usable components according to some specific implementations. Figure 1 The memory controller provides efficient power state change operation; and Figure 6 This is a flowchart illustrating the process of performing a refresh during a power state change, according to some specific implementations.

[0003] In the following description, the same reference numerals are used in different figures to indicate similar or identical items. Unless otherwise stated, the word “coupled” and its associated verb form include both direct connection and indirect electrical connection by means known in the art, and unless otherwise stated, any description of direct connection also implies an alternative specific implementation using a suitable form of indirect electrical connection. The following detailed description relates to electronic circuitry, and unless otherwise stated, the description of the blocks shown in the figures implies the use of suitable electronic circuitry to implement the described functions. Detailed Implementation

[0004] Memory controllers and their associated DRAM memory can be placed in different power states to improve performance or reduce power consumption. Power states are used in many parts of a computer system, where different power states provide different operational capabilities, such as the processing power for the processor core or the signaling data rate for the communication bus. A popular standard for managing such power modes is the Advanced Configuration and Power Interface (ACPI), which is a power management and configuration standard for computers such as personal computers (PCs) and servers. ACPI allows the computer operating system to control the amount of power given to each device by changing the device's operating mode from a finite set of modes. For example, such changes may include changing the device's clock speed to a higher or lower frequency or putting the device into standby or power-down mode.

[0005] Modern DRAM (e.g., Double Data Rate 5 (DDR5) DRAM) has a large set of operating parameters that must be trained during operation and a large number of mode registers that must be programmed for each specific operating speed. The sheer number of these operating parameters and mode registers makes the mode-change sequence so long that some or all memory cells must be refreshed during that sequence. Performing refreshes under these conditions is difficult without risking data loss in the DRAM or wasting valuable time refreshing memory cells that do not need to be refreshed.

[0006] A data processor operable to be coupled to a memory includes a memory operation array, a controller, refresh logic circuitry, and a selector. The memory operation array stores memory operations for a first power state of the memory. The controller, in response to a power state change request, executes multiple memory operations from the memory operation array when the first power state is selected. The refresh logic circuitry periodically generates refresh cycles for the memory. The selector multiplexes these refresh cycles with the memory operations during a power state change to the first power state.

[0007] A data processing system includes a data processor and a memory coupled to the data processor. The data processor includes a memory operation array, a controller, refresh logic circuitry, and a selector. The memory operation array is used to store memory operations for a first power state of the memory. The controller, in response to a power state change request, executes multiple memory operations from the memory operation array when the first power state is selected. The refresh logic circuitry periodically generates refresh cycles for the memory. The selector is used to multiplex these refresh cycles with the memory operations during a power state change to the first power state.

[0008] A method for accessing memory includes storing memory operations for a first power state of the memory in a memory operation array. Multiple memory operations from the memory operation array are executed in response to a power state change request for the first power state. A refresh cycle is periodically generated for the memory. The refresh cycle occurs along with the memory operations during a power state change to the first power state.

[0009] Figure 1 A data processing system 100 according to some specific implementations is illustrated in block diagram form. The data processing system 100 includes a data processor 110 in the form of a system-on-a-chip (SOC), a basic input / output system (BIOS) memory 157 labeled "BIOS," and a memory 180 in the form of an external double data rate version 5 synchronous dynamic random access memory (DDR5 SDRAM) system. Many other components typically present in actual data processing systems but are irrelevant to understanding this disclosure and are not shown for illustrative purposes. Figure 1 As shown in the image.

[0010] Data processor 110 typically includes a system management unit (SMU) 111, a system management network (SMN) 112, a data processor core 120 in the form of a central processing unit (CPU) core complex labeled "CCX", a graphics controller 130 labeled "GFX", a real-time client subsystem 140, a memory / client subsystem 150, a data texture 160, a memory channel 170 to memory 180, and a peripheral component interface fast (PCIe) subsystem 190. As will be understood by those skilled in the art, data processor 110 may not have all of these elements present in every specific implementation, and may also have additional elements included therein.

[0011] SMU 111 is bidirectionally connected to the main components in data processor 110 via SMN 112. SMN 112 forms the control texture of data processor 110. SMU 111 is a local controller that controls the operation of resources on data processor 110 and synchronizes communication between these resources. SMU 111 manages the power-on sequence of various processors on data processor 110 and controls multiple off-chip devices via reset, enable, and other signals. SMU 111 includes one or more clock sources (not shown), such as phase-locked loops (PLLs), to provide clock signals to each component in data processor 110. SMU 111 also manages the power of various processors and other functional blocks and can receive measured power consumption values ​​from the CPU core in data processor core 120 and graphics controller 130 to determine appropriate P states.

[0012] The data processor core 120 includes a group of CPU cores, each of which is bidirectionally connected to the SMU 111 via the SMN 112. Each CPU core may be a single core that shares the final cache only with other CPU cores, or it may be combined with some, but not all, of the cores in the cluster.

[0013] The graphics controller 130 is bidirectionally connected to the SMU 111 via SMN 112. The graphics controller 130 is a high-performance graphics processing unit capable of performing graphics operations, such as vertex processing, fragment processing, shading, and texture blending, in a highly integrated and parallel manner. To perform its operations, the graphics controller 130 requires periodic access to external memory. Figure 1 In the specific implementation shown, the graphics controller 130 and the CPU core in the data processor core 120 share a common memory subsystem, which is called a unified memory architecture. Because the data processor 110 includes both a CPU and a GPU, it is also called an accelerated processing unit (APU).

[0014] The real-time client subsystem 140 includes a group of real-time clients, such as representative real-time clients 142 and 143, and a memory management hub 141 labeled "MM Hub". Each real-time client is bidirectionally connected to the SMU 111 via SMN 112 and bidirectionally connected to the memory management hub 141. The real-time client subsystem 140 may include any type of peripheral controller that requires periodic data movement, such as an image signal processor (ISP), an audio encoder-decoder (codec), a display controller that renders and rasterizes objects generated by the graphics controller 130 for display on a monitor, etc.

[0015] The memory / client subsystem 150 includes a set of memory elements or peripheral controllers, such as memory / client devices 152 and 153, and a system and I / O hub 151 labeled “SYSHUB / IOHUB”. Each memory / client device is bidirectionally connected to the SMU 111 via SMN 112 and bidirectionally connected to the system and I / O hub 151. Memory / client devices 152 and 153 are circuits that store data or require non-cyclic access to data, such as non-volatile memory, static random access memory (SRAM), external disk controllers such as Serial Advanced Technology Attachment (SATA) interface controllers, Universal Serial Bus (USB) controllers, system management hubs, etc. In the data processor 110, memory / client device 153 is adapted to connect to external memory storing the Basic Input / Output System (BIOS), namely BIOS memory 157.

[0016] Data texture 160 is an interconnect that controls the flow of traffic in data processor 110. Data texture 160 is bidirectionally connected to SMU 111 via SMN 112, and bidirectionally connected to data processor core 120, graphics controller 130, memory management hub 141, and system and I / O hub 151. Data texture 160 includes crossbar switches for routing memory-mapped access requests and responses between any of the various devices in data processor 110. The data texture includes system memory maps defined by the Basic Input / Output System (BIOS) for determining the destination of memory access based on system configuration, and buffers for each virtual connection.

[0017] Memory channel 170 is circuitry that controls data transfers to and from memory 180. Memory channel 170 includes a final-level cache 171 (labeled "LLC0") for a first channel, a final-level cache 172 (labeled "LLC1") for a second channel, a memory controller 173, and a physical interface circuitry 174 (labeled "PHY") connected to memory 180. Final-level cache 171 is bidirectionally connected to SMU 111 via SMN 112 and has a downlink port and an uplink port bidirectionally connected to the downlink port of data texture 160. Final-level cache 172 is bidirectionally connected to SMU 111 via SMN 112 and has an uplink port bidirectionally connected to the downlink port of data texture 160, as well as a downlink port. Memory controller 174 has a first uplink port bidirectionally connected to the downlink port of final-level cache 171, a second uplink port bidirectionally connected to the downlink port of final-level cache 172, and a first downlink port and a second downlink port. The physical interface circuit 174 has a first uplink port bidirectionally connected to a first downlink port of the memory controller 173, a second uplink port bidirectionally connected to a second downlink port of the memory controller 173, and a downlink port bidirectionally connected to the memory 180. For example... Figure 1 As shown, the physical interface circuit 174 includes a training controller 175, the operation of which will be described below.

[0018] In the illustrated embodiment, memory 180 includes a set of DDR5 dual in-line memory modules (DIMMs), including DIMM 181 and DIMM 192. Each DIMM includes a set of DDR5 memory chips operating according to the DDR5 standard. In some embodiments, DIMMs 181 and 192 are unbuffered DIMMs supporting two channels labeled “CHA” and “CHB”, and multiple columns on each channel, each column having multiple memory chips. In one example, each column may have ten by four ('4) memory chips, with eight memory chips storing data forming a '32 data width and two memory chips storing error correction code (ECC) bits for the data. In other embodiments, DIMMs 181 and 192 may be load-reduced DIMMs (LRDIMMs), which include a register clock driver and a set of data buffers that buffer and redistribute signals between the physical interface circuitry 174 and the individual memory chips in each of DIMMs 181 and 192.

[0019] The bidirectional connection between the physical interface circuit 174 and the memory 180 includes signal groups as defined by the JEDEC DDR5 standard, including individual signals for each channel and shared control signals.

[0020] In operation, the data processor 110 integrates various complex computing and storage devices, including a data processor core 120 and a graphics controller 130, on a single chip as memory access agents. Most of these controllers are well-known and will not be discussed further. The data processor 110 includes multiple internal buses for high-speed data transfer between these circuits. For example, the data processor core 120 accesses data on a high-speed 32-bit bus via an uplink port of the data texture 160. The data texture 160 performs multiplexed access between any memory access agent among the multiple memory access agents connected to its uplink port and a memory access responder connected to its downlink port. Due to the large number of memory access agents and memory access responders, the number of internal bus lines is also quite large, and crossbar switches in the data texture 160 multiplex these wide buses to form virtual connections between memory access requesters and memory access responders.

[0021] Each processing node also maintains its own cache hierarchy. In a typical configuration, data processor core 120 comprises four data processor cores, each with its own dedicated Level 1 (L1) and Level 2 (L2) caches, and a Level 3 (L3) cache shared among the four CPU cores in the cluster. In this example, the last-level caches 171 and 172 will form a Level 4 (L4) cache, but regardless of the internal organization of the cache hierarchy within data processor core 120, this Level 4 cache operates as the last-level cache in the cache hierarchy. In one example, last-level caches 171 and 172 implement an inclusive cache, where any cache lines stored in any higher-level cache of data processor 110 will also be stored. In another example, last-level caches 171 and 172 are victim caches and include cache lines, each of which contains data requested by the data processor at an earlier point in time but eventually becomes the least recently used cache line and is evicted from all parent caches.

[0022] According to the various specific embodiments described herein and further detailed below, data processor 110 stores parameters from BIOS memory 157 in the controller of memory controller 173 to allow it to efficiently execute power state change requests for memory 180. Upon power-up, a designated CPU core in data processor core 120 loads instructions from BIOS memory 157 to boot the system. Among these instructions are instructions that allow the training controller 175 to determine various timing and voltage parameters in the system. They also include instructions that allow memory controller 173 to efficiently implement memory power state change requests by utilizing the complexity of memory 180 to avoid stopping the issuance of mode register commands used by the DDR5 memory chip and the system for changing the power state. Therefore, they improve the efficiency of power state change requests compared to known systems.

[0023] Figure 2 The diagram illustrates, in the form of a block diagram, the usable components according to some specific implementations. Figure 1 The memory controller 173 includes a memory controller 200. The memory controller 200 typically includes a front-end interface 210, a command queue 220 labeled "DCQ", an arbitrator 230, a back-end queue 240, and a self-refreshing state machine and power engine 250 labeled "SLFREF / PE".

[0024] Front-end interface 210 is a circuit including front-end interface circuits 211 and 212, each labeled "FEI". Front-end interface circuit 211 has a downlink port and an uplink port connected to the first downlink port of data texture 160 via a final-level cache 171. Figure 2 In a specific implementation, the uplink port uses an interface called an Extensible Data Port (SDP), and is therefore labeled "SDP PC0", while the downlink port makes memory access requests for pseudo-channel 0, and is therefore labeled "PC0". The front-end interface circuit 212 has an uplink port labeled "SDP PC1" connected to the data texture 160 via the final cache 172, and a downlink port labeled "PC1".

[0025] Command queue 220 is a circuit that includes DRAM command queues 221 and 222, each labeled "DCQ". DRAM command queue 221 has an uplink port connected to the downlink port of front-end interface circuit 211, and a downlink port similarly labeled "PC0". DRAM command queue 222 has an uplink port connected to the downlink port of front-end interface circuit 212, and a downlink port similarly labeled "PC1".

[0026] Arbitrator 230 is a circuit comprising arbitrators 231 and 232, each labeled "ARB," and a pseudo-channel arbitrator 233, labeled "PCARB." Arbitrator 231 has a first uplink port, a second uplink port, and a downlink port similarly labeled "PC0," all connected to the downlink port of DRAM command queue 221. Arbitrator 232 has a first uplink port, a second uplink port, and a downlink port similarly labeled "PC1," all connected to the downlink port of DRAM command queue 222. Pseudo-channel arbitrator 233 has a first uplink port connected to the downlink port of arbitrator 231, a second uplink port connected to the downlink port of arbitrator 232, a first downlink port labeled "Timeslot 0," and a second downlink port labeled "Timeslot 1." Arbitrator 230 improves efficiency by intelligently scheduling access to enhance memory bus utilization. Generally, arbitrator 230 selects access from command queue 220 according to a set of arbitration rules. Arbitrator 230 implements correct timing relationships by determining whether certain accesses in command queue 220 are eligible to be issued based on DRAM timing parameters. Arbitrator 230 uses decoded address information, timing eligibility information, and active page information to efficiently schedule memory accesses while adhering to other criteria such as Quality of Service (QoS) requirements. For example, arbitrator 230 prioritizes access to open pages to avoid the overhead of precharge and activation commands required to change memory pages, and hides overhead access to one bank by interleaving overhead access to one bank with read and write access to another bank. During normal operation, arbitrator 230 typically keeps pages open in different banks until precharge of those pages is required, then selects the appropriate page.

[0027] Back-end queue 240 is a circuit comprising back-end queues 241 and 242, each labeled "BEQ," and command replay queues 243 and 244, each labeled "REC." Back-end queue 241 has a first uplink port and a second uplink port connected to a first downlink port of pseudo-channel arbiter 233, and a downlink port connected to physical interface circuitry 174, for providing a signal for a first phase labeled "Phase 0." Back-end queue 242 has a first uplink port and a second uplink port connected to a second downlink port of pseudo-channel arbiter 233, and a downlink port connected to physical interface circuitry 174, for providing a signal for a second phase labeled "Phase 1." Command replay queue 243 has a downlink port bidirectionally connected to the second uplink port of back-end queue 241. Command replay queue 244 has a downlink port bidirectionally connected to the second uplink port of back-end queue 242.

[0028] The self-refresh state machine and power engine 250 have a bidirectional connection to SMN 112, a first output connected to the second input of arbitrator 231, and a second output connected to the second input of arbitrator 232. The self-refresh state machine and power engine 250 are circuits that provide memory commands to the command stream of PC1 or PC2, such as mode register settings for different memory power states. In DDR5 SDRAM, many settings affecting operation under the selected power state are set via corresponding mode registers. These are well known from the DDR5 standard published by JEDEC. Because the supported clock frequencies can be very high, such as 3.2 GHz, the settings are important and have different values ​​for each clock frequency.

[0029] Based on the characteristics of DDR5, parameters can be identified in several different groups. The first group is called the Duty Cycle Regulator (DCA) group. When the DDR5 memory chip has a data width of four times ('4), fourteen mode registers MR43, MR44, MR103, MR104, MR105, MR106, MR133, MR134, MR141, MR142, MR149, MR150, MR157, and MR158 need to be reprogrammed for power state changes. When the memory chip has a data width of eight times (́'8), this number increases to twenty-two mode registers, and when the DDR5 memory chip has a data width of sixteen times ('16), this number increases to forty-two registers. There are several other groups of mode registers associated with the decision feedback equalizer (DFE) input signal architecture, including a group for each of the four DFE taps, a group for DFE gain enable, and a group for data mask enable. The total number of registers whose settings need to be changed for different operating frequencies is 39 for '4 organizations, 67 for '8 organizations, and 132 for '16 organizations.

[0030] However, when updating the mode register value during a power state change, the memory controller 173 must observe the timing parameter t. MRW . t MRW This is the mode register set command latency, and defines the minimum amount of time between a mode register set command that loads parameters into the mode register of the accessed memory and any other command that includes another mode register set command. For example, in the basic DDR5 specification JESD79-5 (July 2020) released by JEDEC, t... MRW This is equivalent to 8 clock cycles or 5 nanoseconds (ns), whichever is greater. Therefore, to program a '16 memory chip for the new speed settings, a minimum of 132'10 = 1320 clock cycles will be required. The latency increases accordingly for programming multiple columns.

[0031] Figure 3 The diagram illustrates, in the form of a block diagram, the usable components according to some specific implementations. Figure 2 The self-refreshing state machine and power engine 250 and the self-refreshing state machine and power engine 300 typically include a memory operation (MOP) array 310, a controller 320, and interface circuitry 330.

[0032] Interface circuit 330 connects the self-refreshing state machine and power engine 300 to data texture 160 to receive power state change commands from SMN 112 and provide power state change confirmations thereto, and to receive data to be programmed into MOP array 310. Interface circuit 330 has a first port bidirectionally connected to data texture 160 as described above, and, as shown in the relevant details here, has an input for receiving a power state change request signal labeled “Power Request” from data texture 160, an output for providing a power state change confirmation signal labeled “Power Confirmation” to data texture 160, and a second port for receiving data labeled “Programming MOP Array” for programming MOP array 310 from SMU 111 via SMN 112. Interface circuit 330 also has a second port having a first output for providing a memory power state change request signal labeled “M_PSTATE REQ”, and a second output for providing data to be stored in MOP array 310.

[0033] The controller 320 has an input terminal connected to a first output terminal of the second port of the interface circuit 330, a bidirectional port, and an output terminal for providing the decoded MOP to the arbitrator 231 or arbitrator 232. The controller 320 is a circuit that reads and executes commands stored in the MOP array 310 in a manner that will be further described below.

[0034] The MOP array 310 has an input terminal connected to the second output terminal of the second port of the interface circuit 330, and a bidirectional connection to the controller 320. The MOP array 310 is divided into a command section 311 for storing MOPs and a data section 312 for storing data.

[0035] Stored at startup Figure 1The BIOS query memory 180 in the BIOS memory 157 determines the type and organization of the installed memory. This is typically achieved by reading small non-volatile memory chips present on each DIMM in the system. In an exemplary embodiment, the physical interface circuitry 174 is configured to support DDR5 memory. In response to detecting the type and capability of the memory installed in memory 180 and performing training using training controller 175, the system BIOS populates the MOP array 310. The MOP array 310 is programmed in the command section 311 with a sequence of commands to initiate low-power modes supporting specific types of memory, where values ​​acquired during training are present in the data section 312. This is done by providing commands to write to the mode registers of the DDR5 memory chips in a valid order to reduce or eliminate channel stalling based on timing requirements.

[0036] exist Figure 1 In the illustrated implementation, the memory controller 173 operates according to a model described by the Advanced Configuration and Power Interface (ACPI) specification. It supports various power states (e.g., P0, P1, P2, and P3) in the memory's operating (or D0) state, as well as various low-power states (e.g., D1, D2, and D3 states). According to the ACPI specification, the operating state of a device (such as memory controller 173 or memory 180) is referred to as D0 or the "fully on" state. Other states are low-power states and include D1, D2, and D3 states, where D3 is the "off" state. The memory controller 173 is capable of frequency and / or voltage changes within the D0 state and correspondingly altering the memory chip to operate at a speed corresponding to a selected P state in the D0 state. The memory controller also controls the placement of memory 180 in a lower power state corresponding to the available D states of memory controller 173.

[0037] Upon receiving a power request, interface circuitry 330 provides the controller 320 with an M_PSTATE REQ signal to indicate which power state is requested. In response, controller 320 accesses MOP array 310 to execute a MOP sequence that places the memory chip in the appropriate state for the requested D state, and specifically the appropriate power state (P state) within the D0 state. Controller 320 outputs an index to command section 311 of MOP array 310, and MOP array 310 returns an encoded command (MOP) in response. In one example, controller 320 linearly decodes and issues MOPs from entries in command section 311, with data coming from data section 312, without branching until the first empty entry is read from command section 311. Many of these commands are Mode Register Set (MRS) commands that use data values ​​stored in data section 312. For example, these data values ​​could be specific settings of a large set of DDR5 mode registers that need to be programmed for a particular selected power state.

[0038] Specifically, the BIOS in BIOS memory 157 stores command sequences sequentially in MOP array 310, such that consecutive memory operations programming different parameters of the same region of memory under the selected power state are separated into multiple cycles in the sequence, ensuring that certain timing parameters are met without causing stalls. For example, a predetermined minimum timing parameter (such as the minimum time from the mode register) is written to t MRW .

[0039] For example, to ensure that commands exhibit this behavior and are therefore efficiently programmable during power state change requests, these commands iterate in a hierarchical order of device, mode register, channel, and chip selection. This assumes a sufficient number of device and chip selections in the system to avoid t-based... MRW If there is a stagnation, then the controller 320 can iterate over the entire memory system without stagnation. In other words, the controller 320 reduces the time spent waiting for t in a given system. MRW The amount of stalling due to expiration, if any, provides for efficient and rapid changes in memory power state.

[0040] Figure 4 Memory mapping 400 is illustrated, showing the contents of the command section of the MOP array. For example... Figure 4As shown, memory map 400 includes representative portions, which include portions 410, 420, 430, and 440. Portion 410 includes a sequence of mode register write cycles labeled "Extended". Portion 420 is the portion providing refresh commands labeled "Refresh". Portion 430 is another sequence of mode register write cycles similarly labeled "Extended". Portion 440 is another portion providing refresh commands similarly labeled "Refresh". The system BIOS continues this mode until the complete set of mode registers has been programmed for the newly requested power state. Therefore, the BIOS needs to know the refresh timing requirements and the refresh interval (referred to as "t"). REFI The corresponding number of loops (the timing parameter).

[0041] This technique for programming the memory operation array 310 has several drawbacks. First, the interval of refresh commands in the MOP array 310 can be estimated based on the worst-case power state change, but in this case, the controller 320 performs unnecessary refreshes for most typical power state changes. For example, if the number of refreshes interleaved with power state change commands is reduced, the risk of data loss increases when capacitors in memory cells lose too much charge due to too few refreshes. Second, the amount of time required for power state changes increases, thereby reducing the predictability of entering and returning from lower operating power states. Third, the size of the MOP array 310 needs to be increased to accommodate additional refresh commands. Fourth, if the refresh interval t REFI Changes, such as when the temperature exceeds a high-temperature threshold, avoid the need to modify the allocation between the refresh command and the extension in the command section of the MOP array.

[0042] Figure 5 The diagram illustrates, in the form of a block diagram, the usable components according to some specific implementations. Figure 1 The memory controller 173 provides efficient power state changing operation compared to the memory controller 500. The memory controller 500 is similar to... Figure 2 The memory controller 200 is adapted to a more efficient technique for generating refresh operations during power state changes. Components of the memory controller 500 that are common to the components of the memory controller 200 have the same reference numerals and operate as described above.

[0043] The memory controller 500 further includes refresh logic circuitry 510, multiplexer 520, and multiplexer 530. Refresh logic circuitry 510 has a first output for providing a refresh cycle for pseudo-channel 0 and a second output for providing a refresh cycle for pseudo-channel 1. Multiplexer 520 has a first input connected to the first output of refresh logic circuitry 510, a second input connected to the first output of self-refresh controller and power engine 250, and an output connected to a third input of back-end queue 241. Multiplexer 530 has a first input connected to the second output of refresh logic circuitry 510, a second input connected to the second output of self-refresh controller and power engine 250, and an output connected to the third input of back-end queue 241.

[0044] Generally speaking, the refresh logic circuit 510 is based on the minimum refresh interval, i.e., t. REFI Parameters are used to generate refresh commands. The refresh logic circuit 510 satisfies t. REFI The refresh command is generated at a rate that targets the actual memory in the data processing system enumerated at startup, and this refresh command is separate for each pseudo-channel. The refresh commands include commands generated during normal operation (i.e., when the memory controller 200 does not perform memory power state changes), and commands generated when preparing to change the power state but before the programming of the mode register is complete. Multiplexers 520 and 530 together operate as selectors to multiplex these refresh commands with other commands (i.e., MOPs) generated to implement the power state changes as described above.

[0045] In one example, the multiplexing scheme ensures that refresh commands take precedence over any commands generated by the self-refresh controller and power engine 250 during power state changes. Therefore, a control signal indicating that a new valid refresh command has been generated controls multiplexers 520 and 530 to select their first input. Clearly, multiplexers 520 and 530 allow refresh commands to be interleaved with normal power state change commands and can be implemented with more complex circuitry, such as an arbitration engine that measures the duration of the command and the latency of the refresh command. Furthermore, in other specific implementations, additional functions can be multiplexed with refresh and MOP.

[0046] When no power state change is required, back-end queues 241 and 242 select from commands present in DRAM command queues 221 and 222, and refresh commands received at their second inputs, respectively. In some implementations, refresh logic circuitry 510 can provide "normal" refresh requests that are advantageously interleaved with normal memory access commands in back-end queues 241 and 242, and "urgent" refresh requests that take precedence over all other memory access requests. In one example, in response to receiving a power state change request, memory controller 500 stops issuing all commands in DRAM command queues 221 and 222 until the power state change request is completed. In another example, memory controller 500 stops receiving new memory access requests into DRAM command queues 221 and 222 by signaling backpressure at a port of data texture 160, while simultaneously removing existing commands from DRAM command queues 221 and 222 before a power state transition begins.

[0047] Figure 6 This is a flowchart illustrating a process 600 of performing a refresh during a power state change according to some specific implementation. Process 600 begins in action block 610. For example, the data processing system may start and begin executing instructions from system BIOS memory 157 before passing control to the operating system. At some point, the system BIOS stored in BIOS memory 157 enumerates all memories present in the data processing system and begins populating MOP array 310 in response to the type and configuration of the memories. Action block 620 includes storing memory operations for a first power state of the memory in a memory operation array. Action block 620 may include a training controller 175 that performs training operations to obtain values ​​for certain operating parameters for each power state, and the BIOS in BIOS memory 157 subsequently programs MOP array 310 according to the supported power states and using mode registers for the specific memory type used. Action block 630 includes performing multiple memory operations from the memory operation array in response to a power state change request for the first power state. For example, action block 630 may occur during an operation in which the memory power state changes in response to system activity. Memory operations include mode register setting commands to program the mode register according to the memory operation speed while using certain values ​​acquired during training. Action block 640 includes periodically generating refresh cycles for the memory. In the example shown, refresh logic circuitry 510 periodically generates refresh commands to satisfy t REFI The parameters are such that all memory cells in all memory chips of the memory system are refreshed sufficiently frequently to retain their contents. Action block 650 includes multiplexing the refresh cycle with memory operations during a power state change to a first power state. Figure 5 In the example shown, multiplexers 520 and 530 immediately allow the refresh cycle to interrupt memory operations generated by the self-refreshing state machine and power engine. For example, after controller 320 has performed all memory operations for the memory power state change request, process 600 ends in action block 660. The process can then resume at action block 630.

[0048] While specific implementations have been described, various modifications to these implementations will be apparent to those skilled in the art. For example, the techniques described above can be advantageously used with DDR5 DRAM or other memory types requiring training and mode register programming sequences that are long enough to necessitate refresh sequences. Although the exemplary DDR5 DRAM implements a pseudo-channel, the disclosed techniques can also be used with non-pseudo-channel memories. The techniques described above are applicable to systems with only a single memory column or multiple columns. The size and organization of the command portion of the MOP array can vary between different implementations. The number of supported operating power states can vary between implementations. The memory controller can also take various actions during a power state change request, such as allowing an existing memory access request to be issued without storing additional memory access requests in the command queue, thereby emptying the command queue, or stopping all memory access requests until the power state change is complete.

[0049] Therefore, the appended claims are intended to cover all modifications of the disclosed embodiments that fall within the scope of the disclosed embodiments.

Claims

1. A data processor operable to be coupled to a memory, the data processor comprising: A memory operation array for storing memory operations for a first power state of the memory; A controller that responds to a power state change request to perform a plurality of memory operations from the memory operation array when the first power state is selected; A refresh logic circuit that periodically generates a refresh cycle for the memory; and A selector is configured to multiplex the refresh cycle with the memory operation during a power state change to the first power state.

2. The data processor of claim 1, wherein the refresh logic circuit is operable to generate the refresh cycle according to a predetermined refresh interval.

3. The data processor of claim 2, wherein the refresh logic circuit selectively adjusts the predetermined refresh interval in response to temperature.

4. The data processor of claim 1, wherein the selector prioritizes the generation of the refresh cycle over the plurality of memory operations during a power state change.

5. The data processor of claim 1, wherein the refresh logic circuitry further generates the refresh cycle during normal operation.

6. The data processor according to claim 5, further comprising: A command queue for storing multiple memory access requests from at least one memory access agent; An arbitrator is configured to select a memory access request from the command queue according to a plurality of arbitration rules; and A backend queue is used to select memory access requests from the arbitrator and memory operations from the selector.

7. The data processor of claim 1, wherein the controller is operable to perform an extension of the plurality of memory operations in the memory operation array in response to at least one of the following: the number of channels, the number of columns, the number of devices, and the number of mode registers of the plurality of memory devices of the memory.

8. A data processing system, the data processing system comprising: The data processor according to any one of claims 1 to 7, and A memory, wherein the memory is coupled to the data processor.

9. The data processing system of claim 8, wherein the memory comprises at least one Double Data Rate (DDR) Version 5 (DDR5) memory chip.

10. The data processing system according to claim 8, further comprising an initialization circuit, wherein the initialization circuit includes: Data processor core; Basic Input / Output System Memory; and Training controller, The instructions stored in the basic input / output system memory cause the data processor core to use the training controller to initiate training operations on the memory, and in response to the training operations and the configuration of the memory, to populate the data portion of the memory operation array.

11. The data processing system of claim 10, wherein the initialization circuit further fills the data portion with parameters of at least one additional power state, such that consecutive memory operations programming different parameters of the first region of the memory under the at least one additional power state are separated in the sequence by an amount corresponding to a predetermined minimum timing parameter.

12. The data processing system according to claim 8, wherein the memory operation includes a mode register setting command.

13. A method for accessing memory, the method comprising: The memory operations for the first power state of the memory are stored in the memory operation array; In response to a power state change request for the first power state, perform a plurality of memory operations from the memory operation array; A refresh cycle is periodically generated for the memory; as well as The refresh cycle is multiplexed with the memory operation during the power state change to the first power state.

14. The method of claim 13, wherein periodically generating the refresh cycle for the memory comprises: The refresh cycle is generated according to a predetermined refresh interval; as well as The predetermined refresh interval is selectively adjusted in response to temperature.

15. The method of claim 13, further comprising prioritizing the refresh cycle over the plurality of memory operations during a power state change.

Images