Method and system for preparing automatic layer classification in PCB design Gerber data
By automatically identifying and transforming Gerber data through machine learning algorithms and building a classification model, the cumbersome problem of Gerber data layer classification in PCB design is solved, and simplified and efficient layer attribute settings are achieved, improving the user experience.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SIMENS INDASTRI SOFTVEAR INK
- Filing Date
- 2023-09-11
- Publication Date
- 2026-04-24
AI Technical Summary
In existing technologies, the layer classification process of Gerber data in PCB design is cumbersome, requiring manual setting of layer attributes, relying on user experience and software development skills, and lacking intuitive and simple automated methods.
Machine learning algorithms are used to train the transformation algorithm, which automatically identifies and transforms Gerber data through training steps, constructs binary and multi-class classification models, and uses features such as pad count, line count, arc count and surface count for layer classification, simplifying the determination of layer type and context.
It enables automatic layer classification of Gerber data, reducing workload by 50%, improving user productivity, simplifying the layer attribute setting process, and making it suitable for operation by the new generation of workers.
Smart Images
Figure CN121925659A_ABST
Abstract
Description
Technical Field
[0001] This disclosure generally relates to computer-aided systems for the manufacture of printed circuit boards (“PCBs”) and surface mount technology (“SMT”) and for the quality inspection and analysis of circuit boards. More specifically, this disclosure relates to a method and system for automatically classifying layers in PCB design Gerber data. Background Technology
[0002] In PCB manufacturing, there is a widely accepted industry standard for storing and transmitting CAD data: the Gerber RX-274X data format (hereinafter referred to as "Gerber"). While this data format has a long history, its use has one major drawback—it can be considered a "non-intelligent" format. The Gerber format is essentially a collection of basic shapes describing the PCB layout (design layer). The Gerber format specification is updated regularly and is currently managed by Ucamco NV. Currently, there is a version, "Revision 2019.06" (see also https: / / www.ucamco.com / en / gerber / downloads).
[0003] However, in order to use CAD data in process preparation applications for PCB manufacturing, the data needs to be prepared in a 'smart' format or imported in some other data format, such as ODB++, which already accurately describes the PCB layout. Smart data means knowing the exact types of different design layers, their order relative to each other (called "layer stacking"), which layer features include "nets", what the actual components assembled on the board are, which layer pads connect to which component pins, and so on.
[0004] Preparing “non-intelligent” data is a tedious task involving many steps. Currently, there is no easy way to do it—this skill can only be learned correctly through frequent practice. However, the next generation of workers will expect a simpler, more intuitive way to accomplish this task.
[0005] For customers using typical process preparation applications such as Valor, the typical process involves manually applying the "Context," "Layer Type," and "Side" values based on experience. The first opportunity to make these selections occurs during the Gerber file import process (see...). Figure 1 The image shows an example of preparing Gerber data for the Gerber data file import process. If no selections are made during the import process, or if adjustments to the selections are needed, this can be done using the layer stacking tool (see Figure 2).
[0006] Figure 3 The layer stacking tool prepared for the Valor process in Figure 2 is illustrated schematically; the data represents an example of manually setting the values of a layer. Figure 4 The layer stacking tool for process preparation shown in Figure 2 is illustrated schematically; this data also represents the demo data layer after manual processing. As mentioned above, manually setting the layer values correctly is a laborious task and requires a skilled and experienced user.
[0007] Experienced users typically consider the following sources of information when making decisions:
[0008] i) The format of the identified layer file (see Figure 1 (See the "Format" column in the documentation). Specifically, if the format is a drill format, such as Excellon, then the known context is "Hole," layer type is "Drill," and sidewalls are "None." It's important to note that this information is only available during the Gerber import process. This file format information will be lost after the import is complete.
[0009] ii) The appearance of the layer (see Figure 3 It is important to note here that this information is not available during the Gerber import process.
[0010] Sometimes, Gerber layer files follow certain indicative naming conventions (see...). Figure 5 Naming conventions depend on the data source, so even with this information, some knowledge is still required. Figure 5 The diagram illustrates the naming conventions for Gerber layer files, which can provide useful information. For example, the data "smb" represents "solder resist" and "bottom," indicating the final information the layer classification process is looking for.
[0011] It should be noted that once it is understood that the "context" of a layer is merely to determine whether the layer is one of the following, determining the "context" of the layer is not a major problem:
[0012] 1) Part of the physical board, making the data "context = board".
[0013] Possible layer types include:
[0014] a) Solder paste
[0015] b) Silkscreen
[0016] c) Solder mask
[0017] d) Signal
[0018] e) Power supply grounding
[0019] f) Mask
[0020] g) Mix
[0021] h) Dielectric
[0022] 2) Drill or mill the layer so that the data "context = hole"
[0023] Possible layer types include:
[0024] a) Drilling
[0025] b) Milling
[0026] 3) Miscellaneous layers that are not part of the physical board, where the data "context = miscellaneous"
[0027] Possible layer types include:
[0028] a) Other
[0029] In addition to manually setting these properties, Valor process preparation also utilizes a rule-based mechanism. The core idea behind this mechanism is to directly translate layer properties from the original Gerber layer name. An example of this process is provided in... Figure 6 It is shown schematically in the middle.
[0030] The rule mechanism has existed in Valor crafting applications (or its predecessors) for approximately 20 years. However, in practice, setting up workable rules has been too cumbersome for users, and therefore, few rules are seen in production use. This is because rules are based on pattern matching (regular expressions), which requires almost all software development skills from the user. Another possible reason is that the naming conventions encountered may not be as static as initially imagined.
[0031] When it comes to various process preparation applications, it's unclear to what extent this specific issue has been considered. Users of any software that supports Gerber file import are domain experts who should know the actual layer type of the Gerber layer file, which appears to be mainstream best practice.
[0032] Therefore, the next generation of workers will want an easier and more intuitive way to accomplish the task of automatically classifying layers in PCB design Gerber data. Summary of the Invention
[0033] Various disclosed embodiments include methods, systems, and computer-readable media for determining assembly risks of electronic components intended for mounting to a printed circuit board (PCB). The method includes a step of automatically classifying layers in PCB design Gerber data to support PCB design processes. The method includes providing a list of Gerber data for a process preparation layer stacking tool, the Gerber data including at least a plurality of electronic layer designs and information related to the manifestation of electronic layer designs in the PCB. Other steps include importing the list of Gerber data into the process preparation layer stacking tool and converting the list of Gerber data into manufacturing data via the process preparation layer stacking tool, thereby enabling PCB production. There, the conversion is supported by a machine learning process that has been executed to train a conversion algorithm; the machine learning process includes multiple training steps, wherein, as a result of the training steps, a predetermined set of Gerber data is automatically identified and converted into corresponding manufacturing data. After this conversion is completed, the execution of PCB production is prepared based on the thus generated production data, and can then be executed accordingly.
[0034] Various disclosed implementations include methods, systems, and computer-readable media, wherein relevant information about the Gerber data includes data relating to the context of the electronic layer design in the final PCB, the layer type of the electronic layer design, and the sides.
[0035] Various disclosed implementations include methods, systems, and computer-readable media, wherein a conversion algorithm is trained in a first step, wherein a binary classification model is constructed to classify between features: board and hole, and a second step is used to train with another multi-class classification model, which is constructed to classify between features: signal layer, silkscreen layer, and solder layer for the board context.
[0036] Various disclosed implementations include methods, systems, and computer-readable media, wherein, for the classification of layer types, a separate model of layer types has been constructed for the board context, wherein the model classifies between “Solder Paste Layer”, “Silkscreen Layer”, “Solder Mask Layer”, “Signal Layer”, “Power Ground Layer”, “Mixed Layer”, and “Mask Layer”, wherein the layer types “Power Ground Layer”, “Mixed Layer”, and “Mask Layer” are merged into “Other Layer”, and the layer types “Solder Paste Layer” and “Solder Mask Layer” are merged into “Solder Layer”.
[0037] Various disclosed implementations include methods, systems, and computer-readable media, in which, during the machine learning phase, four features—PadCount, LineCount, ArcCount, and SurfaceCount—indicating the total number of pads, lines, arcs, and surfaces in a PCB design, are used to learn layer stacking.
[0038] The foregoing has already provided a fairly broad overview of the features and technical advantages of this disclosure, enabling those skilled in the art to better understand the detailed description that follows. Additional features and advantages of this disclosure that form the subject matter of the claims will be described below. Those skilled in the art will understand that they can readily use the disclosed concepts and specific embodiments as a basis for modifying or designing other structures for achieving the same purpose as this disclosure. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the broadest form of this disclosure.
[0039] Before proceeding with the detailed description below, it may be advantageous to define certain words or phrases used throughout this patent document: the terms “include” and “comprise” and their derivatives mean including but not limited to; the term “or” is inclusive, meaning and / or; the phrases “associated with” and “related to” and their derivatives may mean including, being included in, interconnected with, containing, contained in, connected to or connected to, coupled to or coupled to, able to communicate with, cooperate with, interleaved, juxtaposed, proximate, bound to or bound to, having, having attributes, etc.; and the term “controller” means any device, system, or part thereof that controls at least one operation, whether such device is implemented in hardware, firmware, software, or some combination of at least two of them. It should be noted that the functionality associated with any particular controller can be centralized or distributed, whether local or remote. Definitions of certain words and phrases are provided throughout this patent document, and those skilled in the art will understand that these definitions apply in many (if not most) cases to the prior and future use of the words and phrases defined herein. While some terms may encompass a wide variety of implementations, the appended claims may expressly limit these terms to specific implementations. Attached Figure Description
[0040] To gain a more complete understanding of this disclosure and its advantages, the following description is now taken in conjunction with the accompanying drawings, wherein like reference numerals denote like objects, and in the drawings:
[0041] Figure 1 The data processing system used in layer classification in preparing Gerber data for PCB design is illustrated schematically.
[0042] Figure 2 shows an example of preparing Gerber data for the Gerber data file import process.
[0043] Figure 3 An example of an imported demo data layer is illustrated in a layer stacking tool prepared according to prior art processes.
[0044] Figure 4 schematically shown Figure 3 The process preparation layer stacking tool; this data represents an example of manually setting the value of a layer.
[0045] Figure 5 The diagram schematically illustrates a layer stacking tool for process preparation, which now includes a manually processed demo data layer.
[0046] Figure 6This schematically illustrates the Gerber layer file naming convention that can provide useful information during the layer classification process.
[0047] Figure 7 An example of a layer description rule manager for process preparation is illustrated schematically.
[0048] Figure 8 A stable data extraction pipeline for machine learning processes is illustrated schematically in terms of the evaluation of contextual and layer-type data.
[0049] Figure 9 The confidence levels of the training and test data during the data classification process are illustrated schematically.
[0050] Figure 10 The diagram illustrates the confidence levels of the training and test data during the data classification process after further fine-tuning of the data analysis.
[0051] Figure 11 schematically illustrates the confidence levels of the training and test data during the data classification process after further fine-tuning of the data analysis.
[0052] Figure 12 This illustration schematically demonstrates the confidence level of the test data during the data classification process after further fine-tuning of the data analysis.
[0053] Figure 13 The data analysis is illustrated schematically, in which pads connected to a line are counted in PadsWithLines Count.
[0054] Figure 14 This illustration schematically shows the confidence level of the training data in the data classification process after final fine-tuning of the data analysis. Detailed Implementation
[0055] The following discussion Figures 1 to 14 The various embodiments used to describe the principles of this disclosure in this patent document are merely illustrative and should not be construed as limiting the scope of this disclosure in any way. Those skilled in the art will understand that the principles of this disclosure can be implemented in any suitably arranged device. Many of the innovative teachings of this application will be described with reference to exemplary, non-limiting embodiments.
[0056] Furthermore, the following describes a solution based on an implementation method and system for automatic layer classification in preparing PCB design Gerber data, designed to support the design process of printed circuit boards.
[0057] The features, advantages, or alternative implementations described herein may be assigned to other claimed objects, and vice versa.
[0058] In other words, the claims to methods and systems for automatic layer classification in preparing PCB design Gerber data can be improved by utilizing features described or claimed in the context of methods and systems for determining assembly risks of electronic components intended to be mounted onto printed circuit boards.
[0059] As used herein, the terms “PCB board,” “SMT board,” and simply “board” refer to an electronic circuit consisting of multiple electronic components connected to the board via wires or traces through their respective leads.
[0060] Typical examples of electronic components include, but are not limited to, resistors, transistors, capacitors, inductors, and diodes.
[0061] As used herein, the term “component” in a broader sense refers to any element or feature or layer of a board, including, for example, traces, which can be the object of a method for automatic layer classification in preparing PCB design Gerber data, designed to support the design process of printed circuit boards.
[0062] As used in this article, the term "automatic layer classification" broadly refers to the automatic layer classification in the preparation of PCB design Gerber data, which is intended to support the design process of printed circuit boards.
[0063] Previous techniques have not provided an efficient method for automatic layer classification in preparing PCB design Gerber data, designed to support the design process of printed circuit boards prior to their manufacture in an electronics shop. The embodiments disclosed herein offer numerous technical benefits, including but not limited to the following examples.
[0064] Figure 1 A block diagram of a data processing system 100 is shown, in which implementations may be, for example, a PDM system, specifically configured by software or otherwise to perform the processes described herein, and particularly implemented as each of the plurality of interconnect and communication systems described herein. The data processing system 100 shown may include a processor 102 connected to a secondary cache / bridge 104, which in turn is connected to a local system bus 106. The local system bus 106 may be, for example, a Peripheral Component Interconnect (PCI) architecture bus. In the example shown, main memory 108 and a graphics adapter 110 are also connected to the local system bus. The graphics adapter 110 may be connected to a display 111.
[0065] Other peripheral devices, such as LAN / WAN / wireless (e.g., WiFi) adapter 112, can also be connected to the local system bus 106. An expansion bus interface 114 connects the local system bus 106 to the input / output (I / O) bus 116. The I / O bus 116 connects to a keyboard / mouse adapter 118, a disk controller 120, and an I / O adapter 122. The disk controller 120 can be connected to a storage device 126, which can be any suitable machine-usable or machine-readable storage medium, including but not limited to non-volatile, hard-coded media such as read-only memory (ROM) or erasable, electrically programmable read-only memory (EEPROM), magnetic tape storage, and user-recordable media such as floppy disks, hard disk drives, and optical disc read-only memory (CD-ROM) or digital universal disc (DVD), as well as other known optical, electrical, or magnetic storage devices.
[0066] In the example shown, an audio adapter 124 is also connected to the I / O bus 116, and a speaker (not shown) can be connected to the audio adapter 124 to play sound. A keyboard / mouse adapter 118 provides connectivity for pointing devices (not shown), such as a mouse, trackball, trackpoint indicator, touchscreen, etc.
[0067] Those skilled in the art will understand that Figure 1 The hardware shown can vary for a particular implementation. For example, other peripheral devices such as optical disc drives may be used in addition to or in place of the hardware shown. The examples shown are provided for illustrative purposes only and are not intended to imply any architectural limitations with respect to this disclosure.
[0068] Data processing systems according to embodiments of this disclosure may include an operating system employing a graphical user interface (GUI). The operating system allows multiple display windows to be presented simultaneously in the GUI, each providing an interface to a different application or different instances of the same application. A user can manipulate a cursor in the GUI using a pointing device. The cursor position can be changed and / or events such as clicking a mouse button can be generated to actuate a desired response.
[0069] One of various commercial operating systems, such as a version of Microsoft Windows™, can be used with appropriate modifications from Microsoft Corporation, located in Redmond, Washington. The aforementioned operating system has been modified or created in accordance with this disclosure as described.
[0070] LAN / WAN / wireless adapter 112 can connect to network 130 (not part of data processing system 100), which can be any public or private data processing system network or combination of networks known to those skilled in the art, including the Internet. Data processing system 100 can communicate with server system 140 via network 130, which is also not part of data processing system 100, but can be implemented as a separate data processing system 100, for example. Figure 3 A block diagram illustrating a method for training a function using an ML algorithm to model a false error detector, according to the disclosed embodiment, is shown schematically.
[0071] As explained above, the method according to the present invention aims to help users set up context and layer types with minimal effort and little or no domain expertise. For large Gerber datasets, the data preparation task of setting up context and layer types can easily take anywhere from minutes to hours. This concept arose during the development of the present invention with the goal of reducing workload by 50%, which will have a significant impact on user productivity and product expectations.
[0072] This invention addresses the aforementioned problem of automatic layer classification in preparing Gerber data for PCB design by automatically learning patterns from historical data. Leveraging current domain expertise and machine learning, numerous innovative features have been created from historical data. These features are not collected in the data but are cleverly designed to aid current machine learning models.
[0073] The historical dataset consists of several databases that contain only data that has undergone the aforementioned data preparation according to existing techniques. This effectively means that most of the data is already suitable for machine model training. Figure 8 A stable data extraction pipeline is shown.
[0074] Based on the problem definition, the typical machine learning problem has always been formulated as a multi-class, multi-label classification problem. However, after several experiments, for simplicity and interpretability, the problem has been split into two classification problems. Heuristics have also been used to provide appropriate support for machine learning to keep ML simple but more accurate. For example, for context classification, the problem has been formulated as a binary classification problem by using ML to predict only the board and the hole and using rules to determine the miscellaneous context.
[0075] For layer type classification, once the context was determined, a separate model for each layer type was built within that context. For example, for the board context, a model was built to classify layers among ["solder paste layer", "silk screen layer", "solder mask layer", "signal layer", "power / ground layer", "mixed layer", and "mask layer"]. Based on data analysis, the problem was further simplified by examining the percentage of data represented by each layer type. Based on this, ["power / ground layer", "mixed layer", and "mask layer"] were merged into "other layers". In another experiment, ["solder paste layer", "solder mask layer"] were also merged into "solder layer". Therefore, the final ML problem was to classify layers among ["signal layer", "silk screen layer", and "solder layer"], which represented over 93% of the data.
[0076] Therefore, in summary, a binary classification model was established to classify boards and vias. Another multi-class classification model was constructed to classify between signal layers, silkscreen layers, and solder layers, depending on the board context. These two models handle approximately 90% of the problem space; the remainder can be best solved using heuristic-based rules.
[0077] In the ML phase, four features are initially used: pad count, line count, arc count, and surface count, indicating the total number of pads, lines, arcs, and surfaces in the PCB design. The feature also includes layer name, but it has high cardinality, making it difficult to find patterns. The initial binary classification model with only four numerical features yielded encouraging results, indicating the existence of salient patterns to be learned.
[0078] Total: 37131
[0079] Board: 32501 (87.53%)
[0080] Hole: 4630 (12.47%)
[0081] Ratio: 7.02:1
[0082] Using only pad counts, line counts, arc counts, and surface counts as features, and with 90% of the data used for training and 10% for testing, the classification model was trained. The following results were achieved with the training data (see [link to training data]). Figure 9 (a) and (b), and see for test data. Figure 9 (c) and (d)).
[0083] It can be seen that a higher percentage (approximately 19% in the training data and 17% in the test data) of boards were misclassified as holes, although a very small percentage of holes (approximately 3%) were misclassified as boards. While indeed encouraging, this result prompted further research into data quality. It was decided to further refine the pad counts into counts of individual shapes (symbols). Following this feature engineering exercise, 13 features emerged: [“circle”, “square”, “rectangle”, “ellipse”, “rhombus”, “ring”, “square ring”, “hexagon”, “empty”, “special”, “line”, “arc”, “surface”]. The researchers also extracted a larger dataset for the next experiment.
[0084] Note: The symbol types ["Circle", "Square", "Rectangle", "Oval", "Diamond", "RoundDonut", "SquareDonut", "HexagonL", "Null", "Special"] correspond to Valor process preparation symbols that can be directly imported from Gerber files. However, historical process preparation datasets may contain more symbol types. To treat historical data as pure Gerber data, all other process preparation symbol types are counted as "Special" symbols. This means that if the Gerber file contains the following symbol types, these symbol types will be imported as "special" symbols in the process preparation: ["Hole", "RectangleR", "RectangleC", "Octagon", "RoundedSquareDonut", "SquareRoundDonut", "RectangleDonut", "RoundedRectangleDonut", "OvalDonut", "RoundButterfly", "SquareButterfly", "Triangle", "Oval_H", "RoundThermal", "SquareThermal", "RoundRoundThermal", "RectangleThermal", "RoundedSquare"]. Thermal, Rounded Rectangle Thermal, Oval Thermal, Ellipse, Moire, H Plate, RH Plate, FH Plate, Radial H Plate, D Shape, Cross Shape, Dogbone Shape, D Pack, Oblong Thermal, Line Thermal.
[0085] Training was conducted based on these assumptions:
[0086] Total: 92840
[0087] Board: 87217 (93.94%)
[0088] Hole: 5623 (6.06%)
[0089] Ratio: 15.51:1
[0090] A classification model was trained using 13 new features, with 90% of the data used for training and 10% for testing. The following results were obtained for the training data (for training data such as...). Figure 10 As shown in (a) and (b), and for test data as Figure 10 As shown in (c) and (d).
[0091] Moving on to the second question regarding layer type classification, several experiments were conducted again. For the board context, a model was built to classify layers into [“Solder Paste Layer,” “Silkscreen Layer,” “Solder Mask Layer,” “Signal Layer,” “Power / Ground Layer,” “Mixed Layer,” and “Mask Layer”]. Based on data analysis by examining the percentage of data represented by each layer type, the problem was further simplified. Based on this, [“Power / Ground Layer,” “Mixed Layer,” and “Mask Layer”] were merged into “Other Layers.” This was not included in the experiments.
[0092] The experimental results are shown in Figure 11. As mentioned earlier, 13 features were used, with 90% of the data used for training and 10% for testing to train the classification model. The results obtained for the training data are shown in Figure 11(a) and (b), and the results obtained for the test data are shown in Figure 11(c) and (d).
[0093] As shown in Figure 11, the classifier exhibited confusion between the solder mask and solder paste layers (10.36% of the solder paste samples were incorrectly classified as solder mask, and 9.44% of the solder mask samples were incorrectly classified as solder paste). Therefore, it was decided to further merge ["solder paste layer", "solder mask"] into "solder layer".
[0094] Figure 12 The results of this experiment on the test data are shown. It can be seen that these results are very encouraging. However, a relatively high classification error can still be observed in the feature solder layer. Further research led to the introduction of another feature called "line pad," which calculates the number of pads connected to a line so that the start or end point of the line is inside the pad. This... Figure 13 As shown in the image.
[0095] By using this new feature in conjunction with earlier features, the most robust results have been achieved for layer-type classification models, such as Figure 14The confidence scores are shown in the results. Our best model achieves an accuracy close to 95% across all layer types.
[0096] Our focus on data quality, incremental data cleaning, and innovative feature engineering helped us solve the problem with very high accuracy, far exceeding our initial goals.
[0097] Those skilled in the art will recognize that, for simplicity and clarity, not all the structures and operations of all data processing systems suitable for use with respect to this disclosure are illustrated or described herein. Rather, only data processing systems specific to or necessary for understanding this disclosure are shown and described. The remainder of the construction and operation of data processing system 100 may conform to any of the various current implementations and practices known in the art.
[0098] It is important to note that while this disclosure is described in the context of a full-function system, those skilled in the art will understand that at least a portion of this disclosure can be distributed in the form of instructions contained in a machine-usable, computer-usable, or computer-readable medium, which can take many forms, and this disclosure applies equally regardless of the specific type of instruction or signal-bearing medium or storage medium used to actually perform the distribution. Examples of machine-usable / readable or computer-usable / readable media include: non-volatile, hard-coded media such as read-only memory (ROM) or erasable, electrically programmable read-only memory (EEPROM), and user-recordable media such as floppy disks, hard disk drives, and optical disc read-only memory (CD-ROM) or digital universal disc (DVD).
[0099] While exemplary embodiments of this disclosure have been described in detail, those skilled in the art will understand that various changes, substitutions, modifications, and improvements disclosed herein can be made without departing from the spirit and scope of this disclosure in its broadest form.
[0100] Nothing described in this application should be construed as implying that any particular element, step, or function is an essential element that must be included within the scope of the claims: the scope of the patent subject matter is limited only by the permitted claims.
Claims
1. A method for automatic layer classification in preparing PCB design Gerber data to support the design process of printed circuit boards, the method comprising: A list of Gerber data for process preparation layer stacking tools is provided, the Gerber data including at least a number of electronic layer designs and information related to the presentation of electronic layer designs in printed circuit boards; The list of Gerber data is imported into the process preparation layer stacking tool, and the process preparation layer stacking tool converts the list of Gerber data into manufacturing data, thereby enabling the production of the printed circuit board; wherein: The conversion is supported by a machine learning process that has been executed to train the conversion algorithm; the machine learning process includes multiple training steps, wherein, as a result of the training steps, a predetermined set of Gerber data is automatically identified and converted into corresponding manufacturing data; and The production data generated in this way is used to prepare for the execution of printed circuit board production.
2. The method according to claim 1, wherein, The relevant information in the Gerber data includes data related to the context of the electronic layer design in the final PCB, the layer type of the electronic layer design, and the sides.
3. The method according to claim 1 or 2, wherein, The conversion algorithm is trained in the first step, wherein a binary classification model is constructed to classify between the following features: board and hole, while the second step is used to train with another multi-class classification model, which is constructed to classify between the following features for the board context: signal layer, silkscreen layer and solder layer.
4. The method according to any one of the preceding claims, wherein, For the classification of the layer types, a separate model for the layer types has been constructed for the board context. The model classifies the layers among "solder paste layer", "silk screen layer", "solder mask layer", "signal layer", "power / ground layer", "hybrid layer" and "mask layer". The layer types "power / ground layer", "hybrid layer" and "mask layer" are merged into "other layers", and the layer types "solder paste layer" and "solder mask layer" are merged into "solder layer".
5. The method according to any one of the preceding claims, wherein, During the machine learning phase, four features—pad count, line count, arc count, and surface count—that indicate the total number of pads, lines, arcs, and surfaces in the PCB design are used to learn the layer stack.
6. A data processing system, comprising: processor; as well as Accessible memory, the data processing system is specifically configured to perform automatic layer classification in preparing PCB design Gerber data to support printed circuit board design processes, including: A list of Gerber data for process preparation layer stacking tools is provided, the Gerber data including at least a number of electronic layer designs and information related to the presentation of electronic layer designs in printed circuit boards; The list of Gerber data is imported into the process preparation layer stacking tool, and the process preparation layer stacking tool converts the list of Gerber data into manufacturing data, thereby enabling the production of the printed circuit board; wherein: The conversion is supported by a machine learning process that has been executed to train the conversion algorithm; the machine learning process includes multiple training steps, wherein, as a result of the training steps, a predetermined set of Gerber data is automatically identified and converted into corresponding manufacturing data; and The production data generated in this way is used to prepare for the execution of printed circuit board production.
7. The data processing system according to claim 6, wherein, The relevant information in the Gerber data includes data related to the context of the electronic layer design in the final PCB, the layer type of the electronic layer design, and the sides.
8. The data processing system according to claim 6 or 7, wherein, The conversion algorithm is trained in the first step, wherein a binary classification model is constructed to classify between the following features: board and hole, while the second step is used to train with another multi-class classification model, which is constructed to classify between the following features for the board context: signal layer, silkscreen layer and solder layer.
9. The data processing system according to any one of claims 6 to 8, wherein, For the classification of the layer types, a separate model for the layer types has been constructed for the board context. The model classifies the layers among "solder paste layer", "silk screen layer", "solder mask layer", "signal layer", "power / ground layer", "hybrid layer" and "mask layer". The layer types "power / ground layer", "hybrid layer" and "mask layer" are merged into "other layers", and the layer types "solder paste layer" and "solder mask layer" are merged into "solder layer".
10. The data processing system according to any one of claims 6 to 9, wherein, During the machine learning phase, four features—pad count, line count, arc count, and surface count—that indicate the total number of pads, lines, arcs, and surfaces in the PCB design are used to learn the layer stack.
11. A non-transitory computer-readable medium encoded with executable instructions, which, when executed, cause one or more data processing systems to perform automatic layer classification in preparing PCB design Gerber data to support the design process of printed circuit boards, comprising: A list of Gerber data for process preparation layer stacking tools is provided, the Gerber data including at least a number of electronic layer designs and information related to the presentation of electronic layer designs in printed circuit boards; The list of Gerber data is imported into the process preparation layer stacking tool, and the process preparation layer stacking tool converts the list of Gerber data into manufacturing data, thereby enabling the production of the printed circuit board; wherein: The conversion is supported by a machine learning process that has been executed to train the conversion algorithm; the machine learning process includes multiple training steps, wherein, as a result of the training steps, a predetermined set of Gerber data is automatically identified and converted into corresponding manufacturing data; and The production data generated in this way is used to prepare for the execution of printed circuit board production.
12. The non-transitory computer-readable medium according to claim 11, wherein, The relevant information in the Gerber data includes data related to the context of the electronic layer design in the final PCB, the layer type of the electronic layer design, and the sides.
13. The non-transitory computer-readable medium according to claim 11 or 12, wherein, The conversion algorithm is trained in the first step, wherein a binary classification model is constructed to classify between the following features: board and hole, while the second step is used to train with another multi-class classification model, which is constructed to classify between the following features for the board context: signal layer, silkscreen layer and solder layer.
14. The non-transitory computer-readable medium according to any one of claims 11 to 13, wherein, For the classification of the layer types, a separate model for the layer types has been constructed for the board context. The model classifies the layers among "solder paste layer", "silk screen layer", "solder mask layer", "signal layer", "power / ground layer", "hybrid layer" and "mask layer". The layer types "power / ground layer", "hybrid layer" and "mask layer" are merged into "other layers", and the layer types "solder paste layer" and "solder mask layer" are merged into "solder layer".
15. The non-transitory computer-readable medium according to any one of claims 11 to 14, wherein, during the machine learning phase, four feature pad counts, line counts, arc counts, and surface counts, indicating the total number of pads, lines, arcs, and surfaces in a PCB design, are used to learn the layer stack.