Circuit board and semiconductor package including same

Abstract

A circuit board according to an embodiment includes: a laminated structure including an insulating layer and a wiring layer; a protective layer disposed on the laminated structure; and a bonding portion penetrating the protective layer and electrically connected to the build-up structure, wherein a side surface of the bonding portion includes a portion that does not overlap the protective layer in a horizontal direction and has a reduced inclination angle with respect to an upper surface of the protective layer.

Description

Technical Field

[0001] The embodiments relate to a circuit board and a semiconductor substrate including the circuit board. Background Technology

[0002] With the improvement of electrical / electronic product performance, techniques for arranging a greater number of semiconductor devices on semiconductor packaging substrates of limited size have been proposed and studied. However, since typical semiconductor packages are basically configured to mount a single semiconductor device, there are limitations in achieving the desired performance.

[0003] Therefore, a semiconductor package has recently been provided in which multiple circuit boards are used to arrange multiple semiconductor devices. This semiconductor package has a structure in which multiple semiconductor devices are interconnected on the circuit boards in a horizontal and / or vertical direction. Therefore, the semiconductor package has the advantages of: efficient use of the mounting area of ​​the semiconductor devices, and transmission of high-speed signals through short signal transmission paths between the semiconductor devices.

[0004] In addition, as the number of semiconductor devices and / or the size of each semiconductor device increases in line with the trend of high integration, or as the functional parts of semiconductor devices are divided, semiconductor packaging used in products such as the Internet of Things (IoT), autonomous vehicles, and high-performance servers is conceptually expanding to semiconductor chiplets.

[0005] Therefore, communication between semiconductor devices and / or semiconductor chiplets becomes important, and thus, there is a trend to place an interposer between the semiconductor packaging substrate and the semiconductor device on the motherboard connected to the electronic device.

[0006] Interposers can facilitate communication between semiconductor devices and / or semiconductor chiplets, or they can be used as redistribution layers that gradually increase the width of the circuit pattern from the semiconductor device toward the semiconductor package to interconnect the semiconductor device with the semiconductor package substrate. Therefore, they can be used to facilitate electrical signals between the semiconductor package substrate and the semiconductor device, which have a circuit pattern relatively larger than that of the semiconductor device.

[0007] Meanwhile, the semiconductor packaging substrate and / or interposer used in semiconductor packaging includes: a multilayer structure 100 comprising insulating and wiring layers stacked in a vertical direction, a protective layer disposed on the multilayer structure 100, and a plurality of bonding portions electrically connected to the multilayer structure 100 through the protective layer. Here, the plurality of bonding portions are configured to be formed by performing a plating process as the final step in the manufacturing process of the semiconductor packaging substrate and / or interposer. At this time, differences in plating conditions (such as plating current applied to each bonding portion) may occur during the plating process of the plurality of bonding portions, and therefore, the plurality of bonding portions may have different heights. Therefore, height deviations may occur between the plurality of bonding portions, and semiconductor devices may not be stably disposed on the plurality of bonding portions.

[0008] Additionally, the connecting member can be embedded in the semiconductor package substrate and / or the interposer. In this case, the package substrate and / or the interposer may include multiple junctions connected to the semiconductor device and / or semiconductor chiplet. The junctions may include a first junction that does not overlap with the connecting member in the vertical direction, and a second junction that overlaps with the connecting member in the vertical direction and with the first junction in the horizontal direction.

[0009] At this point, the first and second joints may have different widths in the horizontal direction and / or different thicknesses in the vertical direction. That is, the width and / or thickness of the second joint may depend on the width of the pads included in the connecting member and the height of the upper surface of the pads, but the width and height of the first joint do not depend on the width and / or height of the pads included in the connecting member. In other words, as the integration density of the I / O (input and output) terminals of the connecting member increases, the amount of current generated during plating of the first and second joints differs depending on the diameter and density of the vias in the insulating and / or protective layers provided on the pads of the connecting member, and therefore, the height of the second joint may differ from the height of the first joint.

[0010] Therefore, in related technologies, height deviations may occur among multiple joints due to differences in width and / or thickness. Furthermore, when height deviations occur among multiple joints, problems may arise where semiconductor devices and / or semiconductor chiplets cannot be stably mounted on the multiple joints. Consequently, issues may arise regarding the deterioration of the operating characteristics, reliability, and yield of the semiconductor devices and / or semiconductor chiplets (chiplets). Summary of the Invention

[0011] Technical issues

[0012] The embodiments provide a circuit board with a novel structure and a semiconductor package including the circuit board.

[0013] Additionally, the embodiments provide a circuit board with improved height misalignment between multiple joints and a semiconductor package including the circuit board.

[0014] Additionally, the embodiments provide a circuit board capable of miniaturizing multiple joints and a semiconductor package including the circuit board.

[0015] Furthermore, the embodiments provide a circuit board capable of improving electrical reliability issues that may occur when multiple adjacent coupling components are connected to each other, and a semiconductor package including the circuit board.

[0016] The technical problems to be solved by the proposed embodiments are not limited to those described above, and other technical problems can be clearly understood by those skilled in the art from the embodiments described below.

[0017] Technical solution

[0018] The circuit board according to an embodiment includes: a multilayer structure including an insulating layer and a wiring layer; a protective layer disposed on the multilayer structure; and a joint extending through the protective layer and electrically connected to the multilayer structure, wherein the side surface of the joint includes a portion in which the angle of inclination relative to the upper surface of the protective layer decreases and does not overlap with the protective layer in the horizontal direction.

[0019] Additionally, the side surface of the joint includes a first side surface that overlaps with the protective layer in the horizontal direction, and a second side surface disposed on the first side surface and corresponding to the portion in which the inclination angle relative to the upper surface of the protective layer decreases, wherein the second side surface has a predetermined inclination relative to the first side surface, and wherein the length of the first side surface in the vertical direction is greater than the length of the second side surface in the vertical direction.

[0020] Furthermore, the length of the first side surface in the vertical direction is less than the thickness of the protective layer in the vertical direction.

[0021] Furthermore, the side surface of the protective layer includes an inner surface forming a through hole and an outer surface surrounding the inner surface, wherein the second side surface does not contact the inner surface of the protective layer.

[0022] In addition, the difference between the thickness of the protective layer in the vertical direction and the length of the first side surface in the vertical direction is less than the length of the first side surface in the vertical direction.

[0023] In addition, the difference between the thickness of the protective layer in the vertical direction and the length of the first side surface in the vertical direction is less than the length of the second side surface in the vertical direction.

[0024] In addition, the upper surface of the protective layer includes at least one of a convex portion and a concave portion.

[0025] In addition, the protective layer includes multiple fillers, and each of the multiple fillers does not contact the joint.

[0026] In addition, at least one of the multiple fillers is exposed on the upper surface of the protective layer.

[0027] In addition, the circuit board further includes a connecting member embedded in the multilayer structure, wherein the connecting member overlaps with the side surface of the joint in the vertical direction.

[0028] In addition, at least one of the multiple fillers is in contact with an insulating layer and a wiring layer of a multilayer structure.

[0029] Furthermore, the lower surface of the protective layer includes at least one of a concave portion and a convex portion, and at least one of the insulating layer and the wiring layer of the laminated structure includes a convex portion and a concave portion corresponding to at least one of the concave portion and the convex portion included in the lower surface of the protective layer.

[0030] In addition, the upper surface of the insulating layer includes a groove, the wiring layer is disposed in the groove of the insulating layer, and the joint overlaps with the wiring layer disposed in the groove in the vertical direction.

[0031] In addition, the wiring layers are configured as multiple and spaced apart from each other in a vertical direction. The stacked structure includes multiple through electrodes connecting the multiple wiring layers. The side surfaces of the multiple through electrodes have the same inclination as each other, and the inclination of the second side surface of the junction is in the same direction as the inclination of the side surfaces of the multiple through electrodes.

[0032] In addition, the circuit board further includes connection members embedded in the multilayer structure, and the pad portion of the connection member is electrically connected to the junction via a wiring layer.

[0033] In addition, at least a portion of the second side surface overlaps with the protective layer in the horizontal direction and is spaced apart from the inner surface of the through-hole of the protective layer.

[0034] In addition, the length of the first side surface in the vertical direction is in the range of 1.2 to 3 times the length of the second side surface in the vertical direction.

[0035] Meanwhile, the circuit board according to the embodiment includes: a multilayer structure including an insulating layer and a wiring layer; a protective layer disposed on the multilayer structure; and a joint portion penetrating the protective layer and electrically connected to the multilayer structure. The joint portion includes an upper surface, a lower surface, and a side surface between the upper surface and the lower surface. The side surface of the joint portion includes a first side surface having a first tilt angle relative to the lower surface of the joint portion and a second side surface having a second tilt angle relative to the lower surface of the joint portion that is less than the first tilt angle. The length of the first side surface in the vertical direction is greater than the length of the second side surface in the vertical direction.

[0036] Furthermore, the first side surface completely overlaps the protective layer in the horizontal direction, the second side surface partially overlaps the protective layer in the horizontal direction, and the second side surface includes a portion of the inner surface of the through-hole that overlaps the protective layer in the horizontal direction but does not contact the protective layer.

[0037] In addition, the upper surface of the protective layer includes irregularities.

[0038] In addition, the protective layer includes multiple fillers, and at least one of the multiple fillers contacts at least one of the insulating layer and the wiring layer.

[0039] Beneficial effects

[0040] The embodiment includes a multilayer structure comprising an insulating layer and wiring layers, a protective layer disposed on the multilayer structure, and a bonding portion penetrating the protective layer and electrically connected to the multilayer structure. In this case, the bonding portion can be formed before the multilayer structure in the circuit board manufacturing process. Specifically, the embodiment can prepare a carrier component provided with metal components, and then form the bonding portion on the metal components of the carrier component. Furthermore, after the protective layer covering the bonding portion is laminated onto the metal components of the carrier component, the protective layer can be etched with a chemical solution so that the thickness of the protective layer becomes equal to or less than the thickness of the bonding portion, and thereafter, the multilayer structure stacking process can be performed with the bonding portion and protective layer in place. Therefore, since the bonding portion is formed first in the circuit board manufacturing process, the embodiment can allow multiple bonding portions to have a uniform height. Therefore, the embodiment can allow semiconductor devices to be stably mounted on the bonding portion, and can correspondingly improve the connection reliability between the semiconductor device and the circuit board.

[0041] Additionally, the joint may include a side surface between the upper and lower surfaces. The side surface of the joint may include a first portion that overlaps with the protective layer in a horizontal direction and a second portion that does not overlap with the protective layer in a horizontal direction. In this case, the first side surface of the first portion of the joint may have a first inclination, and the first inclination may be perpendicular to the upper and / or lower surfaces of the joint. In this case, when the first inclination is greater than 90°, it may be difficult to reduce the spacing between multiple joints. Therefore, by setting the first inclination to approximately 90° relative to the lower surface of the joint, the spacing between multiple joints can be reduced while increasing the contact area between the joint and the wiring layer, thereby improving adhesion.

[0042] Furthermore, the second portion of the joint may include a second inclined second side surface having a first inclination different from the first side surface of the first portion, and in particular, may have an inclination such that the width in the horizontal direction increases along the direction from the upper surface of the joint toward its lower surface. In this case, the second side surface of the second portion of the joint is the portion that contacts a coupling member such as solder, and because the second side surface of the second portion of the joint has the aforementioned inclination, the horizontal spacing between the plurality of joints can be increased while maintaining the spacing between the plurality of joints. That is, the embodiment can increase the spacing distance between the second portions of the plurality of joints by using the inclination of the second side surface of the second portion of the joint. Therefore, the embodiment can further prevent electrical short circuit problems caused by two adjacent coupling members connected to each other, and can correspondingly improve the mechanical and / or electrical reliability of the circuit board and semiconductor package.

[0043] Furthermore, the embodiment allows the coupling member to flow obliquely along the second side surface of the second portion of the joint, thereby improving the fluidity of the coupling member. Additionally, the oblique direction of the second side surface of the second portion of the joint can be the same as the oblique direction of the through electrode disposed in the multilayer structure. Therefore, the embodiment can facilitate control of stress applied to the circuit board, and furthermore, can facilitate the design of the thickness, wiring density, and width of the wiring layers and through electrodes to prevent the circuit board from warping in a particular direction.

[0044] Furthermore, the vertical length of the first side surface of the first portion of the joint can be greater than the vertical length of the second side surface of the second portion of the joint. Therefore, the embodiment can allow the joint to be stably protected by the protective layer and can improve the adhesion between the joint and the protective layer and / or wiring layer. For example, when the vertical length of the first side surface of the first portion is less than the vertical length of the second side surface of the second portion, stress may be applied to the joint during the process of etching and removing a portion of the protective layer with a chemical solution, and therefore, the joint may peel off from the wiring layer and / or the protective layer. Therefore, the embodiment can improve the reliability of the joint peeling off from the protective layer and / or wiring layer by setting the vertical length of the first side surface of the first portion of the joint to be greater than the vertical length of the second side surface of the second portion.

[0045] Furthermore, the vertical length of the first side surface of the first portion of the joint can be less than the thickness of the protective layer. That is, the lowermost end of the second side surface of the second portion of the joint can be positioned below the upper surface of the protective layer. At least a portion of the second side surface of the second portion of the joint can overlap the protective layer in the horizontal direction and can be spaced apart from the inner surface of the through-hole in the protective layer. For example, a separation space can be provided between the second side surface of the second portion of the joint and the inner surface of the protective layer. The separation space can act as a dam to block the flow of coupling members applied to the joint. That is, when the coupling members applied to the joint extend in the horizontal direction, the separation space can prevent the coupling members from extending to a location where another adjacent joint is provided, thereby further improving the electrical reliability of the circuit board and / or semiconductor package.

[0046] In this case, the difference between the thickness of the protective layer in the vertical direction and the vertical length of the first side surface of the first portion of the joint can be less than the vertical length of the first side surface of the first portion and / or the vertical length of the second side surface of the second portion. Therefore, in the process of removing a portion of the protective layer, excessive removal of the joint can be prevented, thereby preventing deformation of the joint and the possibility that the semiconductor device may not be stably mounted as the joint does not protrude from the protective layer.

[0047] Furthermore, convex and / or concave portions can be provided on the upper surface of the protective layer. The convex and / or concave portions provided on the upper surface of the protective layer can be used to increase the contact area with the molding components of the molded semiconductor device, thereby improving the adhesion between the protective layer and the molding components.

[0048] Furthermore, the convex and concave portions provided on the upper surface of the protective layer can increase the surface area of ​​the upper surface of the protective layer. Therefore, the embodiment can prevent cracking in the joint due to stress caused by thermal cycling. For example, due to thermal expansion and / or contraction in the manufacturing process and / or operating environment, stress may be applied to the circuit board according to thermal cycling, and this stress may be transmitted to the joint. When stress is continuously applied to the joint, cracks may appear in the joint, thus potentially causing mechanical and / or electrical reliability problems. Furthermore, when the aforementioned stress is applied to coupling members such as solder, cracks may appear in the coupling members, leading to electrical open circuit problems between the semiconductor device and the joint. In this case, the convex and / or concave portions provided on the upper surface of the protective layer increase the surface area and increase the transmission distance of stress acting along the upper surface of the protective layer, thereby minimizing the magnitude of stress transmitted to the joint. Therefore, the embodiment can minimize stress transmission to the joint, thereby allowing the semiconductor device to be stably attached to the circuit board and correspondingly improving the mechanical and electrical reliability between the circuit board and the semiconductor device. Furthermore, the embodiments can allow semiconductor devices to operate stably, thereby improving the operational reliability of electronic products such as servers that utilize semiconductor packaging.

[0049] In addition, at least one filler may be exposed on the upper surface of the protective layer. In this case, the exposed filler can be used to prevent stress acting in the horizontal direction from being transmitted to the joint, thereby further improving the electrical and / or mechanical reliability of the joint.

[0050] Furthermore, at least one filler can be exposed on the lower surface of the protective layer, and the insulating layer disposed on the uppermost side of the laminated structure can contact the filler disposed in the protective layer. In this case, the adhesion between the insulating layer and the filler of the protective layer is better than the adhesion of the resin of the protective layer, thereby further improving the bonding strength between the protective layer and the insulating layer.

[0051] Furthermore, convex and / or concave portions can be provided on the lower surface of the protective layer. Therefore, the upper surface of the insulating layer and / or the upper surface of the wiring layer may include concave and / or convex portions corresponding to the convex and / or concave portions provided on the lower surface of the protective layer. Thus, the embodiments can further improve the adhesion between the protective layer and the insulating layer and / or wiring layer, thereby further improving the mechanical reliability of the circuit board and semiconductor package. Attached Figure Description

[0052] Figure 1a This is a cross-sectional view of a circuit board according to an embodiment.

[0053] Figure 1b This is a view showing the curved portion of the joint according to the prior art.

[0054] Figure 2 This is an enlarged view of region A in FIG1 according to the first embodiment.

[0055] Figure 3a This is an enlarged view of region A in FIG1 according to the second embodiment.

[0056] Figure 3b This is an enlarged view of region A in FIG1 according to the third embodiment.

[0057] Figure 4a This is an enlarged view of region A in FIG1 according to the fourth embodiment.

[0058] Figure 4b This is an enlarged view of region A in FIG1 according to the fifth embodiment.

[0059] Figure 5 This is a cross-sectional view showing a circuit board and a semiconductor package including the circuit board according to the sixth embodiment.

[0060] Figure 6 This is a cross-sectional view showing a semiconductor package according to an embodiment.

[0061] Figures 7 to 17 This is a cross-sectional view illustrating the method of manufacturing the circuit board shown in Figure 1 according to the process sequence. Detailed Implementation

[0062] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0063] However, the spirit and scope of this disclosure are not limited to the portion of the described embodiments and may be implemented in a variety of other forms, and one or more elements of the embodiments may be selectively combined and rearranged within the spirit and scope of this disclosure.

[0064] Furthermore, unless otherwise expressly defined and described, the terms (including technical and scientific terms) used in the embodiments of this disclosure may be interpreted as having the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains, and terms such as those defined in common dictionaries may be interpreted as having a meaning consistent with their meaning in the context of the relevant field. Additionally, the terminology used in the embodiments of this disclosure is for describing embodiments and is not intended to limit the scope of this disclosure.

[0065] In this specification, the singular form may also include the plural form unless specifically stated in the phrase, and when described in “at least one (or more) of A (and), B and C”, it may include at least one of all combinations that can be combined with A, B and C. Furthermore, when describing elements of embodiments of this disclosure, terms such as first, second, A, B, (a) and (b) may be used.

[0066] These terms are used only to distinguish one element from other elements, and these terms are not limited to the nature, order, or sequence of elements. Furthermore, when an element is described as being “connected,” “coupled,” or “in contact” with another element, it can include not only when the element is directly “connected,” “coupled,” or “in contact” with other elements, but also when the element is “connected,” “coupled,” or “in contact” with another element between the element and other elements.

[0067] Furthermore, when described as being formed or positioned “above” or “below” in each element, “above” or “below” can include not only when two elements are directly connected to each other, but also when one or more other elements are formed or positioned between the two elements. Additionally, when expressed as “above” or “below”, it can include not only the upward direction based on a single element, but also the downward direction.

[0068] The terminology used in this application is for describing specific embodiments only and is not intended to limit the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, terms such as “comprising” or “having” specify the presence of features, numbers, steps, operations, components, portions, or combinations thereof described in the specification, and should not be construed as pre-excluding the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, portions, or combinations thereof.

[0069] Unless otherwise defined, all terms used herein, including technical or scientific terms, shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms such as those defined in common dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and shall not be interpreted in an ideal or overly formal sense unless expressly defined in this application.

[0070] In the following description, embodiments will be described in detail with reference to the accompanying drawings, and regardless of the reference numerals in the drawings, the same or corresponding parts will be given the same reference numerals, and redundant descriptions will be omitted.

[0071] Before describing the embodiments, a semiconductor-packaged electronic device (not shown) of the application embodiments will be briefly described. The electronic device may be a smartphone, personal digital assistant, digital video camera, digital still camera, vehicle, high-performance server, network system, computer, monitor, tablet, laptop, netbook, television, videogame, smartwatch, or automotive device, etc. However, the electronic device is not limited to these and may be any other electronic device that processes data.

[0072] The electronic device includes a motherboard (not shown). The motherboard may be physically and / or electrically connected to various components. For example, the motherboard may be connected to a semiconductor package according to an embodiment. Additionally, the semiconductor package includes a circuit board, a semiconductor device, a bonding portion for electrically connecting the semiconductor device and the circuit board, a resin portion filling the space between the semiconductor device and the circuit board, and a molding portion completely surrounding the semiconductor device.

[0073] Semiconductor devices can include active and / or passive devices and can have a variety of functions. Active devices can be in the form of integrated circuits (ICs), in which hundreds to millions or more transistors are integrated into a single semiconductor device, and can be, for example, logic chips, memory chips, etc. For example, a logic chip can be an application processor (AP) device that includes at least one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, a cryptographic processor, a microprocessor, and a microcontroller, or it can be an analog-to-digital converter, an ASIC (application-specific IC), or a set of devices that includes specific combinations of those listed above. Memory chips can be stacked memories such as HBM. In addition, memory chips can include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, etc.

[0074] The semiconductor package of the embodiment can be any of the following, but is not limited to: CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package).

[0075] Figure 1 is a cross-sectional view of a circuit board according to an embodiment. Figure 2 This is an enlarged view of region A in FIG1 according to the first embodiment. Figure 3a This is an enlarged view of region A in FIG1 according to the second embodiment. Figure 3b This is an enlarged view of region A in FIG1 according to the third embodiment. Figure 4a This is an enlarged view of region A in FIG1 according to the fourth embodiment. Figure 4b This is an enlarged view of region A in FIG1 according to the fifth embodiment. Figure 5 This is a cross-sectional view showing a circuit board according to the sixth embodiment and a semiconductor package including the circuit board, and Figure 6 This is a cross-sectional view showing a semiconductor package according to an embodiment.

[0076] In the following, with reference to Figures 1 to 6, a circuit board and a semiconductor package including the circuit board according to an embodiment will be described in detail.

[0077] Referring to FIG1, the circuit board 10 includes a multilayer structure 100, a protective layer 140 disposed on the upper and / or lower surfaces of the multilayer structure 100, and a bonding portion 150 penetrating the protective layer 140 and electrically connected to the multilayer structure 100. The protective layer 140 may include a first protective layer 141 disposed on a first surface of the multilayer structure 100 and a second protective layer 142 disposed on a second surface of the multilayer structure 100, and the bonding portion 150 may be provided to pass through the first protective layer 141 disposed on the first surface of the multilayer structure 100. Here, being disposed on the first and second surfaces does not imply a configuration that directly contacts the first and second surfaces, and should be understood to also include a configuration in which another configuration exists between the first surface of the multilayer structure 100 and the first protective layer 141 and between the second surface of the multilayer structure 100 and the second protective layer 142.

[0078] The multilayer structure 100 includes an insulating layer 110, a wiring layer 120, and a through electrode 130.

[0079] The insulating layer 110 may have a structure in which multiple layers are stacked along a vertical direction. The insulating layer 110 may include a first insulating layer 111 that is closest to the first protective layer 140 or the junction 150 along the vertical direction, a second insulating layer 112 that is further away from the first protective layer 140 or the junction 150 along the vertical direction than the first insulating layer 111, a third insulating layer 113 that is further away from the first protective layer 140 or the junction 150 along the vertical direction than the second insulating layer 112, and a fourth insulating layer 114 that is further away from the first protective layer 140 or the junction 150 along the vertical direction than the third insulating layer 113. In this case, the first insulating layer 111 may refer to the uppermost insulating layer disposed on the uppermost side of the insulating layer 110 having a structure in which multiple layers are stacked, and the fourth insulating layer 114 may refer to the lowermost insulating layer disposed on the lowermost side of the insulating layer 110 having a structure in which multiple layers are stacked. However, the insulating layer 110 is not limited to this, and may also include a fifth insulating layer (not shown) disposed between the fourth insulating layer 114 and the second protective layer 125, a sixth insulating layer (not shown) disposed between the fifth insulating layer (not shown) and the second protective layer 125, etc.

[0080] The first to fourth insulating layers 111, 112, 113, and 114 are configured to provide insulation in the vertical direction between the first to fifth wiring layers 121, 122, 123, 124, and 125, which will be described later. For example, the first to fourth insulating layers 111, 112, 113, and 114 can be formed from a thermosetting insulating material containing inorganic fillers in a resin, and ABF (Ajinomoto Build-up Film) manufactured by Ajinomoto can be used. However, the embodiments are not limited to this, and photoimageable dielectric resin (PID), a photocurable insulating material used to form fine patterns, can be used.

[0081] At least one of the first to fourth insulating layers 111, 112, 113, and 114 may include an insulating material different from the insulating material of at least one of them. For example, at least one of the first to fourth insulating layers 111, 112, 113, and 114 may include a reinforcing member 114R. In one embodiment, the reinforcing member 114R may be glass fiber. In another embodiment, the reinforcing member 114R may be GCP (Glass Core Primer). The reinforcing member 114R may be disposed in at least one of the first to fourth insulating layers 111, 112, 113, and 114 to improve the rigidity of the circuit board 10. The reinforcing member 114R can prevent the circuit board 10 from warping excessively in a certain direction, thereby improving the positional alignment of the wiring layer 120 and the through electrode 130, and improving the electrical and / or mechanical reliability of the circuit board 10 and the semiconductor package. In addition, the reinforcing member 114R increases the rigidity of the circuit board 10, thereby improving the manufacturability in the process of mounting semiconductor devices on the circuit board 10 and increasing product yield. Therefore, the reinforcing member 114R allows the semiconductor device to be stably mounted on the circuit board 10 and to operate stably. This improves the operational reliability of electronic products such as servers using semiconductor packaging. As shown in FIG1, the reinforcing member 114R can be disposed in the fourth insulating layer 114. That is, the circuit board 10 is manufactured with a carrier member (not shown) present, and the fourth insulating layer 114 is the layer furthest from the carrier member. In this case, when the reinforcing member 114R is disposed in the fourth insulating layer 114, warping of the circuit board 10 in a specific direction can be further prevented during the process of removing the carrier member. However, the embodiment is not limited to this, and the reinforcing member 114R can be disposed in insulating layers other than the fourth insulating layer 114. For example, the reinforcing member 114R can be alternately disposed in the first to fourth insulating layers 111, 112, 113, and 114 in the vertical direction, thereby further improving the rigidity of the circuit board 10.

[0082] The wiring layer 120 may include a first wiring layer 121 that is closest to the first protective layer 141 or the junction 150 in the vertical direction, a second wiring layer 122 that is further away from the first protective layer 141 or the junction 150 than the first wiring layer 121, a third wiring layer 123 that is further away from the first protective layer 141 or the junction 150 than the second wiring layer 122, a fourth wiring layer 124 that is further away from the first protective layer 141 or the junction 150 than the third wiring layer 123, and a fifth wiring layer 125 that is further away from the first protective layer 141 or the junction 150 than the fourth wiring layer 124. The wiring layer 120 may have, for example, an ETS (Embedded Trace Substrate) structure to achieve fine patterning. Specifically, among the first to fifth wiring layers 121, 122, 123, 124, and 125, the wiring layer disposed on the uppermost or lowermost side may be embedded in the insulating layer 110. Here, "embedded" means that at least a portion of the side surface of the wiring layer having the ETS structure is covered by the insulating layer 110. The first wiring layer 121 can be embedded in the first insulating layer 111. The first wiring layer 121 is the wiring layer closest to the semiconductor device disposed on the circuit board 10. When the first wiring layer 121 is manufactured using the ETS process, the pads and traces constituting the first wiring layer 121 can be stably protected by the insulating layer, thereby enabling miniaturization of the first wiring layer 121 and increasing circuit integration density. Therefore, electrical connections with the semiconductor device disposed on the circuit board 10 can be more easily achieved, and stable operation of the semiconductor device can be ensured.

[0083] According to an embodiment with an ETS structure, a concave portion recessed toward the lower surface of the first insulating layer 111 can be disposed on the upper surface of the first insulating layer 111, and a first wiring layer 121 can be disposed in the concave portion of the first insulating layer 111. Additionally, a second wiring layer 122 can be disposed in a concave portion disposed on the upper surface of the second insulating layer 112, a third wiring layer 123 can be disposed in a concave portion disposed on the upper surface of the third insulating layer 113, and a fourth wiring layer 124 can be disposed in a concave portion disposed on the upper surface of the fourth insulating layer 114. A fifth wiring layer 125 can protrude below the lower surface of the fourth insulating layer 114. Therefore, as described above, the first to fifth wiring layers 121, 122, 123, 124, and 125 can be miniaturized to improve circuit integration density, protect against contaminants such as external moisture, and improve the reliability of the semiconductor package.

[0084] Each of the first to fifth wiring layers 121, 122, 123, 124, and 125 may include traces for transmitting signals and / or power, and pads for connecting the traces of each wiring layer to other components. For example, referring to FIG1, the first wiring layer 121 and the second wiring layer 122 are connected by a first through electrode 131. In this case, to connect the traces of the first through electrode 131 and the second wiring layer 122, the second wiring layer 122 may include pads connected to the first through electrode 131. In addition, the first wiring layer 121 includes a junction 150 connected to an external component of the multilayer structure 100, such as a semiconductor device, and the junction 150 is connected to the pads of the first wiring layer 121. Although FIG1 only shows the pads of the first wiring layer 121, the first wiring layer 121 may further include traces connecting the plurality of pads shown in FIG1. ​​When the first wiring layer 121 includes traces, a first protective layer 141 must be provided to protect the traces, and in this case, the effect of the structural features of the junction 150 described below can be further maximized.

[0085] The first to fifth wiring layers 121, 122, 123, 124, and 125 can electrically connect to semiconductor devices disposed on the circuit board 10. Each of the first to fifth wiring layers 121, 122, 123, 124, and 125 can be freely designed taking impedance into account. Additionally, a through electrode 130 can be disposed in the insulating layer 110 to connect the first to fifth wiring layers 121, 122, 123, 124, and 125. The through electrode 130 may include first to fourth through electrodes 131, 132, 133, and 134. For example, the first through electrode 131 is disposed between the first wiring layer 121 and the second wiring layer 122, the second through electrode 132 is disposed between the second wiring layer 122 and the third wiring layer 123, the third through electrode 133 is disposed between the third wiring layer 123 and the fourth wiring layer 124, and the fourth through electrode 134 is disposed between the fourth wiring layer 124 and the fifth wiring layer 125. The first to fifth wiring layers 121, 122, 123, 124 and 125 are electrically connected to each other through the first to fourth through electrodes 131, 132, 133 and 134.

[0086] The first to fourth through electrodes 131, 132, 133, and 134 can be formed simultaneously in the process of forming the second to fifth wiring layers 122, 123, 124, and 125. For example, in the process of disposing the second wiring layer 122 below the first wiring layer 121, a via can be formed in the first insulating layer 111 to expose a portion of the first wiring layer 121, and the second wiring layer 122 can be formed together with the first through electrode 131 filling the via of the first insulating layer 111. Therefore, the first through electrode 131 can be considered as a protrusion of the second wiring layer 122. Similarly, each of the second to fourth through electrodes 132, 133, and 134 can be considered as a protrusion of each of the third to fifth wiring layers 123, 124, and 125, and can be connected to another wiring layer disposed thereon.

[0087] Since the first to fifth wiring layers 121, 122, 123, 124, and 125 are stacked sequentially in a vertical direction from the lower surface of the first protective layer 141, the tilt directions of the first to fourth through electrodes 131, 132, 133, and 134 can be the same as each other. For example, each of the first to fourth through electrodes 131, 132, 133, and 134 disposed in the multilayer structure 100 can be tilted such that the width increases toward the second protective layer 142.

[0088] The protective layer 140 may include a first protective layer 141 disposed on the upper surface of the multilayer structure 100 and / or a second protective layer 142 disposed on the lower surface of the multilayer structure 100. The first protective layer 141 may protect the upper surfaces of the first wiring layer 121 and / or the first insulating layer 111 from external moisture or contaminants. Furthermore, when semiconductor devices are mounted on the circuit board 10 using materials such as solder, the first protective layer 141 may prevent short circuits between solders due to the low wettability of the solder. The first protective layer 141 may be formed of a photocurable insulating material (e.g., solder resist). However, embodiments are not limited thereto, and the first protective layer 141 may be formed of the same thermosetting insulating material as the insulating layer 110. The first protective layer 141 may include the same insulating material as the first insulating layer 111, such as ABF manufactured by Ajinomoto.

[0089] The bonding portion 150 passes through the first protective layer 141 and is electrically connected to the multilayer structure 100. For example, the first protective layer 141 may include a through-hole 141H that overlaps with the first wiring layer 121 in the vertical direction, and the bonding portion 150 may be disposed in the through-hole of the first protective layer 141 and electrically connected to the first wiring layer 121. The bonding portion 150 may refer to an electrode having a coupling member (e.g., solder) for bonding with a semiconductor device, and may include a protrusion 152a protruding above the first protective layer 141, such as... Figure 2As shown in the diagram, with the increase in functionality and performance provided by semiconductor devices, the number of I / O terminals included in semiconductor devices also increases. Therefore, as the width and / or spacing of the I / O terminals of semiconductor devices decreases, electrical short circuits may occur due to the contact between multiple coupling members in the process of connecting the I / O terminals of semiconductor devices using coupling members such as solder. Therefore, as the density of terminals in semiconductor devices increases, in order to reduce the amount of solder, a fine bonding process can be performed, such as applying coupling members to the upper surface of the protrusion 152a protruding above the first protective layer 141 of the junction 150 and performing thermal compression bonding (TC bonding). In such a fine bonding process, the junction 150 may include the protrusion 152a as described above to improve the alignment between the semiconductor device terminals and the junction 150.

[0090] The structure of the circuit board 10 described above is merely for explaining embodiments of the present invention, and the technical spirit of the present invention is not limited to the stacked structure of this embodiment.

[0091] For stable mounting of semiconductor devices, the circuit board 10 requires high uniformity of the joints 150. Here, high uniformity refers to the high uniformity between the upper surfaces of the second portions 152 of the plurality of joints 150. The connection reliability between the semiconductor devices and the circuit board 10 is determined based on the high uniformity of the joints 150.

[0092] In a conventional circuit board 10, a manufacturing process is performed in which the bonding portions 150 are finally formed after the fabrication of the multilayer structure 100. In this case, due to process variations in the plating process of the multiple bonding portions 150 and / or differences in the width and / or area of ​​the lower surfaces of the multiple bonding portions 150 in the horizontal direction, the current applied during the plating process may vary, and therefore the plating rate may vary. As a result, the heights among the multiple bonding portions 150 may become uneven. When the heights of the bonding portions 150 are uneven, semiconductor devices may not be stably mounted on the bonding portions 150, and the reliability of the electrical connection between the semiconductor devices and the circuit board 10 may be reduced. For example, when a height deviation of the bonding portions 150 occurs, at least one bonding portion may not be electrically connected to the terminals of the semiconductor device, resulting in an open circuit problem. In addition, when increasing the volume of coupling members, such as solder disposed on the bonding portions 150, to address the open circuit problem, horizontal diffusion of the coupling members may occur due to the pressure applied during the semiconductor device mounting process, resulting in an electrical short circuit problem in which adjacent coupling members are connected to each other.

[0093] To address this issue, in the embodiment, the bonding portion 150 is formed in the manufacturing process of the circuit board 10 before the multilayer structure 100 is formed. For example, a carrier member with a metal layer is prepared, and the bonding portion 150 can be formed on the metal layer of the carrier member. Furthermore, after a first protective layer 141 covering the bonding portion 150 is laminated onto the metal layer of the carrier member, a portion of the first protective layer 141 can be etched by a chemical solution and / or dry etching, such that the first protective layer 141 has a thickness less than or equal to the thickness of the bonding portion 150. Thereafter, with the bonding portion 150 and the first protective layer 141 provided, the process of stacking the multilayer structure 100 can be performed. In this case, each of the plurality of bonding portions 150 may include one surface contacting the metal layer of the carrier member and another surface contacting the multilayer structure 100. The metal layer of the carrier member may have a uniform thickness and may be flat, and therefore, the surfaces of the plurality of bonding portions 150 that contact the metal layer of the carrier member may have a uniform height. Furthermore, one surface of the metal layer of the contact carrier member of the plurality of joints 150 can be used as a bonding surface on which coupling members for mounting semiconductor devices are disposed. Therefore, the height uniformity of the joints 150 can be improved, and the connection reliability between the semiconductor devices and the circuit board 10 can be enhanced.

[0094] Furthermore, the joint 150 can be implemented by filling the through-holes of the dry film resist (DFR) disposed on the metal layer of the carrier member with a conductive material. Therefore, compared to a conventional structure in which through-holes are formed in the first protective layer 141 and then filled with a conductive material, the width and / or spacing of the joint 150 can be further reduced. Thus, circuit integration density can be increased by miniaturizing the width and / or spacing of the joint 150, and electrical short-circuit problems caused by contact between multiple coupling components (e.g., solder) can be solved.

[0095] Usually, such as Figure 1bAs shown, after forming a wiring layer 2 on the upper surface of the insulating layer 1, a protective layer 3 is stacked, and then a bonding portion 4 is formed in the protective layer 3. In this case, to reduce the width and / or spacing of the bonding portion 4, vias are formed in the protective layer 3 by laser processing or exposure processing. Therefore, the side surface of the bonding portion 4 includes a bent portion 5 recessed in the portion adjacent to the wiring layer 2. When the bonding portion 4 has the bent portion 5, cracks may occur due to the load applied to the bent portion 5 of the bonding portion 4 when the semiconductor device is coupled to the circuit board by thermocompression bonding. In contrast, according to the embodiment, the bonding portion 150 is formed before the multilayer structure 100 using a dry film, thereby achieving miniaturization of the bonding portion 150 and eliminating the bent portion that may be formed in the bonding portion 150. Furthermore, in the manufacturing environment and / or operating environment, stress caused by thermal cycling (such as thermal shrinkage and / or thermal expansion) may be applied to the circuit board 10. By eliminating the bent portion, the joint 150 can be more stably protected from the aforementioned stresses, thereby solving the electrical and / or mechanical reliability problems in which the joint 150 is peeled from the multilayer structure 100 or separated from the terminals of the semiconductor device.

[0096] Reference Figure 2The bonding portion 150 may include an upper surface 150T, a lower surface 150B opposite to the upper surface 150T, and a side surface 150S between the upper surface 150T and the lower surface 150B. The lower surface 150B of the bonding portion 150 may contact the upper surface of the first wiring layer 121. The upper surface 150T of the bonding portion 150 may be positioned above the upper surface of the first protective layer 141. The upper surface 150T of the bonding portion 150 may be a bonding surface on which coupling members such as solder are applied for mounting semiconductor devices. The side surface 150S of the bonding portion 150 may be connected between the upper surface 150T and the lower surface 150B of the bonding portion 150. The bonding portion 150 may include a first portion 151 that overlaps with the first protective layer 141 in a horizontal direction and a second portion 152 that does not overlap with the first protective layer 141 in a horizontal direction. The second portion 152 of the joint 150 may include a protrusion 152a that does not overlap with the first protective layer 141 in the horizontal direction and protrudes above the first protective layer 141, and a connecting portion 152b disposed between the protrusion 152a and the first portion 151, the connecting portion 152b having a side surface that overlaps with the first protective layer 141 in the horizontal direction but does not contact the first protective layer 141. The first portion 151 of the joint 150 may refer to the area in the entire region of the joint 150 that includes the side surface 151S that contacts the first protective layer 141, and the second portion 152 may refer to the area in the entire region of the joint 150 where the side surface 152S does not contact the first protective layer 141 and may include the protrusion 152a and the connecting portion 152b. Therefore, the lower surface 150B of the joint 150 may refer to the lower surface of the first portion 151, and the upper surface 150T of the joint 150 may refer to the upper surface of the second portion 152. The side surface 150S of the joint 150 may include a first side surface 151S of a first portion 151 that overlaps with the first protective layer 141 in the horizontal direction and a second side surface 152S of a second portion 152 that does not overlap with the first protective layer 141 in the horizontal direction. In this case, the second side surface 152S of the second portion 152 of the joint 150 may be disposed on the first side surface 151S of the first portion 151 of the joint 150, and may have a predetermined inclination relative to the first side surface 151S of the first portion 151.

[0097] That is, the first side surface 151S of the first portion 151 of the joint 150 can be connected to the lower surface 150B of the joint 150, and can be configured to have a first inclination toward the upper surface 150T of the joint 150. The first side surface 151S of the first portion 151 of the joint 150 can overlap with and contact the first protective layer 141 in the horizontal direction. That is, the first protective layer 141 can include an inner surface forming a through hole 141H and an outer surface surrounding the inner surface of the through hole 141H, and the first side surface 151S of the first portion 151 of the side surface 150S of the joint 150 can contact the inner surface of the first protective layer 141. The first side surface 151S of the first portion 151 of the side surface 150S of the joint 150 can be perpendicular to the lower surface 150B of the joint 150. In other words, the inclination of the first side surface 151S of the first portion 151 of the junction 150 can be closer to 90° than the inclination of each of the first to fourth through electrodes 131, 132, 133, and 134 disposed in the multilayer structure 100. Therefore, when miniaturizing the spacing between the plurality of junctions 150, the contact area between the junction 150 and the first wiring layer 121 can be increased to improve adhesion. For example, when the inclination of the first side surface 151S of the first portion 151 of the junction 150 relative to the lower surface 150B of the junction 150 is greater than 90°, it may be difficult to miniaturize the spacing between the plurality of junctions 150. However, the embodiments are not limited to this, and when ensuring the bonding force between the coupling member of the junction 150 and the upper surface of the second portion 152, the inclination of the first side surface 151S of the first portion 151 can be set to less than 90° to provide a finer bond between the semiconductor device and the multilayer structure 100.

[0098] The second side surface 152S of the second portion 152 of the joint 150 may have a predetermined inclination relative to the first side surface 151S of the first portion 151, and may be disposed between the upper surface 150T of the joint 150 and the first side surface 151S of the first portion 151. That is, the inclination of the second side surface 152S of the second portion 152 may be less than the inclination of the first side surface 151S of the first portion 151. For example, the inclination of the first side surface 151S of the side surface 150S of the joint 150 relative to the lower surface 150B of the joint 150 may be greater than the inclination of the second side surface 152S of the second portion 152 of the joint 150 relative to the lower surface 150B of the joint 150, and may be 90° or less. The second side surface 152S of the second portion 152 of the joint 150 may be inclined such that the width of the joint 150 in the horizontal direction increases along the direction from the upper surface 150T of the joint 150 toward the lower surface 150B. Therefore, the side surface 150S of the joint 150 includes a first side surface 151S with a width that does not change substantially along the direction from the lower surface 150B to the upper surface 150T, and a second side surface 152S inclined to a second portion 152 such that its width decreases along the direction from the lower surface 150B to the upper surface 150T. The second portion 152 of the joint 150 is the portion where coupling members such as solder are applied, and due to the inclination of the second side surface 152S of the second portion 152, the horizontal spacing between the plurality of joints 150 can be increased while maintaining the spacing between the plurality of joints 150. That is, according to the embodiment, by utilizing the inclination of the second side surface 152S of the second portion 152 of the joint 150, the separation distance between the second portions 152 of the plurality of joints 150 can be increased. Therefore, the embodiment can further prevent electrical short-circuit problems caused by the connection between two adjacent coupling members and can improve the mechanical and / or electrical reliability of the circuit board and semiconductor package. Furthermore, the embodiment allows the coupling member to flow along the inclined direction of the second side surface 152S of the second portion 152 of the joint 150, thereby improving the fluidity of the coupling member. Additionally, the inclination direction of the second side surface 152S of the second portion 152 of the joint 150 can be the same as the inclination direction of the through electrode 130 disposed in the laminated structure 100. That is, the inclination direction of the second side surface 152S of the second portion 152 of the joint 150 can be the same as the inclination direction of each of the first to fourth through electrodes 131, 132, 133, and 134.Therefore, the second side surface 152S of the second portion 152 of the joint 150 and each of the first to fourth through electrodes 131, 132, 133 and 134 can be tilted in the same direction, so that the stress applied to the circuit board 10 can be easily controlled. In addition, the thickness, wiring density and width of the wiring layer 121 and the through electrodes 130 can be easily designed to prevent the circuit board 10 from bending in a specific direction.

[0099] At this time, after the carrier member and metal layer are removed in the manufacturing process of the circuit board 10, the second portion 152 of the joint 150 can have the aforementioned inclination in the process of removing a portion of the first protective layer 141 by etching. That is, after the manufacturing process of the circuit board 10 is completed, a process of removing a portion of the first protective layer 141 can be performed, such that the thickness T2 of the first protective layer 141 is less than the thickness T1 of the joint 150, and in this process, a portion of the joint 150 can also be etched together, and therefore, the joint 150 can include a first portion 151 having a first side surface 151S and a second portion 152 having a second side surface 152S with a predetermined inclination relative to the first side surface 151S.

[0100] Furthermore, the thickness T1 of the joint 150 is greater than the thickness T2 of the first protective layer 141; therefore, the joint 150 is configured to protrude onto the first protective layer 141. For example, the joint 150 includes a second portion 152, and the second portion 152 may include a protrusion 152a protruding onto the first protective layer 141. In this case, the vertical length T11 of the first side surface 151S of the first portion 151 of the joint 150 may be different from the vertical length T12 of the second side surface 152S of the second portion 152 of the joint 150. Preferably, the vertical length T11 of the first side surface 151S of the first portion 151 is greater than the vertical length T12 of the second side surface 152S of the second portion 152. In this case, the fact that the vertical length T11 of the first side surface 151S of the first portion 151 is greater than the vertical length T12 of the second side surface 152S of the second portion 152 can mean that, throughout the entire region of the joint 150, the thickness of the area embedded in the first protective layer 141 is greater than the thickness of the area protruding onto the first protective layer 141. Therefore, the joint 150 can be stably protected by the first protective layer 141, and the adhesion between the joint 150 and the first protective layer 141 and / or the first wiring layer 121 can be improved. For example, when the vertical length T11 of the first side surface 151S of the first portion 151 is less than the vertical length T12 of the second side surface 152S of the second portion 152, stress may be applied to the joint 150 during the process of removing a portion of the first protective layer 141 by chemical solution and / or dry etching, and thus the joint 150 may peel off from the first wiring layer 121 and / or the first protective layer 141. Therefore, the embodiment allows the vertical length T11 of the first side surface 151S of the first portion 151 of the joint 150 to be greater than the vertical length T12 of the second side surface 152S of the second portion 152, and thus, the reliability problem of the joint 150 being peeled off from the first protective layer 141 and / or the first wiring layer 121 can be improved.

[0101] Furthermore, the vertical length T11 of the first side surface 151S of the first portion 151 can be between 1.2 and 3 times the vertical length T12 of the second side surface 152S of the second portion 152. If the vertical length T11 of the first side surface 151S of the first portion 151 is less than 1.2 times the vertical length T12 of the second side surface 152S of the second portion 152, the joint 150 may not be adequately protected by the first protective layer 141, and therefore, during the manufacturing process and / or operating environment of the circuit board 10, the joint 150 may peel off from the first protective layer 141 and / or the first wiring layer 121. Furthermore, if the vertical length T11 of the first side surface 151S of the first portion 151 exceeds three times the vertical length T12 of the second side surface 152S of the second portion 152, the vertical length T11 of the first side surface 151S of the first portion 151 may be too large relative to the vertical length T12 of the second side surface 152S of the second portion 152. This may become a factor that increases the thickness T1 of the joint 150. Therefore, when the aspect ratio of the joint 150 is not properly ensured, cracks may occur due to the load during the coupling of the semiconductor device to the joint 150, and it may be difficult to thin the circuit board 10 and / or the semiconductor package.

[0102] Furthermore, the vertical length T11 of the first side surface 151S of the first portion 151 of the joint 150 can be less than the thickness T2 of the first protective layer 141. That is, the uppermost end of the first side surface 151S of the first portion 151 of the joint 150 can be positioned below the upper surface of the first protective layer 141. This can mean that the lowermost end of the second side surface 152S of the second portion 152 of the joint 150 is positioned below the upper surface of the first protective layer 141. In other words, at least a portion of the second side surface 152S of the second portion 152 of the joint 150 can overlap with the first protective layer 141 in the horizontal direction and can be spaced apart from the inner surface of the through-hole 141H of the first protective layer 141. For example, a separation space SS can be provided between the second side surface 152S of the second portion 152 of the joint 150 and the inner surface of the first protective layer 141. The separation space SS can serve as a dam to block the flow of coupling members applied to the joint 150. In other words, when the coupling member applied to the joint 150 extends in the horizontal direction, the separation space SS can prevent the coupling member from extending to the location where another adjacent joint is provided, thereby further improving the electrical reliability of the circuit board and / or semiconductor package.

[0103] At this time, the difference TΔ between the thickness T2 of the first protective layer 141 in the vertical direction and the vertical length T11 of the first side surface 151S of the first portion 151 of the joint 150 can be less than the vertical length T11 of the first side surface 151S of the first portion 151. If the difference TΔ between the thickness T2 of the first protective layer 141 in the vertical direction and the vertical length T11 of the first side surface 151S of the first portion 150 of the joint 150 is greater than the vertical length T11 of the first side surface 151S of the first portion 151, then the joint 150 may be over-removed during the removal of a portion of the first protective layer 141, and therefore the width of the upper surface 150T of the joint 150 in the horizontal direction may become excessively narrow. Furthermore, the difference TΔ between the thickness T2 of the first protective layer 141 in the vertical direction and the vertical length T11 of the first side surface 151S of the first portion 151 of the joint 150 can be less than the vertical length T12 of the second side surface 152S of the second portion 152. If the difference TΔ between the thickness T2 of the first protective layer 141 in the vertical direction and the vertical length T11 of the first side surface 151S of the first portion 151 of the junction 150 is greater than the vertical length T12 of the second side surface 152S of the second portion 152, the junction 150 may not protrude from the first protective layer 141, and therefore the semiconductor device may not be stably mounted on the junction 150.

[0104] according to Figure 3a In one embodiment, an uneven surface may be formed on the upper surface of the first protective layer 141. That is, in one embodiment, the first protective layer 141 may include an insulating material different from the insulating material of the first insulating layer 111, and may be, for example, a solder resist layer. In another embodiment, the first protective layer 141 may include the same insulating material as the first insulating layer 111, and may be, for example, an ABF or PID layer.

[0105] At this time, the first protective layer 141 may include a plurality of fillers 141F. Furthermore, the upper surface of the first protective layer 141 may include irregularities corresponding to the plurality of fillers 141F. For example, the upper surface of the first protective layer 141 may include a convex portion 141T1. The convex portion 141T1 may correspond to the filler 141F disposed in the first protective layer 141. Furthermore, the upper surface of the first protective layer 141 may include a concave portion 141T2. Furthermore, the upper surface of the first protective layer 141 may include a concave portion 141T2 corresponding to the filler 141F disposed in the first protective layer 141. For example, the concave portion 141T2 may be formed during a process in which a portion of the upper surface of the first protective layer 141 is removed by etching, as at least one filler disposed in the first protective layer 141 is removed. That is, the upper surface of the first protective layer 141 may include at least one of the convex portion 141T1 and the concave portion 141T2. Furthermore, the convex portion 141T1 and concave portion 141T2 disposed on the upper surface of the first protective layer 141 can be used to increase the contact area with the molding component of the semiconductor device molded on the first protective layer 141, thereby improving the adhesion between the first protective layer 141 and the molding component.

[0106] Furthermore, the convex portion 141T1 and concave portion 141T2 disposed on the upper surface of the first protective layer 141 can increase the surface area of ​​the upper surface of the first protective layer 141. Therefore, the embodiment can prevent cracks from appearing in the joint 150 due to stress caused by thermal cycling. For example, stress may be applied to the circuit board due to thermal expansion and / or contraction caused by the manufacturing process and / or operating environment, and this stress may be transmitted to the joint 150. When stress is continuously applied to the joint 150, cracks may appear in the joint 150, which may lead to mechanical and / or electrical reliability problems. Furthermore, when the aforementioned stress is applied to coupling members such as solder, cracks may appear in the coupling members, thereby causing an electrical open circuit problem between the semiconductor device and the joint 150. At this time, the concave portion 141T2 and the convex portion 141T1 provided on the upper surface of the first protective layer 141 are used to increase the surface area, thereby increasing the transmission distance of stress acting along the upper surface of the first protective layer 141 and minimizing the magnitude of stress transmitted to the joint 150. Therefore, the embodiment can minimize the transmission of stress to the joint 150, thereby enabling the semiconductor device to be stably attached to the circuit board and improving the mechanical and electrical reliability between the circuit board and the semiconductor device. In addition, the embodiment can allow the semiconductor device to operate stably, thereby improving the operational reliability of electronic products such as servers using semiconductor packaging.

[0107] Additionally, at least one exposed filler 141F1 may be present on the upper surface of the first protective layer 141. In this case, the exposed filler 141F1 can be used to prevent stress acting in the horizontal direction from being transmitted to the joint 150, thereby further improving the electrical and / or mechanical reliability of the joint 150. However, the embodiment is not limited thereto, and the exposed filler 141F1 can be removed by an additional etching process, and thus can be configured as a concave portion 141T2.

[0108] Additionally, at least one filler may be exposed on the lower surface of the first protective layer 141. That is, when performing the manufacturing process of the circuit board 10 described above, in addition to the process of removing the upper surface of the first protective layer 141 by etching, the embodiment may also perform a process of removing the lower surface of the first protective layer 141 by etching. After performing the process of removing the lower surface of the first protective layer 141 by etching, a polishing process may be performed, and thus the lower surface of the first protective layer 141 and the lower surface 150B of the joint 150 may be located on the same plane. At this time, in the process of removing the lower surface of the first protective layer 141 by etching, at least one filler may be exposed on the lower surface of the first protective layer 141, and the filler exposed on the lower surface of the first protective layer 141 may be removed to be positioned on the same plane as the lower surface of the joint 150 in the polishing process. At this time, the filler exposed on the lower surface of the first protective layer 141 may be retained without being completely removed. Therefore, at least a portion of the upper surface of the first insulating layer 111 may contact the filler 141F2 exposed on the lower surface of the first protective layer 141. In addition, at least a portion of the upper surface of the first wiring layer 121 may come into contact with the filler 141F3 exposed on the lower surface of the first protective layer 141.

[0109] In this embodiment, since the process of stacking the first protective layer 141 is performed after the joint 150 is formed, the joint 150 may not contact the filler 141F disposed in the first protective layer 141, but the embodiment is not necessarily limited to this.

[0110] In addition, with Figure 3a The implementation methods differ, depending on Figure 3b In this embodiment, the polishing process performed after etching away the lower surface of the first protective layer 141 can be omitted. In this case, bumps and recesses can be formed on the lower surface of the first protective layer 141. Furthermore, the bumps and recesses formed on the lower surface of the first protective layer 141 can contact the first insulating layer 111 or the first wiring layer 121. In this case, the contact area between the first insulating layer 111 and the first protective layer 141 and / or the contact area between the first protective layer 141 and the first wiring layer 121 can be increased, thereby further improving the bonding strength between them.

[0111] according to Figure 4a The circuit board of the embodiment may further include a barrier layer 160 disposed between the joint 150 and the first wiring layer 121. The barrier layer 160 may be disposed on the first barrier layer 141 and may overlap with the first protective layer 141 in the horizontal direction. The joint 150 and the barrier layer 160 may be provided by filling an opening in the dry film. For example, the embodiment may form the joint 150 by filling a portion of the opening in the dry film, and then form the barrier layer 160 by filling the remaining portion of the opening in the dry film. In this case, the width of the barrier layer 160 in the horizontal direction may correspond to the width of the lower surface of the joint 150 in the horizontal direction. In the process of applying a coupling member, such as solder, to the joint 150, the barrier layer 160 may serve as a barrier to prevent the coupling member from penetrating into the first wiring layer 121. For example, when a coupling member, such as solder, is disposed on the joint 150, the coupling member and the first wiring layer 121 may come into contact with each other due to solder diffusion to form an intermetallic compound, thereby degrading electrical properties or causing cracks due to the brittleness of the intermetallic compound. The barrier layer 160 can prevent the diffusion of coupling components such as solder, thereby preventing the coupling components and the first wiring layer 121 from coming into contact with each other due to solder diffusion.

[0112] Furthermore, when the circuit board 10 and the semiconductor device are coupled by a fine bonding method, such as thermoforming, cracks may appear in the lower portion of the joint 150 that contacts the first wiring layer 121 due to the load generated during bonding. Therefore, a material having a higher modulus than the first wiring layer 121 and / or the joint 150 can be provided between the joint 150 and the first wiring layer 121 to prevent cracking. Such a material can be nickel (Ni), but it can also be provided as a copper layer with a low grain density due to chemical plating. Additionally, the barrier layer 160 can address the cracking problem that occurs when stress caused by the expansion and / or contraction of the first protective layer 141 due to thermal cycling is applied to the bonding portion between the joint 150 and the first wiring layer 121.

[0113] In addition, according to Figure 4b In one embodiment, a barrier layer 170 having a width greater than the width of the joint 150 can be disposed between the joint 150 and the first wiring layer 121. In this case, the barrier layer 170 can be disposed on the lower surface of the first protective layer 141 and the lower surface of the joint 150. The barrier layer 170 can be disposed between the joint 150 and the first wiring layer 121, while having a width greater than the width of the lower surface of the joint 150. When the width of the barrier layer 170 in the horizontal direction is greater than the width of the joint 150 in the horizontal direction, the penetration of coupling components such as solder can be more effectively prevented, thereby further improving the electrical characteristics of the circuit board. At this time, although... Figure 4bThe diagram shows that the width of the barrier layer 170 in the horizontal direction is the same as the width of the first wiring layer 121 in the horizontal direction, but the embodiment is not limited to this. For example, the width of the barrier layer 170 in the horizontal direction may be greater than the width of the lower surface of the joint 150 in the horizontal direction, and may be greater than or less than the width of the first wiring layer 121 in the horizontal direction.

[0114] In addition, according to Figure 5 The circuit board of the embodiment includes a multilayer structure 200, which includes a first wiring layer 210, a first protective layer 220, and a bonding portion 230. The multilayer structure 200 including the first wiring layer 210, the first protective layer 220, and the bonding portion 230 has substantially the same function as the components with the same names shown in Figures 1 to 4, and its redundant description will be omitted.

[0115] Additionally, the connection member 240 can be embedded in the multilayer structure 200 of the circuit board. Recently, with the increasing number of signals to be processed by semiconductor devices, the size of semiconductor devices has tended to increase in area, and this increase in area has led to a decrease in semiconductor device yield. Therefore, there is a trend to divide the semiconductor device into pattern sizes or functional portions, place chiplets on a circuit board, and embed the connection member 240 in the circuit board, the connection member 240 having the function of electrically connecting the chiplets. However, the connection member 240 is not limited to this, and can also connect the semiconductor device to another semiconductor device with different functions, such as a memory.

[0116] The connecting member 240 can be disposed in the insulating layer adjacent to the junction 220 in the multilayer structure 200. In this case, the signal transmission distance between the multiple semiconductor devices 260 and 270 and the connecting member 240 can be reduced, which is beneficial to prevent signal loss. That is, the connecting member 240 is electrically connected between multiple semiconductor devices disposed on the circuit board, and therefore it is advantageous to reduce signal transmission loss by reducing the signal transmission distance when adjacent to multiple semiconductor devices.

[0117] Additionally, the first wiring layer 210 includes wiring electrodes that overlap with the connecting member 240 in the vertical direction. Furthermore, a first coupling member 250 is disposed on the lower surface of the wiring electrodes that overlap with the connecting member 240 in the vertical direction. The first coupling member 250 may be solder, but is not limited thereto. The connecting member 240 includes a pad portion 245, and the pad portion 245 of the connecting member 240 is electrically connected to the wiring electrodes of the first wiring layer 210 via the first coupling member 250.

[0118] Furthermore, a second coupling member 280 may be disposed on the junction 220, and a plurality of semiconductor devices 260 and 270 may be mounted via the second coupling member 280. Each of the plurality of semiconductor devices 260 and 270 may include terminals 265 and 275, and may be electrically connected to the junction 220 via the second coupling member 280.

[0119] In addition, according to Figure 6 In some embodiments, the circuit board described above can be used as an intermediary layer disposed between the semiconductor package substrate and the semiconductor device in a semiconductor package.

[0120] That is, as the terminal density of semiconductor devices increases, the wiring becomes more complex, and thus the thickness of the circuit board increases. As the thickness increases, the yield of the circuit board may decrease. Therefore, the circuit board can be divided into an interposer and a semiconductor packaging substrate 300 for use, and the circuit board can be used not only as a semiconductor packaging substrate 300 but also as an interposer.

[0121] Semiconductor devices 260 and 270 are disposed on the interposer. Multiple semiconductor devices 260 and 270 may be disposed, spaced horizontally from each other on the interposer, but are not limited thereto. For example, semiconductor devices 260 and 270 may be stacked and disposed on the interposer not only horizontally but also vertically. Connecting members 240 electrically connecting semiconductor devices 260 and 270 are disposed in the interposer.

[0122] The connecting member 240 can be used to electrically connect terminals 631 and 641 of semiconductor devices 260 and 270 disposed on the interposer. In this case, the connecting member 240 can be a bridge die. For example, the connecting member 240 may be perpendicularly overlapped with portions of semiconductor devices 260 and 270 disposed on the interposer. Furthermore, the connecting member 240 is electrically connected between a portion of terminal 265 of the first semiconductor device 260 and a portion of terminal 275 of the second semiconductor device 270. The connecting member 240 may comprise the same material as the semiconductor devices, such as silicon, and may also comprise organic materials such as photosensitive resin or thermosetting resin. Multiple semiconductor devices with different functions (such as chiplets divided according to function and / or spacing, or CPU and GPU, or GPU and HBM) can be mounted on a circuit board, and the connecting member 240 can be used to electrically connect multiple semiconductor devices in the horizontal direction.

[0123] The connecting member 240 can be an organic bridge capable of smoothly supplying power from bottom to top while minimizing power loss. In this case, an inorganic bridge including the silicon substrate can be powered via a TSV (Through Silicon Via), but this increases the process cost of TSV processing and reduces product yield. Therefore, the connecting member 240 in this embodiment is preferably an organic bridge.

[0124] A semiconductor packaging substrate 300 is disposed on the lower surface of the interposer. The semiconductor packaging substrate 300 can be electrically connected between the motherboard of an electronic device and the interposer.

[0125] At this time, the third coupling member 310 can be disposed between the interposer and the semiconductor packaging substrate 300, and thus the interposer and the semiconductor packaging substrate 300 can be electrically coupled.

[0126] The method for manufacturing the circuit board shown in Figure 1 will be described below. Figures 7 to 17 This is a cross-sectional view showing the method of manufacturing the circuit board shown in Figure 1 in the order of processes.

[0127] refer to Figure 7 The embodiment can prepare a carrier component 400, which is the base material for manufacturing the circuit board 10. The carrier component 400 may include an insulating component 410 and a metal component 420 disposed on at least one surface of the insulating component 410. Although the figures show the metal component 420 disposed on only one surface of the insulating component 410, the embodiment is not limited thereto. For example, the metal component 420 may be disposed on both surfaces of the insulating component 410, and therefore, the circuit board manufacturing process, described later, can be performed simultaneously on both sides of the insulating component 410. In this case, the metal component 420 can be used as a seed layer for electroplating of the bonding portion 150 for the embodiment. In one embodiment, the metal component 420 may include the same metal material as the metal material of the bonding portion 150. In another embodiment, the metal component 420 may include a metal material different from the metal material of the bonding portion 150. In this case, in the process of finally removing the metal component 420 by etching, only the metal component 420 can be selectively removed without damaging the bonding portion 150. Thereafter, the embodiment can perform a process of stacking a dry film 430 on the lower surface of the metal component 420. At this point, the dry film 430 may include at least one opening 430H. The opening 430H may be configured to correspond to the area in which the joint 150 is disposed on the lower surface of the metal member 420.

[0128] Next, refer to Figure 8 In this embodiment, the process of forming the joint 150 of the opening 430H of the dry film 430 can be performed by using a metal component 420 as a seed layer to perform electroplating.

[0129] Next, refer to Figure 9 The embodiment can perform a process of peeling off the dry film 430. Thereafter, the embodiment can perform a process of stacking a first protective layer 141 covering the joint 150 onto the lower surface of the metal member 420. In this case, the first protective layer 141 can be stacked while completely covering both the side and lower surfaces of the joint 150.

[0130] Next, refer to Figure 10 In this embodiment, a process can be performed to remove a portion of the lower surface of the first protective layer 141 by etching. For example, an embodiment can remove a portion of the first protective layer 141 such that the lower surface of the first protective layer 141 is at least the height of the lower surface of the joint 150. Therefore, the lower surface of the joint 150 can be exposed. In this case, in one embodiment, after performing the process of removing a portion of the first protective layer 141 by etching, a polishing process can be performed such that the lower surface of the first protective layer 141 and the lower surface of the joint 150 are on the same plane. However, the embodiment is not limited to this, and the polishing process can be omitted. Furthermore, when the polishing process is performed, the lower surface of the first protective layer 141 can have the structure of FIG. 3, and when the polishing process is omitted, the lower surface of the first protective layer 141 can have the structure of FIG. 4.

[0131] Next, refer to Figure 11 In this embodiment, the process of forming the first wiring layer 121 connected to the junction 150 can be performed by using a metal component 420 as a seed layer to perform electroplating.

[0132] Next, refer to Figure 12 The embodiment can perform a process of stacking a first insulating layer 111 covering the first wiring layer 121 on the lower surface of the first protective layer 141.

[0133] Next, refer to Figure 13 The embodiment can perform a process of stacking a first through electrode 131 through the first insulating layer 111 and a second wiring layer 122 connected to the first through electrode 131.

[0134] Next, refer to Figure 14 The implementation examples can be repeated. Figure 12 and Figure 13 The process is used to perform the process of forming a multilayer structure 100, which includes a second insulating layer 112, a third insulating layer 113, a fourth insulating layer 114, a third wiring layer 123, a fourth wiring layer 124, a fifth wiring layer 125, a second through electrode 132, a third through electrode 133, a fourth through electrode 134, and a second protective layer 142.

[0135] Next, refer to Figure 15 The embodiment can perform a process to remove the insulating component 410 of the carrier component 400.

[0136] Next, refer to Figure 16 The embodiment can perform a process of removing the metal component 420 by etching.

[0137] Next, refer to Figure 17 In this embodiment, a process can be performed to remove a portion of the upper surface of the first protective layer 141 by etching, such that the upper surface of the first protective layer 141 is positioned below the upper surface of the joint 150. In this case, during the process of etching a portion of the upper surface of the first protective layer 141, a portion of the joint 150 can also be etched and removed. Therefore, the joint 150 can include a first portion 151 and a second portion 152, and the inclination of the first side surface 151S of the first portion 151 and the inclination of the second side surface 152S of the second portion 152 can be different from each other.

[0138] Furthermore, when a circuit board with the features of the above invention is used in IT equipment or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board with the features of the present invention performs a semiconductor packaging function, it can safely protect the semiconductor chip from external moisture or contaminants, and can solve problems of leakage current or short circuits or open circuits between terminals used to supply power to the semiconductor chip. Additionally, when the circuit board is responsible for signal transmission, it can solve noise problems. In this way, a circuit board with the features of the above invention can maintain the stable function of IT equipment or home appliances, enabling the entire product and circuit board to achieve functional integrity or technical interlocking.

[0139] When a circuit board with the features of the above invention is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, or safely protect the semiconductor chip used to control the transportation device from external influences, and solve the problems of leakage current or electrical short circuits or electrical open circuits between terminals used to supply power to the semiconductor chip, thereby further improving the stability of the transportation device. Therefore, the transportation device and circuit board to which this invention is applied can achieve functional integrity or technical interlocking with each other.

[0140] The features, structures, and effects described in the above embodiments are included in at least one embodiment, but are not limited to one embodiment. Furthermore, the features, structures, and effects shown in each embodiment can even be combined or modified by those skilled in the art relative to other embodiments. Therefore, it should be understood that content associated with such combinations and such modifications are included within the scope of the embodiments.

[0141] The description has focused on the embodiments, but it is illustrative only and does not limit the embodiments. Those skilled in the art will understand that various modifications and applications not described above are possible without departing from the essential characteristics of the embodiments. For example, each component specifically represented in the embodiments can be modified and implemented. Furthermore, it should be understood that differences associated with such changes and applications are included within the scope of the embodiments defined in the appended claims.

Claims

1. A circuit board, comprising: A multilayer structure including insulating layers and wiring layers; A protective layer disposed on the laminated structure; as well as It penetrates the protective layer and is electrically connected to the joint of the laminated structure. The side surface of the joint includes a portion in which the angle of inclination relative to the upper surface of the protective layer decreases and does not overlap with the protective layer in the horizontal direction.

2. The circuit board of claim 1, wherein the side surface of the bonding portion includes a first side surface that overlaps with the protective layer in a horizontal direction, and a second side surface disposed on the first side surface and corresponding to the portion wherein the tilt angle relative to the upper surface of the protective layer decreases. The second side surface has a predetermined inclination relative to the first side surface, and The length of the first side surface in the vertical direction is greater than the length of the second side surface in the vertical direction.

3. The circuit board according to claim 2, wherein the length of the first side surface in the vertical direction is less than the thickness of the protective layer in the vertical direction.

4. The circuit board of claim 3, wherein the side surface of the protective layer includes an inner surface forming a through-hole and an outer surface surrounding the inner surface, and The second side surface does not contact the inner surface of the protective layer.

5. The circuit board according to claim 3, wherein the difference between the thickness of the protective layer in the vertical direction and the length of the first side surface in the vertical direction is less than the length of the first side surface in the vertical direction.

6. The circuit board of claim 3, wherein the difference between the thickness of the protective layer in the vertical direction and the length of the first side surface in the vertical direction is less than the length of the second side surface in the vertical direction.

7. The circuit board according to claim 3, wherein the upper surface of the protective layer includes at least one of a convex portion and a concave portion.

8. The circuit board of claim 7, wherein the protective layer comprises a plurality of fillers, and Each of the plurality of fillers does not contact the joint.

9. The circuit board of claim 8, wherein at least one of the plurality of fillers is exposed on the upper surface of the protective layer.

10. The circuit board according to claim 1, further comprising: Connecting members embedded in the layered structure The connecting member overlaps with the side surface of the joint in the vertical direction.

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