Inverter parallel operation wiring error detection method and device

Abstract

The invention relates to the technical field of photovoltaic energy storage power generation, and discloses an inverter parallel operation wiring error detection method and device, and the method comprises the steps: multiplexing a carrier synchronization IO used for eliminating a high-frequency circulating current during the parallel operation of an inverter into a state synchronization IO during the fault detection of a power grid relay and the parallel operation wiring detection; and in combination with IO bus signal interaction and voltage effective value detection at two ends of the relay, accurate identification of wiring errors of a power grid end and a backup end is realized, and the risk of machine damage caused by the wiring errors is effectively avoided. According to the invention, there is no need to add a detection device and a circuit, the system cost and complexity are reduced, the system can adapt to a single-camera and three-camera parallel operation system and a plurality of parallel operation control modes, the detection comprehensiveness and universality are high, machine damage caused by wiring errors can be effectively avoided, and safe and stable operation of the inverter parallel operation system is ensured.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic energy storage power generation technology, specifically to a method and device for detecting inverter parallel wiring errors. Background Technology

[0002] In recent years, with the increasing sophistication of photovoltaic energy storage power generation systems and the continuous optimization of solutions, the expansion of system scale has become an inevitable trend. Therefore, the multi-unit parallel connection scheme of photovoltaic energy storage inverters has emerged and has been widely used in various scenarios.

[0003] However, in the parallel application of multiple photovoltaic energy storage inverters, the accuracy of the wiring at the AC grid end and backup end is crucial. A typical AC parallel wiring diagram is shown in Figure 1. If a phase line L of a device is reversed with the neutral line N, or if the phase sequence of one of the three phase-switching inverters is inconsistent with the others (e.g., L1 and L2 are swapped), forming a loop is equivalent to adding twice the grid voltage to the line impedance. Due to the relatively low line impedance, a huge current will be generated when the grid-side relay GridRly closes, which can easily damage the grid-side relay.

[0004] Therefore, the detection of AC-side parallel wiring in inverters is particularly critical. Currently, mainstream AC-side parallel wiring detection methods have significant limitations: one method uses an external rapid parallel wiring detection device, which can reliably identify faults, but requires dedicated external equipment, increasing system cost and complexity; another method uses grid voltage phase detection to determine if the grid-side phase line L and neutral line N are reversed, but this method is only suitable for single-phase parallel systems, cannot be adapted to three-phase parallel systems, and cannot detect wiring errors at the backup end of the energy storage unit, thus limiting its detection range and applicability. Summary of the Invention

[0005] This invention provides a method and apparatus for detecting inverter parallel wiring errors, which solves the problems of existing technologies requiring additional equipment for inverter parallel wiring detection, having a narrow scope of application, and being incomplete in detection.

[0006] In a first aspect, the present invention provides a method for detecting inverter parallel wiring errors, the method comprising: Pull the parallel synchronization IO low, detect the voltage across each grid relay, perform fault detection on the grid relays of the master and slave machines based on the voltage across each grid relay, and pull the parallel synchronization IO high after the fault detection is passed; Close the main power grid relay to control the main unit to send a preset duty cycle to the IO bus; After detecting the preset duty cycle, the slave's synchronization IO is pulled low, the effective value of the voltage across the slave's mains relay is detected, and wiring fault detection is performed on the slave's mains terminal and backup terminal based on the effective value of the voltage across the slave's mains relay. After the detection is passed, the slave's mains relay is closed, and the slave's synchronization IO is pulled high. Detect the I / O bus input signal and determine whether there is a fault in the parallel wiring based on the input signal.

[0007] This invention provides a method for detecting inverter parallel wiring errors. By multiplexing the carrier synchronization I / O used to eliminate high-frequency circulating current during inverter parallel operation into a status synchronization I / O for grid relay fault detection and parallel wiring detection, and combining I / O bus signal interaction with the detection of the effective voltage value across the relay, accurate identification of wiring errors at both the grid and backup ends is achieved, effectively avoiding the risk of machine damage caused by wiring errors. This application eliminates the need for additional detection devices and circuits, reducing system cost and complexity. It is adaptable to single-phase and three-phase parallel systems and various parallel control modes, offering comprehensive and versatile detection capabilities. It effectively prevents machine damage caused by wiring errors, ensuring the safe and stable operation of the inverter parallel system.

[0008] In one optional implementation, the parallel synchronization IO is pulled low, the voltage across each grid relay is detected, fault detection is performed on the grid relays of the master and slave units based on the voltage across each grid relay, and the parallel synchronization IO is pulled high after the fault detection passes, including: When all inverters are in standby mode, pull the synchronous I / O of the host low; The voltage across the mains relay of the host computer is detected, and fault detection of the mains relay of the host computer is performed based on the voltage across the mains relay of the host computer. If the mains relay is fault-free, then the mains synchronous I / O is pulled high.

[0009] In one optional implementation, the parallel synchronization IO is pulled low, the voltage across each grid relay is detected, fault detection is performed on the grid relays of the master and slave machines based on the voltage across each grid relay, and the parallel synchronization IO is pulled high after the fault detection is passed. The implementation also includes: When all inverters are in standby mode, pull the slave's synchronous IO low; The voltage across the mains relay of the slave device is detected, and fault detection of the mains relay of the slave device is performed based on the voltage across the mains relay of the slave device; If the slave device's power grid relay is fault-free, then the slave device's synchronous IO will be pulled high.

[0010] In one optional implementation, the parallel synchronization IO is pulled low, the voltage across each grid relay is detected, fault detection is performed on the grid relays of the master and slave machines based on the voltage across each grid relay, and the parallel synchronization IO is pulled high after the fault detection is passed. The implementation also includes: After the main and slave power grid relays have completed fault detection, the I / O bus input signal is detected after a first preset time delay. If the I / O bus is high, it is determined that the mains relays of both the master and slave are normal. If the I / O bus is low, it is determined that a slave device's power grid relay has failed.

[0011] In one optional implementation, after detecting the preset duty cycle, the slave's synchronization IO is pulled low, the effective value of the voltage across the slave's mains relay is detected, and wiring fault detection is performed on the slave's mains terminal and backup terminal based on the effective value of the voltage across the slave's mains relay. After the detection passes, the slave's mains relay is closed, and the slave's synchronization IO is pulled high, including: After detecting the preset duty cycle, delay for a second preset time and pull down the slave's synchronous I / O; Detect the effective value of the voltage across the mains relay of the slave device; If the effective value of the voltage across each phase relay is less than the first preset value, it is determined that the wiring of the slave's mains terminal and backup terminal is correct, the slave's mains relay is closed, and the slave's synchronization IO is pulled high; If the effective value of the voltage across any phase of the relay is not less than the first preset value, then the wiring fault of the slave's mains terminal and backup terminal is determined, and the slave's synchronization IO is continuously pulled low.

[0012] In one optional implementation, detecting the I / O bus input signal and determining whether there is a fault in the parallel wiring based on the input signal includes: Detect I / O bus input signals; If the input signal has a preset duty cycle, then it is determined that the grid terminal and backup terminal wiring of all inverters are correct; If the input signal remains low, the parallel wiring is determined to be incorrect.

[0013] In one alternative implementation, the synchronous I / O is controlled using AND logic.

[0014] Secondly, the present invention provides an inverter parallel wiring error detection device, the device comprising: The first detection module is used to pull down the parallel synchronization IO, detect the voltage across each grid relay, perform fault detection on the grid relays of the master and slave based on the voltage across each grid relay, and pull up the parallel synchronization IO after the fault detection is passed. The signal transmission module is used to close the main power grid relay of the host and control the host to send a preset duty cycle to the IO bus; The second detection module is used to pull down the slave's synchronization IO after detecting the preset duty cycle, detect the effective value of the voltage across the slave's mains relay, perform wiring fault detection on the slave's mains terminal and backup terminal based on the effective value of the voltage across the slave's mains relay, close the slave's mains relay after the detection is passed, and pull up the slave's synchronization IO. The fault diagnosis module is used to detect the IO bus input signal and determine whether there is a fault in the parallel wiring based on the input signal.

[0015] This invention provides an inverter parallel wiring error detection device. By multiplexing the carrier synchronization I / O used to eliminate high-frequency circulating current during inverter parallel operation as both a grid relay fault detection device and a status synchronization I / O device for parallel wiring detection, and combining I / O bus signal interaction with the detection of the effective voltage value across the relay, it achieves accurate identification of wiring errors on both the grid and backup sides, effectively avoiding the risk of machine damage caused by wiring errors. This application eliminates the need for additional detection devices and circuits, reducing system cost and complexity. It is adaptable to single-phase and three-phase parallel systems and various parallel control modes, offering comprehensive and versatile detection capabilities. It effectively prevents machine damage caused by wiring errors, ensuring the safe and stable operation of the inverter parallel system.

[0016] Thirdly, the present invention provides an electronic device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the inverter parallel wiring error detection method of the first aspect or any corresponding embodiment described above.

[0017] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to execute the inverter parallel wiring error detection method of the first aspect or any corresponding embodiment described above. Attached Figure Description

[0018] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 This is the inverter parallel wiring diagram; Figure 2This is a schematic diagram of a parallel synchronous I / O bus; Figure 3 This is a flowchart illustrating an inverter parallel wiring error detection method according to an embodiment of the present invention; Figure 4 This is a structural block diagram of an inverter parallel wiring error detection device according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the hardware structure of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] It is understood that before using the technical solutions disclosed in the various embodiments of the present invention, users should be informed of the types, scope of use, and usage scenarios of the personal information involved in the present invention and their authorization should be obtained in accordance with relevant laws and regulations through appropriate means.

[0022] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0023] According to an embodiment of the present invention, an embodiment of a method for detecting inverter parallel wiring errors is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0024] Considering the high-frequency circulating current generated at the switching frequency level during inverter parallel operation, the carrier synchronization I / O pins of each inverter are typically connected in parallel to eliminate this high-frequency circulating current. The specific connection method is shown in Figure 2: all inverter input and output I / O pins are connected to the same I / O bus via isolation conversion chips, and the I / O outputs use AND logic control; that is, when any inverter's I / O output is low, the entire I / O bus is low. It should be noted that the carrier synchronization I / O pins are only enabled in grid-connected and off-grid operating states after the inverters are paralleled. However, during grid relay fault detection and parallel connection detection, they can be temporarily reused as state synchronization I / O pins to achieve multi-machine state coordination during the detection process.

[0025] Based on this, this embodiment provides a method for detecting inverter parallel wiring errors. Figure 3 This is a flowchart of an inverter parallel wiring error detection method according to an embodiment of the present invention, such as... Figure 3 As shown, the process includes the following steps: Step S1: Pull down the parallel synchronization IO, detect the voltage across each grid relay, perform fault detection on the grid relays of the master and slave based on the voltage across each grid relay, and pull up the parallel synchronization IO after the fault detection is passed.

[0026] Specifically, when all inverters are in standby mode, both the master and slave inverters pull their own synchronization I / O low to check the voltage across their respective grid relays, completing a grid relay fault self-check. If the grid relay is fault-free, the master inverter pulls its own synchronization I / O high. The master inverter checks the I / O bus level; if it does not detect a high level on the I / O bus within a timeout, it determines that a grid relay fault exists in a slave inverter and enters a fault state. Step S2: Close the main power grid relay of the host and control the host to send a preset duty cycle to the IO bus.

[0027] Specifically, after all inverter relays pass their self-tests, the master inverter closes its own grid relay and sends a duty cycle (e.g., 75%) on the I / O bus. The slave inverter does not close its own relay. When the slave inverter detects that the I / O bus is at duty cycle, it delays for a period of time, pulls the I / O low, and begins wiring fault detection.

[0028] Step S3: After detecting the preset duty cycle, pull down the slave's synchronization IO, detect the effective value of the voltage across the slave's mains relay, and perform wiring fault detection on the slave's mains terminal and backup terminal based on the effective value of the voltage across the slave's mains relay. After the detection is passed, close the slave's mains relay and pull up the slave's synchronization IO.

[0029] Specifically, the slave device keeps the relay open. After detecting the preset duty cycle signal, it delays and pulls the IO low to collect the effective value of the voltage across its own grid relay. Based on this, it checks the wiring at the grid end and backup end. If the effective value of the voltage across the relay of each phase is <0.4pu, the wiring is qualified, the slave device's relay is closed, and the IO is pulled high. If the effective value of the voltage across the relay of any phase is >0.4pu, a wiring fault is determined, the device enters a fault state, and the IO is continuously pulled low.

[0030] Step S4: Detect the IO bus input signal and determine whether there is a fault in the parallel wiring based on the input signal.

[0031] Specifically, after a certain delay, the host detects the IO bus input signal. If the IO bus input signal is detected to be at the preset duty cycle, it is determined that there is no fault in the parallel connection of the grid end and backup end of all inverters. If the IO bus input signal is detected to be continuously low, a wiring error is reported and the system enters a fault state.

[0032] This invention provides a method for detecting inverter parallel wiring errors. By multiplexing the carrier synchronization I / O used to eliminate high-frequency circulating current during inverter parallel operation into a status synchronization I / O for grid relay fault detection and parallel wiring detection, and combining I / O bus signal interaction with the detection of the effective voltage value across the relay, accurate identification of wiring errors at both the grid and backup ends is achieved, effectively avoiding the risk of machine damage caused by wiring errors. This application eliminates the need for additional detection devices and circuits, reducing system cost and complexity. It is adaptable to single-phase and three-phase parallel systems and various parallel control modes, offering comprehensive and versatile detection capabilities. It effectively prevents machine damage caused by wiring errors, ensuring the safe and stable operation of the inverter parallel system.

[0033] In one optional implementation, step S1 above includes: Step S11: When all inverters are in standby mode, pull down the synchronous IO of the host.

[0034] Specifically, when all inverters are in standby mode (not connected to the grid, not started), the host first pulls its own synchronous IO low. This operation is to uniformly detect the initial state. Since all inverters' synchronous IOs are connected via a bus and controlled by AND logic, the host pulling its own synchronous IO low first avoids its initial signal interfering with the bus state, and at the same time prepares for subsequent feedback of detection results through IO level.

[0035] Step S12: Detect the voltage across the mains relay of the host computer, and perform fault detection on the mains relay of the host computer based on the voltage across the mains relay of the host computer.

[0036] Specifically, the host determines the relay status through voltage data: for example, if the voltage is within the normal no-load range during standby, it indicates that the relay is not stuck or open-circuited; if the voltage is abnormal (such as a short circuit causing the voltage to approach 0, or an open circuit causing the voltage to be abnormally high), then the host directly determines that the relay is faulty.

[0037] Step S13: If the main power grid relay of the host is fault-free, then pull the synchronous IO of the host high.

[0038] Specifically, if the host relay fault detection passes (no fault), its own synchronous IO is pulled high from low level to high level, and the host relay's normal status signal is fed back to the IO bus through the IO level change; if a fault is detected, the IO is kept low level, and the entire machine will be triggered into a fault state, terminating the detection process.

[0039] In an optional implementation, step S1 above further includes: Step S14: When all inverters are in standby mode, pull down the synchronous IO of the slave device.

[0040] Specifically, when all inverters are in standby mode, each slave device synchronously pulls its own synchronization IO to a low level. This operation is consistent with the logic of the master S11, which not only unifies the initial detection state of all devices, but also adapts to the AND logic control rules of the IO bus, avoiding interference from the initial signal of a single slave device with the overall bus state.

[0041] Step S15: Detect the voltage across the mains relay of the slave device, and perform fault detection on the mains relay of the slave device based on the voltage across the mains relay of the slave device.

[0042] Specifically, each slave device independently detects the voltage signal across its own power grid relay using its own voltage sampling module, and determines the relay status based on the voltage data.

[0043] Step S16: If the mains relay of the slave device is fault-free, then pull the synchronous IO of the slave device high.

[0044] Specifically, if the power grid relay fault detection of a slave device passes (no fault), it will pull its own synchronous IO from low level to high level to feed back the normal status signal of its own relay to the IO bus; if a relay fault is detected, it will keep the IO at low level, and will be recognized by the master through the bus signal, triggering the overall fault state.

[0045] In an optional implementation, step S1 above further includes: Step S17: After the fault detection of the main and slave power grid relays is completed, the I / O bus input signal is detected after a first preset time delay.

[0046] Specifically, after the master and all slave devices have completed their respective relay fault detections, the master will not immediately check the I / O bus, but will delay for a first preset time. This delay is to give all devices sufficient time to switch their level states, ensuring that devices that have passed the fault detection have enough time to pull their I / O signals from low to high, avoiding misjudgment by the master due to delayed signal switching from some devices. At the same time, synchronous I / O uses AND logic control, and the bus level can only truly reflect the overall status after all device signals have stabilized.

[0047] In step S18, if the IO bus is at a high level, it is determined that the mains relays of both the master and slave are normal.

[0048] Specifically, if the host detects that the IO bus is high after the delay, and considering the AND logic of the IO bus (if any device's IO is low, the bus is low), it can be inferred that the IOs of all inverters (host + slave) have been pulled high. The prerequisite for the IOs to go high is that their respective relay fault detections have passed. Therefore, it can be directly determined that the grid relays of all devices are fault-free and have passed self-tests, allowing the subsequent wiring test process to proceed.

[0049] Step S19: If the IO bus is low, it is determined that a slave device's power grid relay has failed.

[0050] Specifically, if the host detects that the I / O bus is still low after the delay, since the host has already completed its self-test (pulling the I / O high if there is no fault), the possibility of a host fault causing the bus to be low can be ruled out. Therefore, it can be determined that at least one slave device's relay is faulty (the faulty slave device must keep the I / O low). At this time, the host directly triggers the fault state, terminates subsequent detection, and avoids the participation of faulty devices in parallel operation.

[0051] In one optional implementation, step S3 includes: Step S31: After detecting the preset duty cycle, delay for a second preset time and pull down the slave's synchronous IO.

[0052] Specifically, after the slave device detects the preset duty cycle signal sent by the master on the I / O bus, it first delays for a second preset time before pulling its own synchronization I / O low. The delay is to wait for the master signal to stabilize and avoid false triggering caused by signal jitter; pulling the I / O low is an indicator of entering the wiring detection state, and at the same time, it adapts to the I / O bus AND logic control to ensure that the status signal during the slave device's detection can be accurately fed back to the bus.

[0053] Step S32: Detect the voltage across the mains relay of the slave device.

[0054] Specifically, the slave device uses a built-in voltage sampling module to detect the effective values ​​of the voltages of each phase across its own grid relay. This detection logic can be flexibly adapted to different models: for single-phase inverters, it detects the effective value of a single voltage group; for three-phase inverters, it detects the effective values ​​of all three voltage groups, ensuring that the detection solution fully covers parallel operation scenarios for various single-phase and three-phase inverters.

[0055] Step S33: If the effective value of the voltage across the relay of each phase is less than the first preset value, it is determined that the wiring of the slave's grid terminal and backup terminal is correct, the grid relay of the slave is closed, and the synchronous IO of the slave is pulled high.

[0056] Specifically, if the effective voltage value across each phase relay of the slave device is less than the first preset value (e.g., 0.4 pu), it indicates that there are no errors in the wiring of the slave device's grid terminal and backup terminal (no issues such as reversed phase and neutral wires or incorrect phase sequence). At this time, the slave device closes its own grid relay, officially connects to the parallel system, and pulls the synchronization IO from low level to high, feeding back the correct wiring and ready status to the IO bus.

[0057] Step S34: If the effective value of the voltage across any phase of the relay is not less than the first preset value, then it is determined that there is a wiring fault at the slave's mains terminal and backup terminal, and the slave's synchronization IO is continuously pulled low.

[0058] Specifically, if the effective value of any phase voltage of the slave device is not less than the first preset value (e.g., 0.4 pu), it indicates a wiring error. In this case, the slave device is directly identified as having a wiring fault, enters a fault state, and continuously pulls its own synchronization IO low. Through the bus AND logic control, the master device can quickly identify the fault, preventing damage to the equipment caused by connecting a slave device with incorrect wiring to the system.

[0059] In one optional implementation, step S4 includes: Step S41: Detect the IO bus input signal.

[0060] Specifically, after the master inverter completes its own operations (closing the grid relay and sending a preset duty cycle signal) and waits for the slave inverter to complete the wiring detection, it starts detecting the input signals of the IO bus. At this time, the signal state of the IO bus is a centralized feedback of the wiring detection results of all inverters (especially the slave inverters). Because the bus uses AND logic control, the state of any slave inverter will directly affect the bus level.

[0061] Step S42: If the input signal has a preset duty cycle, then it is determined that the grid terminal and backup terminal wiring of all inverters are correct.

[0062] Specifically, if the master unit detects that the IO bus input signal is its own preset duty cycle, it indicates that all slave units have passed the wiring test: after the slave unit is correctly wired, it will close its own grid relay and pull the synchronization IO high. At this time, all device IOs are at a high level, and the bus resumes the duty cycle signal sent by the master unit. Based on this, it can be determined that the grid terminal and backup terminal wiring of all inverters are correct, the entire unit has passed the test, and it can enter the subsequent parallel operation process.

[0063] Step S43: If the input signal remains at a low level (IO), then the parallel wiring is determined to be incorrect.

[0064] Specifically, if the host continuously detects a low level I / O bus input signal, combined with the I / O bus AND logic control and the premise that the host's own I / O is already high, it can be inferred that at least one slave device has a wiring fault. The faulty slave device needs to continuously pull its own I / O low, causing the bus to be locked to a low level. At this time, the host directly determines that the parallel connection is incorrect, triggers a fault alarm and enters a fault state, terminating the parallel connection process to avoid equipment damage caused by operating with incorrect wiring.

[0065] This embodiment also provides an inverter parallel wiring error detection device, which is used to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0066] This embodiment provides a device for detecting inverter parallel wiring errors, such as... Figure 4 As shown, it includes: The first detection module 41 is used to pull down the parallel synchronization IO, detect the voltage across each grid relay, perform fault detection on the grid relays of the master and slave based on the voltage across each grid relay, and pull up the parallel synchronization IO after the fault detection is passed.

[0067] The signal transmission module 42 is used to close the main power grid relay of the host and control the host to send a preset duty cycle to the IO bus.

[0068] The second detection module 43 is used to pull down the slave's synchronization IO after detecting the preset duty cycle, detect the voltage across the slave's mains relay, perform fault detection on the slave's mains terminal and backup terminal wiring based on the voltage across the slave's mains relay, and pull up the slave's synchronization IO after the detection is passed.

[0069] The fault diagnosis module 44 is used to detect the IO bus input signal and determine whether there is a fault in the parallel wiring based on the input signal.

[0070] The inverter parallel wiring error detection device provided in this embodiment of the invention can execute the inverter parallel wiring error detection method provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects for executing the method. Further functional descriptions of the above modules and units are the same as in the corresponding embodiments described above, and will not be repeated here.

[0071] This invention provides an inverter parallel wiring error detection device. By multiplexing the carrier synchronization I / O used to eliminate high-frequency circulating current during inverter parallel operation as both a grid relay fault detection device and a status synchronization I / O device for parallel wiring detection, and combining I / O bus signal interaction with the detection of the effective voltage value across the relay, it achieves accurate identification of wiring errors on both the grid and backup sides, effectively avoiding the risk of machine damage caused by wiring errors. This application eliminates the need for additional detection devices and circuits, reducing system cost and complexity. It is adaptable to single-phase and three-phase parallel systems and various parallel control modes, offering comprehensive and versatile detection capabilities. It effectively prevents machine damage caused by wiring errors, ensuring the safe and stable operation of the inverter parallel system.

[0072] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention.

[0073] The following is a detailed reference. Figure 5 The diagram illustrates a structural schematic suitable for implementing an electronic device according to embodiments of the present invention. The electronic device may include a processor (e.g., a central processing unit, graphics processor, etc.) 501, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 502 or a program loaded from memory 508 into random access memory (RAM) 503. The RAM 503 also stores various programs and data required for the operation of the electronic device. The processor 501, ROM 502, and RAM 503 are interconnected via a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0074] Typically, the following devices can be connected to I / O interface 505: input devices 506 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 507 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; memory devices 508 including, for example, magnetic tapes, hard disks, etc.; and communication devices 509. Communication device 509 allows electronic devices to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 5 Electronic devices with various devices are shown, but it should be understood that it is not required to implement or have all of the devices shown, and more or fewer devices may be implemented or have instead.

[0075] In particular, according to embodiments of the present invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of the present invention include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 509, or installed from a memory 508, or installed from a ROM 502. When the computer program is executed by the processor 501, it performs the functions defined in the inverter parallel wiring error detection method of the embodiments of the present invention.

[0076] Figure 5 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments of the present invention.

[0077] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the inverter parallel wiring error detection method shown in the above embodiments is implemented.

[0078] A portion of this invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the invention through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0079] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and all such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A method for detecting parallel wiring errors in inverters, characterized in that, The method includes: Pull the parallel synchronization IO low, detect the voltage across each grid relay, perform fault detection on the grid relays of the master and slave machines based on the voltage across each grid relay, and pull the parallel synchronization IO high after the fault detection is passed; Close the main power grid relay to control the main unit to send a preset duty cycle to the IO bus; After detecting the preset duty cycle, the slave's synchronization IO is pulled low, the effective value of the voltage across the slave's mains relay is detected, and wiring fault detection is performed on the slave's mains terminal and backup terminal based on the effective value of the voltage across the slave's mains relay. After the detection is passed, the slave's mains relay is closed, and the slave's synchronization IO is pulled high. Detect the I / O bus input signal and determine whether there is a fault in the parallel wiring based on the input signal.

2. The inverter parallel wiring error detection method according to claim 1, characterized in that, Pull the parallel synchronization IO low, detect the voltage across each grid relay, perform fault detection on the grid relays of both the master and slave units based on the voltage across each grid relay, and pull the parallel synchronization IO high after the fault detection passes, including: When all inverters are in standby mode, pull the synchronous I / O of the host low; The voltage across the mains relay of the host computer is detected, and fault detection of the mains relay of the host computer is performed based on the voltage across the mains relay of the host computer. If the mains relay is fault-free, then the mains synchronous I / O is pulled high.

3. The inverter parallel wiring error detection method according to claim 2, characterized in that, The parallel synchronization IO is pulled low to detect the voltage across each grid relay. Based on the voltage across each grid relay, fault detection is performed on the grid relays of both the master and slave units. After the fault detection passes, the parallel synchronization IO is pulled high. This also includes: When all inverters are in standby mode, pull the slave's synchronous IO low; The voltage across the mains relay of the slave device is detected, and fault detection of the mains relay of the slave device is performed based on the voltage across the mains relay of the slave device; If the slave device's power grid relay is fault-free, then the slave device's synchronous IO will be pulled high.

4. The inverter parallel wiring error detection method according to claim 3, characterized in that, The parallel synchronization IO is pulled low to detect the voltage across each grid relay. Based on the voltage across each grid relay, fault detection is performed on the grid relays of both the master and slave units. After the fault detection passes, the parallel synchronization IO is pulled high. This also includes: After the main and slave power grid relays have completed fault detection, the I / O bus input signal is detected after a first preset time delay. If the I / O bus is high, it is determined that the mains relays of both the master and slave are normal. If the I / O bus is low, it is determined that a slave device's power grid relay has failed.

5. The inverter parallel wiring error detection method according to claim 1, characterized in that, After detecting the preset duty cycle, the slave's synchronization IO is pulled low, the effective value of the voltage across the slave's mains relay is detected, and wiring fault detection is performed on the slave's mains terminal and backup terminal based on the effective value of the voltage across the slave's mains relay. After the detection passes, the slave's mains relay is closed, and the slave's synchronization IO is pulled high, including: After detecting the preset duty cycle, delay for a second preset time and pull down the slave's synchronous I / O; Detect the effective value of the voltage across the mains relay of the slave device; If the effective value of the voltage across each phase relay is less than the first preset value, it is determined that the wiring of the slave's mains terminal and backup terminal is correct, the slave's mains relay is closed, and the slave's synchronization IO is pulled high; If the effective value of the voltage across any phase of the relay is not less than the first preset value, then the wiring fault of the slave's mains terminal and backup terminal is determined, and the slave's synchronization IO is continuously pulled low.

6. The inverter parallel wiring error detection method according to claim 1, characterized in that, Detecting the I / O bus input signal and determining whether there is a fault in the parallel wiring based on the input signal, including: Detect I / O bus input signals; If the input signal has a preset duty cycle, then it is determined that the grid terminal and backup terminal wiring of all inverters are correct; If the input signal remains low, the parallel wiring is determined to be incorrect.

7. The inverter parallel wiring error detection method according to claim 1, characterized in that, The synchronous I / O uses AND logic control.

8. A device for detecting parallel wiring errors in inverters, characterized in that, The device includes: The first detection module is used to pull down the parallel synchronization IO, detect the voltage across each grid relay, perform fault detection on the grid relays of the master and slave based on the voltage across each grid relay, and pull up the parallel synchronization IO after the fault detection is passed. The signal transmission module is used to close the main power grid relay of the host and control the host to send a preset duty cycle to the IO bus; The second detection module is used to pull down the slave's synchronization IO after detecting the preset duty cycle, detect the effective value of the voltage across the slave's mains relay, perform wiring fault detection on the slave's mains terminal and backup terminal based on the effective value of the voltage across the slave's mains relay, close the slave's mains relay after the detection is passed, and pull up the slave's synchronization IO. The fault diagnosis module is used to detect the IO bus input signal and determine whether there is a fault in the parallel wiring based on the input signal.

9. An electronic device, characterized in that, include: The system includes a memory and a processor, which are interconnected. The memory stores computer instructions, and the processor executes the computer instructions to perform the inverter parallel wiring error detection method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to execute the inverter parallel wiring error detection method according to any one of claims 1 to 7.

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