High-resolution azimuth parallel detection device

Abstract

The invention belongs to the technical field of space environment detection, and relates to a high-resolution azimuth angle parallel detection device, which comprises an anode assembly, a front placing plate and a digital acquisition processing plate, and is characterized in that the anode assembly comprises a top anode plate and a bottom anode plate which are stacked up and down and are divided into a plurality of anode sectors, and anodes on the upper and lower layers are arranged in a staggered manner; the adjacent anodes are positioned on different anode plates to realize physical isolation and suppress crosstalk, each anode output is connected in series with a current-limiting resistor, and a charge signal output by each anode is transmitted to a front amplifier plate through an inter-plate connector; the preamplifier adopts an integrated charge sensitive amplifier, amplifies multiple paths of charge signals output by the anode assembly, outputs multiple paths of digital pulses, and inputs the digital pulses to the digital acquisition and processing board through an inter-board connector; and the digital acquisition processing board performs parallel detection counting on multiple paths of digital pulses output by the pre-amplification board according to scientific data acquisition logic, avoids an electromagnetic interference time period, and periodically packs and outputs the digital pulses to a PC (Personal Computer) end.

Description

[0001] This application claims priority to Chinese Patent Application No. 2025101041558, filed on January 23, 2025, entitled "An ASIC-based Multichannel Parallel Charge Detection Device for Space Charged Particle Detection", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention belongs to the field of space environment detection technology, and in particular relates to a high-resolution azimuth parallel detection device. Background Technology

[0003] Space charged particle detectors are an important component of space environment detectors. Their detection principle involves measuring data such as the energy, direction, and flux of charged particles in the space environment, and then analyzing and calculating these data to derive space environment parameters. Most particle receivers in space particle detectors use semiconductor sensors, whose output is a weak charge signal. The detector's signal processing circuitry cannot directly measure this signal; therefore, a charge-sensitive amplifier is used to amplify it. After amplification, a digital acquisition circuit detects and counts the pulses.

[0004] A typical charged particle measurement sensor comprises: a pitch deflection system, an electrostatic analyzer system, a microchannel plate gain amplification system, and an anode plate counting system. Direction measurement is a crucial detection element for space charged particle detectors, with directional parameters including azimuth and pitch angles. The azimuth measurement method involves: charged particles passing through a grid, being deflected by the pitch deflection system, entering the electrostatic analyzer system for energy filtering, and then being output to the microchannel plate gain amplification system. This system performs primary amplification before outputting to the anode receiver on the anode plate. The anode receiver is typically a ring anode divided into N distinct sectors, each representing a specific azimuth region. Each anode sector output is connected to a charge-sensitive amplifier, which amplifies the received charge. A digital acquisition circuit then detects and counts the pulses, ultimately achieving azimuth detection.

[0005] The accuracy of azimuth detection is mainly determined by the angles divided by the annular anode plane.

[0006] Current anode plate designs use a single printed circuit board to design multiple anodes. Due to the small anode area and close proximity of adjacent anodes, issues such as… Figure 2 The problem of crosstalk interference is shown; in addition, the charge-sensitive amplifier connected to the anode sector output previously used discrete anodes, and the detectors were relatively large in size and weight, resulting in low azimuth measurement accuracy. Summary of the Invention

[0007] To address the shortcomings of existing technologies, such as significant anode crosstalk, low detector sensitivity, large size and weight, and susceptibility to crosstalk interference between adjacent anodes, a high-resolution azimuth parallel detection device is proposed. For example... Figure 1 The anode design features a double-layer stacked configuration, with the microchannel board, top anode, and bottom anode tightly bonded together. Adjacent anodes are located on different printed circuit boards on the upper and lower layers, achieving physical isolation through a cross-anodine design, effectively avoiding crosstalk between channels. An integrated charge-sensitive amplifier is also incorporated, containing 16 channels to amplify the signals from all 16 anodes.

[0008] In view of this, the present invention proposes a high-resolution azimuth parallel detection device, comprising: an anode assembly, a preamplifier board, and a digital acquisition and processing board, wherein signal transmission is performed between the anode assembly and the preamplifier board, and between the preamplifier board and the digital acquisition and processing board, using board-to-board connectors. The anode assembly includes a top anode plate and a bottom anode plate stacked one on top of the other. Both the top anode plate and the bottom anode plate are divided into multiple anode sectors. The anodes of the two layers are arranged alternately, and adjacent anodes are located on different anode plates to achieve physical isolation and suppress crosstalk. Each anode output is connected in series with a current-limiting resistor, and the charge signal of each anode output is transmitted to the front amplifier board through the board-to-board connector. The preamplifier board uses an integrated charge-sensitive amplifier to amplify the multiple charge signals output by the anode assembly and output multiple digital pulses to the digital acquisition and processing board via the board-to-board connector. Each input path of the integrated charge-sensitive amplifier is designed with overload input protection. The digital acquisition and processing board, following scientific data acquisition logic and avoiding periods of electromagnetic interference, performs parallel detection and counting of multiple digital pulses output from the preamplifier board, and periodically packages and outputs them to the PC.

[0009] As an improvement to the above device, both the top anode plate and the bottom anode plate are divided into multiple sector anodes, and a grounding network is laid between and below each anode. Each anode output is connected in series with a 20Ω current-limiting resistor.

[0010] As an improvement to the above-mentioned device, the number of sector anodes is 48, and each anode covers an azimuth angle of 7.5°.

[0011] As an improvement to the above device, the preamplifier board uses three integrated charge-sensitive amplifiers, each with 16 preamplifier channels; it supports parameter configuration via the SPI communication interface, including the threshold value of each charge-sensitive amplification channel, the test signal amplitude, and enable / disable control; the clock signal for SPI communication and the clock signal for the test signal are shared in a time-division multiplexing manner.

[0012] As an improvement to the above device, the integrated charge-sensitive amplifier has a built-in test signal circuit. The test signal is applied in the following way: each excitation is applied to only one charge-sensitive amplifier channel, and test pulses are injected into each channel in a sequential cycle to measure the response of each channel and the crosstalk between channels.

[0013] As an improvement to the aforementioned device, the digital acquisition and processing board includes: an FPGA, an SRAM, and an EEPROM; wherein, The FPGA includes a high-voltage output control module, a charge-sensitive amplifier configuration module, a scientific data acquisition module, a key telemetry acquisition module, an electromagnetic interference suppression module, a multi-element data arrangement and packaging processing module, and an external communication module. The FPGA performs unified time management according to the scientific data acquisition logic, coordinates the periodic work of each module of the FPGA, counts the multiple digital pulses input from the preamplifier board according to the scientific data acquisition logic in each working cycle, arranges the data according to different parameters and packages it into SRAM, and outputs the count value to the PC for analysis and processing at the end of the working cycle. The SRAM is used to cache the pulse count; The EPROM is used to store configuration parameters of the detection device, which can be updated on-orbit via ground commands.

[0014] As an improvement to the above-mentioned device, the FPGA suppresses electromagnetic interference by controlling the high-voltage scanning output and the timing of scientific data acquisition. Specifically, it includes: waiting for a set time after each high-voltage switch before starting scientific data acquisition, and stopping scientific data acquisition before the next high-voltage switch begins, so that the scientific data acquisition period effectively avoids the electromagnetic interference generated by the high-voltage switch; the scientific data acquisition includes scanning detection of elevation angle, energy and azimuth angle. The high-voltage scanning output method is as follows: taking the high voltage of the electrostatic analyzer as the reference high voltage, the first deflection high voltage, the second deflection high voltage, and the geometric factor high voltage are output in combination according to the geometric relationship with the high voltage of the electrostatic analyzer. The high voltage of the electrostatic analyzer is output in an up-and-down cyclic scanning mode, and the high voltage is increased by odd steps and decreased by even steps to avoid the introduction of electromagnetic interference by excessive high voltage jump amplitude.

[0015] As an improvement to the above-mentioned device, the scientific data acquisition logic includes: dividing each working cycle into multiple different working units, sequentially controlling the first deflection high voltage, the second deflection high voltage, the geometric factor high voltage and the electrostatic analyzer high voltage to perform scanning output, and sequentially completing the scanning detection of pitch angle, azimuth angle and energy; when the working cycle ends, the multi-element data arrangement and packaging processing module groups the data according to pitch angle, energy and azimuth angle.

[0016] As an improvement to the above device, the FPGA controls the integrated charge-sensitive amplifier via SPI communication, configuring the threshold of the charge-sensitive amplifier channel, the amplitude of the test signal, and enable / disable.

[0017] As an improvement to the above-mentioned device, the inter-board connector between the front amplifier board and the anode plate assembly adopts a stacked and raised design to compensate for the thickness difference of the double-layer anode plates; the front amplifier board adopts equal-length wiring to ensure that the signal lines output by the top anode and the bottom anode plate are of equal length; a grounding point is set on the front amplifier board near the integrated charge-sensitive amplifier and connected to the metal shell of the detection device through a wire to form an electromagnetic shielding structure.

[0018] Compared with the prior art, the advantages of the present invention are: 1. The present invention adopts a double-layer cross anode design, which physically separates adjacent anodes and can effectively avoid the problem of crosstalk / interference between channels.

[0019] 2. This invention utilizes an integrated charge-sensitive amplifier circuit array to achieve multi-channel parallel detection, thereby realizing the miniaturization of the detector.

[0020] 3. The digital acquisition and processing board of the present invention integrates the scientific data acquisition logic with the high-voltage output control module, which effectively avoids electromagnetic interference and improves the anti-interference capability of charge sensitive amplification. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the upper and lower anode design; Figure 2 This is a crosstalk phenomenon between adjacent azimuth angles; Figure 3 It is the test signal output logic Figure 4 It is a block diagram of modular circuit design; Figure 5 This is the circuit block diagram of the preamplifier board; Figure 6 This is a schematic diagram of an integrated charge-sensitive amplifier circuit. Figure 7 This is a block diagram of the circuit schematic of the digital acquisition and processing board; Figure 8 It is the azimuth response curve; Figure 9 This is a high-voltage scanning output curve. Figure 10 This is a diagram illustrating the time periods for scientific data collection. Detailed Implementation

[0022] This invention discloses a high-resolution azimuth parallel detection device, comprising: an anode assembly consisting of a top anode and a bottom anode stacked vertically, a front-amplifier board, and a digital acquisition and processing board, wherein signal transmission is performed between the top anode and the bottom anode and the front-amplifier board, and between the front-amplifier board and the digital acquisition and processing board, using board-to-board connectors. Multiple sector anodes are designed on the top anode. The middle of the adjacent anodes of the top anode is hollowed out to expose the bottom anode, which can realize that the receiving anodes below the MCP are staggered. Grounding is laid between each anode to avoid electromagnetic interference. A current limiting resistor is connected in series at the output. The charge signal output by each anode is transmitted to the front amplifier board through the board connector. Multiple sector anodes are designed on the bottom anode, and the bottom anodes and top anodes are arranged alternately. The hollowed-out position of the top anode is aligned with the bottom anode. Grounding is laid between each bottom anode to avoid electromagnetic interference. A current-limiting resistor is connected in series at the output. The charge signal output by each anode is transmitted to the front amplifier board through the board-to-board connector. In one embodiment, 24 anodes are designed on both the top and bottom anode plates. The anodes are arranged vertically and horizontally, with copper laid between adjacent anodes and below the anodes, and a GND network laid to prevent electromagnetic interference and crosstalk. Each anode output is connected in series with a current-limiting resistor, and the charge signal output by each anode is transmitted to the front-end board through an inter-board connector. The thickness of both the top and bottom anode plates is 1mm. The two anode plates are tightly bonded together, and the center position is supported by a polyimide pillar and fixed together with the structure to prevent uneven stress on the printed circuit board from causing deformation.

[0023] The preamplifier board uses an integrated charge-sensitive amplifier to amplify the multiple charge signals output from the anode plate and output multiple digital pulses to the digital acquisition and processing board via the inter-board connector. Each input path of the integrated charge-sensitive amplifier is designed with input protection. In one embodiment, four inter-board connectors are arranged above the preamplifier board. Two of them interact with the digital acquisition and processing board, while the other two interact with the top anode and bottom anode boards, respectively. The inter-board connector interacting with the top anode board is raised by 1mm using a lamination mechanism to compensate for the distance difference between the inter-board connectors of the two anode layers. Simultaneously, equal-length wiring is used on the preamplifier board to ensure that the signal lines output from the top and bottom anode boards are of equal length. To avoid external electromagnetic interference, a grounding point is placed near the integrated charge-sensitive amplifier on the preamplifier board. A wire connects the detector's internal ground to the detector's metal structure, creating an electromagnetic shielding effect on the detector's metal casing, effectively preventing electromagnetic radiation interference from the outside.

[0024] The integrated charge-sensitive amplifier has a parameter modulation SPI communication interface, a threshold register, and a built-in test signal circuit. The threshold of the charge-sensitive amplifier, the amplitude of the built-in test signal, the test signal enable, and the test signal disable can be configured through SPI communication. The threshold of the integrated charge-sensitive amplifier includes a threshold register with 16 channels. The threshold of each of the 16 channels can be adjusted independently or set uniformly.

[0025] The SPI communication interface is a point-to-point master-slave communication, transmitting data bit by bit. The integrated charge-sensitive amplifier serves as the standby device, and the controller on the digital acquisition and processing board serves as the master device. The communication signals include: master output chip select signal CS, master output clock signal SCLK, master output data signal MOSI, and standby data output signal MISO. SPI communication constraints: at the start of communication, the clock signal SCLK strobe signal RST_STIM is set to low level; the clock signal SCLK is only valid during the communication period; the chip select signal CS goes low, and during idle periods, the chip select is high. This method can effectively avoid bit misalignment in SPI communication.

[0026] The test signal shares the same clock signal SCLK. Therefore, when enabling the test signal, the SCLK strobe signal RST_STIM is set to a high level. The frequency of the test signal is the same as that of the SCLK clock signal, and the amplitude is the value configured in the parameters. The test logic is as follows: Figure 3 As shown, the test signal is injected into only one charge-sensitive amplifier channel at a time. The excitation pulse is injected into 16 channels in a cyclic manner. This test logic can effectively measure the crosstalk of the integrated charge-sensitive amplifier.

[0027] The digital acquisition and processing board, following scientific data acquisition logic, avoids periods of significant electromagnetic interference and enables each working unit to perform parallel detection and counting of multiple digital pulses output from the preamplifier board, periodically packaging and outputting them to the PC.

[0028] The scientific data acquisition logic divides each work cycle into multiple different work units, sequentially completing the scanning and detection of pitch angle and energy, and packaging the data after the detection is completed.

[0029] The scientific data acquisition logic and the high-voltage output control module are designed in conjunction to effectively avoid electromagnetic interference. That is, after each minimum working unit starts, the high voltage needs to be set first. During the high voltage switching process, the charge sensitive amplifier will have significantly increased noise due to electromagnetic interference. The digital acquisition board needs to start counting the output pulses of the charge sensitive amplifier only after the high voltage output is stable.

[0030] Preferably, the digital acquisition and processing board includes an FPGA, SRAM, and EEPROM. The FPGA comprises a high-voltage output control module, a charge-sensitive amplifier configuration module, a scientific data acquisition module, a key telemetry acquisition module, an electromagnetic interference suppression module, a multi-element data arrangement and packaging processing module, and an external communication module. The FPGA performs unified time management according to the scientific data acquisition logic, coordinating the periodic operation of each module within the FPGA. Within each working cycle, it counts the multiple digital pulses input from the preamplifier board according to the scientific data acquisition logic. Each smallest working unit needs to count the multiple pulses from the charge-sensitive amplifier array. After the unit ends, the data is stored in the FPGA's internal BRAM. After multiple probes are completed, the data in the BRAM is transferred to the external SRAM. At the end of the work cycle, the count values ​​are packaged and output to the PC for analysis and processing. The scientific data acquisition logic includes: dividing each work cycle into multiple different work units, and sequentially controlling the first deflection high voltage, the second deflection high voltage, the geometric factor high voltage, and the electrostatic analyzer high voltage to scan and output, thereby completing the scientific data acquisition, including: elevation angle, azimuth angle, and energy scanning and detection; when the work cycle ends, the multi-element data arrangement and packaging processing module groups and processes the data according to elevation angle, energy, and azimuth angle.

[0031] FPGA suppresses electromagnetic interference by controlling the high-voltage scanning output and the timing of scientific data acquisition. Specifically, it waits a set time after each high-voltage switch before starting scientific data acquisition, and stops scientific data acquisition before the next high-voltage switch, so that the scientific data acquisition period effectively avoids electromagnetic interference caused by high-voltage switching. The high-voltage scanning output method is as follows: the high voltage of the electrostatic analyzer is used as the reference high voltage. The first deflection high voltage, the second deflection high voltage, and the geometric factor high voltage are output in combination according to the geometric relationship with the high voltage of the electrostatic analyzer. The high voltage of the electrostatic analyzer is output in an up-and-down cyclic scanning mode, and the high voltage is increased by odd steps and decreased by even steps to avoid the introduction of electromagnetic interference by excessive high voltage jump amplitude.

[0032] The SRAM is used to cache pulse counts.

[0033] The EEPORM is used to store configuration parameters of the detection device, which can be updated on-orbit via ground commands.

[0034] Preferably, the FPGA simultaneously controls the integrated charge-sensitive amplifier via SPI communication and configures the threshold parameters of the integrated charge-sensitive amplifier.

[0035] Preferably, the digital acquisition and processing board includes a crystal oscillator and a refresh circuit, wherein the crystal oscillator is used to provide a 20MHz clock signal to the FPGA; and the refresh circuit is used to refresh the configuration signals of the FPGA.

[0036] Preferably, the digital acquisition and processing board communicates with the PC via an RS422 bus.

[0037] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0038] Example An embodiment of the present invention provides a high-resolution azimuth parallel detection device.

[0039] This invention adopts a modular design, such as Figure 4 As shown, the anode circuit, charge-sensitive amplifier circuit, and digital acquisition and processing circuit within the detection device are divided into four printed circuit boards: the top anode board, the bottom anode board, the preamplifier board, and the digital acquisition and processing board. Signal transmission between the four boards is achieved through inter-board connectors, and physical isolation is used to prevent interference from digital signals on the weak charge signal output by the anode.

[0040] like Figure 4 As shown, in one embodiment, the top anode and bottom anode are designed with 48 anodes, each covering an azimuth angle of 7.5°, and each anode output is connected in series with a 20Ω current-limiting resistor. The charge signal output by each anode is transmitted to the front amplifier board through the board-to-board connector.

[0041] The preamplifier board needs to amplify the charge signal output from the anode, and the amplified signal outputs a digital pulse to the digital acquisition and processing board. To amplify minute charge signals, a high-sensitivity preamplifier is required; to achieve instrument miniaturization and low power consumption, discrete components should be avoided. Figure 5 As shown, in one embodiment, three ASICs are used, each with 16 preamplifiers. The circuit principle of each ASIC is as follows. Figure 6 As shown.

[0042] The digital acquisition and processing board performs parallel detection and counting of the digital pulses output from the preamplifier board, and periodically packages and outputs them. For example... Figure 7 As shown, the digital acquisition and processing board includes FPGA (Field-Programmable Gate Array) minimum unit circuitry, SRAM (Static Random Access Memory), and EEPROM (Electrically Erasable Programmable Read-Only Memory). The FPGA operates periodically, such as... Figure 9 Control the high voltage up and down scanning, such as Figure 10The collaborative scientific data acquisition module suppresses electromagnetic interference. In each working cycle, it counts the digital pulses input to the preamplifier board and packages the data into SRAM. At the end of the working cycle, it packages the count value and outputs it to the PC for analysis and processing. The FPGA controls the ASIC through SPI communication to configure parameters such as the ASIC threshold. The SRAM in the detection device is used to buffer the pulse count, and the EEPROM is used to store the configuration parameters of this detection device.

[0043] By employing a high-resolution parallel azimuth detection device, charge is sequentially injected onto 48 anodes, and the output data is analyzed to obtain azimuth measurement data, such as... Figure 8 The test curves for 48 azimuth angles are shown. The device of this invention can achieve an azimuth angle resolution of 7.5°.

[0044] The device of this invention improves the azimuth angle detection accuracy from 22.5° to 7.5°, and the integrated charge-sensitive amplifier weighs only 1 / 3 of the discrete charge-sensitive amplifier. Using this invention reduces the detector weight by 60g and the single-unit power consumption by 1W. Specific parameter comparisons are shown in Table 1: Table 1

[0045] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to the embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of the present invention do not depart from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A high-resolution parallel azimuth detection device, characterized in that, include: The anode assembly, the preamplifier board, and the digital acquisition and processing board are equipped with board-to-board connectors for signal transmission between the anode assembly and the preamplifier board, as well as between the preamplifier board and the digital acquisition and processing board. The anode assembly includes a top anode plate and a bottom anode plate stacked one on top of the other. Both the top anode plate and the bottom anode plate are divided into multiple anode sectors. The anodes of the two layers are arranged alternately, and adjacent anodes are located on different anode plates to achieve physical isolation and suppress crosstalk. Each anode output is connected in series with a current-limiting resistor, and the charge signal of each anode output is transmitted to the front amplifier board through the board-to-board connector. The preamplifier board uses an integrated charge-sensitive amplifier to amplify the multiple charge signals output by the anode assembly and output multiple digital pulses to the digital acquisition and processing board via the inter-board connector; The digital acquisition and processing board, following scientific data acquisition logic and avoiding periods of electromagnetic interference, performs parallel detection and counting of multiple digital pulses output from the preamplifier board, and periodically packages and outputs them to the PC.

2. The high-resolution azimuth parallel detection device according to claim 1, characterized in that, Both the top anode plate and the bottom anode plate are divided into multiple sector anodes, and a grounding network is laid between and below each anode. Each anode output is connected in series with a 20Ω current-limiting resistor.

3. The high-resolution azimuth parallel detection device according to claim 2, characterized in that, The sector has 48 anodes, each covering an azimuth angle of 7.5°.

4. The high-resolution azimuth parallel detection device according to claim 1, characterized in that, The preamplifier board uses three integrated charge-sensitive amplifiers, each with 16 preamplifier channels; it supports parameter configuration via SPI communication interface, including threshold values, test signal amplitude, and enable / disable control for each charge-sensitive amplification channel; the SPI communication clock signal and the test signal clock are shared in a time-division multiplexing manner.

5. The high-resolution azimuth parallel detection device according to claim 4, characterized in that, The integrated charge-sensitive amplifier has a built-in test signal circuit. The test signal is applied in the following way: each excitation is applied to only one charge-sensitive amplifier channel, and test pulses are injected into each channel in a cyclic manner to measure the response of each channel and the crosstalk between channels.

6. The high-resolution azimuth parallel detection device according to claim 1, characterized in that, The digital acquisition and processing board includes: FPGA, SRAM, and EEPROM; wherein... The FPGA includes a high-voltage output control module, a charge-sensitive amplifier configuration module, a scientific data acquisition module, a key telemetry acquisition module, an electromagnetic interference suppression module, a multi-element data arrangement and packaging processing module, and an external communication module. The FPGA performs unified time management according to the scientific data acquisition logic, coordinates the periodic work of each module of the FPGA, counts the multiple digital pulses input from the preamplifier board according to the scientific data acquisition logic in each working cycle, arranges the data according to different parameters and packages it into SRAM, and outputs the count value to the PC for analysis and processing at the end of the working cycle. The SRAM is used to cache the pulse count; The EPROM is used to store configuration parameters of the detection device, which can be updated on-orbit via ground commands.

7. The high-resolution azimuth parallel detection device according to claim 6, characterized in that, The FPGA suppresses electromagnetic interference by controlling the high-voltage scanning output and the timing of scientific data acquisition. Specifically, it waits a set time after each high-voltage switch before starting scientific data acquisition, and stops scientific data acquisition before the next high-voltage switch begins, so that the scientific data acquisition period effectively avoids electromagnetic interference caused by high-voltage switching. The scientific data acquisition includes scanning detection of elevation angle, energy, and azimuth angle. The high-voltage scanning output method is as follows: taking the high voltage of the electrostatic analyzer as the reference high voltage, the first deflection high voltage, the second deflection high voltage, and the geometric factor high voltage are output in combination according to the geometric relationship with the high voltage of the electrostatic analyzer. The high voltage of the electrostatic analyzer is output in an up-and-down cyclic scanning mode, and the high voltage is increased by odd steps and decreased by even steps to avoid the introduction of electromagnetic interference by excessive high voltage jump amplitude.

8. The high-resolution azimuth parallel detection device according to claim 6, characterized in that, The scientific data acquisition logic includes: dividing each work cycle into multiple different work units, and sequentially controlling the first deflection high voltage, the second deflection high voltage, the geometric factor high voltage, and the electrostatic analyzer high voltage to perform scanning output, thereby completing the scanning detection of elevation angle, azimuth angle, and energy in sequence; when the work cycle ends, the multi-element data arrangement and packaging processing module groups the data according to elevation angle, energy, and azimuth angle.

9. The high-resolution azimuth parallel detection device according to claim 6, characterized in that, The FPGA controls the integrated charge-sensitive amplifier via SPI communication, configuring the threshold of the charge-sensitive amplifier channel, the amplitude of the test signal, and enabling / disabling.

10. The high-resolution azimuth parallel detection device according to claim 1, characterized in that, The inter-board connector between the front amplifier board and the anode plate assembly adopts a stacked and raised design to compensate for the thickness difference of the two anode plates; the front amplifier board adopts equal-length wiring to ensure that the signal lines output by the top anode and the bottom anode plate are of equal length; a grounding point is set on the front amplifier board near the integrated charge-sensitive amplifier and connected to the metal shell of the detection device through a wire to form an electromagnetic shielding structure.

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