Circuit detection method, device and system and storage medium
By constructing a circuit model and performing leakage fault analysis, the problem of rapid location of leakage fault points in complex circuit systems was solved, achieving efficient and accurate leakage fault detection.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- TECHTOTOP MICROELECTRONICS
- Filing Date
- 2026-02-13
- Publication Date
- 2026-04-28
AI Technical Summary
Existing technologies struggle to quickly and accurately locate leakage faults in complex circuit systems, and the lack of global circuit topology modeling leads to low detection efficiency and insufficient reliability.
By acquiring circuit topology information, a circuit model is constructed, and leakage fault detection is performed based on the model. The leakage test signals are sent and received using acquisition equipment for fault analysis. The fault probability is assessed in conjunction with an intelligent agent to determine the leakage fault point.
It improves the efficiency and accuracy of detecting leakage faults, reduces the difficulty of detection, and enhances the credibility and reliability of the detection results.
Smart Images
Figure CN121933981A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of measurement technology, and more specifically, to a circuit testing method, apparatus, system, and storage medium. Background Technology
[0002] In the field of circuit system fault detection, rapid location of leakage faults is crucial for safe maintenance. Current technologies for leakage detection largely rely on manual inspection or monitoring based on a single sensor, making it difficult to comprehensively acquire electrical connection relationships in complex systems with multiple circuit interfaces. This leads to inaccurate fault location and low efficiency. Furthermore, traditional methods lack global modeling of the circuit topology, causing the detection process to depend on experience-based judgment, resulting in insufficient reliability. Summary of the Invention
[0003] This disclosure provides a new solution for detecting leakage faults in a circuit.
[0004] According to a first aspect of this disclosure, a circuit detection method is provided, comprising: The acquisition device collects circuit topology information for the target circuit system; the target circuit system is configured with multiple circuit interfaces, each circuit interface is connected to an acquisition device, and the circuit topology information includes the electrical connection information between any two connection interfaces. Based on circuit topology information, construct the circuit model corresponding to the target circuit system; Based on the circuit model, leakage fault detection is performed on the target circuit system to obtain leakage fault information of the target circuit system; the leakage fault information includes the location of the fault point where the leakage fault occurs. Display leakage fault information based on circuit model.
[0005] In some embodiments, leakage fault detection is performed on the target circuit system based on a circuit model to obtain leakage fault information of the target circuit system, including: Based on the circuit model, the acquisition device sequentially sends leakage current test signals; When controlling any acquisition device to send a leakage current test signal, the target test signal corresponding to the leakage current test signal received by each acquisition device of the target circuit system is acquired. Fault analysis is performed based on the leakage current test signal and the target test signal to obtain leakage current test data. The leakage current test data includes the location of the candidate point and the first confidence level and the second confidence level of the candidate point. The first confidence level is the probability of a fault occurring, and the second confidence level is the probability that the fault type is a leakage current fault. Leakage current analysis is performed based on leakage current test data to obtain leakage current fault information.
[0006] In some embodiments, the circuit interface includes a live wire interface and a neutral wire interface; the leakage test signal includes a live wire leakage test signal sent from the live wire interface and a neutral wire leakage test signal sent from the neutral wire interface, and the target test signal corresponding to the leakage test signal includes a live wire target test signal received from the live wire interface and a neutral wire target test signal received from the neutral wire interface. Fault analysis is performed based on the leakage current test signal and the target test signal to obtain leakage current test data, including: Based on the leakage current test signal, waveform feature comparison and screening are performed on the live wire target test signal and the neutral wire target test signal in the target test signal to obtain the positions of multiple candidate points corresponding to each target test signal; Based on the leakage current test signal, fault analysis is performed according to the target test signal and the locations of multiple candidate points corresponding to the target test signal to obtain leakage current test data; wherein, the leakage current test data includes the first confidence level and the second confidence level of multiple candidate points.
[0007] In some embodiments, based on the leakage current test signal, fault analysis is performed according to the target test signal and the locations of multiple candidate points corresponding to the target test signal to obtain leakage current test data, including: Based on the location of the candidate point, fault analysis is performed using multiple leakage current test signals and corresponding target test signals passing through the candidate point location to obtain multiple first confidence levels and multiple second confidence levels corresponding to the location of the candidate point. Normalize the multiple first confidence scores and multiple second confidence scores corresponding to the locations of the candidate points to obtain the first confidence scores and second confidence scores of the candidate points; Based on the first and second confidence levels of all candidate points, leakage current test data are obtained. Based on the leakage current test data, leakage current analysis is performed to obtain leakage current fault information, including: The location of the leakage point is determined based on the preset leakage judgment conditions and the product of the first confidence level and the second confidence level of the candidate point; Based on the location of the leakage point, leakage fault information is obtained.
[0008] In some embodiments, acquiring circuit topology information collected by the acquisition device for the target circuit system includes: Based on the acquisition device, the path detection of the target circuit system is performed to obtain the connectivity status between any two circuit interfaces in the target circuit system; Based on the data acquisition device performing distance detection on the target circuit system according to the connectivity status, the line distance between any two connection interfaces in the target circuit system is obtained. Based on the line distance between any two connection interfaces in the target circuit system, the circuit topology information of the target circuit system is obtained.
[0009] In some embodiments, the circuit topology information of the target circuit system is obtained based on the line distance between any two connection interfaces in the target circuit system, including: Based on the connectivity state, determine one or more target interface sets in the target circuit system, each target interface set including three interconnected connection interfaces in pairs; For each target interface set, the location information of the intermediate node corresponding to the target interface set is determined based on the line distance between every two connection interfaces in the three connection interfaces of the target interface set. Based on multiple target interface sets and the location information of the intermediate nodes corresponding to the target interface sets, the circuit topology information of the target circuit system is generated.
[0010] According to a second aspect of this disclosure, a circuit detection device is provided, including a memory and a processor.
[0011] At least one processor; and a memory communicatively connected to the at least one processor; The memory stores instructions that can be executed by at least one processor to enable the at least one processor to perform the method of any embodiment of the first aspect.
[0012] According to a third aspect of this disclosure, a data acquisition device is provided, comprising: a processor; Memory used to store processor-executable instructions; The processor is configured to perform the following method steps when executing instructions stored in memory: As a signal transmitting device, it sends test signals to other acquisition devices according to the signal transmitting command, and uploads test signals to the circuit detection device according to the signal uploading command; Furthermore, as a signal receiving device, it receives test signals sent by other acquisition devices according to the signal receiving instruction, and feeds back the time information of the received test signals to the processor; it obtains the delay value based on the timestamp of the test signal sent by the signal transmitting device and the timestamp of the received test signal; and it uploads the test signals and delay values sent by other acquisition devices to the circuit detection device according to the signal uploading instruction.
[0013] According to a fourth aspect of this disclosure, a circuit testing system is provided, characterized in that it includes a circuit testing device according to a second aspect and a plurality of acquisition devices according to a third aspect, the acquisition devices being used to connect to the circuit interface of a target circuit system.
[0014] According to a fifth aspect of this disclosure, a non-transitory computer-readable storage medium is provided, the non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform the method of any embodiment of the first aspect.
[0015] This disclosure embodiment can connect a data acquisition device to each circuit interface of the target circuit system to obtain the circuit topology information of the target circuit system, thereby constructing a circuit model corresponding to the target circuit system. Based on the circuit model, leakage fault detection is performed on the target circuit system, and the location of the fault point is visualized through the circuit model. This disclosure embodiment can perform various circuit detections through the data acquisition device to determine the leakage fault point in the target circuit system, reducing the difficulty of detecting leakage fault points in the circuit system and improving the detection efficiency of leakage faults in the circuit system.
[0016] Other features and advantages of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description
[0017] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the present disclosure and, together with their description, serve to explain the principles of the present disclosure.
[0018] Figure 1 A schematic flowchart of a circuit detection method provided in an embodiment of this disclosure is shown.
[0019] Figure 2 A schematic diagram of a leakage fault information display method provided in an embodiment of this disclosure is shown.
[0020] Figure 3 A schematic diagram of a circuit testing device provided in an embodiment of this disclosure is shown.
[0021] Figure 4 A schematic diagram of a data acquisition device provided in an embodiment of this disclosure is shown.
[0022] Figure 5 A schematic diagram of a circuit detection system provided in an embodiment of this disclosure is shown. Detailed Implementation
[0023] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.
[0024] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use.
[0025] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.
[0026] In all the examples shown and discussed herein, any specific values should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.
[0027] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.
[0028] Figure 1 The following is a schematic flowchart of a circuit detection method provided in some embodiments of this disclosure, such as... Figure 1 As shown, this disclosure provides a circuit detection method, including the following steps S110 to S140: Step S110: Obtain circuit topology information collected by the acquisition device for the target circuit system; wherein, the target circuit system is configured with multiple circuit interfaces, each circuit interface is connected to an acquisition device, and the circuit topology information includes electrical connection information between any two connection interfaces.
[0029] In the example, before starting the detection of circuit leakage faults, a data acquisition device needs to be connected to each circuit interface of the target circuit system. The data acquisition device runs a pre-set detection program to determine the circuit topology information. The circuit topology information includes the electrical connection information between any two interconnected circuit interfaces, and the electrical connection information can include the line distance between the two connection interfaces. A connection interface is defined as having at least one interconnecting line between two circuit interfaces.
[0030] In some possible embodiments, acquiring the circuit topology information collected by the acquisition device for the target circuit system may specifically include: performing path detection on the target circuit system based on the acquisition device to obtain the connectivity status between any two circuit interfaces in the target circuit system; performing distance detection on the target circuit system based on the connectivity status based on the acquisition device to obtain the line distance between any two connection interfaces in the target circuit system; and obtaining the circuit topology information of the target circuit system based on the line distance between any two connection interfaces in the target circuit system.
[0031] To acquire circuit topology information of the target circuit system, the acquisition device needs to perform path detection and distance detection sequentially. Path detection involves sending DC signals through the live and neutral wires of each circuit interface to test the connectivity between the live and neutral wires of the circuit interfaces connected to each acquisition device. The connectivity status is determined by how other acquisition devices receive the DC signals at their connected circuit interfaces. The connectivity status specifically includes the following four cases: If the DC signal transmitted by the transmitting acquisition device via the live wire is received by the live wire of the circuit interface to which the receiving acquisition device is connected, and the DC signal transmitted by the transmitting acquisition device via the neutral wire is received by the neutral wire of the circuit interface to which the receiving acquisition device is connected, then the connectivity status is normal connectivity. If the DC signal transmitted by the transmitting acquisition device via the live wire is received by the neutral wire of the circuit interface to which the receiving acquisition device is connected, and the DC signal transmitted by the transmitting acquisition device via the neutral wire is received by the live wire of the circuit interface to which the receiving acquisition device is connected, then the connectivity status is reverse connectivity. If neither the live wire nor the neutral wire of the circuit interface to which the receiving acquisition device is connected receives the DC signal transmitted by the transmitting acquisition device via the live wire, and neither the live wire nor the neutral wire of the circuit interface to which the receiving acquisition device is connected receives the DC signal transmitted by the transmitting acquisition device via the neutral wire, then the connectivity status is open circuit. If both the live wire and the neutral wire of the circuit interface to which the receiving acquisition device is connected receive the DC signal transmitted by the transmitting acquisition device via the live wire, and both the live wire and the neutral wire of the circuit interface to which the receiving acquisition device is connected receive the DC signal transmitted by the transmitting acquisition device via the neutral wire, then the connectivity status is short circuit.
[0032] If only the DC signal transmitted via the live wire of the transmitting acquisition device is not received by the live wire and neutral wire of the circuit interface connected to the receiving acquisition device, the continuity status is a live wire open circuit. Similarly, if only the DC signal transmitted via the neutral wire is not received by the live wire and neutral wire of the circuit interface connected to the receiving acquisition device, the continuity status is a neutral wire open circuit.
[0033] If the connectivity status of two connection interfaces determined in the path detection is normal connection, reverse connection, or only one side of the live wire and neutral wire is open, then distance detection is performed on the line distance between the two connection interfaces. Distance detection involves sending long pulse signals (e.g., 1ms pulses) between the two connection interfaces via interconnected acquisition devices. The line distance between the two connection interfaces is calculated by calculating the time delay from transmission to reception of the long pulse signal, as well as the electrical conduction speed of the wiring used in the target circuit system. If at least two calculated results for the line distance between the two connection interfaces (one result for each signal transmission direction in the case of a single-sided open circuit) are different, the minimum value is taken.
[0034] The electrical conduction speed of the circuit wires used in the target circuit system is generally set to a preset value. When the circuit wires used in the target circuit system are non-standard wires, the electrical conduction speed parameter can be adjusted according to the actual circuit wires of the target circuit system.
[0035] This embodiment obtains the circuit topology information of the target circuit system through path detection and distance detection, and clarifies the circuit structure of the target circuit system. This can effectively simplify the detection steps of leakage fault detection, shorten the detection time of leakage fault detection, and thus improve the overall efficiency of circuit detection.
[0036] In some possible embodiments, the locations of intermediate nodes in the target circuit system can be calculated using a mathematical model through three interconnected connection interfaces. Specific steps include: determining one or more target interface sets in the target circuit system based on connectivity status, each target interface set including three interconnected connection interfaces; for each target interface set, determining the location information of the intermediate nodes corresponding to the target interface set based on the line distance between every two connection interfaces in the three connection interfaces of the target interface set; and generating circuit topology information of the target circuit system based on multiple target interface sets and the location information of the intermediate nodes corresponding to the target interface sets.
[0037] Based on the connectivity of each circuit interface with other circuit interfaces, three interconnected connection interfaces can be obtained. These three connection interfaces constitute a target interface set. Since circuit interfaces typically connect the live and neutral wires separately before branching the circuit, a circuit system may actually contain one or more target interface sets. Based on the line distance between each pair of connection interfaces in the target interface set, the following formula can be established to calculate the location of intermediate nodes:
[0038] Among them, l A L is the line distance from the intermediate node to circuit interface A. AB L is the line distance between interfaces A and B. AC L is the line distance between interfaces A and C. BC This represents the distance between interfaces B and C. The above formula can be used to calculate the location information of intermediate nodes in any set of target interfaces.
[0039] By combining the location information of the intermediate nodes in each target interface set in the target circuit system and the line distance between each connection interface, the overall circuit topology information of the target circuit system can be obtained.
[0040] In some circuit systems, there may be multiple target interface sets with the same pair of connection interfaces. If the distance between the intermediate node of two target interface sets and the line of the same circuit interface is within a preset error threshold, the intermediate nodes of the two target interface sets can be merged, that is, the two target interface sets can be merged. Similarly, multiple target interface sets can be merged in this way.
[0041] For example, both target interface set ABC and target interface set ABD contain connection interface AB. The distance between the intermediate node in target interface set ABC and circuit interface A is 2m, and the distance between the intermediate node in target interface set ABD and circuit interface A is 2.1m. The preset error threshold is 0.2m. The difference in distance between the intermediate node in the two target interface sets and circuit interface A is within the preset error threshold. Therefore, target interface set ABC and target interface set ABD can be merged into target interface set ABCD.
[0042] This embodiment improves the accuracy of circuit topology information by calculating the position of intermediate nodes, thereby improving the accuracy of circuit detection.
[0043] Step S120: Based on the circuit topology information, construct the circuit model corresponding to the target circuit system.
[0044] Based on the circuit topology information of the target circuit system, a corresponding circuit model can be constructed. This model describes the connectivity status of each circuit interface, the distance between interconnected interfaces, the location of intermediate nodes, and other circuit topology information. This circuit model is used for subsequent leakage fault detection and visualization of the target circuit system.
[0045] Step S130: Perform leakage fault detection on the target circuit system based on the circuit model to obtain leakage fault information of the target circuit system; wherein, the leakage fault information includes the location of the fault point where the leakage fault occurs.
[0046] Based on the circuit model, leakage current test signals are sent by acquisition devices connected to various circuit interfaces in the target circuit system. The intelligent agent analyzes the leakage current test signals sent / received by each acquisition device to obtain leakage current fault information.
[0047] In some possible embodiments, the leakage fault testing process may include: based on a circuit model, the acquisition device sequentially sends leakage test signals; when controlling any acquisition device to send a leakage test signal, acquiring the target test signals corresponding to the leakage test signals received by each acquisition device of the target circuit system, performing fault analysis based on the leakage test signals and the target test signals to obtain leakage test data; wherein, the leakage test data includes the location of the candidate point and the first confidence level and the second confidence level of the candidate point, the first confidence level being the probability of a fault occurring, and the second confidence level being the probability that the fault type is a leakage fault; performing leakage analysis based on the leakage test data to obtain leakage fault information.
[0048] Based on the connectivity between each circuit interface and other circuit interfaces in the circuit model, each acquisition device can send leakage test signals in a pre-set order, acquire the target test signal from the corresponding target test signal acquisition device, and perform fault analysis by comparing the target test signal and the leakage test signal to obtain leakage test data.
[0049] Leakage test data includes the location of the candidate point and its first and second confidence levels. The location of the candidate point is determined by comparing the target test signals of the live wire and neutral wire with the leakage test signal to identify the location where abnormal signal changes occur. Abnormal signal changes can include positive pulse reduction, positive pulse becoming zero, positive pulse becoming negative, etc.
[0050] The first and second confidence levels for the candidate points are probability values obtained by the agent performing fault analysis on all target test signals. To prevent the agent's model for fault analysis from being overly sensitive, a third confidence level can be added in addition to the first and second confidence levels. The third confidence level represents the probability that the candidate point is fault-free. Furthermore, the agent can analyze the probability of other types of faults occurring simultaneously with the analysis of the second confidence level.
[0051] This embodiment calls an intelligent agent to perform fault analysis on the target test signal, determines the location of the candidate point and the probability of the candidate point malfunctioning and the probability of leakage fault, and performs leakage analysis based on the above leakage test data, thereby improving the objectivity of the detection results and thus improving the reliability and accuracy of the detection results.
[0052] In some possible embodiments, the circuit interface includes a live wire interface and a neutral wire interface; the leakage test signal includes a live wire leakage test signal sent from the live wire interface and a neutral wire leakage test signal sent from the neutral wire interface, and the target test signal corresponding to the leakage test signal includes a live wire target test signal received from the live wire interface and a neutral wire target test signal received from the neutral wire interface.
[0053] Fault analysis may include comparing and filtering waveform features of the live wire target test signal and the neutral wire target test signal based on the leakage current test signal to obtain the location of multiple candidate points corresponding to each target test signal; based on the leakage current test signal, fault analysis is performed according to the target test signal and the location of multiple candidate points corresponding to the target test signal to obtain leakage current test data; wherein, the leakage current test data includes the first confidence level and the second confidence level of multiple candidate points.
[0054] Fault analysis of the target circuit system can be performed under the premise that the live wire leakage test signal and the neutral wire leakage test signal are the same. By comparing the waveform characteristics of the target test signals for the live wire and the neutral wire, the location of the candidate point is where the waveforms of the live wire and the neutral wire show a significant difference after comparison. An intelligent agent analyzes the reasons for the waveform difference between the leakage test signal and the target test signal at the candidate point to obtain the probability of the candidate point failing and the probability of leakage or other faults occurring, i.e., to obtain the first confidence level and the second confidence level of the candidate point. Alternatively, the intelligent agent can analyze the waveform characteristics to determine the cause of the leakage fault, such as grounding or water immersion. Different causes of leakage will change the internal resistance of the leakage point differently, which can be analyzed by comparing sample data.
[0055] This embodiment further specifies the method of obtaining candidate points by comparing and analyzing the target test signals of the live wire and the neutral wire, rather than detecting leakage faults through a single line, which improves the reliability of the determined candidate points and thus improves the accuracy of leakage fault detection.
[0056] In some possible embodiments, since the location of the same candidate point may be included in the transmission paths of multiple leakage current test signals, the fault analysis may include: based on the location of the candidate point, performing fault analysis according to multiple leakage current test signals passing through the candidate point location and the corresponding multiple target test signals to obtain multiple first confidence levels and multiple second confidence levels corresponding to the location of the candidate point; normalizing the multiple first confidence levels and multiple second confidence levels corresponding to the location of the candidate point to obtain the first confidence level and second confidence level of the candidate point; and obtaining leakage current test data based on the first confidence level and second confidence level of all candidate points.
[0057] In this example, since multiple different acquisition devices send leakage test signals through the candidate point, and the leakage analysis obtains the first confidence level and the second confidence level corresponding to the location of the candidate point for each leakage test signal and the corresponding target test signal, it can be said that each acquisition device will vote on the candidate point for failure. The intelligent system normalizes the multiple first confidence levels and multiple second confidence levels corresponding to the location of each candidate point, that is, it calculates the mean of the first confidence level and the mean of the second confidence level, which are used as the first confidence level and the second confidence level of the candidate point.
[0058] In some possible embodiments, leakage fault information can be obtained by determining the location of the leakage point based on preset leakage judgment conditions and the product of the first confidence level and the second confidence level of the candidate point.
[0059] In the example, for each candidate point, the first confidence level and the second confidence level of that candidate point are multiplied together, and the product is the leakage current assessment value of that candidate point. A preset leakage current determination criterion can be that candidate points whose leakage current assessment values exceed a preset leakage current assessment threshold are determined as leakage points. The leakage point and its location are determined through the preset leakage current determination criteria, and relevant information such as the cause of the leakage can be combined to form leakage fault information.
[0060] For example, if the first confidence level of a candidate point is 0.7 and the second confidence level is 0.8, then the leakage current assessment value of the candidate point is 0.7 × 0.8, which is 0.56. The preset leakage current judgment condition is that if the leakage current assessment value of the candidate point exceeds 0.55, then the candidate point is judged to be a leakage current point. The candidate point meets the preset leakage current judgment condition and is judged to be a leakage current point.
[0061] This embodiment provides a scoring mechanism for leakage faults at candidate points. By analyzing the fault results of multiple data, the probability of a fault occurring at the candidate point and the probability of a leakage fault are calculated, which further improves the objectivity of the detection results, thereby increasing the reliability and accuracy of the detection results.
[0062] Step S140: Display leakage fault information based on the circuit model.
[0063] Figure 2 This is a schematic diagram of a leakage fault information display method provided by some embodiments of this disclosure.
[0064] The leakage fault information obtained in step S130 is visualized on the circuit model obtained in steps S110 to S120. The displayed content may include each circuit interface in the target circuit system and the circuit interface number, the connection relationship and line distance between circuit interfaces, the intermediate node corresponding to the target interface set, and the location of the leakage point.
[0065] For example, such as Figure 2 As shown, P1, P3, and P4 are circuit interfaces, and P2 is an intermediate node. The numbers in parentheses after the circuit interface numbers (P1, P3, P4) are the numbers of the acquisition devices connected to the circuit interfaces. It can be seen from the figure that the line distance from circuit interface P1 to intermediate node P2 is 2.8m, and the line distance from circuit interface P4 to intermediate node P2 is 4.4m. There is a leakage point in the line from intermediate node P2 to circuit interface P3, and the line distance between this leakage point and intermediate node P2 is 3m.
[0066] The embodiments disclosed herein can sequentially perform path detection, distance detection, and leakage fault detection using a data acquisition device to determine the leakage fault point in the target circuit system, thereby reducing the difficulty of detecting leakage fault points in the circuit system and improving the detection efficiency of leakage faults in the circuit system.
[0067] Figure 3 A schematic diagram of a circuit testing apparatus 300 provided in some embodiments of the present disclosure is shown. The circuit testing apparatus 300 includes a memory 310 and a processor 320. At least one processor 320 and a memory 310 communicatively connected to the at least one processor 320 are included. The memory 310 stores instructions executable by the at least one processor 320, which, when executed, enable the at least one processor 320 to perform any embodiment of the circuit testing method provided in the present disclosure.
[0068] Figure 4 The diagram shows a data acquisition device 400 provided in some embodiments of the present disclosure. The data acquisition device 400 includes a processor 420 and a memory 410 for storing executable instructions of the processor 420.
[0069] The processor 420 is configured to perform the following method steps when executing instructions stored in the memory 410: When used as a signal transmitting device, it sends test signals to other acquisition devices according to the signal transmitting command, and uploads test signals to the circuit detection device according to the signal uploading command.
[0070] When acting as a signal receiving device, it receives test signals sent by other acquisition devices according to the signal receiving instruction, and feeds back the time information of the received test signals to the processor 420; it obtains the delay value based on the timestamp of the test signal sent by the signal transmitting device and the timestamp of the received test signal; and it uploads the test signals and delay values sent by other acquisition devices to the circuit detection device according to the signal uploading instruction.
[0071] Figure 5 This invention illustrates a schematic diagram of a circuit detection system 500 provided in some embodiments. The circuit detection system 500 includes... Figure 3 The circuit testing device 300 and multiple circuit testing devices shown Figure 4 The acquisition device 400 shown is used to connect to the circuit interface of the target circuit system. The circuit testing device 300 and multiple acquisition devices 400 can be wirelessly connected via WiFi, Bluetooth, or other means.
[0072] This disclosure also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method as described in any of the above method embodiments.
[0073] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0074] This disclosure may be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement any of the methods in the foregoing embodiments of this disclosure.
[0075] Computer-readable storage media can be tangible devices capable of holding and storing instructions for use by an instruction execution device. Computer-readable storage media may include, for example, electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), static random access memory (SRAM), compact disc-read-only memory (CD-ROM), digital versatile disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any combination thereof. The computer-readable storage medium used herein is not to be interpreted as a transient signal itself, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.
[0076] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include one or more of copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to computer-readable storage media in the respective computing / processing device.
[0077] The computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source or object programs written in any combination of one or more programming languages, including object-oriented programming languages (such as Smalltalk, C++, etc.) and conventional procedural programming languages (such as the "C" language or similar programming languages). The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network (e.g., a local area network or a wide area network), or it may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays, or programmable logic arrays, can execute computer-readable program instructions to implement various aspects of the embodiments of this disclosure by utilizing state information from the computer-readable program instructions.
[0078] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus, and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.
[0079] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.
[0080] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions that execute on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.
[0081] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions. It should be noted that implementation in hardware, implementation in software, and implementation using a combination of software and hardware are all equivalent.
[0082] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, and are not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein. The scope of this disclosure is defined by the appended claims.
Claims
1. A circuit detection method, characterized in that, include: The circuit topology information collected by the acquisition device for the target circuit system is acquired; wherein the target circuit system is configured with multiple circuit interfaces, each circuit interface is connected to an acquisition device, and the circuit topology information includes the electrical connection information between any two connection interfaces. Based on the circuit topology information, a circuit model corresponding to the target circuit system is constructed; Based on the circuit model, leakage fault detection is performed on the target circuit system to obtain leakage fault information of the target circuit system; wherein, the leakage fault information includes the location of the fault point where the leakage fault occurs; The leakage fault information is displayed based on the circuit model.
2. The method according to claim 1, characterized in that, The step of performing leakage fault detection on the target circuit system based on the circuit model to obtain leakage fault information of the target circuit system includes: Based on the circuit model, the acquisition device sequentially sends leakage current test signals; When controlling any acquisition device to send a leakage current test signal, the target test signal corresponding to the leakage current test signal received by each acquisition device of the target circuit system is acquired. Fault analysis is performed based on the leakage current test signal and the target test signal to obtain leakage current test data. The leakage current test data includes the location of the candidate point and the first confidence level and the second confidence level of the candidate point. The first confidence level is the probability of a fault occurring, and the second confidence level is the probability that the fault type is a leakage current fault. Based on the leakage test data, leakage current analysis is performed to obtain leakage fault information.
3. The method according to claim 2, characterized in that, The circuit interface includes a live wire interface and a neutral wire interface; the leakage test signal includes a live wire leakage test signal sent from the live wire interface and a neutral wire leakage test signal sent from the neutral wire interface, and the target test signal corresponding to the leakage test signal includes a live wire target test signal received from the live wire interface and a neutral wire target test signal received from the neutral wire interface. The step of performing fault analysis based on the leakage current test signal and the target test signal to obtain leakage current test data includes: Based on the leakage current test signal, waveform feature comparison and screening are performed on the live wire target test signal and the neutral wire target test signal in the target test signal to obtain the positions of multiple candidate points corresponding to each target test signal; Based on the leakage current test signal, fault analysis is performed according to the target test signal and the locations of multiple candidate points corresponding to the target test signal to obtain leakage current test data; wherein, the leakage current test data includes the first confidence level and the second confidence level of the multiple candidate points.
4. The method according to claim 3, characterized in that, The process involves fault analysis based on the leakage current test signal, according to the target test signal and the locations of multiple candidate points corresponding to the target test signal, to obtain leakage current test data, including: Based on the location of the candidate point, fault analysis is performed on multiple leakage current test signals passing through the location of the candidate point and the corresponding multiple target test signals to obtain multiple first confidence levels and multiple second confidence levels corresponding to the location of the candidate point; Normalization is performed on the multiple first confidence scores and multiple second confidence scores corresponding to the locations of the candidate points to obtain the first confidence scores and second confidence scores of the candidate points; Based on the first and second confidence levels of all the candidate points, the leakage current test data is obtained; The step of performing leakage current analysis based on the leakage current test data to obtain leakage current fault information includes: The location of the leakage point is determined based on the preset leakage determination conditions and the product of the first confidence level and the second confidence level of the candidate point. Based on the location of the leakage point, leakage fault information is obtained.
5. The method according to claim 1, characterized in that, The acquisition of circuit topology information of the target circuit system by the acquisition device includes: Based on the acquisition device, the target circuit system is subjected to path detection to obtain the connectivity status between any two circuit interfaces in the target circuit system; Based on the data acquisition device performing distance detection on the target circuit system according to the connectivity status, the line distance between any two connection interfaces in the target circuit system is obtained; Based on the line distance between any two connection interfaces in the target circuit system, the circuit topology information of the target circuit system is obtained.
6. The method according to claim 5, characterized in that, The step of obtaining the circuit topology information of the target circuit system based on the line distance between any two connection interfaces in the target circuit system includes: Based on the connectivity state, one or more target interface sets are determined in the target circuit system, and each target interface set includes three interconnected connection interfaces in pairs. For each target interface set, the location information of the intermediate node corresponding to the target interface set is determined based on the line distance between every two connection interfaces in the three connection interfaces of the target interface set. Based on the multiple target interface sets and the location information of the intermediate nodes corresponding to the target interface sets, the circuit topology information of the target circuit system is generated.
7. A circuit testing device, characterized in that, This includes memory and processor. At least one processor; as well as A memory that is communicatively connected to the at least one processor; The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-6.
8. A data acquisition device, characterized in that, include: processor; Memory used to store processor-executable instructions; The processor is configured to perform the following method steps when executing instructions stored in the memory: As a signal transmitting device, it sends test signals to other acquisition devices according to the signal transmitting instruction, and uploads the test signals to the circuit detection device according to the signal uploading instruction; as well as, As a signal receiving device, it receives test signals sent by other acquisition devices according to a signal receiving instruction, and feeds back the time information of the received test signals to the processor; it obtains a delay value based on the timestamp of the test signal sent by the signal transmitting device and the timestamp of the received test signal; and it uploads the test signals sent by other acquisition devices and the delay value to the circuit detection device according to a signal uploading instruction.
9. A circuit detection system, characterized in that, It includes the circuit testing device of claim 7 and a plurality of acquisition devices of claim 8, wherein the acquisition devices are used to connect to the circuit interface of the target circuit system.
10. A non-transitory computer-readable storage medium, characterized in that, The non-transitory computer-readable storage medium stores computer instructions for causing the computer to perform the method of any one of claims 1-6.