High-resolution close-in radar target simulation method and system based on drfm

Abstract

The present application belongs to the technical field of radar target simulation, and relates to a high-resolution near-range radar target simulation method and system based on a DRFM. The present application completes target modeling through a dynamic filter network, generates a target feature sequence that dynamically changes with a radar field of view; completes inherent delay calibration and cross-cycle compensation parameter calculation through measurement; after receiving a radar transmission signal, obtains a zero intermediate frequency IQ signal through frequency conversion, sampling and mixing; completes convolution modulation of the IQ signal and the target feature sequence through an adaptive segmented convolution algorithm, generates a high-resolution target echo signal; superimposes Doppler frequency shift and distance offset, completes digital-to-analog conversion and radio frequency up-conversion after cross-cycle compensation, and outputs a target echo radio frequency signal. The present application greatly reduces the calculation complexity and hardware cost of high-resolution target simulation, realizes multi-signal system adaptation for super-near-range simulation, effectively suppresses Doppler spread distortion in a large bandwidth scene, and has wide applicability.

Description

Technical Field

[0001] This invention belongs to the field of radar target simulation technology, and more specifically, relates to a high-resolution short-range radar target simulation method and system based on DRFM. Background Technology

[0002] Target simulation is an important technical guarantee and support for the research and development of radar detector equipment. By accurately simulating complex and expensive field test scenarios in a controllable and reproducible laboratory environment, the testing capability is brought forward and internalized into the scheme demonstration, engineering design, system integration and test verification stages, which greatly improves the efficiency of equipment research and development testing.

[0003] In traditional narrowband applications, target models often employ multi-scattering point models, echo simulations typically use vector synthesis or convolutional modulation methods, and near-range target simulations often utilize frequency domain prediction and compensation methods. Multi-scattering point models and related simulation methods are usually processed in parallel in the time domain. However, broadband systems place higher demands on the refined characteristics of the target. With few scattering points, it is difficult to fully represent the target features. Furthermore, if the number of scattering points increases synchronously with the bandwidth and sampling rate, both scattering point vector synthesis and convolutional modulation methods essentially involve linear matrix operations of the sampling points in the time domain. The computational complexity is related to the square of the sampling rate, significantly increasing the algorithm's time and space complexity, which is difficult for current mainstream hardware resources to meet. In addition, while frequency domain compensation methods can effectively solve near-range simulations with delays below the system's inherent latency, their applicability is limited to a very small number of signal systems such as frequency-modulated continuous wave (FM), resulting in a narrow scope.

[0004] In the existing technology, there is a high-resolution short-range radar target simulation method based on DRFM. This method first inputs the simulation scene environment calculation data in the modeling stage. After geometric operations on the target resolution unit, the target is simplified into a dynamic filter network, and a target feature sequence that dynamically changes with the radar field of view of the detector under discrete scene slices is established and stored in the system's high-speed storage device. In the test preparation stage, the distance of the test antenna and the inherent delay of the system are accurately measured, and the target feature sequence is preprocessed and calculated offline. After the test begins, the received radar signal is frequency-converted, orthogonally sampled, and digitally mixed to obtain a zero intermediate frequency digital IQ signal. The IQ signal is convolved and modulated with the synchronously extracted target feature sequence to obtain a high-resolution target echo signal. The target range delay is superimposed on the echo signal, and the sampling point is finely adjusted according to the range migration. Doppler frequency shift modulation is superimposed to accurately simulate the target's dynamic range and velocity changes. The echo signal is compensated across the cycle time domain according to the calibration data to realize the simulation of the target at extremely close range. The target echo signal is digitally up-converted, and the analog intermediate frequency is generated by DA playback. The up-converted signal generates the target echo radio frequency. However, this method has obvious shortcomings: First, it is difficult to obtain high-resolution target scattering characteristics, requiring a large number of experimental tests, measurements and data acquisition, and involves a complex process of target scattering characteristic analysis, extraction, model reconstruction and verification; Second, for high-bandwidth, high-speed and wide-beam scenarios, there is a certain degree of Doppler broadening distortion, making it difficult to completely retain the time-related characteristics of the target; Third, the hardware system requires high-sampling AD / DA and data processing chips, high-speed data transmission interfaces, and high-speed large-capacity storage, resulting in high system complexity and cost, making it difficult to achieve real-time high-resolution echo simulation with limited FPGA resources. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention provides a high-resolution short-range radar target simulation method and system based on DRFM.

[0006] In the first aspect, the present invention provides a high-resolution short-range radar target simulation method based on DRFM, including target modeling, test preparation, signal acquisition and transmission, echo generation calculation, echo delay control and signal playback;

[0007] Target modeling includes: generating discrete scene slices that dynamically change with the detector's radar field of view based on the simulated scene environment parameters; modeling the target region as a dynamic filter network; extracting the amplitude and phase of range resolution units to form a target feature sequence; preprocessing the target feature sequence; and storing it in a high-speed storage device.

[0008] Test preparation includes: measuring the distance between the detector and the target simulation system antenna, measuring the inherent delay of the target simulation system's radio frequency and digital links, performing delay calibration compensation and manual fine-tuning, and confirming that the zero-distance simulated transmit and receive signals coincide;

[0009] Signal acquisition and transmission include: receiving signals transmitted by the detector, performing frequency conversion, quadrature sampling and digital mixing processing, and transmitting the zero intermediate frequency digital IQ signal to the real-time signal processing module through a high-speed data interface;

[0010] The echo generation calculation includes: extracting the target model feature sequence from the high-speed storage device according to the scene time, performing convolution modulation between the zero intermediate frequency digital IQ signal and the target model feature sequence to generate a high-resolution target echo signal, and superimposing Doppler frequency shift on the echo signal to simulate radial velocity;

[0011] Echo delay control includes: shifting the target distance delay sampling points of the echo signal, shifting the sampling points by distance migration, shifting the sampling points by cross-cycle compensation, simulating the target distance, and transmitting the shifted echo signal to the signal playback module;

[0012] Signal playback includes: digital up-conversion and digital-to-analog conversion of the target echo signal to generate the target echo intermediate frequency signal, and transmitting the target echo radio frequency signal to the detector under test.

[0013] Secondly, the present invention provides a high-resolution short-range radar target simulation system based on DRFM, including a target modeling unit, an experiment preparation unit, a signal acquisition and transmission unit, an echo generation and calculation unit, an echo delay control unit, and a signal playback unit;

[0014] The target modeling unit is configured to: generate discrete scene slices that dynamically change with the radar field of view of the detector based on the simulated scene environment parameters; model the target region as a dynamic filter network; extract the amplitude and phase of the range resolution unit to form a target feature sequence; preprocess the target feature sequence; and store it in a high-speed storage device.

[0015] The test preparation unit is configured to: measure the distance between the detector and the target simulation system antenna, measure the inherent delay of the target simulation system's radio frequency and digital links, perform delay calibration compensation and manual fine-tuning, and confirm the overlap of zero-distance simulated transmit and receive signals;

[0016] The signal acquisition and transmission unit is configured to receive the signal transmitted by the detector, perform frequency conversion, quadrature sampling and digital mixing processing, and transmit the zero intermediate frequency digital IQ signal to the real-time signal processing module through a high-speed data interface.

[0017] The echo generation computing unit is configured to: extract the target model feature sequence from the high-speed storage device according to the scene time, perform convolution modulation between the zero intermediate frequency digital IQ signal and the target model feature sequence to generate a high-resolution target echo signal, and superimpose Doppler frequency shift onto the echo signal to simulate radial velocity.

[0018] The echo delay control unit is configured to: offset the target distance delay sampling point of the echo signal, offset the sampling point by distance migration, offset the sampling point by cross-cycle compensation, simulate the target distance, and transmit the offset echo signal to the signal playback module.

[0019] The signal playback unit is configured to perform digital up-conversion and digital-to-analog conversion on the target echo signal to generate a target echo intermediate frequency signal, and transmit the target echo radio frequency signal to the detector under test.

[0020] Based on the above technical solution, the present invention can be further improved as follows.

[0021] Optionally, generate discrete scene slices that dynamically change with the detector's radar field of view, including: dividing the discrete scene slices at fixed time intervals according to the relative motion trajectory between the detector and the target, the radar beamwidth and elevation angle parameters, with each slice corresponding to the radar field of view coverage of the detector at the current moment.

[0022] Optionally, the target region can be modeled as a dynamic filter network, including:

[0023] Based on the geometric relationship of discrete scene slices, the beam coverage area is divided into multiple equidistant ring resolution units according to the distance resolution corresponding to the detector radar signal bandwidth.

[0024] Based on the target scattering characteristics data and spatial geometric projection relationship of each resolution cell, the amplitude and phase parameters of the corresponding resolution cell are calculated.

[0025] The filter impulse response is constructed for each resolution unit from near to far. The filter network structure is dynamically updated according to discrete scene slices to generate a target feature sequence that evolves over time.

[0026] Optionally, the target feature sequence is preprocessed and stored in a high-speed storage device, including:

[0027] The target feature sequence is segmented, aligned, and padded with zeros according to the number of parallel processing paths of the FPGA. A sequence index data structure is constructed, and the preprocessed target feature sequence is stored in the corresponding address space of the high-speed storage device according to the slice timing.

[0028] Optionally, delay calibration compensation is performed, including: directly connecting the RF transmitter and receiver of the target simulation system through an RF cable to construct a closed-loop calibration link; generating a standard pulse modulation signal through the system's built-in DDS, transmitting it through the closed-loop link, comparing the envelope delay of the transmitted signal and the received signal, and measuring the inherent delay of the entire system link; calculating cross-cycle compensation parameters based on the inherent delay to complete the initial calibration.

[0029] Optionally, the convolution modulation employs an adaptive segmented convolution algorithm, including:

[0030] Based on the length of the target model feature sequence corresponding to the current discrete scene slice, the segment length is adaptively determined, and the target model feature sequence is segmented.

[0031] Each segment of the target model feature sequence and the corresponding length of the input IQ signal are zero-padded and expanded, and then transformed to the frequency domain by FFT.

[0032] The frequency domain convolution operation is completed by multiplying the target model feature sequence in the frequency domain with the IQ signal using complex numbers.

[0033] The multiplication result is transformed back to the time domain by IFFT, and the non-aliased effective part of each segment is extracted. Multiple effective segments are spliced ​​together to obtain the target echo baseband signal as the linear convolution result.

[0034] Optionally, the adaptive segmented convolution algorithm is implemented based on a pipeline architecture within the FPGA. The pipeline architecture includes multiple reusable FFT / IFFT cores, a ping-pong buffer, a complex multiplier, and a state control machine. The state control machine is used to control the timing synchronization of the pipeline's segmentation, zero-padding, FFT transformation, frequency domain multiplication, IFFT transformation, data truncation, and concatenation.

[0035] Optionally, sampling point offset is performed using a cross-cycle compensation method to simulate target distance, including: obtaining the period of the signal transmitted by the detector under test, measuring the inherent delay of the entire link of the target simulation system; performing a modulo operation on the inherent delay according to the signal period to obtain the remainder, calculating the difference between the period of the signal transmitted by the detector under test and the remainder to obtain the cross-cycle compensation time difference; when the echo signal sampling point is offset, the sampling point offset corresponding to the compensation time difference is superimposed on the two-way delay offset corresponding to the target distance, plus the inherent delay of the system link and transmission, to obtain the two-way delay corresponding to the set target distance in the cross-cycle simulation.

[0036] Optionally, based on the relative motion parameters between the detector and the target, the corresponding instantaneous Doppler frequency and range migration offset are calculated for each sampling point, and a control signal aligned with the adaptive convolution pipeline is generated to complete Doppler frequency shift modulation and range migration offset compensation point by point; the control signal includes address, coefficient index and fractional delay phase shift.

[0037] The beneficial effects of this invention are:

[0038] (1) This invention uses a dynamic filter network to model the target and removes the distance coupling of each resolution unit. While fully preserving the target’s temporal scattering and time-related features, it significantly shortens the length of the target feature sequence. At the same time, through an adaptive segmented convolution algorithm, the temporal linear convolution of the high-resolution long sequence is converted into a multi-segment adaptive cyclic convolution. The calculation process is optimized using FFT / IFFT kernels, reducing the computational complexity from the square of the sampling rate to the logarithmic level. Under the limited FPGA logic unit scale, it can realize real-time calculation of long sequence echo simulation within a single clock cycle without the need for ultra-high-specification hardware chips, significantly reducing system complexity and hardware cost.

[0039] (2) This invention breaks through the limitation of the inherent delay of the system by using the cross-cycle remainder compensation method, and can achieve sub-nanosecond level distance simulation accuracy. The minimum simulation distance can be within 0.1m. At the same time, it can be adapted to various periodic signal systems such as linear frequency modulated continuous wave, pseudo-code phase modulation, and pulse Doppler. It solves the problem of the narrow applicability of the existing frequency domain compensation method, and is especially suitable for the short-range testing requirements of radio fuze radar.

[0040] (3) This invention models the target’s time correlation characteristics and fine scattering features by using a dynamic filter network that updates dynamically with the radar field of view. At the same time, it uses a pipelined Doppler control that is strictly aligned with the convolutional pipeline to match the instantaneous Doppler parameters for each sampling point, which effectively solves the Doppler broadening distortion problem in high bandwidth, high speed and wide beam scenarios and greatly improves the fidelity of echo simulation.

[0041] (4) Based on the mature DRFM hardware architecture, the entire process of target modeling, convolution operation and delay compensation is implemented through FPGA programmable logic. It can be flexibly configured according to the signal system, bandwidth and resolution parameters of the radar under test. It does not require complex field measurement data acquisition, which greatly reduces the engineering implementation difficulty of high-resolution target simulation. It can be widely used in the research and development testing scenarios of various radar detectors. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of the high-resolution short-range radar target simulation method based on DRFM provided in Embodiment 1 of the present invention;

[0043] Figure 2 This is a schematic diagram illustrating the principle of time delay calibration and compensation under the desired scenario;

[0044] Figure 3 This is a schematic diagram illustrating the delay calibration and compensation principle in a real-world system scenario.

[0045] Figure 4 This is a schematic diagram illustrating the principle of delay calibration compensation in a system compensation calibration scenario.

[0046] Figure 5This is a schematic diagram of a high-resolution short-range radar target simulation system based on DRFM provided in Embodiment 1 of the present invention. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0048] Example 1

[0049] As an example, see the attached document. Figure 1 As shown, in order to solve the above-mentioned technical problems, this embodiment provides a high-resolution short-range radar target simulation method based on DRFM, including target modeling, test preparation, signal acquisition and transmission, echo generation calculation, echo delay control and signal playback.

[0050] Target modeling includes: generating discrete scene slices that dynamically change with the detector's radar field of view based on the simulated scene environment parameters; modeling the target region as a dynamic filter network; extracting the amplitude and phase of the range resolution unit to form a target feature sequence; preprocessing the target feature sequence; and storing it in a high-speed storage device.

[0051] Optionally, generate discrete scene slices that dynamically change with the detector's radar field of view, including: dividing the discrete scene slices at fixed time intervals according to the relative motion trajectory between the detector and the target, the radar beamwidth and elevation angle parameters, with each slice corresponding to the radar field of view coverage of the detector at the current moment.

[0052] Scene slicing includes: dividing the scene into discrete slices at fixed time intervals (e.g., 10μs) based on the relative motion trajectory of the radio fuze detector and the target, the radar beamwidth and elevation angle parameters. Each slice corresponds to the radar field of view coverage of the detector at the current moment, completely covering the entire process of the detector approaching the target.

[0053] As an optional implementation, the target region is modeled as a dynamic filter network, including:

[0054] Based on the geometric relationship of discrete scene slices, the beam coverage area is divided into multiple equidistant ring resolution units according to the range resolution corresponding to the detector radar signal bandwidth; optionally, the width of each range ring is equal to the range resolution.

[0055] Based on the target scattering characteristics data and spatial geometric projection relationship of each resolution cell, the amplitude and phase parameters of the corresponding resolution cell are calculated.

[0056] Dynamic filter network construction: A corresponding filter impulse response is constructed for each resolution unit from near to far. The filter network structure is dynamically updated according to discrete scene slices, generating a target feature sequence that evolves over time. Optionally, the distance coupling between resolution units is removed, compressing the sequence length to less than 1 / 10 of the traditional multi-scattering point model while preserving the target scattering features.

[0057] Amplitude and phase calculation of resolution unit: Based on the preset target material scattering characteristic data and spatial geometric projection relationship, the echo amplitude and phase parameters of each resolution unit are calculated. The amplitude parameter is positively correlated with the target projection area and scattering coefficient within the resolution unit, and the phase parameter is positively correlated with the two-way delay corresponding to the distance of the resolution unit.

[0058] This invention employs dynamic filter network target modeling to eliminate range coupling between resolution units, significantly shortening the target feature sequence length while fully preserving the target's temporal scattering and temporal correlation characteristics. By using a dynamic filter network modeling that updates dynamically with the radar field of view, this invention fully preserves the target's temporal correlation characteristics and fine scattering features. Simultaneously, through pipelined Doppler control strictly aligned with the convolutional pipeline, instantaneous Doppler parameters are matched to each sampling point, effectively solving the Doppler broadening distortion problem in high-bandwidth, high-speed, and wide-beam scenarios, and significantly improving the fidelity of echo simulation.

[0059] Optionally, the target feature sequence is preprocessed and stored in a high-speed storage device, including:

[0060] The target feature sequence is segmented, aligned, and padded with zeros according to the number of parallel processing paths of the FPGA. A sequence index data structure is constructed, and the preprocessed target feature sequence is stored in the corresponding address space of the high-speed storage device according to the slice timing.

[0061] The test preparation included: measuring the distance between the detector and the target simulation system antenna, measuring the inherent delay of the target simulation system's radio frequency and digital links, performing delay calibration compensation and manual fine-tuning, and confirming that the zero-distance simulated transmit and receive signals overlapped.

[0062] As an optional implementation method, delay calibration compensation includes: directly connecting the RF transmitter and receiver of the target simulation system through an RF cable to construct a closed-loop calibration link; generating a standard pulse modulation signal through the system's built-in DDS, transmitting it through the closed-loop link, comparing the envelope delay of the transmitted signal and the received signal, and measuring the inherent delay of the entire system link; calculating cross-cycle compensation parameters based on the inherent delay to complete the initial calibration.

[0063] By using a closed-loop calibration link, the influence of antenna spacing is eliminated. The inherent system delay is measured, for example: a standard pulse modulation signal with a 1GHz frequency and 1μs pulse width is generated using the FPGA's built-in DDS, transmitted through the closed-loop link, and then the pulse envelopes of the transmitted and received signals are compared using a digital detection unit. The measured inherent delay of the entire system link is 200ns.

[0064] Optionally, sampling point offset is performed using a cross-cycle compensation method to simulate target distance, including: obtaining the period of the signal transmitted by the detector under test, measuring the inherent delay of the entire link of the target simulation system; performing a modulo operation on the inherent delay according to the signal period to obtain the remainder, calculating the difference between the period of the signal transmitted by the detector under test and the remainder to obtain the cross-cycle compensation time difference; when the echo signal sampling point is offset, the sampling point offset corresponding to the compensation time difference is superimposed on the two-way delay offset corresponding to the target distance, plus the inherent delay of the system link and transmission, to obtain the two-way delay corresponding to the set target distance in the cross-cycle simulation.

[0065] Cross-cycle compensation parameter calculation, for example: Let the period of the linear frequency modulated signal for the detector under test be τ, τ = 1ms; let the modulo operation of the inherent delay over the signal period be ΔTr, ΔTr = 200ns; let the cross-cycle compensation time difference be ΔTc, ΔTc = τ - ΔTr = 999.8μs. (See attached...) Figures 2-4 As shown, the horizontal axis represents time, the vertical axis represents frequency, S1 is the transmitted signal, and S2 is the echo signal. (See attached diagram.) Figure 2 As shown, the desired scenario is ΔTr = t2 - t1. (See attached diagram) Figure 3 As shown, in the actual system scenario, the inherent system delay for calibration measurement is ΔTd, where ΔTd is t4-t3. (See attached diagram.) Figure 4 As shown, in the system calibration compensation scenario, the cross-cycle compensation time difference ΔTc is t8-t7. Let the actual echo delay be ΔTt, the actual echo delay be t6-t5, the echo control delay be ΔTe, and the echo control delay be t6-t7.

[0066] This invention overcomes the limitations of inherent system delay by using a cross-cycle remainder compensation method, achieving sub-nanosecond range simulation accuracy with a minimum simulation distance of less than 0.1m. It is also compatible with various periodic signal systems such as linear frequency modulated continuous wave, pseudo-code phase modulation, and pulse Doppler, solving the problem of the narrow applicability of existing frequency domain compensation methods. It is especially suitable for the short-range testing requirements of radio fuze radars.

[0067] Signal acquisition and transmission include: receiving signals transmitted by the detector, performing frequency conversion, quadrature sampling and digital mixing processing, and transmitting the zero intermediate frequency digital IQ signal to the real-time signal processing module through a high-speed data interface.

[0068] The specific process of signal acquisition and transmission is as follows: the K-band radio frequency signal emitted by the detector is received by the microwave frequency conversion front end and down-converted to a 1GHz intermediate frequency signal; orthogonal sampling is completed by a high-speed AD chip with a 5GHz sampling rate to obtain a digital intermediate frequency signal; digital mixing and decimation filtering are completed by a digital down-conversion DDC unit to obtain a zero intermediate frequency digital IQ signal, which is then transmitted in real time to the echo calculation module through a high-speed data interface in the FPGA.

[0069] The echo generation calculation includes: extracting the target model feature sequence from the high-speed storage device according to the scene time, performing convolution modulation between the zero intermediate frequency digital IQ signal and the target model feature sequence to generate a high-resolution target echo signal, and superimposing the Doppler frequency shift on the echo signal to simulate the radial velocity.

[0070] Optionally, the convolution modulation employs an adaptive segmented convolution algorithm, including:

[0071] Based on the length of the target model feature sequence corresponding to the current discrete scene slice, the segment length is adaptively determined, and the target model feature sequence is segmented.

[0072] Each segment of the target model feature sequence and the corresponding length of the input IQ signal are zero-padded and expanded, and then transformed to the frequency domain by FFT.

[0073] The frequency domain convolution operation is completed by multiplying the target model feature sequence in the frequency domain with the IQ signal using complex numbers.

[0074] The multiplication result is transformed back to the time domain by IFFT, and the non-aliased effective part of each segment is extracted. Multiple effective segments are spliced ​​together to obtain the target echo baseband signal as the linear convolution result.

[0075] For example:

[0076] (1) Sequence extraction and adaptive segmentation: According to the temporal sequence of the current scene slice, the corresponding target feature sequence is extracted from the memory. The length of the target feature sequence can be selected as 1024 points, and the length of a single segment is adaptively determined to be 256 points, and the feature sequence is divided into 4 segments;

[0077] (2) Data caching and expansion: The input IQ signal is cached by a ping-pong buffer. Each feature sequence is padded with zeros and expanded to 512 points. The length of each segment of the input IQ signal is set to 512 points, of which the first 255 sampling points are the tail sampling points of the previous segment of the IQ signal, and the last 257 sampling points are the new sampling points of the current segment. The overlap retention method is used to remove aliasing.

[0078] (3) FT frequency domain transformation: The 512-point FFT core that can be reused in the FPGA is used to perform FFT transformation on each feature sequence and IQ signal respectively, and transform them to the frequency domain;

[0079] (4) Frequency domain complex multiplication: The feature sequence in the frequency domain is multiplied point by point with the IQ signal by a complex multiplier to complete the frequency domain convolution operation;

[0080] (5) IFFT time domain transformation and effective data truncation: The multiplication result is transformed back to the time domain through a 512-point IFFT kernel. The first 255 aliased sampling points of each segment of the result are discarded, and the last 257 effective sampling points are retained.

[0081] (6) Segment splicing and Doppler modulation: The four effective results are spliced ​​to obtain a complete 1024-point linear convolution result, namely the high-resolution target echo baseband signal; based on the relative motion speed between the detector and the target, the corresponding instantaneous Doppler frequency is calculated for each sampling point, and a control signal that is strictly aligned with the convolution pipeline is generated. The Doppler frequency shift modulation of each sampling point is completed by a complex multiplier, which effectively suppresses Doppler broadening distortion in large bandwidth scenarios.

[0082] Optionally, the adaptive segmented convolution algorithm is implemented based on a pipeline architecture within the FPGA. The pipeline architecture includes multiple reusable FFT / IFFT cores, a ping-pong buffer, a complex multiplier, and a state control machine. The state control machine is used to control the timing synchronization of the pipeline's segmentation, zero-padding, FFT transformation, frequency domain multiplication, IFFT transformation, data truncation, and concatenation.

[0083] This invention uses an adaptive segmented convolution algorithm to convert the temporal linear convolution of high-resolution long sequences into multi-segment adaptive cyclic convolution. By optimizing the calculation process with FFT / IFFT kernels, the computational complexity is reduced from the square of the sampling rate to the logarithmic level. With a limited FPGA logic unit size, real-time calculation of long sequence echo simulation within a single clock cycle can be achieved without ultra-high-specification hardware chips, significantly reducing system complexity and hardware cost.

[0084] Echo delay control includes: shifting the target distance delay sampling points of the echo signal, shifting the sampling points by distance migration, shifting the sampling points by cross-cycle compensation, simulating the target distance, and transmitting the shifted echo signal to the signal playback module.

[0085] The specific process of echo delay control is as follows:

[0086] (1) Calculate the corresponding two-way delay based on the set target simulation distance, convert it into sampling point offset, and control the read and write address of DDR3 through the dynamic address generation unit to realize the distance delay offset of the whole sampling point;

[0087] (2) Range migration fine-tuning: Based on the relative position change between the target and the radar beam, the range migration offset corresponding to each scene slice is calculated, and the offset compensation of the subsampling points is completed by fractional delay filter;

[0088] (3) Cross-cycle compensation: Based on the calculated cross-cycle compensation time difference △Tc, it is converted into the corresponding sampling point offset. The compensation offset is injected through the cross-cycle compensation control unit to break through the limitation of the inherent delay of the system and realize the simulation of ultra-close target.

[0089] (4) Timing synchronization: Through the synchronization control unit, ensure that the control signals for distance offset, distance migration fine adjustment and cross-cycle compensation are strictly aligned with the timing of the adaptive convolution pipeline to avoid signal distortion caused by timing misalignment.

[0090] As an optional implementation, based on the relative motion parameters between the detector and the target, the corresponding instantaneous Doppler frequency and range migration offset are calculated for each sampling point, and a control signal aligned with the adaptive convolution pipeline is generated. Doppler frequency shift modulation and range migration offset compensation are completed point by point. The control signal includes address, coefficient index and fractional delay phase shift.

[0091] Signal playback includes: digital up-conversion and digital-to-analog conversion of the target echo signal to generate the target echo intermediate frequency signal, and transmitting the target echo radio frequency signal to the detector under test.

[0092] The zero-IF echo baseband signal is upconverted to 1GHz IF by a digital upconversion (DUC) unit; a high-speed DA chip completes the digital-to-analog conversion to generate an analog IF signal; the analog IF signal is upconverted to the detector's transmit RF band by a microwave frequency converter front-end, and after power amplification, it is radiated to the detector under test through a transmitting antenna to complete the target echo simulation.

[0093] This invention is based on a mature DRFM hardware architecture. The entire process of target modeling, convolution operation, and delay compensation is implemented through FPGA programmable logic. It can be flexibly configured according to the signal system, bandwidth, and resolution parameters of the radar under test. It eliminates the need for complex field measurement data acquisition, greatly reducing the engineering implementation difficulty of high-resolution target simulation. It can be widely used in the research and development testing scenarios of various radar detectors.

[0094] Example 2

[0095] Based on the same principle as the method shown in Embodiment 1 of the present invention, as illustrated in the appendix. Figure 5 As shown, the embodiments of the present invention also provide a high-resolution short-range radar target simulation system based on DRFM, including a target modeling unit, an experiment preparation unit, a signal acquisition and transmission unit, an echo generation and calculation unit, an echo delay control unit, and a signal playback unit;

[0096] The target modeling unit is configured to: generate discrete scene slices that dynamically change with the radar field of view of the detector based on the simulated scene environment parameters; model the target region as a dynamic filter network; extract the amplitude and phase of the range resolution unit to form a target feature sequence; preprocess the target feature sequence; and store it in a high-speed storage device.

[0097] The test preparation unit is configured to: measure the distance between the detector and the target simulation system antenna, measure the inherent delay of the target simulation system's radio frequency and digital links, perform delay calibration compensation and manual fine-tuning, and confirm the overlap of zero-distance simulated transmit and receive signals;

[0098] The signal acquisition and transmission unit is configured to receive the signal transmitted by the detector, perform frequency conversion, quadrature sampling and digital mixing processing, and transmit the zero intermediate frequency digital IQ signal to the real-time signal processing module through a high-speed data interface.

[0099] The echo generation computing unit is configured to: extract the target model feature sequence from the high-speed storage device according to the scene time, perform convolution modulation between the zero intermediate frequency digital IQ signal and the target model feature sequence to generate a high-resolution target echo signal, and superimpose Doppler frequency shift onto the echo signal to simulate radial velocity.

[0100] The echo delay control unit is configured to: offset the target distance delay sampling point of the echo signal, offset the sampling point by distance migration, offset the sampling point by cross-cycle compensation, simulate the target distance, and transmit the offset echo signal to the signal playback module.

[0101] The signal playback unit is configured to perform digital up-conversion and digital-to-analog conversion on the target echo signal to generate a target echo intermediate frequency signal, and transmit the target echo radio frequency signal to the detector under test.

[0102] Optionally, generate discrete scene slices that dynamically change with the detector's radar field of view, including: dividing the discrete scene slices at fixed time intervals according to the relative motion trajectory between the detector and the target, the radar beamwidth and elevation angle parameters, with each slice corresponding to the radar field of view coverage of the detector at the current moment.

[0103] Optionally, the target region can be modeled as a dynamic filter network, including:

[0104] Based on the geometric relationship of discrete scene slices, the beam coverage area is divided into multiple equidistant ring resolution units according to the distance resolution corresponding to the detector radar signal bandwidth.

[0105] Based on the target scattering characteristics data and spatial geometric projection relationship of each resolution cell, the amplitude and phase parameters of the corresponding resolution cell are calculated.

[0106] The filter impulse response is constructed for each resolution unit from near to far. The filter network structure is dynamically updated according to discrete scene slices to generate a target feature sequence that evolves over time.

[0107] Optionally, the target feature sequence is preprocessed and stored in a high-speed storage device, including:

[0108] The target feature sequence is segmented, aligned, and padded with zeros according to the number of parallel processing paths of the FPGA. A sequence index data structure is constructed, and the preprocessed target feature sequence is stored in the corresponding address space of the high-speed storage device according to the slice timing.

[0109] Optionally, delay calibration compensation is performed, including: directly connecting the RF transmitter and receiver of the target simulation system through an RF cable to construct a closed-loop calibration link; generating a standard pulse modulation signal through the system's built-in DDS, transmitting it through the closed-loop link, comparing the envelope delay of the transmitted signal and the received signal, and measuring the inherent delay of the entire system link; calculating cross-cycle compensation parameters based on the inherent delay to complete the initial calibration.

[0110] Optionally, the convolution modulation employs an adaptive segmented convolution algorithm, including:

[0111] Based on the length of the target model feature sequence corresponding to the current discrete scene slice, the segment length is adaptively determined, and the target model feature sequence is segmented.

[0112] Each segment of the target model feature sequence and the corresponding length of the input IQ signal are zero-padded and expanded, and then transformed to the frequency domain by FFT.

[0113] The frequency domain convolution operation is completed by multiplying the target model feature sequence in the frequency domain with the IQ signal using complex numbers.

[0114] The multiplication result is transformed back to the time domain by IFFT, and the non-aliased effective part of each segment is extracted. Multiple effective segments are spliced ​​together to obtain the target echo baseband signal as the linear convolution result.

[0115] Optionally, the adaptive segmented convolution algorithm is implemented based on a pipeline architecture within the FPGA. The pipeline architecture includes multiple reusable FFT / IFFT cores, a ping-pong buffer, a complex multiplier, and a state control machine. The state control machine is used to control the timing synchronization of the pipeline's segmentation, zero-padding, FFT transformation, frequency domain multiplication, IFFT transformation, data truncation, and concatenation.

[0116] Optionally, sampling point offset is performed using a cross-cycle compensation method to simulate target distance, including: obtaining the period of the signal transmitted by the detector under test, measuring the inherent delay of the entire link of the target simulation system; performing a modulo operation on the inherent delay according to the signal period to obtain the remainder, calculating the difference between the period of the signal transmitted by the detector under test and the remainder to obtain the cross-cycle compensation time difference; when the echo signal sampling point is offset, the sampling point offset corresponding to the compensation time difference is superimposed on the two-way delay offset corresponding to the target distance, plus the inherent delay of the system link and transmission, to obtain the two-way delay corresponding to the set target distance in the cross-cycle simulation.

[0117] Optionally, based on the relative motion parameters between the detector and the target, the corresponding instantaneous Doppler frequency and range migration offset are calculated for each sampling point, and a control signal aligned with the adaptive convolution pipeline is generated to complete Doppler frequency shift modulation and range migration offset compensation point by point; the control signal includes address, coefficient index and fractional delay phase shift.

[0118] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A high-resolution short-range radar target simulation method based on DRFM, characterized in that, This includes target modeling, test preparation, signal acquisition and transmission, echo generation and calculation, echo delay control and signal playback; Target modeling includes: generating discrete scene slices that dynamically change with the detector's radar field of view based on the simulated scene environment parameters; modeling the target region as a dynamic filter network; extracting the amplitude and phase of range resolution units to form a target feature sequence; preprocessing the target feature sequence; and storing it in a high-speed storage device. Test preparation includes: measuring the distance between the detector and the target simulation system antenna, measuring the inherent delay of the target simulation system's radio frequency and digital links, performing delay calibration compensation and manual fine-tuning, and confirming that the zero-distance simulated transmit and receive signals coincide; Signal acquisition and transmission include: receiving signals transmitted by the detector, performing frequency conversion, quadrature sampling and digital mixing processing, and transmitting the zero intermediate frequency digital IQ signal to the real-time signal processing module through a high-speed data interface; The echo generation calculation includes: extracting the target model feature sequence from a high-speed storage device according to scene time; performing convolution modulation on the zero-IF digital IQ signal and the target model feature sequence to generate a high-resolution target echo signal; and superimposing a Doppler frequency shift on the echo signal to simulate radial velocity. The convolution modulation adopts an adaptive segmented convolution algorithm, including: adaptively determining the segment length according to the length of the target model feature sequence corresponding to the current discrete scene slice; segmenting the target model feature sequence; and zero-padding and expanding each segment of the target model feature sequence with the corresponding length of the input IQ signal, and converting it to the frequency domain through FFT transformation. The target model feature sequence in the frequency domain is multiplied by the IQ signal to complete the frequency domain convolution operation. The multiplication result is transformed back to the time domain by IFFT transformation. The non-aliased effective part of each segment of the result is extracted and the multiple effective segments are concatenated to obtain the target echo baseband signal as the linear convolution result. The adaptive segmented convolution algorithm is implemented based on the pipeline architecture in the FPGA. The pipeline architecture includes multiple reusable FFT / IFFT cores, ping-pong buffers, complex multipliers and state control machines. The state control machine is used to control the timing synchronization of the pipeline segmentation, zero padding, FFT transformation, frequency domain multiplication, IFFT transformation, data extraction and concatenation. Echo delay control includes: shifting the target distance delay sampling points of the echo signal, shifting the sampling points by distance migration, shifting the sampling points by cross-cycle compensation, simulating the target distance, and transmitting the shifted echo signal to the signal playback module; Signal playback includes: digital up-conversion and digital-to-analog conversion of the target echo signal to generate the target echo intermediate frequency signal, and transmitting the target echo radio frequency signal to the detector under test.

2. The high-resolution short-range radar target simulation method based on DRFM according to claim 1, characterized in that, Generate discrete scene slices that dynamically change with the detector's radar field of view, including: dividing the discrete scene slices at fixed time intervals based on the relative motion trajectory between the detector and the target, the radar beamwidth and elevation angle parameters, with each slice corresponding to the radar field of view coverage of the detector at the current moment.

3. The high-resolution short-range radar target simulation method based on DRFM according to claim 1, characterized in that, Modeling the target region as a dynamic filter network includes: Based on the geometric relationship of discrete scene slices, the beam coverage area is divided into multiple equidistant ring resolution units according to the distance resolution corresponding to the detector radar signal bandwidth. Based on the target scattering characteristics data and spatial geometric projection relationship of each resolution cell, the amplitude and phase parameters of the corresponding resolution cell are calculated. The filter impulse response is constructed for each resolution unit from near to far. The filter network structure is dynamically updated according to discrete scene slices to generate a target feature sequence that evolves over time.

4. The high-resolution short-range radar target simulation method based on DRFM according to claim 1, characterized in that, The target feature sequence is preprocessed and stored in a high-speed storage device, including: The target feature sequence is segmented, aligned, and padded with zeros according to the number of parallel processing paths of the FPGA. A sequence index data structure is constructed, and the preprocessed target feature sequence is stored in the corresponding address space of the high-speed storage device according to the slice timing.

5. The high-resolution short-range radar target simulation method based on DRFM according to claim 1, characterized in that, Delay calibration compensation includes: directly connecting the RF transmitter and receiver of the target simulation system through an RF cable to build a closed-loop calibration link; generating a standard pulse modulation signal through the system's built-in DDS, transmitting it through the closed-loop link, comparing the envelope delay of the transmitted signal and the received signal, and measuring the inherent delay of the entire system link; calculating cross-cycle compensation parameters based on the inherent delay to complete the initial calibration.

6. The high-resolution short-range radar target simulation method based on DRFM according to claim 1, characterized in that, The sampling point offset is performed using a cross-cycle compensation method to simulate the target distance. This includes: obtaining the period of the signal transmitted by the detector under test and measuring the inherent delay of the entire link of the target simulation system; performing a modulo operation on the inherent delay according to the signal period to obtain the remainder, and calculating the difference between the period of the signal transmitted by the detector under test and the remainder to obtain the cross-cycle compensation time difference; when the echo signal sampling point is offset, the sampling point offset corresponding to the compensation time difference is superimposed on the two-way delay offset corresponding to the target distance, plus the inherent delay of the system link and transmission, to obtain the two-way delay corresponding to the set target distance in the cross-cycle simulation.

7. The high-resolution short-range radar target simulation method based on DRFM according to claim 1, characterized in that, Based on the relative motion parameters between the detector and the target, the instantaneous Doppler frequency and range migration offset are calculated for each sampling point, and a control signal aligned with the adaptive convolution pipeline is generated. Doppler frequency shift modulation and range migration offset compensation are completed point by point. The control signal includes address, coefficient index and fractional delay phase shift.

8. A high-resolution short-range radar target simulation system based on DRFM, characterized in that, It includes a target modeling unit, an experiment preparation unit, a signal acquisition and transmission unit, an echo generation and calculation unit, an echo delay control unit, and a signal playback unit; The target modeling unit is configured to: generate discrete scene slices that dynamically change with the radar field of view of the detector based on the simulated scene environment parameters; model the target region as a dynamic filter network; extract the amplitude and phase of the range resolution unit to form a target feature sequence; preprocess the target feature sequence; and store it in a high-speed storage device. The test preparation unit is configured to: measure the distance between the detector and the target simulation system antenna, measure the inherent delay of the target simulation system's radio frequency and digital links, perform delay calibration compensation and manual fine-tuning, and confirm the overlap of zero-distance simulated transmit and receive signals; The signal acquisition and transmission unit is configured to receive the signal transmitted by the detector, perform frequency conversion, quadrature sampling and digital mixing processing, and transmit the zero intermediate frequency digital IQ signal to the real-time signal processing module through a high-speed data interface. The echo generation computing unit is configured to: extract the target model feature sequence from the high-speed storage device according to the scene time, perform convolution modulation between the zero intermediate frequency digital IQ signal and the target model feature sequence to generate a high-resolution target echo signal, and superimpose Doppler frequency shift onto the echo signal to simulate radial velocity. The convolutional modulation employs an adaptive segmented convolution algorithm, which includes: adaptively determining the segment length based on the length of the target model feature sequence corresponding to the current discrete scene slice, and segmenting the target model feature sequence; zero-padding and expanding each segment of the target model feature sequence and the corresponding length of the input IQ signal, and converting it to the frequency domain through FFT transformation; The target model feature sequence in the frequency domain is multiplied by the IQ signal to complete the frequency domain convolution operation. The multiplication result is transformed back to the time domain by IFFT transformation. The non-aliased effective part of each segment of the result is extracted and the multiple effective segments are concatenated to obtain the target echo baseband signal as the linear convolution result. The adaptive segmented convolution algorithm is implemented based on the pipeline architecture in the FPGA. The pipeline architecture includes multiple reusable FFT / IFFT cores, ping-pong buffers, complex multipliers and state control machines. The state control machine is used to control the timing synchronization of the pipeline segmentation, zero padding, FFT transformation, frequency domain multiplication, IFFT transformation, data extraction and concatenation. The echo delay control unit is configured to: offset the target distance delay sampling point of the echo signal, offset the sampling point by distance migration, offset the sampling point by cross-cycle compensation, simulate the target distance, and transmit the offset echo signal to the signal playback module. The signal playback unit is configured to perform digital up-conversion and digital-to-analog conversion on the target echo signal to generate a target echo intermediate frequency signal, and transmit the target echo radio frequency signal to the detector under test.

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