Analog divider

Abstract

The analog divider comprises an input integral unit, a logical operation unit and an output integral unit, the input integration unit integrates the divisor voltage signal and then inputs the divisor voltage signal into the logical operation unit, the logical operation unit completes logical operation and transmits a result to the output integration unit, and the output integration unit performs integration or stopping on the dividend voltage signal according to the result and finally outputs a simulation division result. The two voltages Vx and Vy to be measured are two voltages for division. The input integration unit is used for integrating and outputting to the two comparators for comparison, whether a high level is output to open the NMOS switching tube or not is judged through the exclusive-OR gate, after the NMOS switching tube is opened, the output integration unit is used for integrating Vy, and after the output integration unit is stable, an output value Vout is a proportional result obtained by dividing two voltages. The analog divider is simple in circuit, convenient to operate and accurate in result, and has practical significance in application scenes such as measurement of on resistance of a power semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of analog computing technology, and more specifically to an analog divider. Background Technology

[0002] Analog dividers are core analog computing units widely used in industrial measurement and control, instrumentation, and signal processing. Their computational accuracy, structural complexity, and cost can affect the performance and application potential of electronic systems. As a key component in the proportional calculation of two voltage signals, its function is to quickly and accurately complete the nonlinear signal conversion and proportional solution. Defects such as large measurement deviations, structural redundancy, and excessively high costs can lead to computational distortion, affecting the reliability of signal processing and failing to meet the needs of precision equipment, thus hindering applications. With the development of electronic technology towards high precision, low cost, and miniaturization, existing defects have become a bottleneck for technological upgrades. Summary of the Invention

[0003] This invention provides an analog divider circuit that is simple in structure, accurate in operation, and low in cost. It can resolve the contradiction between performance and cost, while providing reliable support for precision equipment. It is suitable for applications in multiple fields and the needs of measuring the on-resistance of power semiconductor devices, and has practical value.

[0004] The technical solution adopted in this invention is as follows: An analog divider, the analog divider comprising: Input integration unit, logic operation unit, output integration unit; The input integration unit integrates the divisor voltage signal and then inputs it into the logic operation unit. The logic operation unit performs the logic operation and transmits the result to the output integration unit. The output integration unit integrates or stops the dividend voltage signal accordingly, and finally outputs the analog division result.

[0005] The input integration unit is connected to the divisor voltage signal, integrates the divisor voltage signal, and also provides input signals to the logic operation unit.

[0006] The logic operation unit performs logic operations based on the received input integration unit signal, and then outputs the result to the subsequent output integration unit.

[0007] The logic operation unit includes an XOR gate, and the output integration unit includes an NMOS switch. The XOR gate performs operations on the logic states of the two input signals and outputs the result signal to the NMOS switch.

[0008] The input integration unit receives the dividend voltage signal and the operation result signal from the preceding logic unit. The output integration unit determines whether the NMOS switch is turned on or off based on the operation result signal, thereby enabling the output integration unit to start and stop integrating the dividend voltage signal. Finally, the stable output result of the output integration unit is the analog division result.

[0009] An analog divider, the analog divider comprising: Input integration unit, logic operation unit, output integration unit; The input integration unit includes: operational amplifier OP1, resistors R1 and R4, and capacitor C1; The non-inverting input of operational amplifier OP1 is connected to one end of pull-down resistor R4, and the other end of pull-down resistor R4 is connected to GND. The signal Vx terminal is connected to one end of resistor R1, and the other end of resistor R1 is connected to one end of capacitor C1 and the inverting input terminal of operational amplifier OP1. The logic operation unit includes: a first comparator, a second comparator, and an XOR gate; The first comparator includes: operational amplifier OP3, resistors R5, R6, and R7; The other end of capacitor C1 is connected to one end of resistor R5, and the other end of resistor R5 is connected to the non-inverting input of operational amplifier OP3. The inverting input of operational amplifier OP3 is connected to one end of resistor R6, the other end of resistor R6 is connected to the negative terminal of voltage source U1, and the positive terminal of voltage source U1 is connected to GND. The output of operational amplifier OP3 is connected to one end of resistor R7, and the other end of resistor R7 is connected to one of the inputs of an XOR gate. The second comparator includes: operational amplifier OP4, resistors R8, R9, and R10; One end of resistor R8 is connected to the output terminal of operational amplifier OP1, and the other end of resistor R8 is connected to the non-inverting input terminal of operational amplifier OP4. The inverting input terminal of operational amplifier OP4 is connected to one end of resistor R9, and the other end of resistor R9 is connected to the negative terminal of voltage source U2. The positive terminal of voltage source U2 is connected to the GND terminal. The output of operational amplifier OP4 is connected to one end of resistor R10, and the other end of resistor R10 is connected to the other input of the XOR gate. The output integration unit includes: operational amplifier OP2, resistors R2 and R3, capacitor C2, and NMOS switch. The signal Vy terminal is connected to the drain of the NMOS switch, the source of the NMOS switch is connected to one end of the resistor R2, and the gate of the NMOS switch is connected to the output terminal of the XOR gate. The other end of resistor R2 is connected to one end of capacitor C2 and the inverting input of operational amplifier OP2. The non-inverting input of operational amplifier OP2 is connected to one end of resistor R3, and the other end of resistor R3 is connected to GND. The other end of capacitor C2 is connected to the output terminal Vout of operational amplifier OP2.

[0010] An analog divider: Two voltages, Vx and Vy, are used for division. The input integrator integrates the voltages and outputs the result to two comparators for comparison. After passing through an XOR gate, a high-level output is used to activate an NMOS switch. Once the NMOS switch is activated, the output integrator integrates Vy. After the output integrator stabilizes, the output value Vout is the ratio of the two voltages divided.

[0011] The workflow is as follows: First, after the circuit starts working, the input integration unit integrates the signal Vx. The integrated voltage is then compared with the voltages of two comparators to determine whether the voltage output by the integration circuit has reached the set value of the comparator voltage. If it has, the comparator outputs a high level; otherwise, the comparator outputs a low level. The comparator's output voltage is fed to an XOR gate. The XOR gate determines whether the voltage outputs of the two comparators are a combination of high and low levels. If they are a combination of high and low levels, the comparator outputs a high level; otherwise, the comparator outputs a low level.

[0012] The comparator's output voltage controls the NMOS switch's on / off state. When the comparator outputs a low level, the NMOS switch is off, and the output integration unit stops integrating. When the XOR gate outputs a high level, the NMOS switch is on, and the output integration unit integrates the signal Vy.

[0013] Once the output of the integrator unit stabilizes, the output Vout is the ratio of the division of signal Vy and signal Vx.

[0014] This invention provides an analog divider, with the following technical advantages: 1) High-precision measurement: This invention uses two voltage parameters in the same time domain for measurement and calculation, eliminating the influence of circuit delay and ensuring the accuracy of analog division. It avoids the drawback of traditional analog dividers that perform measurement and calculation when the voltage is unstable at the beginning. This method can perform analog division of various voltages and ensures the accuracy of the measurement results.

[0015] 2) The measurement circuit is simple: it consists of two integrators, two comparators, one XOR gate, and one NMOS switch. It has a simple structure and is easy to operate.

[0016] 3) High cost-effectiveness: Compared with the traditional complex analog division circuit that uses instruments, the present invention reduces the measurement cost of analog division. Attached Figure Description

[0017] The present invention will be further described below with reference to the accompanying drawings and embodiments: Figure 1 This is a system block diagram of the analog divider circuit of the present invention.

[0018] Figure 2 This is a flowchart illustrating the overall operation of the analog divider circuit of this invention.

[0019] Figure 3 This is a circuit diagram of the analog divider circuit of the present invention.

[0020] Figure 4 This is a diagram illustrating an application example of measuring the on-resistance of a simulated divider circuit in the LTspice simulation software.

[0021] Figure 5 Simulation results for an application example of a simulating divider. Detailed Implementation

[0022] like Figure 1 The diagram shown is a circuit block diagram of the analog divider of this invention. It includes two integrators, two comparators, one NMOS switch, and one XOR gate.

[0023] The circuit working principle of this invention is as follows: like Figure 1 As shown in the system block diagram of the division circuit, the two voltages to be measured, Vx and Vy, are the two voltages used for division. The input integrator integrates the voltages and outputs the result to two comparators for comparison. After passing through an XOR gate, a high-level output is used to activate the NMOS switch. Once the NMOS switch is activated, the output integrator integrates Vy. After the output integrator stabilizes, the output value Vout is the ratio of the two voltages divided.

[0024] like Figure 2 As shown, the overall workflow of the analog division circuit is as follows: First, after the circuit starts working, the input integration unit integrates the signal Vx. The integrated voltage is then compared with the voltages of two comparators to determine whether the voltage output by the integration circuit has reached the set value of the comparator voltage. If it has, the comparator outputs a high level; otherwise, the comparator outputs a low level. The comparator's output voltage is fed to an XOR gate. The XOR gate determines whether the voltage outputs of the two comparators are a combination of high and low levels. If they are a combination of high and low levels, the comparator outputs a high level; otherwise, the comparator outputs a low level.

[0025] The output voltage of the comparator is used to control the turn-off and turn-on of the NMOS switch. When the comparator outputs a low level, the NMOS switch is turned off, and the output integration unit will stop integrating. When the XOR gate outputs a high level, the NMOS switch is turned on, and the output integration unit will integrate the signal Vy.

[0026] After the output of the output integration unit stabilizes, the output Vout is the proportional multiple of the division of the signal Vy by the signal Vx.

[0027] As Figure 3 shown, the circuit schematic diagram of the analog division circuit includes voltage sources U1, U2, two integration circuits, and four operational amplifiers OP1, OP2, OP3, OP4 in two comparators, as well as resistors R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, and capacitors C1, C2. Figure 3 In, the voltages of the voltage sources U1 and U2 are the set comparison voltage values of the two comparators. Assuming U1 < U2, since the two voltage sources provide voltages in reverse connection, the output of OP1 in the integration circuit is negative, which is: (1); That is: (2); The output of OP2 is: (3); That is: (4); Assume that the output voltage integration change of OP2 in the time period from ta to tb is selected; When the time is ta, the output voltage of OP2 is: (5); When the time is ta, the output voltage of OP2 is: (6); Then it can be obtained that: (7); (8); Then the integral of the voltage output of OP2 in the time period from ta to tb is: (9); That is: (10); Substitute equations (7) and (8) into equation (10) and after arrangement, we get: (11); Since it starts changing from 0, the output value after Vout stabilizes is a proportional multiple of the voltage Vy and Vx divided by the given values. This can be adjusted... and as well as These quantities are the coefficients that affect the result of the division. Because If the quantity is known, and the value of Vout is also known, then it can be calculated. The value is used to complete the simulated division process.

[0028] Example: In this embodiment, a circuit model for measuring the on-resistance of a power semiconductor device was built using LTspice simulation software, and the analog division circuit of this invention was used to measure the on-resistance of the power semiconductor device. Figure 4 As shown.

[0029] In the simulation circuit, the loop on the left, consisting of a voltage source V1, resistor RG, and R0, represents the on-resistance of the power semiconductor device under test. RG is used to simulate the on-resistance of the device. The voltage source is set to output 3V, the sampling resistor R0 is 0.3Ω, and the preset on-resistance RG is 0.15Ω. In the analog division circuit on the right, R3 is 10kΩ, R1 is 10kΩ, R2 is 10kΩ, R4 is 5kΩ, R5 is 5kΩ, R8 is 10kΩ, R6 is 1kΩ, R7 is 1kΩ, R9 is 1kΩ, C1 is 0.0001F, and C2 is 0.0001F. Ua is -3V, Ub is -7V. All four operational amplifiers are ideal operational amplifiers. The NMOS is a transistor with a threshold voltage of 0.7V and an on-resistance of 0.01Ω. The parameters set are used to obtain... The calculated result is -4V.

[0030] After turning on the voltage source, observe the waveform, such as... Figure 5 As shown in the diagram, the blue voltage waveform is the output voltage of the XOR gate, the red voltage waveform is the output voltage Vout1 of the first integrator circuit, and the green waveform is the final output Vout of the entire analog division circuit. The diagram shows that the first integrator circuit continuously integrates, and a comparator triggers the XOR gate output for a period of time, which in turn triggers the second integrator circuit to integrate, ultimately resulting in the stable output of the division circuit. It is -6V. Therefore, by =-4, thus obtaining ,Depend on The calculated value of RG is 0.15, which is consistent with the preset value of RG.

[0031] The accuracy of the on-resistance measurement confirms the high precision of this analog division circuit. This invention avoids the shortcomings of traditional circuits—traditional circuits often initiate integration before the circuit has stabilized; however, this invention's analog division circuit waits for the circuit to stabilize before starting the second integrator to perform integration and output the result. Furthermore, the signal from the first integrator is transmitted through two comparators, an XOR gate, and an NMOS transistor, ensuring that the delay time for starting and stopping the second integrator is completely consistent. Because the integration result has linear characteristics, this delay only causes a slight shift in the integration result, without affecting the final output accuracy, thus further guaranteeing the precision of the analog division result.

[0032] The practical application of the analog division circuit of this invention has verified its advantages such as accuracy, versatility, economy and ease of operation, and it has practical significance in application scenarios such as measuring the on-resistance of power semiconductor devices.

Claims

1. An analog divider, characterized in that: The analog divider includes: Input integration unit, logic operation unit, output integration unit; The input integration unit integrates the divisor voltage signal and then inputs it into the logic operation unit. The logic operation unit performs the logic operation and transmits the result to the output integration unit. The output integration unit integrates or stops the dividend voltage signal accordingly, and finally outputs the analog division result.

2. The analog divider according to claim 1, characterized in that: The input integration unit is connected to the divisor voltage signal, integrates the divisor voltage signal, and also provides input signals to the logic operation unit.

3. The analog divider according to claim 2, characterized in that: The logic operation unit performs logic operations based on the received input integration unit signal, and then outputs the result to the subsequent output integration unit.

4. The analog divider according to claim 3, characterized in that: The logic operation unit includes an XOR gate, and the output integration unit includes an NMOS switch. The XOR gate performs operations on the logic states of the two input signals and outputs the result signal to the NMOS switch.

5. The analog divider according to claim 4, characterized in that: The input integration unit receives the dividend voltage signal and the operation result signal from the preceding logic unit. The output integration unit determines whether the NMOS switch is turned on or off based on the operation result signal, thereby enabling the output integration unit to start and stop integrating the dividend voltage signal. Finally, the stable output result of the output integration unit is the analog division result.

6. An analog divider, characterized in that: The analog divider includes: Input integration unit, logic operation unit, output integration unit; The input integration unit includes: operational amplifier OP1, resistors R1 and R4, and capacitor C1; The non-inverting input of operational amplifier OP1 is connected to one end of pull-down resistor R4, and the other end of pull-down resistor R4 is connected to GND. The signal Vx terminal is connected to one end of resistor R1, and the other end of resistor R1 is connected to one end of capacitor C1 and the inverting input terminal of operational amplifier OP1. The logic operation unit includes: a first comparator, a second comparator, and an XOR gate; The first comparator includes: operational amplifier OP3, resistors R5, R6, and R7; The other end of capacitor C1 is connected to one end of resistor R5, and the other end of resistor R5 is connected to the non-inverting input of operational amplifier OP3. The inverting input of operational amplifier OP3 is connected to one end of resistor R6, the other end of resistor R6 is connected to the negative terminal of voltage source U1, and the positive terminal of voltage source U1 is connected to GND. The output of operational amplifier OP3 is connected to one end of resistor R7, and the other end of resistor R7 is connected to one of the inputs of an XOR gate. The second comparator includes: operational amplifier OP4, resistors R8, R9, and R10; One end of resistor R8 is connected to the output terminal of operational amplifier OP1, and the other end of resistor R8 is connected to the non-inverting input terminal of operational amplifier OP4. The inverting input terminal of operational amplifier OP4 is connected to one end of resistor R9, and the other end of resistor R9 is connected to the negative terminal of voltage source U2. The positive terminal of voltage source U2 is connected to the GND terminal. The output of operational amplifier OP4 is connected to one end of resistor R10, and the other end of resistor R10 is connected to the other input of the XOR gate. The output integration unit includes: operational amplifier OP2, resistors R2 and R3, capacitor C2, and NMOS switch. The Vy terminal of the signal is connected to the drain of the NMOS switch transistor. The source of the NMOS switch transistor is connected to one end of the resistor R2. The gate of the NMOS switch transistor is connected to the output terminal of the exclusive-OR gate. The other end of the resistor R2 is respectively connected to one end of the capacitor C2 and the inverting input terminal of the operational amplifier OP2. The non-inverting input terminal of the operational amplifier OP2 is connected to one end of the resistor R3. The other end of the resistor R3 is connected to the GND terminal. The other end of the capacitor C2 is connected to the output terminal Vout of the operational amplifier OP2.

7. The analog divider as described in claim 6, characterized in that: Two measured voltages Vx and Vy are the two voltages for division. They are integrated by the input integration unit and output to two comparators for comparison. After being judged by the exclusive-OR gate, whether to output a high level to turn on the NMOS switch transistor. After the NMOS switch transistor is turned on, the output integration unit integrates Vy. After the output integration unit is stable, the output value Vout is the proportional result of the division of the two voltages.

8. The analog divider according to claim 6, wherein: First, after the circuit starts to work, the input integration unit first integrates the signal Vx. The integrated voltage needs to be compared by the voltages of two comparators to judge whether the voltage output by the integration circuit reaches the set value of the comparator voltage. If it reaches, the comparator outputs a high level, otherwise the comparator outputs a low level. The output voltage of the comparator is given to the exclusive-OR gate. The exclusive-OR gate judges whether the voltage outputs of the two comparators are a combination of high and low levels. If it is a combination of high and low levels, the comparator outputs a high level, otherwise, the comparator outputs a low level. The output voltage of the comparator is used to control the turn-off and turn-on of the NMOS switch transistor. When the comparator outputs a low level, the NMOS switch transistor is turned off, and the output integration unit will stop integrating. When the exclusive-OR gate outputs a high level, the NMOS switch transistor is turned on, and the output integration unit will integrate the signal Vy. After the output integration unit outputs stably, the output Vout is the proportional multiple of the division of the signal Vy and the signal Vx.

9. The analog divider according to claim 8, wherein: The voltages of the voltage sources U1 and U2 are the set comparison voltage values of the two comparators. When assuming U1 < U2, since the two voltage sources provide voltages in reverse connection, the output of OP1 in the integration circuit is negative, which is: （1）； That is: （2）； The output of OP2 is: （3）； That is: （4）； Assume to select the integral change of the output voltage of OP2 during the time period from ta to tb. When the time is ta, the output voltage of OP2 is: （5）； When the time is ta, the output voltage of OP2 is: （6）； Then it can be obtained that: （7）； （8）； ​ （9）； ​ （10）； ​ （11）。 ​ Since it starts changing from 0, the output value after Vout stabilizes is a proportional multiple of the voltage Vy and Vx divided by the given values, which can be adjusted... and as well as These quantities are the coefficients that affect the result of the division; because If the quantity is known, and the value of Vout is also known, then it can be calculated. The value is used to complete the simulated division process.

Images